SN54ABT240, SN74ABT240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS098I – JANUARY 1991 – REVISED JUNE 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Typical VOLP (Output Ground Bounce)
<1 V at VCC = 5 V, TA = 25°C
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Ioff Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. Together with the SN54ABT241,
SN74ABT241A, SN54ABT244, and
SN74ABT244A, these devices provide the choice
of selected combinations of inverting and
noninverting outputs, symmetrical active-low
output-enable (OE) inputs, and complementary
OE and OE inputs.
The SN54ABT240 and SN74ABT240A are
organized as two 4-bit buffers/line drivers with
separate OE inputs. When OE is low , the devices
pass inverted data from the A inputs to the Y
outputs. When OE is high, the outputs are in the
high-impedance state.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74ABT240AN SN74ABT240AN
SOIC DW
Tube SN74ABT240ADW
ABT240A
40
°
Cto85
°
C
SOIC
–
DW
Tape and reel SN74ABT240ADWR
ABT240A
–
40°C
to
85°C
SOP – NS Tape and reel SN74ABT240ANSR ABT240A
SSOP – DB Tape and reel SN74ABT240ADBR AB240A
TSSOP – PW Tape and reel SN74ABT240APWR AB240A
CDIP – J Tube SNJ54ABT240J SNJ54ABT240J
–55°C to 125°CCFP – W Tube SNJ54ABT240W SNJ54ABT240W
LCCC – FK Tube SNJ54ABT240FK SNJ54ABT240FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54ABT240 ...J OR W PACKAGE
SN74ABT240A . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
SN54ABT240 . . . FK PACKAGE
(TOP VIEW)
2Y4
1A1
1OE
1Y4
2A2 2OE
2Y1
GND
2A1 VCC
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ABT240, SN74ABT240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS098I – JANUARY 1991 – REVISED JUNE 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each buffer)
INPUTS OUTPUT
OE A Y
L H L
LLH
H X Z
logic diagram (positive logic)
1
218
1Y1
1OE
1A1
416
1Y2
1A2
614
1Y3
1A3
812
1Y4
1A4
19
11 9 2Y1
2OE
2A1
13 7 2Y2
2A2
15 5 2Y3
2A3
17 3 2Y4
2A4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO –0.5 V to 5.5 V. . . . . . . . .
Current into any output in the low state, IO: SN54ABT240 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT240A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54ABT240, SN74ABT240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS098I – JANUARY 1991 – REVISED JUNE 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ABT240 SN74ABT240A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 5 5 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT240 SN74ABT240A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VOH
VCC = 5 V, IOH = –3 mA 3 3 3
V
V
OH
VCC =45V
IOH = –24 mA 2 2
V
V
CC =
4
.
5
V
IOH = –32 mA 2* 2
VOL
VCC =45V
IOL = 48 mA 0.55 0.55
V
V
OL
V
CC =
4
.
5
V
IOL = 64 mA 0.55* 0.55
V
Vhys 100 mV
IIVCC = 5.5 V, VI = VCC or GND ±1±1±1µA
IOZH VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
IOZL VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
IO‡VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
V55VI0
Outputs high 1 250 250 250 µA
ICC VCC = 5.5 V, IO = 0,
VI=V
CC or GND
Outputs low 24 30 30 30 mA
VI
=
VCC
or
GND
Outputs disabled 0.5 250 250 250 µA
§
Data VCC = 5.5 V,
One input at 3.4 V, Outputs enabled 1.5 1.5 1.5
∆ICC
§
inputs
,
Other inputs at
VCC or GND Outputs disabled 0.05 0.05 0.05 mA
Control
inputs VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 1.5 1.5 1.5
CiVI = 2.5 V or 0.5 V 4 pF
CoVO = 2.5 V or 0.5 V 7.5 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†All typical values are at VCC = 5 V.
‡Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
SN54ABT240, SN74ABT240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS098I – JANUARY 1991 – REVISED JUNE 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT240
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
tPLH
A
Y
1 2.9 4.3 0.8 5.5
ns
tPHL
A
Y
1.6 3.1 4.5 1 5.5
ns
tPZH
OE
Y
1.1 3.1 5.8 0.8 7.5
ns
tPZL
OE
Y
1.1 2.7 6.2 0.8 7.7
ns
tPHZ
OE
Y
1.8 4.6 5.9 1.7 7
ns
tPLZ
OE
Y
1.6 4 5.9 1.3 7.2
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT240A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
tPLH
A
Y
1 2.9 4.1 1 4.8
ns
tPHL
A
Y
1.6 3.1 4.6 1.6 4.8
ns
tPZH
OE
Y
1.1 3.1 4.7 1.1 5.2
ns
tPZL
OE
Y
1.1 2.7 5.8 1.1 6.2
ns
tPHZ
OE
Y
1.8 4.6 5.7 1.8 6.4
ns
tPLZ
OE
Y
1.6 4 5.4 1.6 5.8
ns
SN54ABT240, SN74ABT240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS098I – JANUARY 1991 – REVISED JUNE 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
Output
Control
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 . 5 ns , t f≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ABT240ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74ABT240ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74ABT240ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74ABT240APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ABT240ADBR SSOP DB 20 2000 367.0 367.0 38.0
SN74ABT240ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74ABT240ANSR SO NS 20 2000 367.0 367.0 45.0
SN74ABT240APWR TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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