The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix "MB". However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix "CY". How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB39C031 2ch Buck DC/DC Converter + 1ch LDO with I2C Interface and SW FET Description The MB39C031 contains 2ch buck DC/DC converter and 1ch LDO. It is possible to supply the main power supply line in a system by using only one chip. The current mode system is adopted for the DC/DC converter, and it is possible to use the chip inductor with the high switching frequency operation which contains internal SW FET. The MB39C031 contains the output setting resistor and the the phase compensation circuit, and contributes to reduce the number of external components and the mounting area. 2 Also, it contains the CTL input pin which can control the ON/OFF for each CH, the Power Good signal output pin and the I C communication interface, therefore it is easy to design the power supply sequence. 2 It is possible to tune in the output voltage exactly using the I C communication and possible to correspond to the DVS/ASV system. Features Operating input voltage range:2.5 V to 5.5 V (Maximum rating: 7 V) Output voltage setting range, Maximum output current: DD1*:1.0 V to 1.3 V (20 mV/step), 1.4 A (DC) DD2*:1.2 V to 1.95 V (50 mV/step), 0.6 A (DC) LDO:2.8 V/2.85 V/3.0 V/3.3 V, 0.25 A (DC) Note: Each channel has selective preset voltage (Lineup for a total of 32 kinds) . Soft-start time setting range: 0.9 ms to 14.3 ms (approximately 0.9 ms/step) Switching frequency for the DC/DC block:3 MHz (fixed) 2 Communication interface: I C (ON/OFF, Output voltage, Soft-start time setting) Built-in PFM/PWM auto switching mode Built-in function: Output setting resistor, Phase compensation circuit, Discharge resistor, Soft-start Each Channel Power Good output function (Open-drain) Protection function: Under voltage lockout protection circuit (UVLO), Over current protection circuit (OCP), Thermal shutdown protection circuit (TSD) Error signal output pin installed (Open-drain) Small package: QFN28 (4 mm x 4 mm x 0.8 mm, 0.4 mm pitch) *: DD1,DD2 : DC/DC converter block 1, 2 Applications Network equipment: Wifi-tuner, Surveillance camera Data-storage device: HDD, SSD, Picture recording equipment Image and voice output equipment: MFP, Printer, Scanner, Projector, Electrophone, STB Various terminals: POS, FA, HEMS etc. Cypress Semiconductor Corporation Document Number: 002-08407 Rev. *B * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised May 18, 2017 MB39C031 Contents Description .......................................................................................................................................................... 1 Features ............................................................................................................................................................. 1 Applications ........................................................................................................................................................ 1 1. Application Circuit Example......................................................................................................................... 3 2. Recommended Application Specifications .................................................................................................. 4 3. Pin Assignment ............................................................................................................................................ 6 4. Pin Descriptions (PKG) ............................................................................................................................... 7 5. Block Diagram ............................................................................................................................................. 9 6. Absolute Maximum Ratings....................................................................................................................... 10 7. Recommended Operating Conditions ........................................................................................................11 8. Electrical Characteristics ........................................................................................................................... 12 9. Operation Mode List .................................................................................................................................. 17 10. State Transition Diagram ........................................................................................................................... 18 11. Turning On and Off Sequence (Turning On CTL*:CTL1, CTL2, CTLMAIN=VCC Simultaneously) .......... 19 12. CTL* Turning On and Off Sequence 1 (VCC CTL*: CTL1, CTL2, CTLMAIN) ...................................... 20 13. CTL* Turning On and Off Sequence 2(VCCCTLMAINCTL1CTL2) ................................................ 21 14. CTL* Pin Threshold Voltage ...................................................................................................................... 22 15. Protection Operation Sequence ................................................................................................................ 23 16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit ...................................... 25 17. DD Soft-Start Operation ............................................................................................................................ 26 18. Discharge Operation ................................................................................................................................. 27 19. PG1/PG2/PGL PIN and ERR PIN ............................................................................................................. 29 2 20. I C Interface............................................................................................................................................... 30 2 21. Structure of I C Interface and Data ........................................................................................................... 36 22. I/O Pin Equivalent Circuit Diagram ............................................................................................................ 41 23. I/O Circuit Type .......................................................................................................................................... 42 24. Typical Operation Characteristic Measurement Circuit ............................................................................. 43 25. Reference Data ......................................................................................................................................... 45 26. Usage Precaution ...................................................................................................................................... 65 27. Ordering Information ................................................................................................................................. 66 28. Preset Code (MB39C031) ......................................................................................................................... 66 29. Package Dimensions ................................................................................................................................. 67 Document History ............................................................................................................................................. 68 Sales, Solutions, and Legal Information ........................................................................................................... 69 Document Number: 002-08407 Rev. *B Page 2 of 69 MB39C031 1. Application Circuit Example Vin 5.0V MB39C031 4.7F 4.7F 0.1F PVCC1 PVCC2 PVCCL LX1 IN1 PGND1 VCC VCC LX2 IN2 PGND2 4.7F 0.1F CTL Signal I2C Signal VCCI2C SCL SDA ADDSEL 0.1F VR VREF LDO Vo1 1.2V 1.4A 10F 1.5H CTL1 CTL2 CTLL CTLMAIN 0.47F 1.5H Vo2 1.8V 0.6A 10F LDO 3.3V 0.25A 10F 100k 100k 100k 100k PG1 PG2 PGL ERR GND GND Document Number: 002-08407 Rev. *B Page 3 of 69 MB39C031 2. Recommended Application Specifications [Input Voltage Range] Input voltage VCC (V) Min Typ Max 2.5 3.6 5.5 [Output Specification] Accuracy Symbol Channel (Ta=+25C) Output Limit Output voltage current Current (V) (mA) (mA) Min Typ Max Max Min 14.3 1.01 1.02 1.03 0.9* 1.03 1.04 1.05 1.8 1.05 1.06 1.07 2.7 1.07 1.08 1.09 3.6 1.09* 1.10* 1.11* 4.5 1.13 1.14 1.15 1.15 1.16 1.17 5.4 Buck 1400 1.17 1.18 1.19 2000 (synchronous rectification) C-mode 3.0 1.5 10 6.3 7.2 9.0 1.21 1.22 1.23 9.9 1.23 1.24 1.25 10.8 1.24 1.26 1.28 11.6 1.26 1.28 1.30 12.5 1.28* 1.30* 1.32* 13.4 1.19* 1.20* 1.21* 14.3 1.24 1.25 1.27 0.9* 1.28 1.30 1.32 1.8 1.33* 1.35* 1.37* 2.7 1.38 1.40 1.42 3.6 1.43 1.45 1.47 4.5 1.53 1.55 1.57 1.58 1.60 1.62 5.4 Buck 600 1.63 1.65 1.67 900 (synchronous rectification) C-mode 3.0 1.5 10 6.3 7.2 8.1 1.68 1.70 1.72 9.0 1.73 1.75 1.77 9.9 1.78* 1.80* 1.82* 10.8 1.83 1.85 1.87 11.6 1.88 1.90 1.92 12.5 1.93 1.95 1.97 13.4 Document Number: 002-08407 Rev. *B 5 8.1 1.19* 1.20* 1.21* 1.48* 1.50* 1.52* DD2 Vo2 1.2% Switching Coil Output Soft-start Discharge frequency capacitance time resistance Remarks (MHz) (H) (F) (ms) (k) 0.99* 1.00* 1.01* 1.11 1.12 1.13 DD1 Vo1 1.2% Mode 5 Built-in SW FET Built-in output setting resistors Operation mode switching (Fixed PWM, PFM/PWM) Built-in SW FET Built-in output setting resistors Operation mode switching (Fixed PWM, PFM/PWM) Page 4 of 69 Accuracy Symbol Channel MB39C031 LDO LDO 1.8% Output Limit Output voltage current Current (V) (mA) (mA) Min Typ Max Max Mode Min Switching Coil Output Soft-start Discharge frequency capacitance time resistance Remarks (MHz) (H) (F) (ms) (k) 2.75 2.80 2.85 14.3 2.80* 2.85* 2.90* 0.9 2.95 3.00 3.05 1.8 3.24* 3.30* 3.36* 2.7* - - - 3.6 - - - 4.5 - - - 5.4 - - - - - - - - - 8.1 - - - 9.0 - - - 9.9 - - - 10.8 - - - 11.6 - - - 12.5 - - - 13.4 250 300 LDO - - 6.3 4.7 7.2 5 *: Preset value 2 Note: It is possible to set the output voltage and to change the soft-start time using I C. Document Number: 002-08407 Rev. *B Page 5 of 69 MB39C031 3. Pin Assignment VCC ERR PVCCL LDO PGL CTLL GND (TOP VIEW) 28 27 26 25 24 23 22 CTL1 1 21 CTL2 PG1 2 20 PG2 PGND1 3 19 PGND2 LX1 4 18 LX2 PVCC1 5 17 PVCC2 IN1 6 16 IN2 CTLMAIN 7 15 VREF Top View 8 9 10 11 12 13 14 VCC VCCI2C SCL SDA ADDSEL GND VR EP(Exposed Pad) (WNO028) Document Number: 002-08407 Rev. *B Page 6 of 69 MB39C031 4. Pin Descriptions (PKG) Circuit block DD1 DD2 LDO CTL ERR Numb er of Pin Pin name pin for No PKG I/O Description (PKG) PAD PAD PAD PullPAD treatment treatment treatment down treatment when not when not when not 2 resist when not using I C using using ance using LDO communi DD1 DD2 cation IN1 1 6 I DD1*Output voltage feedback pin. - GND connection - - - PVCC1 1 5 - DD1*Output block power supply pin - VCC connection - - - LX1 1 4 O DD1*Pin for inductance connection. - Open - - - PG1 1 2 O DD1*POWERGOO D output pin - Open - - - PGND1 1 3 - DD1*Output block ground pin - GND connection - - - IN2 1 16 I DD2*Output voltage feedback pin. - - GND connection - - PVCC2 1 17 - DD2*Output block power supply pin - - VCC connection - - LX2 1 18 O DD2*Pin for inductance connection. - - Open - - PG2 1 20 O DD2*POWERGOO D output pin - - Open - - PGND2 1 19 - DD2*Output block ground pin - - GND connection - - PVCCL 1 26 - LDO*Power supply pin - - - VCC connection - LDO 1 25 O LDO*Output pin - - - Open - PGL 1 24 O LDO*POWERGOO D output pin - - - Open - CTL1 1 1 I DD1 Control pin CTL2 1 21 I DD2 Control pin - CTLL 1 23 I LDO Control pin - - CTLMAIN 1 7 I Control pin for common block and digital block * - - - - ERR 1 27 O ERR signal output pin - - - - - Document Number: 002-08407 Rev. *B Open Open - - - - Open - Page 7 of 69 MB39C031 Circuit block I2C Commo n - Numb er of Pin Pin name pin for No PKG I/O Description (PKG) PAD PAD PAD PullPAD treatment treatment treatment down treatment when not when not when not 2 resist when not using I C using using ance using LDO communi DD1 DD2 cation VCCI2C 1 9 - Power supply pin for I2C. - - - - GND connection SCL 1 10 I I2C clock pin x - - - Open SDA 1 11 I/O I2C data I/O pin x - - - Open ADDSEL 1 12 I Switch pin for slave address - - - Open VCC 2 8, 28 - Control circuit block power supply pin - - - - - VREF 1 15 O Reference voltage (2.4V) output pin - - - - - VR 1 14 O Reference voltage (0.6V) output pin - - - - - GND 2 13, 22 - Control circuit block ground pin - - - - - GND 1 EP - Ground pin - - - - - *: When turning on DD1, DD2 and LDO, it is also necessary to set CTLMAIN to "H". See 9. Operation Mode List for the details. Document Number: 002-08407 Rev. *B Page 8 of 69 MB39C031 5. Block Diagram IN1 PVCC1 <<DD1>> VCC:2.5V to 5.5V L Priority A VCC VCC VCC ErrAMP ctl1 PWM Logic AST Control ICOMP LX1 Vo1:1.00V to 1.30V (20mV step) Io(Max):1400mA 0.6V DEC UVLO POR A LV CNV PGND1 SLP PG1 IN2 scp1 cs1 vsel1 clk1 PVCC2 <<DD2>> L Priority B VCC VCC PWM Logic AST Control ICOMP LX2 Vo2:1.20V to 1.95V (50mV step) Io(Max):600mA 0.6V DEC UVLO POR B VCC ErrAMP ctl2 LV CNV PGND2 SLP PG2 cs2 vsel2 scp2 clk2 PVCCL <<LDO>> LDO:2.80V/2.85V/ 3.00V/3.30V Io(Max):250mA LDO 0.6V ctll DEC UVLO POR csl vsell PGL scpl VREF CTLMAIN Logic control block ctlmain VCCI2C SCL SDA ADDSEL CTL1 ctl1 CTL2 ctl2 CTLL ctll scp1/2/l ERR SCP (counter & latch) OTP Soft-start control Output voltage switch control Common block power supply ctlmain cs1/2/l Common block vsel1/2/l VR,OSC,logic power supply VREF VCC VCC BGR UVLO VREF VREF Reference 0.6V OSC CT RT VR clk1/2 VREF (2.4V) Document Number: 002-08407 Rev. *B VR GND GND : Pin (0.6V) Page 9 of 69 MB39C031 6. Absolute Maximum Ratings Parameter Power supply voltage Input voltage Symbol Condition Rating Min Max Unit VCC VCC, PVCC1, PVCC2, PVCCL, VCCI2C pins - 7 V VCTL CTLMAIN, 1, 2, L pins - 7 V VOUT IN1, IN2 pins - 7 V Vlogic SDA, SCL pins - 7 V LX voltage VLX LX1, LX2 pins -0.3 +7 V Power dissipation PD - 1720 mW Maximum junction temperature Tjmax - - +125 C Storage temperature TSTG - -55 +125 C Ta +25C Thermal resistor value (j-a):(50C/W*) *: When mounted on a QFN28 (WNO028) PKG, 4layers 0.8 mm thickness 117 mm x 84 mm WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-08407 Rev. *B Page 10 of 69 MB39C031 7. Recommended Operating Conditions Parameter Power supply voltage General DC/DC CH Reference voltage output current Symbol Condition Min Typ Max Unit VCC VCC pin 2.5 3.6 5.5 V IREF VREF pin -1 - 0 mA IR VR pin -1 - 0 A -30 +25 +85 C 2.5 3.6 5.5 V 0 - VCC V 3.5 3.6 5.5 V 0 - VCC V 1.76 - 3.37 V 0 - VCCI2C V Operating temperature Ta Power supply voltage VCC VCC, PVCC1, PVCC2 pins Input voltage VOUT IN1, IN2 pins - VCC, PVCCL pins LDO CH Power supply voltage VCC CTL block Input voltage VCTL CTL* pin Power supply voltage VCC VCCI2C pin Logic input voltage Vlogic SDA, SCL pin Digital block (I2C) Value Output voltage setting: default (3.3V) *: CTLMAIN, CTL1, CTL2, CTLL WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-08407 Rev. *B Page 11 of 69 MB39C031 8. Electrical Characteristics Common Block (Ta=+25C, VCC=PVCC1, PVCC2, L=3.6V) Parameter Symbol Condition Value Min Typ Max Unit VR VR pin =0mA 0.594 0.600 0.606 V VREF1 VREF pin =0mA 2.376 2.400 2.424 V VREF2 VCC pin =2.5V to 5.5V 2.370 2.400 2.430 V VREF3 VREF pin =0mA to -1mA 2.370 2.400 2.430 V Threshold voltage VTH VCC pin = 2.156 2.20 2.244 V Hysteresis width VH - - 0.20 - V Over Current Protection Circuit Block [OCP] Timer time tOCP1 DD1, DD2, LDO Default value 0.5 1 1.5 ms Thermal shutdown Protection Circuit Block [TSD] Stop temperature TTSDH - - 150* - C VCC x 0.7 - VCC V Reference Voltage Block [VR, VREF] Under Voltage Lockout Protection Circuit Block [VCC UVLO] Output voltage Input voltage Control Block (CTL) [CTL] Input current Input pull-down resistor General (DC/DC block) Power supply current VIH CTL* pin VIL CTL* pin ICTLH CTL* pin =3.6V ICTLL 0 - 0.4 V 2.7 3.6 5.1 A CTL* pin =0V - - 1 A RP CTL* pin - 1 - M IVCCS1 CTL* pin =0V - 0 1.0 A IVCCS2 CTLMAIN=3.6V CTL1, CTL2.L pins =0V - 80 120 A IVCC CTLMAIN, L pins =3.6V Only LDO operation No load - 200 300 A IVCC CTL* pin = 3.6V all CH No load (DD operation mode: PFM/PWM mode) - 450 680 A - 10.8 16.2 mA - 7.2 12.0 A IVCC IVCCI2C CTL* pin = 3.6V all CH No load (DD operation mode: Fixed PWM mode) CTLMAIN, L pin=3.6V VCCI2C pin = 1.8V *: These are not the rated values. Use these values as reference when planning. Document Number: 002-08407 Rev. *B Page 12 of 69 MB39C031 DD1, DD2 (Ta=+25C, VCC=PVCC1, PVCC2, L=3.6V) Parameter Symbol Output voltage VOUT Input stability VLINE Load stability VLOAD Condition Value Unit Min Typ Max 1.186 1.20 1.214 V IOUT=-10mA, VCC=2.5V to 5.5V -5 - +5 mV IOUT=-1mA to -1400mA (when in Fixed PWM mode) -10 - - mV IOUT=-1mA to -1400mA (when in PFM/PWM mode) -10 - +15 mV Output voltage setting: 1.2V IOUT=-10mA IN1 pin=1.5V DC/DC Converter Block [DD1] IN1 pin input impedance RIN output voltage setting: 1.2V - 400 - k SW PMOS-Tr ON resistance RPMOS LX1 pin=-30mA - 0.12* - SW NMOS-Tr ON resistance RNMOS LX1 pin= 30mA - 0.09* - SW PMOS-Tr leak current ILEAK LX1 pin=0V -1 - - A SW NMOS-Tr leak current ILEAK LX1 pin=3.6V - - 1 A Overcurrent protection value ILIMIT L=1.5H 2000 - - mA PFM/PWM reshuffling electric current IPFM L=1.5H - 40* - mA Discharge resistor RDIS - 5 - k Soft-start time tSS 0.8 0.9 1.0 ms Switching frequency fOSC 2.7 3.0 3.3 MHz Document Number: 002-08407 Rev. *B Preset value - Page 13 of 69 MB39C031 Parameter Condition Value Min Typ Max Unit Output voltage VOUT Output voltage setting: 1.8V IOUT=-10mA 1.778 1.80 1.822 V Input stability VLINE IOUT=-10mA VCC=2.5V to 5.5V -5 - +5 mV IOUT=-1mA to -600mA (when in Fixed PWM mode) -10 - - mV IOUT=-1mA to -600mA (when in PFM/PWM mode) -10 - +20 mV Load stability DC/DC Converter Block [DD2] Symbol VLOAD IN2 pin input impedance RIN IN2 pin =2.0V Output voltage setting: 1.8V - 300 - k SW PMOS-Tr ON resistance RPMOS LX2 pin =-30mA - 0.16* - SW NMOS-Tr ON resistance RNMOS LX2 pin = 30mA - 0.14* - SW PMOS-Tr leak current ILEAK LX2 pin =0V -1 - - A SW NMOS-Tr leak current ILEAK LX2 pin =3.6V - - 1 A Overcurrent protection value ILIMIT L=1.5H 900 - - mA PFM/PWM reshuffling electric current IPFM L=1.5H - 70* - mA Discharge resistor RDIS - 5 - k Soft-start time tSS 0.8 0.9 1.0 ms Switching frequency fOSC 2.7 3.0 3.3 MHz Preset value - *: These are not the rated values. Use these values as reference when planning. Document Number: 002-08407 Rev. *B Page 14 of 69 MB39C031 LDO (Ta=+25C, VCC=PVCC1, PVCC2, L=3.6V) Parameter LDO Block [LDO] Symbol Output voltage VOUT I/O voltage difference VDIF Input stability VLINE Load stability VLOAD Ripple remove ratio RR Condition Max 3.241 3.300 3.359 V - - 0.20 V -5 - +5 mV IOUT=-1mA to -150mA -30 -20 - mV PVCCL=0.2Vrms, f=10Hz, IOUT=-150mA 35 75 - dB 15 50 - dB 300 - - mA - 0 1 A - 80 105 A - 5 - k 2.4 2.7 3.0 ms Output voltage setting : 3.3V IOUT=-10mA IOUT=-10mA IOUT=-10mA, VCC=3.5V to 5.5V PVCCL=0.2Vrms, f=10kHz, ILIMIT Voutx0.9 Control macro consumption current IPVCCLS At stand-by IPVCCL IOUT=0mA Discharge resistor RDIS Soft-start time tSS Document Number: 002-08407 Rev. *B Unit Typ IOUT=-150mA Overcurrent protection value Value Min Preset value Page 15 of 69 MB39C031 Digital Block (Ta=+25C, VCC=PVCC1, PVCC2, L=3.6V) Parameter Symbol Condition Value Min Typ Max Unit Output voltage VOL PG1, PG2, L pins IOL=1mA - - 0.4 V Output current IOL PG1, PG2, L pins 1 - - mA Low-voltage detection Vth IN1, IN2, LDO pins = - Vo x 0.75* - V Power-on detection voltage Vth - Vo x 0.85* - V Error Block Output voltage VOL ERR pin IOL = 1mA - - 0.4 V [ERR] Output current IOL ERR pin 1 - - mA VIH SCL, SDA pins VCCI2C=3.3V VCCI2C x 0.7 - VCCI2C V VIL SCL, SDA pins VCCI2C=3.3V 0 - VCCI2C x 0.3 V IIH SCL, SDA pins VCCI2C=3.3V - - 10 A IIL SCL, SDA pins VCCI2C=3.3V -10 - - A Output voltage VOL SDA pin IOL =3mA - - 0.4 V Output current IOL SDA pin 3 - - mA Input pull-down resistor RP ADDSEL pin - 1 - M POWER-GOOD Block [Power Good ] IN1, IN2, LDO pins Input voltage I2C Block Input current [I2C] = *: These are not the rated values. Use these values as reference when planning. Document Number: 002-08407 Rev. *B Page 16 of 69 MB39C031 9. Operation Mode List Mode Stand-by Stand-by 2 General ERR detection L H H H CTL1 (External / I C) L L H/L X CTL2 (External / I2C) L L H/L X CTLMAIN (External) 2 CTL Signal 2 CTLL (External / I C) Operation Block L L H/L X General OFF ON ON ON Digital Block OFF ON ON ON 2 OSC, VR Block OFF OFF ON* OFF DD1 OFF OFF ON/OFF OFF DD2 OFF OFF ON/OFF OFF LDO OFF OFF ON/OFF OFF I2C communication Disabled Enabled Enabled Enabled Thermal shutdown Protection (TSD) Not available Not available Available *1 Over Current Protection (OCP) Not available Not available Available *1 2 IC Communication Protection Operating *1:This is the state after detection of ERR. It is possible to release the ERR detection mode by turning the power supply on again or turning CTLMAIN on again. *2:When only LDO is operating, the OSC block stops (OFF) after LDO activation. Also, the VR block keeps operating (ON) after LDO activation. 2 Priority of the external pin/I C communication for CTL1, CTL2 and L CTLMAIN (External pin) CTL* (External pin) CTL* (I2C communication) Relevant CH H H H Unavailable H H L ON H L H ON H L L OFF L X Communication disabled OFF 2 *:The I C communication is enabled after the common block and digital block activation setting the external "H". When executing the ON/OFF control for DD1, DD2 and LDO using the external pin, don't execute the 2 ON/OFF control using I C. Aside from the ON/OFF control, it is possible to control everything else using 2 When executing the ON/OFF control for DD1, DD2 and LDO using I C, input "L" to the CTL* pin (the pin connection condition). Document Number: 002-08407 Rev. *B CTLMAIN pin to 2 I C. is open or in the GND Page 17 of 69 MB39C031 10. State Transition Diagram Stand-by (1) (2) Stand-by 2 (3) (4) General (5) (6) Error detection (1)External CTLMAIN pin "H" (2)External CTLMAIN pin "L" 2 (3)External CTL pin "H" / I C communication "relevant CH_ON" 2 (4)External CTL pin "L" / I C communication "relevant CH_OFF" (5)Error detection (OCP, OCP_1ms continuation) (6)Turning on the power supply again (equal to or less than uvlo_vcc reset voltage) or setting CTLMAIN to "L" Notes: When executing the ON/OFF control for DD1, DD2 and LDO using the external pin, don't execute the 2 2 I C. Aside from the ON/OFF control, it is possible to control everything else using I C. ON/OFF control using 2 When executing the ON/OFF control for DD1, DD2 and LDO using I C, input "L" to the CTL* pin (the pin is open or in the GND connection condition). Document Number: 002-08407 Rev. *B Page 18 of 69 MB39C031 11. Turning On and Off Sequence (Turning On CTL*:CTL1, CTL2, CTLMAIN=VCC Simultaneously) 2.0V 2.2V VCC VCCI2C 0V CTL* uvlo_vcc (IC internal signal) 2.4V VREF 90% VR 0.6V osc (IC internal signal) ctl* (IC internal signal) 85% Discharge 85% Discharge DD1 PG1 DD2 PG2 UVLO release to DD*activation Time till start * Typ:200S Max:300S Soft-start time *: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance. Time in the sequence figure above is applied for the following condition. VREF pin capacitance : 0.1 F VR pin capacitance : 0.47 F Document Number: 002-08407 Rev. *B Page 19 of 69 MB39C031 12. CTL* Turning On and Off Sequence 1 (VCC CTL*: CTL1, CTL2, CTLMAIN) VCC 3.6V VCCI2C 0V CTL* uvlo_vcc (IC internal signal) 2.4V VREF VR osc (IC internal signal) 90% 0.6V ctl* (IC internal signal) 85% Discharge 85% Discharge DD1 PG1 DD2 PG2 Turning on CTL * to DD* activation Time till start * Typ:270S Max:450S Soft-start time *: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance. Time in the sequence figure above is applied for the following condition. VREF pin capacitance : 0.1 F VR pin capacitance : 0.47 F Document Number: 002-08407 Rev. *B Page 20 of 69 MB39C031 13. CTL* Turning On and Off Sequence 2(VCCCTLMAINCTL1CTL2) VCC 3.6V VCCI2C 0V CTLMAIN uvlo_vcc (IC internal signal) VREF 2.4V (1) CTL1 90% VR 0.6V osc (IC internal signal) ctl1 (IC internal signal) (2) Discharge 85% DD1 PG1 Soft-start time CTL2 ctl2 (IC internal signal) 85% DD2 Discharge PG2 Soft-start time (1) Time from turning on CTLMAIN to VREF activation completion (=communication enabled)* Typ: 130 s, Max: 200 s (2) Time from turning on CTL1 to ctll (IC internal signal) "H" Typ: 150 s, Max: 250 s *: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance. Time in the sequence figure above is applied for the following condition. VREF pin capacitance : 0.1 F VR pin capacitance : 0.47 F Document Number: 002-08407 Rev. *B Page 21 of 69 MB39C031 14. CTL* Pin Threshold Voltage The input circuit structure for the CTL* pin is the schmitt trigger style, and the threshold voltage shows the hysteresis characteristics when CTL* OFF ON and ON OFF. (See "*CTL* pin equivalent circuit diagram" below.) Also, the threshold voltage level depends on the VCC pin voltage. Moreover, make sure to input either the "H" level (>"VCCx0.7"V) or "L" level (<0.4 V) to the CTL* pin when in use. CTL* pin equivalent circuit diagram Document Number: 002-08407 Rev. *B Page 22 of 69 MB39C031 15. Protection Operation Sequence DD channel The DD channel monitors the FET current peak value at any time during the operation. When the DD output becomes the over current state, the output voltage is decreased. Afterward, the timer operation is performed and the output stops after about 1ms progress. LDO channel It contains the fold-back type over current protection circuit in order to prevent destroy because of the over load and the output over current. It limits the output current and the output voltage from the peak around the over current protection value for LDO (ILIMIT) to the over current current (Is). At this time, if the output voltage Vo gets lower than the detection voltage Vd (Vd: Vox0.5), the timer operation starts and the output stops after about 1ms progress. Moreover, because the over current protection circuit does not operate at the soft-start (0V to Vo x 0.7), neither the output stops nor the error signal outputs. However, the fold-back type over current protection characteristic functions. The following shows the fold-back type over current protection characteristic. Thermal shutdown protection If the temperature at the junction part reaches +150 C, the thermal shutdown protection circuit turns all channels off. Document Number: 002-08407 Rev. *B Page 23 of 69 MB39C031 Error detection sequence DD1, DD2, LDO The whoIe IC Normal operation Normal operation Over current detection Thermal shutdown protection Voltage drop No 1ms Continue for 1ms? Yes ERR detection mode ERROR signal output (ERR pin) ERR detection mode release It is necessary to turn the power supply on again, or to turn CTLMAIN on again to release the ERR detection mode. Document Number: 002-08407 Rev. *B Page 24 of 69 MB39C031 16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit Channel DD1, DD2 Operation whilst under protection Discharge Over voltage protection (OCP) Under voltage lockout protection (UVLO) Operating condition: Operating condition: After about 1ms progress in the over current condition Process during protection operation: DD1, DD2, LDO stop Recovery condition: (1) Power supply reasserted (2) CTLMAIN reasserted Operating condition: Input voltage drop UVLO operates only when CTLMAIN is "H" (normal operation). LDO Discharge Operating condition: After about 1ms progress in the over current condition Process during protection operation: DD1, DD2, LDO stop Recovery condition: (1) Power supply re-asserted (2) CTLMAIN reasserted ERR output (ERRpin) - "L" output when detecting OCP at CH of DD1, DD2, or LDO Thermal shutdown protection (TSD) Chip temperature increment Process during protection operation: DD1, DD2, LDO stop Recovery condition: Input voltage rise No change Process during protection operation: DD1, DD2, LDO stop Recovery condition: (1) Power supply reasserted (2) CTLMAIN reasserted Only when CTLMAIN is in the "H" state and one of CTL1, CTL2 or L is in the "H" state, TSD will operate. "L" output when detecting TSD Thermal shutdown protection (TSD) operation during over current protection timer operation When the thermal shutdown protection (TSD) operated during the over current protection (OCP) timer operation, the thermal shutdown protection has priority. Operation when releasing under voltage lockout protection (UVLO) DD1, DD2 and LDO: Activation following the condition for CTL* pin Document Number: 002-08407 Rev. *B Page 25 of 69 MB39C031 17. DD Soft-Start Operation The soft-start operation for DD1, DD2 and LDO is enabled in order to prevent the rush current during the DD activation. The 2 soft-start time can be controlled by I C. Soft-start control: enabled to set at DD1, DD2 and LDO DD, LDO soft-start Document Number: 002-08407 Rev. *B Page 26 of 69 MB39C031 18. Discharge Operation DD channel When executing the DD OFF operation at the CH ON/OFF signal, the DC/DC smooth capacitance charged for each output voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the discharge time changes depending on the DC/DC converter load current. The discharge time is calculated by the following equation. Discharge time (time till the output becomes 10% without load) toff(s) 2.3 x RDIS x Cout(F) Note: See the table in ELECTRICAL CHARACTERISTICS for the discharge resistor value. INx A R1 Resistor for discharge R2 PVCCX A Error Amp LXx Cout 0.6V PGNDx CH ON/OFF Cont. LDO channel When executing the LD OFF operation at the CH ON/OFF signal, the output capacitance charged for the output voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the discharge time changes depending on the output load current. The discharge time is calculated by the following equation. Discharge time (time till the output becomes 10 % without load). toff(s) 2.3 x RDISx Cout(F) Note: See the table in ELECTRICAL CHARACTERISTICS for the discharge resistor value. Document Number: 002-08407 Rev. *B Page 27 of 69 MB39C031 PVCCL 0.6V + LDO Resistor for discharge Cout CH ON/OFF Cont. Document Number: 002-08407 Rev. *B Page 28 of 69 MB39C031 19. PG1/PG2/PGL PIN and ERR PIN The following pins for each CH POWER GOOD output are prepared. PG1 It is the pin for DD1 POWER GOOD output. When the output voltage exceeds 85 % of the setting value at the DD1 ON mode, "H" is output. Also, when the output voltage becomes equal to or lower than 75 % of the setting value after the "H" output, "L" is output. "L" is output at the DD1 OFF mode. PG2 It is the pin for DD2 POWER GOOD output. When the output voltage exceeds 85% of the setting value at the DD2 ON mode, "H" is output. Also, when the output voltage becomes equal to or lower than 75% of the setting value after the "H" output, "L" is output. "L" is output at the DD2 OFF mode. PGL It is the pin for LDO POWER GOOD output. When the output voltage exceeds 85 % of the setting value at the LDO ON mode, "H" is output. Also, when the output voltage becomes equal to or lower than 75 % of the setting value after the "H" output, "L" is output. "L" is output at the LDO OFF mode. The following pin for the error state output is prepared. ERR pin It is the pin for the error state output. "L" is output during the error detection mode. The ERR detection mode is released by turning on the power supply or CTLMAIN again. Document Number: 002-08407 Rev. *B Page 29 of 69 MB39C031 I2C Interface 20. 2 1. Structure of I C interface 2 The I C interface executes the data communication in 1 byte (8-bit) units using two signal lines (bus), a SCL (serial clock line) and a SDA (serial data line). This bus is connected to multiple devices; master: device to generate the clock signal and to control the data transfer (CPU and so on) slave: device that an address is specified by a master. This IC is set as the slave and has no function to be the master. Each device is defined due to the communication direction as described below. transmitter: device to send data to bus receiver: device to receive data from bus The IC has the function both transmitter and receiver. SCL SDA transmitter receiver master receiver slave1 transmitter slave2 The IC defines the followings; Write : data is transmitted from master and the IC receives data Read : The IC transmits data and master receives data. 2. Definition of signal lines SCL and SDA are connected to the power supply by the pull-up resistor. The output circuit is the open Drain output. When a bus is not used (waiting state), the open "H" is set changing the open Drain to the OFF state. 2 Note: SCL and SDA pins adopt a different ESD protection system from standard I C specification because of ESD enhancement (see 2.3 I/O CIRCUIT TYPE). When the power supply is in the bus line, don't shut off the power supply for an IC (VCCI2C). Document Number: 002-08407 Rev. *B Page 30 of 69 MB39C031 3. Validity of data Data has the following characteristics; change when SCL is the "L" level valid if the state is kept while SCL is the "H" level. Moreover, the SDA signal change means the start or stop condition when SCL is the "H" level. 4. Definition of start and stop condition The start and stop conditions are output from the master and shows start and stop of communications to the slave. Start : SDA changes from "H" to "L" when SCL is "H". Stop : SDA changes from "L" to "H" when SCL is "H". 5. ACK signal This is a signal to confirm the data reception during communication. The receiver replies the ACK signal to show the data reception to a transmitter every time 1 byte (8-bit) of data is received. The ACK signal is sent in 9clk after sending data 8-bit matching to the SCL signal that the master generates. A transmitter keeps SDA output "open H" in SCL9clk. A receiver informs the data reception situation to a transmitter outputting the followings in SCL 9 clk ; when data was received : SDA output "L" (ACK) when no data was received : SDA output "open H" (NACK) However, if the master is changed to the receiver, ACK is not replied after the last data reception because the bus keeps open stopping the data transmission to the slave transmitter. In this case, the slave transmitter opens the bus (open H) and is set to the stop condition reception waiting state from the master. Document Number: 002-08407 Rev. *B Page 31 of 69 MB39C031 2 6. I C Interface Input Timing (within recommended operating conditions) Value Parameter Symbol SCL=100kHz SCL=400kHz Unit Min Max Min Max SCL clock frequency fSCL - 100 - 400 kHz Start condition hold time tHD:start 4.0 - 0.6 - s Restart condition setup time tSU:start 4.7 - 0.6 - s Stop condition setup time tSU:stop 4.0 - 0.6 - s Stop to Start bus open time tbuf 4.7 - 1.3 - s SCL "L" time tLow 4.7 - 1.3 - s SCL "H" time tHigh 4.0 - 0.6 - s SCL/SDA rising time tr - 1.0 - 0.3 s SCL/SDA falling time tf - 0.3 - 0.3 s Data hold time tHD:data 0.0 - 0.0 - s Data setup time tSU: data 0.25 - 0.10 - s SCL/SDA capacitor load Cb - 400 - 400 pF VIH/VIL level reference 2 Conform to I C bus specifications Document Number: 002-08407 Rev. *B Page 32 of 69 MB39C031 7. Slave Address 2 This is a slave address when communicating with the I C interface. The slave address of this IC is set by the first seven bits as shown below. The seventh bit follows the ADDSEL pin and "0"/"1" are variable. The eighth bit is called the least significant bit (LSB) and determines the message direction. The bit "0" shows that information will be written from the master to the slave. The bit "1" shows that the master reads information from the slave. This does not support the general call address. When the ADDSEL pin is in "H" slave address S T A R T 0 1 0 1 1 1 1 MSB R/W LSB S T O P When the ADDSEL pin is in "L" slave address S T A R T 0 MSB Document Number: 002-08407 Rev. *B 1 0 1 1 1 0 R/W LSB S T O P Page 33 of 69 MB39C031 2 8. Bit structure of data on I C interface (1) Writing data to register and reading data The data line is sent/received in the order from the most significant bit (MSB) to the least significant bit (LSB). *When the ADDSEL pin is in "H" Register DATA address 00H 01H 02H 10H 11H .. .. D07 D06 D05 D04 D03 D02 D01 D00 a b c d e f g h Output the "stop" condition after sending the Write data. 2 (2) I C Interface Data Format 2 I C communication 1. When a different slave address comes, non-matching ID is informed by not replying ACK after receiving the slave address. 2. All registers write to internal registers in the ACK signal after receiving the 8-bit data of each setting. 3. If a non-existing register address is specified, data is not written to a register. 4. Output the "stop" condition after sending the write data. < During write (W)> Document Number: 002-08407 Rev. *B Page 34 of 69 MB39C031 Write is allowed per one address. (sequential writing is not allowed.) Send register address and data as one unit. < During read (R) > Read is allowed per one address. Be sure to perform read by specifying the register addresses. (sequential reading is not allowed.) Document Number: 002-08407 Rev. *B Page 35 of 69 MB39C031 21. Structure of I2C Interface and Data Register map address DATA d07 d06 d05 d04 d03 d02 d01 d00 Writing timing Remarks ACK DD1 output voltage setting ACK DD2 output voltage setting 03H ACK LDO output voltage setting Default 00H* 00H X X X X D03 D02 D01 D00 05H* 0AH* 0FH* Output voltage 00H* 03H* 01H X X X X D03 D02 D01 D00 02H X X X X X X D01 D00 10H X X X X D03 D02 D01 D00 01H ACK DD1 soft-start time setting ACK DD2 soft-start time setting ACK LDO soft-start time setting ACK DD1, DD2 operation mode setting "0": Fixed PWM mode, 06H* 0CH* Soft start 11H X X X X D03 D02 D01 D00 01H*/ 03H* 12H X X X X D03 D02 D01 D00 03H DD operation mode 20H ON/OFF 30H X X X X X D02 D01 D00 00H ACK For test FXH - - - - - - - - - - X X X X X X D01 D00 00H "1": PFM/PWM mode DD1, DD2, LDO output ON/OFF setting "0":Output OFF/ "1":Output ON Disabled *: The value depends on the preset value. Because the "X" block in the register map has no register, "0" is returned when in reading. The address FXH is used for tests. It is normally disabled. Don't read/write to the FXH address. Document Number: 002-08407 Rev. *B Page 36 of 69 MB39C031 (1) DD1 and DD2 output voltage control 1. Addresses 00H, 01H are allocated as registers for the DC/DC output voltage control. 2. The DC/DC output voltage control is controlled by writing data to addresses 00H, 01H. DATA S T A R T 0 0 0 0 D03 D02 D01 MSB D00 A C K LSB S T O P address 00H : For DD1 output voltage setting address 01H : For DD2 output voltage setting D03 to D00: Set the output voltage DD1 output voltage setting table DD2 output voltage setting table DATA Output voltage DATA Output voltage 00H 1.00* 00H 1.20* 01H 1.02 01H 1.25 02H 1.04 02H 1.30 03H 1.06 03H 1.35* 04H 1.08 04H 1.40 05H 1.10* 05H 1.45 06H 1.12 06H 1.50* 07H 1.14 07H 1.55 08H 1.16 08H 1.60 09H 1.18 09H 1.65 0AH* 1.20* 0AH 1.70 0BH 1.22 0BH 1.75 0CH 1.24 0CH* 1.80* 0DH 1.26 0DH 1.85 0EH 1.28 0EH 1.90 0FH 1.95 0FH 1.30* [V] [V] *: The selectable output voltage setting as preset value. Document Number: 002-08407 Rev. *B Page 37 of 69 MB39C031 (2) LDO output voltage control 1. Address 02H is allocated as a register for the LDO output voltage control. 2. The LDO output voltage control is controlled by writing data to addresse 02H. DATA S T A R T 0 0 0 0 0 0 D01 D00 MSB LSB A C K S T O P address 02H: For LDO output voltage setting D01 to D00: Set the output voltage LDO output voltage setting table DATA Output voltage 00H 2.80 01H 2.85* 02H 3.00 03H* 3.30* [V] *: The selectable output voltage using the preset value changing products Document Number: 002-08407 Rev. *B Page 38 of 69 MB39C031 (3) Soft start time 1. Address 10H to 12H are allocated as registers for the soft start time control. 2. The soft start time control is controlled by writing data to addresses 10H to 12H. DATA S T A R T 0 0 0 0 D03 D02 D01 D00 MSB LSB A C K S T O P address10H: For DD1 soft start time setting address11H: For DD2 soft start time setting address12H: For LDO soft start time setting D03 to D00: Set the soft start time Soft start time setting table DATA1 Soft start time 00H 14.3ms 01H 0.9ms 02H 1.8ms 03H 2.7ms 04H 3.6ms 05H 4.5ms 06H 5.4ms 07H 6.3ms 08H 7.2ms 09H 8.1ms 0AH 9.0ms 0BH 9.9ms 0CH 10.8ms 0DH 11.6ms 0EH 12.5ms 0FH 13.4ms Document Number: 002-08407 Rev. *B Default setting DD1, DD2 LDO Page 39 of 69 MB39C031 (4) DC/DC operation mode 1. Address 20H is allocated as a register for the DC/DC operation mode control. 2. The DC/DC operation mode is controlled by writing data to address 20H. DATA S T A R T 0 0 0 0 0 MSB 0 D01 A C K D00 LSB S T O P address20H: For DC/DC operation mode setting D01 to D00: Set the DC/DC operation mode address Bit Value 20H D00 0* DD1 Fixed PWM* 1 DD1 PFM/PWM 20H D01 0* DD2 Fixed PWM* 1 DD2 PFM/PWM Description Value Description *: It is a preset value. (5) ON/OFF for DC/DC and LDO 1. Address 30H is allocated as a register for the DC/DC and LDO ON/OFF. 2. The DC/DC and LDO ON/OFF is controlled by writing data to address 30 H. DATA S T A R T 0 0 0 0 0 MSB D02 D01 D00 LSB A C K S T O P address30H: For DC/DC and LDO ON/OFF D02 to D00: Set ON/OFF for DC/DC and LDO address Bit Value 30H D00 0* DD1 output OFF* 1 DD1 output ON 30H D01 0* DD2 output OFF* 1 DD2 output ON 30H D02 0* LDO output OFF* 1 LDO output ON Description Value Description *: It is a preset value. Document Number: 002-08407 Rev. *B Page 40 of 69 MB39C031 22. I/O Pin Equivalent Circuit Diagram Document Number: 002-08407 Rev. *B Page 41 of 69 MB39C031 23. I/O Circuit Type CTLMAIN/CTL1/CTL2/CTLL/ADDSEL pins VCC CTL* ADDSEL GND SCL pin VCCI2C SCL GND SDA pin VCCI2C SDA GND PG1/PG2/PGL/ERR pins VCC PG*/ERR GND Document Number: 002-08407 Rev. *B Page 42 of 69 MB39C031 24. Typical Operation Characteristic Measurement Circuit Document Number: 002-08407 Rev. *B Page 43 of 69 MB39C031 Part list Symbol Parts (Circuit diagram notation) Part number Specifications Vendor L1 Metal alloy inductor 1299AS-H-1R5N 1.5H TOKO L2 Metal alloy inductor 1299AS-H-1R5N 1.5H TOKO C1 Ceramic Capacitor C1608X5R1H104K 0.1F TDK C2 Ceramic Capacitor C1608X5R1H104K 0.1F TDK C3 Ceramic Capacitor C1608X5R1V475K 4.7F TDK C4 Ceramic Capacitor C1608X5R1V475K 4.7F TDK C5 Ceramic Capacitor C1608X5R1V475K 4.7F TDK C6 Ceramic Capacitor C1608X5R1H104K 0.1F TDK C7 Ceramic Capacitor C1608X5R1H474K 0.47F TDK C8 Ceramic Capacitor C1608X5R1V475K 4.7F TDK C9 Ceramic Capacitor C1608X5R1A106K 10F TDK C10 Ceramic Capacitor C1608X5R1A106K 10F TDK R1 Resistor RR0816P-104-D 100k SSM R2 Resistor RR0816P-104-D 100k SSM R3 Resistor RR0816P-104-D 100k SSM R4 Resistor RR0816P-104-D 100k SSM TOKO : TOKO, INC. TDK : TDK Corporation SSM : SUSUMU CO., LTD. Note: The list above is recommended parts. Document Number: 002-08407 Rev. *B Page 44 of 69 MB39C031 25. Reference Data DC/DC Load efficiency characteristics Vo=1.3V (Max) Load efficiency 100 90 80 70 60 50 40 30 20 10 0 0.001 100 90 80 70 60 50 40 30 20 10 0 0.001 100 90 80 70 60 50 40 30 20 10 0 0.001 PFMPWM 0.01 0.1 1 10 0.1 1 10 PFMPWM 0.01 0.1 1 10 Load efficiency Load efficiency Load efficiency Fixed PWM PFMPWM 0.01 0.1 1 10 100 90 80 70 60 50 40 30 20 10 0 0.001 0.1 1 Document Number: 002-08407 Rev. *B PFMPWM 0.01 0.1 1 10 10 100 90 80 70 60 50 40 30 20 10 0 0.001 PFMPWM 0.01 0.1 1 PFMPWM 0.01 0.1 1 10 Load efficiency Fixed PWM Load current [A] Fixed PWM Load current [A] Load efficiency PFMPWM 0.01 Fixed PWM 100 90 80 70 60 50 40 30 20 10 0 0.001 Load current [A] Fixed PWM Load current [A] Efficiency[%] Load current [A] Efficiency[%] Efficiency[%] 0.01 Fixed PWM Load current [A] Load efficiency Vin=5.5V PFMPWM Load current [A] Load current [A] 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM Efficiency[%] 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM Efficiency[%] Vo=1.2V Load efficiency Efficiency[%] Vo=1.0V (Min) Load efficiency Efficiency[%] Efficiency[%] Efficiency[%] Vin=3.6V Vin=2.5V * DD1 10 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM PFMPWM 0.01 0.1 1 10 Load current [A] Page 45 of 69 MB39C031 * DD2 Vo=1.2V (Min) Vo=1.8V 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 Efficiency[%] Efficiency[%] PFMPWM 100 90 80 70 60 50 40 30 20 10 0 0.001 Load efficiency Fixed PWM PFMPWM 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM PFMPWM 0.01 0.1 1 Load current [A] Load current [A] Load efficiency Load efficiency Load efficiency Fixed PWM PFMPWM 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Efficiency[%] Load current [A] Fixed PWM PFMPWM 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM PFMPWM 0.01 0.1 1 Load current [A] Load current [A] Load current [A] Load efficiency Load efficiency Load efficiency Fixed PWM PFMPWM 0.01 0.1 Load current [A] Document Number: 002-08407 Rev. *B 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Efficiency[%] 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM Efficiency[%] 100 90 80 70 60 50 40 30 20 10 0 0.001 Load efficiency Efficiency[%] Efficiency[%] Efficiency[%] Efficiency[%] Vin=5.5V Vin=3.6V Vin=2.5V Load efficiency Vo=1.95V (Max) Fixed PWM PFMPWM 0.01 0.1 Load current [A] 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM PFMPWM 0.01 0.1 1 Load current [A] Page 46 of 69 MB39C031 DC/DC line efficiency characteristics Vo=1.2V Line efficiency characteristics (Io=400mA) Vo=1.3V (Max) Line efficiency characteristics (Io=400mA) 100 100 100 95 95 95 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 2.5 3.0 3.5 4.0 4.5 5.0 Efficiency[%] Vo=1.0V (Min) Line efficiency characteristics (Io=400mA) Efficiency[%] Efficiency[%] * DD1 90 85 80 75 Fixed PWM 70 PFMPWM 65 85 80 75 Fixed PWM 70 PFMPWM 65 60 60 5.5 90 2.5 Input voltage Vin[V] 3.0 3.5 4.0 4.5 5.0 2.5 5.5 Input voltage Vin[V] 3.0 3.5 4.0 4.5 5.0 5.5 Input voltage Vin[V] * DD2 Vo=1.2V (Min) Vo=1.8V Line efficiency characteristics (Io=400mA) Line efficiency characteristics (Io=400mA) 100 100 95 95 95 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input voltage Vin[V] Document Number: 002-08407 Rev. *B Efficiency[%] 100 Efficiency[%] Efficiency[%] Line efficiency characteristics (Io=400mA) Vo=1.95V (Max) 90 85 80 75 Fixed PWM 70 PFMPWM 65 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 60 2.5 3.0 3.5 4.0 4.5 5.0 Input voltage Vin[V] 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input voltage Vin[V] Page 47 of 69 MB39C031 DC/DC line regulation characteristics * DD1 Vo=1.0V (Min) Vo=1.2V Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 Input voltage Vin[V] 1.220 1.215 1.210 1.205 1.200 1.195 1.190 1.185 1.180 2.50 Line regulation (Io=400mA) Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 Output voltage Vout[V] 1.020 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 2.50 Line regulation (Io=400mA) Output voltage Vout[V] Output voltage Vout[V] Line regulation (Io=400mA) Vo=1.3V (Max) 1.320 1.315 1.310 1.305 1.300 1.295 1.290 1.285 1.280 2.50 Input voltage Vin[V] Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 Input voltage Vin[V] * DD2 Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 Input voltage Vin[V] Document Number: 002-08407 Rev. *B 1.820 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 2.50 Vo=1.95V (Max) Line regulation (Io=400mA) Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 Input voltage Vin[V] 5.50 Output voltage Vout[V] 1.220 1.215 1.210 1.205 1.200 1.195 1.190 1.185 1.180 2.50 Vo=1.8V Line regulation (Io=400mA) Output voltage Vout[V] Output voltage Vout[V] Vo=1.2V (Min) Line regulation (Io=400mA) 1.970 1.965 1.960 1.955 1.950 1.945 1.940 1.935 1.930 2.50 Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 Input voltage Vin[V] Page 48 of 69 MB39C031 LDO line regulation characteristics * LDO Vo=2.8V (Min) Vo=3.3V (Max) Line regulation (Io=50mA) 2.860 2.840 2.820 2.800 2.780 2.760 2.740 3 3.5 4 4.5 Input voltage Vin[V] Document Number: 002-08407 Rev. *B 5 5.5 Output voltage Vout[V] Output voltage Vout[V] Line regulation (Io=50mA) 3.360 3.340 3.320 3.300 3.280 3.260 3.240 3 3.5 4 4.5 5 5.5 Input voltage Vin[V] Page 49 of 69 MB39C031 DC/DC load regulation characteristics * DD1 1.015 Fixed PWM 1.010 PFMPWM 1.005 1.000 0.995 0.990 0.985 0.980 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Fixed PWM 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 1.180 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.320 1.315 Fixed PWM 1.310 PFMPWM 1.305 1.300 1.295 1.290 1.285 1.280 0 0.2 0.4 0.6 0.8 1 1.2 Load regulation Load regulation Load regulation Fixed PWM 1.010 PFMPWM 1.005 1.000 0.995 0.990 0.985 0.980 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.220 1.215 Fixed PWM 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 1.180 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Output voltage [V] Load current [A] 1.015 1.315 Fixed PWM 1.310 PFMPWM PFMPWM 1.005 1.000 0.995 0.990 0.985 0.980 0.2 0.4 0.6 0.8 1 1.2 1.4 Load current [A] Document Number: 002-08407 Rev. *B 1.6 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 1.180 0 0.2 0.4 0.6 0.8 1 1.2 Load current [A] 1.4 1.6 Output voltage [V] 1.010 1.6 1.285 1.280 0 0.2 0.4 0.6 0.8 1 1.2 Load regulation Fixed PWM 1.4 1.290 Load regulation 1.215 1.6 1.295 Load regulation 1.220 1.4 1.300 Load current [A] Fixed PWM 1.6 1.305 Load current [A] 1.015 1.4 1.320 Load current [A] 1.020 0 1.215 Load current [A] 1.020 0 1.220 Load current [A] Output voltage [V] 0 Vo=1.3V (Max) Load regulation Output voltage [V] 1.020 Output voltage [V] Vo=1.2V Load regulation Output voltage [V] Output voltage [V] Output voltage [V] Output voltage [V] Vin=5.5V Vin=3.6V Vin=2.5V Vo=1.0V (Min) Load regulation 1.320 1.315 Fixed PWM 1.310 PFMPWM 1.305 1.300 1.295 1.290 1.285 1.280 0 0.2 0.4 0.6 0.8 1 1.2 Load current [A] Page 50 of 69 MB39C031 * DD2 Vo=1.2V (Min) Vo=1.8V 1.215 Fixed PWM 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 1.180 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Fixed PWM 1.810 PFMPWM 1.805 1.800 1.795 1.790 1.785 1.780 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.970 1.965 Fixed PWM 1.960 PFMPWM 1.955 1.950 1.945 1.940 1.935 1.930 0 0.1 0.2 0.3 0.4 0.5 Load regulation Load regulation Load regulation Fixed PWM 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 1.180 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.820 1.815 Fixed PWM 1.810 PFMPWM 1.805 1.800 1.795 1.790 1.785 1.780 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Output voltage [V] Load current [A] 1.215 1.965 Fixed PWM 1.960 PFMPWM PFMPWM 1.205 1.200 1.195 1.190 1.185 1.180 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Load current [A] Document Number: 002-08407 Rev. *B 1.810 PFMPWM 1.805 1.800 1.795 1.790 1.785 1.780 0 0.1 0.2 0.3 0.4 0.5 Load current [A] 0.6 0.7 Output voltage [V] 1.210 0.7 1.935 1.930 0 0.1 0.2 0.3 0.4 0.5 Load regulation Fixed PWM 0.6 1.940 Load regulation 1.815 0.7 1.945 Load regulation 1.820 0.6 1.950 Load current [A] Fixed PWM 0.7 1.955 Load current [A] 1.215 0.6 1.970 Load current [A] 1.220 0 1.815 Load current [A] 1.220 0 1.820 Load current [A] Output voltage [V] 0 Load regulation Output voltage [V] 1.220 Output voltage [V] Load regulation Output voltage [V] Output voltage [V] Output voltage [V] Output voltage [V] Vin=5.5V Vin=3.6V Vin=2.5V Load regulation Vo=1.95V (Max) 1.970 1.965 Fixed PWM 1.960 PFMPWM 1.955 1.950 1.945 1.940 1.935 1.930 0 0.1 0.2 0.3 0.4 0.5 Load current [A] Page 51 of 69 MB39C031 LDO load regulation characteristics * LDO 2.850 2.840 Vin=3.5V 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.760 2.750 0.05 0.1 0.15 0.2 0.25 3.320 3.300 3.280 3.260 3.240 0 0.05 0.1 0.15 0.2 Load regulation Vin=3.6V 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.760 2.750 0.05 0.1 0.15 0.2 0.25 Output voltage [V] Load regulation 2.840 3.340 3.320 3.300 3.280 3.260 3.240 0 0.05 0.1 0.15 0.2 Load current [A] Load regulation Load regulation 2.840 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.760 2.750 0.05 0.1 0.15 0.2 Load current [A] Document Number: 002-08407 Rev. *B 0.25 0.25 3.360 Load current [A] 2.850 0 3.340 Load current [A] 2.850 0 3.360 Load current [A] Output voltage [V] 0 Output voltage [V] Vo=3.3V (Max) Load regulation Vin=5.5V Output voltage [V] Output voltage [V] Output voltage [V] Vin=5.5V Vin=3.6V Vin=3.0V Vo=2.8V (Min) Load regulation 0.25 3.360 3.340 3.320 3.300 3.280 3.260 3.240 0 0.05 0.1 0.15 0.2 0.25 Load current [A] Page 52 of 69 MB39C031 DC/DC output ripple waveform * DD1 (Fixed PWM mode) Io=400mA Output voltage =1.2V setting Io=1400mA VIN=5.5V VIN=3.6V VIN=2.5V Io=0mA Document Number: 002-08407 Rev. *B Page 53 of 69 MB39C031 * DD1 (PFM/PWM mode) Io=400mA Output voltage =1.2V setting Io=1400mA VIN=5.5V VIN=3.6V VIN=2.5V Io=0mA Document Number: 002-08407 Rev. *B Page 54 of 69 MB39C031 * DD2 (Fixed PWM mode) Io=400mA Output voltage =1.8V setting Io=600mA VIN=5.5V VIN=3.6V VIN=2.5V Io=0mA Document Number: 002-08407 Rev. *B Page 55 of 69 MB39C031 * DD2 (PFM/PWM mode) Io=400mA Output voltage =1.8V setting Io=600mA VIN=5.5V VIN=3.6V VIN=2.5V Io=0mA Document Number: 002-08407 Rev. *B Page 56 of 69 MB39C031 DD1 startup/shutdown waveform Output voltage =1.2V setting Soft-start setting=0.9ms Fixed PWM mode Control using the external pin (CTL1) VCC = 2.5V Io=1400mA Io=0mA VCC = 3.6V Io=1400mA Io=0mA VCC = 5.5V Io=1400mA Io=0mA Document Number: 002-08407 Rev. *B Page 57 of 69 MB39C031 DD2 startup/shutdown waveform Output voltage =1.8V setting Soft-start setting=0.9ms Fixed PWM mode Control using the external pin (CTL2) VCC = 2.5V Io=600mA Io=0mA VCC = 3.6V Io=600mA Io=0mA VCC = 5.5V Io=600mA Io=0mA Document Number: 002-08407 Rev. *B Page 58 of 69 MB39C031 LDO startup/shutdown waveform Output voltage =3.3V setting Soft-start setting=2.7ms Control using the external pin (CTLL) VCC = 3.6V Io=250mA Io=0mA VCC = 5.5V Io=250mA Io=0mA Document Number: 002-08407 Rev. *B Page 59 of 69 MB39C031 DC/DC Sudden load change characteristics * DD1(Fixed PWM mode) 0mA1400mA/10s VCC=5.5V VCC=3.6V VCC=2.5V Output voltage =1.2V setting Document Number: 002-08407 Rev. *B Page 60 of 69 MB39C031 * DD2 (Fixed PWM mode) 0mA600mA/10s VCC=5.5V VCC=3.6V VCC=2.5V Output voltage =1.8V setting Document Number: 002-08407 Rev. *B Page 61 of 69 MB39C031 * DD1 (PFM/PWM mode) 0mA1400mA/10s VCC=5.5V VCC=3.6V VCC=2.5V Output voltage =1.2V setting Document Number: 002-08407 Rev. *B Page 62 of 69 MB39C031 * DD2 (PFM/PWM mode) 0mA600mA/10s VCC=5.5V VCC=3.6V VCC=2.5V Output voltage =1.8V setting Document Number: 002-08407 Rev. *B Page 63 of 69 MB39C031 LDO Sudden load change characteristics * LDO 0mA150mA/2s VCC=5.5V VCC=3.6V Output voltage = 3.3V setting Power dissipation Power dissipation vs. Operation ambient temperature Temperature [C] Document Number: 002-08407 Rev. *B Page 64 of 69 MB39C031 26. Usage Precaution 1. Do not configure the IC over the maximum ratings. If the lC is used over the maximum ratings, the LSl may be permanently damaged. It is preferable for the device to be normally operated within the recommended usage conditions. Usage outside of these conditions can have a bad effect on the reliability of the LSI. 2. Use the devices within recommended operating conditions. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 3. Printed circuit board ground lines should be set up with consideration for common impedance. 4. Take appropriate measures against static electricity. Containers for semiconductor materials should have anti-static protection or be made of conductive material. After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. Work platforms, tools, and instruments should be properly grounded. Working personnel should be grounded with resistance of 250 k to 1 M in series between body and ground. 5. Do not apply negative voltages. The use of negative voltages below -0.3 V may cause the parasitic transistor to be activated on LSI lines, which can cause malfunctions. 6. When all channels are operating, the reliability level is designed under the condition that the average ambient temperature Ta=+60C, the typical input voltage, the typical output voltage and the typical output current condition are used. Document Number: 002-08407 Rev. *B Page 65 of 69 MB39C031 27. Ordering Information Part number Package 28-pin plastic QFN MB39C31WQN 28. Remarks (WNO028) - Preset Code (MB39C031) Preset code DD1 output voltage preset code value DD2 output voltage preset code value LDO output voltage preset code value 111 112 121 122 131 132 141 142 211 212 221 222 231 232 241 242 311 312 321 322 331 332 341 342 411 412 421 422 431 432 441 442 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.10V 1.10V 1.10V 1.10V 1.10V 1.10V 1.10V 1.10V 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V 1.30V 1.30V 1.30V 1.30V 1.30V 1.30V 1.30V 1.30V 1.20V 1.20V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 1.20V 1.20V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 1.20V 1.20V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 1.20V 1.20V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V Document Number: 002-08407 Rev. *B Page 66 of 69 MB39C031 29. Package Dimensions Package Code: WNO028 002-15159 Rev. ** Document Number: 002-08407 Rev. *B Page 67 of 69 MB39C031 Document History 2 Document Title: MB39C031 2ch Buck DC/DC Converter + 1ch LDO with I C Interface and SW FET Document Number: 002-08407 Revision ECN Orig. of Change Submission Date ** TAOA 11/20/2013 *A 5132453 TAOA 03/08/2016 Updated to Cypress template Description of Change Migrated to Cypress and assigned document number 002-08407. No change to document contents or format. Updated Pin Assignment: Change the package name from LCC-28P-M70 to WNO028 Updated Ordering Information: Change the package name from LCC-28P-M70 to WNO028 *B 5734750 HIXT 05/18/2017 Deleted "EV Board Ordering Information" Deleted "Marking Format (Lead Free Version)" Deleted "Labeling Sample (Lead Free Version)" Deleted "MB39C031 Recommended Conditions Of Moisture Sensitivity Level" Updated Package Dimensions: Updated to Cypress format Document Number: 002-08407 Rev. *B Page 68 of 69 MB39C031 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-08407 Rev. *B May 18, 2017 Page 69 of 69