May 2010 Doc ID 13106 Rev 4 1/37
1
VN5E025AJ-E
Single channel high-side driver with analog current sense
for automotive applications
Features
■General
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
– Very low current sense leakage
■Diagnostic functions
– Proportional load current sense
– High current sense precision for wide
currents range
– Current sense disable
– Off state openload detection
– Output short to VCC detection
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
■Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Over-temperature shutdown with
autorestart (thermal shutdown)
– Reverse battery protected
– Electrostatic discharge protection
Application
■All types of resistive, inductive and capacitive
loads
■Suitable as LED driver
Description
The VN5E025AJ-E is a single channel high-side
driver manufactured in the ST proprietary
VIPower M0-5 technology and housed in the tiny
PowerSSO-12 package. The VN5E025AJ-E is
designed to drive 12 V automotive grounded
loads delivering protection, diagnostics and easy
3 V and 5 V CMOS compatible interface with any
microcontroller.
The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, over-temperature shut-off with auto-
restart and over-voltage active clamp. A dedicated
analog current sense pin is associated with every
output channel in order to provide Ehnanced
diagnostic functions including fast detection of
overload and short-circuit to ground through
power limitation indication, over-temperature
indication, short-circuit to VCC diagnosis and ON-
state and OFF-state open load detection.
The current sensing and diagnostic feedback of
the whole device can be disabled by pulling the
CS_DIS pin high to allow sharing of the external
sense resistor with other similar devices
Max supply voltage VCC 41 V
Operating voltage range VCC 4.5 to 28 V
Max On-State resistance RON 25 mΩ
Current limitation (typ) ILIMH 60 A
Off state supply current IS2µA
(1)
1. Typical value with all loads connected.
PowerSSO-12
www.st.com
Contents VN5E025AJ-E
2/37 Doc ID 13106 Rev 4
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolue maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 24
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 Short to VCC and OFF state open load detection . . . . . . . . . . . . . . . . . 27
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28
4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VN5E025AJ-E List of tables
Doc ID 13106 Rev 4 3/37
List of tables
Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching characteristics (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Current sense (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Openload detection (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of figures VN5E025AJ-E
4/37 Doc ID 13106 Rev 4
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Openload Off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Delay response time between rising edge of ouput current and rising edge of current
sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. IOUT / ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. OFF-State Open Load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. TJ evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. Input clamp level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 34. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 29
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 30
Figure 38. Thermal fitting model of a single channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 30
Figure 39. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 40. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VN5E025AJ-E Block diagram and pin description
Doc ID 13106 Rev 4 5/37
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin function
Name Function
VCC Battery connection.
OUTPUT Power output.
GND Ground connection. Must be reverse battery protected by an external diode /
resistor network.
INPUT Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state.
CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
VCC
Control & Diagnostic
LOGIC
DRIVER
VON
Limitation
Current
Limitation
Power
Clamp
OFF State
Open load
Over
temp.
Undervoltage
VSENSEH
Current
Sense
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
IN
CS
CS_
DIS
GND
OUT
Signal Clamp
Block diagram and pin description VN5E025AJ-E
6/37 Doc ID 13106 Rev 4
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Current sense N.C. Output Input CS_DIS
Floating Not allowed X X X X
To ground Through 1kΩ
resistor XThrough 22kΩ
resistor
Through 10kΩ
resistor
Through 10kΩ
resistor
TA B =
Vcc
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
12
11
10
9
8
7
1
2
3
4
5
6
Vcc
Vcc
INPUT
CURRENT_SENSE
GND
CS_DIS
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 7/37
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VF = VOUT - VCC during reverse battery condition.
2.1 Absolue maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
I
S
I
GND
V
CC
V
CC
V
SENSE
OUTPUT
I
OUT
CURRENT SENSE
I
SENSE
INPUT
I
IN
V
IN
V
OUT
GND
CS_DIS
I
CSD
V
CSD
V
F
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage 0.3 V
- IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current 20 A
IIN DC input current -1 to 10 mA
ICSD DC current sense disable input current -1 to 10 mA
-ICSENSE DC reverse CS pin current 200 mA
VCSENSE Current sense maximum voltage VCC-41
+VCC
V
V
EMAX
Maximum switching energy (single pulse)
(L=0.8mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )140 mJ
Electrical specifications VN5E025AJ-E
8/37 Doc ID 13106 Rev 4
2.2 Thermal data
VESD
Electrostatic discharge
(Human Body Model: R=1.5KΩ; C=100pF)
- INPUT
- CURRENT SENSE
- CS_DIS
- OUTPUT
- VCC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter Max. value Unit
Rthj-case Thermal resistance junction-case 1.4 °C/W
Rthj-amb Thermal resistance junction-ambient See Figure 36 °C/W
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 9/37
2.3 Electrical characteristics
Values specified in this section are for 8V<VCC<28V; -40°C<Tj<150°C, unless otherwise
stated.
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4.5 13 28 V
VUSD Undervoltage shutdown 3.5 4.5 V
VUSDhyst
Undervoltage shutdown
hysteresis 0.5 V
RON On state resistance
IOUT= 3A; Tj=25°C
IOUT= 3A; Tj=150°C
IOUT= 3A; VCC=5V; Tj=25°C
25
50
35
mΩ
mΩ
mΩ
Vclamp Clamp voltage IS= 20 mA 41 46 52 V
ISSupply current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V;
IOUT=0A
2(1)
1.5
1. PowerMOS leakage included.
5(1)
3
µA
mA
IL(off1) Off state output current VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
0
0
0.01 3
5µA
VF
Output - VCC diode
voltage -IOUT= 2A; Tj= 150°C 0.7 V
Table 6. Switching characteristics (VCC=13V, Tj=25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-On delay time RL= 4.3Ω (see Figure 6.)15 µs
td(off) Turn-Off delay time RL= 4.3Ω (see Figure 6.)40 µs
(dVOUT/dt)on Turn-On voltage slope RL= 4.3ΩSee
Figure 26 V/µs
(dVOUT/dt)off Turn-Off voltage slope RL= 4.3ΩSee
Figure 28 V/µs
WON
Switching energy losses
during twon RL= 4.3Ω (see Figure 6.)0.4 mJ
WOFF
Switching energy losses
during twoff RL= 4.3Ω (see Figure 6.)0.5 mJ
Electrical specifications VN5E025AJ-E
10/37 Doc ID 13106 Rev 4
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.9 V
IIL Low level input current VIN= 0.9V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN= 2.1V 10 µA
VI(hyst)
Input hysteresis
voltage 0.25 V
VICL Input clamp voltage IIN= 1mA
IIN= -1mA
5.5
-0.7
7V
V
VCSDL
CS_DIS low level
voltage 0.9 V
ICSDL
Low level CS_DIS
current VCSD= 0.9V 1 µA
VCSDH
CS_DIS high level
voltage 2.1 V
ICSDH
High level CS_DIS
current VCSD= 2.1V 10 µA
VCSD(hyst)
CS_DIS hysteresis
voltage 0.25 V
VCSCL CS_DIS clamp voltage ICSD=1mA
ICSD= -1mA
5.5
-0.7
7V
V
Table 8. Protection and diagnostics (1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device operates under
abnormal conditions this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
IlimH DC short circuit current VCC= 13V
5V<VCC<28V
43 60 85
85
A
A
IlimL
Short circuit current
during thermal cycling VCC= 13V; TR<Tj<TTSD 15 A
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature TRS + 1 TRS + 5 °C
TRS Thermal reset of status 135 °C
THYST
Thermal hysteresis
(TTSD-TR)7°C
VDEMAG
Turn-Off output voltage
clamp IOUT= 2A; VIN=0; L= 6mH VCC-41 VCC-46 VCC-52 V
VON
Output voltage drop
limitation
IOUT= 0.1A
Tj= -40°C...150°C
(see Figure 8)
25 mV
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 11/37
Table 9. Current sense (8V<VCC<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
KLED IOUT/ISENSE
IOUT= 0.05A, VSENSE=0.5V,
VCSD=0V
Tj= -40°C...150°C 1370 3180 4930
K0IOUT/ISENSE
IOUT= 0.5A; VSENSE=0.5V;
VCSD=0V;
Tj= -40°C...150°C 1990 3050 4120
K1IOUT/ISENSE
IOUT= 2A; VSENSE=4V; VCSD=0V;
Tj= -40°C...150°C
Tj= 25°C...150°C
2100
2220
2860
2860
3840
3500
dK
1
/K
1(1)
Current sense ratio
drift
IOUT=2A; VSENSE= 4V;
VCSD=0V;
TJ= -40 °C to 150 °C
-10 10 %
K2IOUT/ISENSE
IOUT= 3A; VSENSE=4V; VCSD=0V;
Tj= -40°C...150°C
Tj=25°C...150°C
2300
2420
2850
2850
3520
3300
dK
2
/K
2(1)
Current sense ratio
drift
IOUT=3 A; VSENSE= 4 V;
VCSD=0V;
TJ= -40 °C to 150 °C
-7 7 %
K3IOUT/ISENSE
IOUT= 10A; VSENSE=4V; VCSD=0V;
Tj= -40°C...150°C
Tj=25°C...150°C
2690
2700
2830
2830
3060
3020
dK
3
/K
3(1)
Current sense ratio
drift
IOUT= 10 A; VSENSE= 4 V;
VCSD=0V;
TJ= -40 °C to 150 °C
-4 4 %
ISENSE0
Analog sense
leakage current
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C
VCSD=0V; VIN=5V; Tj=-40°C...150°C
IOUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj=-40°C...150°C
0
0
0
1
2
1
µA
µA
µA
IOL
Open load ON state
current detection
threshold
VIN = 5V, 8V<VCC<18V
ISENSE= 5 µA 530mA
VSENSE
Max analog sense
output voltage IOUT= 3A; VCSD= 0V 5
V
VSENSEH(2)
Analog sense output
voltage in fault
condition
VCC= 13V; RSENSE= 3.9KΩ8
ISENSEH(2)
Analog sense output
current in fault
condition
VCC= 13V; VSENSE= 5V 9 mA
Electrical specifications VN5E025AJ-E
12/37 Doc ID 13106 Rev 4
tDSENSE1H
Delay response time
from falling edge of
CS_DIS pin
VSENSE<4V, 0.5<Iout<10A
ISENSE=90% of ISENSE max
(see Figure 4)
40 100
µs
tDSENSE1L
Delay response time
from rising edge of
CS_DIS pin
VSENSE<4V, 0.5<Iout<10A
ISENSE=10% of ISENSE max
(see Figure 4)
520
tDSENSE2H
Delay response time
from rising edge of
INPUT pin
VSENSE<4V, 0.5<Iout<10A
ISENSE=90% of ISENSE max
(see Figure 4)
80 300
Δ
t
DSENSE2H
Delay response time
between rising edge
of output current
and rising edge of
current sense
VSENSE <4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX= 3A (see Figure 7)
110
tDSENSE2L
Delay response time
from falling edge of
INPUT pin
VSENSE<4V, 0.5<Iout<10A
ISENSE=10% of ISENSE max
(see Figure 4)
80 250
1. Parameter guaranteed by design, it is not tested.
2. Fault condition includes: power limitation, overtemperature and open load OFF state detection.
Table 10. Openload detection (8V<VCC<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VOL
Openload Off state
voltage detection
threshold
VIN = 0V 2 4 V
tDSTKON
Output short circuit to
VCC detection delay at
turn off
See Figure 5. 180 1200 µs
IL(off2)r
Off state output current at
VOUT = 4V
VIN=0V; VSENSE=0V
VOUT rising from 0V to 4V -120 0 µA
IL(off2)f
Off state output current at
VOUT = 2V
VIN=0V; VSENSE=VSENSEH
VOUT falling from VCC to 2V -50 90 µA
td_vol
Delay response from
output rising edge to
VSENSE rising edge in
open load
VOUT= 4 V; VIN= 0V
VSENSE= 90% of VSENSEH
20 µs
Table 9. Current sense (8V<VCC<18V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 13/37
Figure 4. Current sense delay characteristics
Figure 5. Openload Off-state delay timing
Figure 6. Switching characteristics
SENSE CURRENT
INPUT
LOAD CURRENT
CS_DIS
t
DSENSE2H
t
DSENSE2L
t
DSENSE1L
t
DSENSE1H
VIN
VCS
tDSTKON
OUTPUT STUCK TO VCC
VOUT > VOL
VSENSEH
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10% t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff
Electrical specifications VN5E025AJ-E
14/37 Doc ID 13106 Rev 4
Figure 7. Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
Figure 8. Output voltage drop limitation
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90% I
OUTMAX
Δ
t
DSENSE2H
t
t
t
V
on
I
out
V
cc
-V
out
T
j
=150
o
C
T
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T)
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 15/37
Figure 9. IOUT / ISENSE vs IOUT
Figure 10. Maximum current sense ratio drift vs load current
Note: Parameter guaranteed by design; it is not tested.
17 0 0
2200
2700
3200
3700
4200
2345 678910
IOUT (A)
Iout / Isense
max Tj = -40 °C to 150 °C
max Tj = 25 °C to 150 °C
min Tj = 25 °C to 150 °C
min Tj = -40 °C to 150 °C
typical value
-10
-5
0
5
10
2345678910
dk/k(%)
IOUT (A)
Electrical specifications VN5E025AJ-E
16/37 Doc ID 13106 Rev 4
Table 11. Truth table
Conditions Input Output Sense (VCSD=0V)(1)
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation L
H
L
H
0
Nominal
Overtemperature L
H
L
L
0
VSENSEH
Undervoltage L
H
L
L
0
0
Overload
H
H
X
(no power limitation)
Cycling
(power limitation)
Nominal
VSENSEH
Short circuit to GND
(power limitation)
L
H
L
L
0
VSENSEH
Open load OFF state
(with external pull-up) LHV
SENSEH
Short circuit to VCC
(external pull-up
disconnected)
L
H
H
H
VSENSEH
< Nominal
Negative output voltage
clamp LL 0
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 17/37
Table 12. Electrical transient requirements
ISO 7637-2:
2004(E)
Test pulse
Test levels(1)
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/pulse
repetition time Delays and
Impedance
III IV Min. Max.
1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω
2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω
3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω
3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω
4 -6V -7V 1 pulse 100ms, 0.01Ω
5b(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
+65V +87V 1 pulse 400ms, 2Ω
ISO 7637-2:
2004E
Test pulse
Test level results
III VI
1C C
2a C C
3a C C
3b C C
4C C
5b(2) CC
Class Contents
C All functions of the device performed as designed after exposure to disturbance.
EOne or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Electrical specifications VN5E025AJ-E
18/37 Doc ID 13106 Rev 4
2.4 Waveforms
Figure 11. Normal operation
Figure 12. Overload or Short to GND
IOUT
VSENSE
VCS_DIS
INPUT
Nominal load Nominal load
Normal operation
Power Limitation
ILimH >
ILimL >
IOUT
VSENSE
VCS_DIS
INPUT
Thermal cycling
Overload or Short to GND
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 19/37
Figure 13. Intermittent Overload
Figure 14. OFF-State Open Load with external circuitry
IOUT
VSENSE
VCS_DIS
INPUT
ILimH >Nominal load
Intermittent Overload
ILimL >
Overload
VSENSEH>
INPUT
OFF-State Open Load
with external circutry
VOL
IOUT
VSENSE
VCS_DIS
VOUT
VOUT > VOL
tDSTK(on)
VSENSEH >
Electrical specifications VN5E025AJ-E
20/37 Doc ID 13106 Rev 4
Figure 15. Short to VCC
Figure 16. TJ evolution in Overload or Short to GND
tDSTK(on)
VOUT > VOL
Resistive
Short to VCC
Hard
Short to VCC
Short to VCC
IOUT
VCS_DIS
VOUT
VOL
tDSTK(on)
TTSD
TR
TJ evolution in
Overload or Short to GND
ILimH >
< ILimL
TJ_START
THYST
Power Limitation
Self-limitation of fast thermal transients
INPUT
IOUT
TJ
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 21/37
2.5 Electrical characteristics curves
Figure 17. Off state output current Figure 18. High level input current
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
300
600
900
1200
1500
Iloff (nA)
Off State
Vcc=13V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1,5
2
2,5
3
3,5
4
4,5
5
Iih (µA)
Vin=2.1V
Figure 19. Input clamp level Figure 20. Input low level
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6,2
6,4
6,6
6,8
7
Vicl (V)
lin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
Vil (V)
Figure 21. Input high level Figure 22. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
Vihyst (V)
Electrical specifications VN5E025AJ-E
22/37 Doc ID 13106 Rev 4
Figure 23. On state resistance vs Tcase Figure 24. On state resistance vs VCC
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
20
40
60
80
Ron (mOhm)
Iout= 3A
Vcc=13V
0 5 10 15 20 25 30 35 40
Vcc (V)
0
10
20
30
40
50
60
Ron (mOhm)
Tc=-40°C
Tc=25°C
Tc=125°C
Tc=150°C
Figure 25. Undervoltage shutdown Figure 26. Turn-On voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
Vusd (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
(dVout/dt )On (V/ms)
Vcc=13V
RI=4.3 Ohm
Figure 27. ILIMH vs Tcase Figure 28. Turn-Off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
40
50
60
70
80
Ilimh (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
(dVout/dt )Off (V/ms)
Vcc=13V
RI= 4.3 Ohm
VN5E025AJ-E Electrical specifications
Doc ID 13106 Rev 4 23/37
Figure 29. CS_DIS high level voltage Figure 30. CS_DIS clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vcsdh (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
2
3
4
5
6
7
8
9
10
Vcsdcl(V)
Iin = 1 mA
Figure 31. CS_DIS low level voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
Vcsdl (V)
Application information VN5E025AJ-E
24/37 Doc ID 13106 Rev 4
3 Application information
Figure 32. Application schematic
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following show how to dimension the RGND resistor:
1. RGND ≤ 600mV / (IS(on)max)
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0 during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that, if the microprocessor ground is not shared by the device ground, then the
RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
Μ
CU
+5V
V
GND
CS_DIS
IINPUT
R
prot
R
prot
CURRENT SENSE
R
prot
R
SENSE
C
ext
VN5E025AJ-E Application information
Doc ID 13106 Rev 4 25/37
values. This shift varies depending on how many devices are ON in the case of several high
side drivers sharing the same RGND.
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
3.1.2 Solution 2: diode (DGND) in the ground line
Note that a resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives
an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift not varies if more than one HSD shares the same diode/resistor network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/O protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent
the µC I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ
Recommended values: Rprot =10kΩ, CEXT=10nF.
Application information VN5E025AJ-E
26/37 Doc ID 13106 Rev 4
3.4 Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
●Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a know ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V
minimum (see parameter VSENSE in Table 9: Current sense (8V<VCC<18V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8V<VCC<18V)).
●Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a
maximum current ISENSEH in case of the following fault conditions (refer to Tr u th t a ble):
– Power limitation activation
– Over-temperature
–Short to V
CC in OFF state
– Open load in OFF state with additional external components.
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.
Figure 33. Current sense and diagnostic
Main MOSn
41V
OUTn
ILoff2r
RSENSE
RPROT
To uC ADC
RPD
RPU
VPU
Pwr_Lim
VSENSE
PU_CMD
Overtemperature
OL OFF
+
-
VOL
CURRENT
SENSEn
IOUT/KX
ISENSEH
VBAT
ILoff2f
VSENSEH
Load
INPUTn
VCC
GND
CS_DIS
VN5E025AJ-E Application information
Doc ID 13106 Rev 4 27/37
3.4.1 Short to VCC and OFF state open load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off state. Small or no current is delivered by the current sense
during the on state depending on the nature of the short circuit.
OFF state open load with external circuitry
Detection of an open load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module stand-by mode in order to avoid the
overall stand-by current consumption to increase in normal conditions, i.e. when load is
connected.
An external pull down resistor RPD connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in off state (see Figure 33: Current sense and
diagnostic).
RPD must be selected in order to ensure VOUT < VOLmin unless pulled up by the external
circuitry:
RPD ≤ 22 KΩ is recommended.
For proper open load detection in off state, the external pull-up resistor must be selected
according to the following formula:
For the values of VOLmin ,VOLmax, IL(off2)r and IL(off2)f see Table 10: Openload detection
(8V<VCC<18V).
VVIRV OLfoffLPD
OFFupPull
OUT 2
min)2(
_=<⋅=
−
VV
RR
IRRVR
VOL
PDPU
roffLPDPUPUPD
ONupPull
OUT 4
max
)2(
_=>
+
⋅⋅−⋅
=
−
Application information VN5E025AJ-E
28/37 Doc ID 13106 Rev 4
3.5 Maximum demagnetization energy (VCC =13.5V)
Figure 34. Maximum turn off current versus inductance
Note: Values are generated with RL=0Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
1
10
100
0,1 1 10 100L (mH)
I (A)
Demagnetization Demagnetization Demagnetization
t
VIN, IL
C: T
jstart
= 125°C repetitive pulse
A: T
jstart
= 150°C single pulse
B: T
jstart
= 100°C repetitive pulse
A
B
C
VN5E025AJ-E Package and PC board thermal data
Doc ID 13106 Rev 4 29/37
4 Package and PC board thermal data
4.1 PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 36. Rthj-amb vs PCB copper area in open box free air condition
30
35
40
45
50
55
60
65
0246810
RTHj_amb(°C/ W)
PCB Cu heatsink area (cm^ 2)
Package and PC board thermal data VN5E025AJ-E
30/37 Doc ID 13106 Rev 4
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse
Figure 38. Thermal fitting model of a single channel HSD in PowerSSO-12
Equation 1: pulse calculation formula:
0,1
1
10
100
0,0001 0,001 0,01 0,1 1 10 100 1000
Time ( s)
ZTH (°C/ W)
Footprint
8 cm
2
2 cm
2
ZTHδRTH δZTHtp 1δ–()+⋅=
where δtpT⁄=
VN5E025AJ-E Package and PC board thermal data
Doc ID 13106 Rev 4 31/37
Table 13. Thermal parameter
Area/island (cm2)Footprint28
R1 (°C/W) 0.3
R2 (°C/W) 1.3
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1 (W.s/°C) 0.001
C2 (W.s/°C) 0.003
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
Package and packing information VN5E025AJ-E
32/37 Doc ID 13106 Rev 4
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of Second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
5.2 PowerSSO-12 mechanical data
Figure 39. PowerSSO-12 package dimensions
VN5E025AJ-E Package and packing information
Doc ID 13106 Rev 4 33/37
Table 14. PowerSSO-12 mechanical data
Dimension
Millimeters
Min. Typ. Max.
A 1.250 1.620
A1 0.000 0.100
A2 1.100 1.650
B 0.230 0.410
C 0.190 0.250
D 4.800 5.000
E 3.800 4.000
e 0.800
H 5.800 6.200
h 0.250 0.500
L 0.400 1.270
k0º 8º
X 1.900 2.500
Y 3.600 4.200
ddd 0.100
Package and packing information VN5E025AJ-E
34/37 Doc ID 13106 Rev 4
5.3 Packing information
Figure 40. PowerSSO-12 tube shipment (no suffix)
Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
A
C
B
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
saled with cover tape.
User direction of feed
VN5E025AJ-E Order codes
Doc ID 13106 Rev 4 35/37
6 Order codes
Table 15. Device summary
Package
Order codes
Tube Tape and reel
PowerSSO-12 Root part number 2 VN5E025AJTR-E
Revision history VN5E025AJ-E
36/37 Doc ID 13106 Rev 4
7 Revision history
Table 16. Document revision history
Date Revision Changes
24-Jan-2006 1 Initial release.
15-Jan-2007 2 Reformatted.
Section 4.1 restructured.
01-Apr-2008 3
Document reformatted and restructured.
Changed max. operating voltage value from 36V to 28V.
Changed Description on cover page.
Table 6.: Switching characteristics (VCC=13V, Tj=25°C): added
typical values.
Updated Table 9.: Current sense (8V<VCC<18V):
– changed VCC max. value from 16 V to 18 V
– added K, dK/K values
– added IOL parameter
– changed VSENSEH typical value from 9 V to 8 V.
– changed ISENSEH typical value from 8 mA to 9 mA.
– changed tDSENSE1H typical value from 50 µs to 40 µs.
– changed tDSENSE2L typical value from 100 µs to 80 µs.
– changed tDSENSE2H typical value from 70 µs to 80 µs
– added ΔtDSENSE2H parameter
Updated Table 10.: Openload detection (8V<VCC<18V):
– added IL(off2)r, IL(off2)f and td_vol parameters
Added Figure 9.: IOUT / ISENSE vs IOUT.
Added Figure 10.: Maximum current sense ratio drift vs load current
Added Section 2.4: Waveforms.
Added Section 2.5: Electrical characteristics curves.
Updated Section 3: Application information:
– added Section 3.4: Current sense and diagnostic
Added Section 4.1: PowerSSO-12 thermal data.
10-May-2010 4 Updated Figure 9: IOUT / ISENSE vs IOUT
VN5E025AJ-E
Doc ID 13106 Rev 4 37/37
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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