P8
7
/SEG
15
81
M38197MA-XXXFP
P8
6
/SEG
14
82
P8
5
/SEG
13
83
P8
4
/SEG
12
84
P8
3
/SEG
11
85
P8
2
/SEG
10
86
P8
1
/SEG
9
87
P8
0
/SEG
8
88
PA
7
/SEG
7
89
PA
6
/SEG
6
90
V
CC
91
PA
5
/SEG
5
92
PA
4
/SEG
4
93
PA
3
/SEG
3
94
PA
2
/SEG
2
95
PA
1
/SEG
1
96
PA
0
/SEG
0
97
V
EE
98
AV
SS
99
V
REF
100
P1
6
/DIG
14
50
P1
7
/DIG
15
49
P2
0
/DIG
16
48
P2
1
/DIG
17
47
P2
2
/DIG
18
46
P2
3
/DIG
19
45
P2
4
44
P2
5
43
P2
6
42
P2
7
41
V
SS
40
X
OUT
39
X
IN
38
PB
0
/X
COUT
37
PB
1
/X
CIN
36
RESET
35
P4
0
/INT
0
34
P4
1
33
P4
2
/INT
2
32
P4
3
/INT
3
31
P7
7
/AN
7
1
P7
6
/AN
6
2
P7
5
/AN
5
3
P7
4
/AN
4
4
P7
3
/AN
3
5
P7
2
/AN
2
6
P7
1
/AN
1
7
P7
0
/AN
0
8
PB
3
9
PB
2
/DA
10
P5
7
/S
RDY3
/AN
15
11
P5
6
/S
CLK3
/AN
14
12
P5
5
/S
OUT3
/AN
13
13
P5
4
/S
IN3
/AN
12
14
P5
3
/S
RDY2
/AN
11
15
P5
2
/S
CLK2
/AN
10
16
P5
1
/S
OUT2
/AN
9
17
P5
0
/S
IN2
/AN
8
18
P6
7
/S
RDY1
/CS/S
CLK12
19
P6
6
/S
CLK11
20
P6
5
/S
OUT1
21
P6
4
/S
IN1
22
P6
3
/CNTR
1
23
P6
2
/CNTR
0
24
P6
1
/PWM
25
P6
0
26
P4
7
/T3
OUT
27
P4
6
/T1
OUT
28
P4
5
/INT
1
/ZCR
29
P4
4
/INT
4
30
P9
0
/SEG
16
80
P9
1
/SEG
17
79
P9
2
/SEG
18
78
P9
3
/SEG
19
77
P9
4
/SEG
20
76
P9
5
/SEG
21
75
P9
6
/SEG
22
74
P9
7
/SEG
23
73
P3
0
/SEG
24
72
P3
1
/SEG
25
71
P3
2
/SEG
26
70
P3
3
/SEG
27
69
P3
4
/SEG
28
68
P3
5
/SEG
29
67
P3
6
/SEG
30
66
P3
7
/SEG
31
65
P0
0
/SEG
32
/DIG
0
64
P0
1
/SEG
33
/DIG
1
63
P0
2
/SEG
34
/DIG
2
62
P0
3
/SEG
35
/DIG
3
61
P0
4
/SEG
36
/DIG
4
60
P0
5
/SEG
37
/DIG
5
59
P0
6
/SEG
38
/DIG
6
58
P0
7
/SEG
39
/DIG
7
57
P1
0
/SEG
40
/DIG
8
56
P1
1
/SEG
41
/DIG
9
55
P1
2
/DIG
10
54
P1
3
/DIG
11
53
P1
4
/DIG
12
52
P1
5
/DIG
13
51
DESCRIPTION
The 3819 group is a 8-bit microcomputer based on the 740 family
core technology.
The 3819 group has a flourescent display automatic display circuit
and an 16-channel 8-bit A-D converter as additional functions.
The various microcomputers in the 3819 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3819 group, re-
fer to the section on group expansion.
FEATURES
●Basic machine-language instructions ...................................... 71
●The minimum instruction execution time ......................... 0.48 µs
(at 8.4 MHz oscillation frequency)
●Memory size .................................................................................
ROM............................................. 4K to 60 K bytes
RAM ........................................... 192 to 2048 bytes
●Programmable input/output ports ............................................ 54
●High-breakdown-voltage output ports...................................... 52
●Interrupts ................................................. 20 sources, 16 vectors
●Timers............................................................................. 8-bit ✕ 6
●Serial I/O (Serial I/O1 has an automatic transfer function)
...................................................... 8-bit ✕ 3(clock-synchronized)
●PWM output circuit ............... 8-bit ✕ 1(also functions as timer 6)
●A-D converter ............................................... 8-bit ✕ 16 channels
●D-A converter ................................................. 8-bit ✕ 1 channels
●Zero cross detection input............................................ 1 channel
●Fluorescent display function
Segments ........................................................................16 to 42
Digits.................................................................................. 6 to 16
●2 Clock generating circuit
Clock (XIN-XOUT) ................................. Internal feedback resistor
Sub-clock (XCIN-XCOUT) .........Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal oscil-
lator)
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8.4 MHz oscillation frequency and high-speed selected)
In middle-speed mode............................................... 2.8 to 5.5 V
(at 8.4 MHz oscillation frequency)
In low-speed mode .................................................... 2.8 to 5.5 V
(at 32 kHz oscillation frequency)
●Power dissipation
In high-speed mode ..........................................................35 mW
(at 8.4 MHz oscillation frequency)
In low-speed mode ............................................................ 6 0 µW
(at 3 V power source voltage and 32 kHz oscillation frequency )
●Operating temperature range....................................–10 to 85°C
APPLICATION
Musical Instruments, household appliance, etc.
Package type : 100P6S-A
100-pin plastic-molded QFP
PIN CONFIGURATION (TOP VIEW)
3819 Group
SINGLE-CHIP 8-BIT MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
2
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
FUNCTIONAL BLOCK DIAGRAM (Packag e : 100P6S-A)
Interrupt interval
determination
circuit
ROM
CPU
P7 (8)
I/O port P7
12345678
P8 (8)
I/O port P8
81 82 8384 85 86 8788
A-D
converter (8)
P9 (8)
Output port P9
7374 7576 77 78 7980
PA (8)
I/O po rt P A
8990 92 93 94 9596 97
PB (4)
I/O po rt PB
9103637
P6 (8)
I/O po rt P6
1920 2122 23 24 25 2699100
AVSS
VREF
P5 (8)
I/O po rt P5
11 12 13 14 15 16 17 18
P4 (8)
I/O po rt P 4 (6 )
Input port P4(2)
27 28 29 30 31 32 33 34
P3 (8)
Output port P3
65 66 6768 69 70 7172
S I/O3(8)
S I/O2(8)S I/O1(8)
16
P2 (8)
Output port P2(4)
I/O po rt P 2 (4 )
48 47 46 45 44 43 4241
P1 (8)
Output port P1
56 55 54 53 52 51 5049
P0 (8)
Output port P0
64 63 62 6160 59 5857
D-A
converter (8)
PS
PCL
S
Y
X
A
PCH
RAM
Data
bus
Timer 1 (8)
Timer 2 (8)
Timer 3 (8)
Timer 4 (8)
Timer 5 (8)
Timer 6 (8)
T1OUT SI/O
automatic
transfer
controller
FLD
automatic
display
controller
SI/O
automatic
transfer RAM
32 bytes
FLD
automatic
display RAM
96 bytes
Clock generating
circuit
XCOUT
Sub-clock
output
XCIN
Sub-clock
input
Clock
output
XOUT
Clock
input
XIN 92
VEE
40
(0 V)
VSS
91
(5 V)
VCC
35
Reset input
RESET
39
38
XCOUT
XCIN
Zero cross
detection circuit
INT
0
INT
1
/ZCR
INT
2
T3OUT
PWM
CNTR0
CNTR1
Local data
bus
INT
3
, INT
4
3
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
•Reset input pin for active “L”
VCC, VSS
PIN DESCRIPTION
Pin Name Function Function except a port function
Power source •Apply voltage of 4.0 to 5.5 V to VCC, and 0 V to VSS.
•Applies voltage supplied to pull-down resistors of ports P0, P1, P20–P23, P3, and P9.
•Reference voltage input pin for A-D converter and D-A converter
•GND input pin for A-D converter and D-A converter
•Connect AVSS to VSS.
•Input and output pins for the main clock generating circuit
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN pin and XOUT pin to
set oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin
open.
•This clock is used as the oscillating source of system clock.
•8-bit output port
•This port builds in pull-down resistor between
port P0 and the VEE pin.
•At reset this port is set to VEE level.
•The high-breakdown-voltage P-channel
open-drain
VEE
VREF
AVSS
RESET
XIN
XOUT
P00/SEG32/
DIG0–P07/
SEG39/DIG7
P10/SEG40/
DIG8–P17/
DIG15
P20/DIG16–
P23/DIG19
P24–P27
•8-bit output port with the same function as
port P0
•4-bit output port with the same function as
port P0
•4-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•At reset this port is set to input mode.
•TTL input level
•CMOS 3-state output
P30/SEG24–
P37/SEG31
P40/INT0,
P45/INT1/
ZCR
P42/INT2–
P44/INT4
P41
P46/T1OUT,
P47/T3OUT
Pull-down
Power source
Analog reference
voltage
Reset input
Analog power source
Clock input
Clock output
Output port P0
Output port P1
Output port P2
I/O port P2
Output port P3
Input port P4
I/O port P4
•8-bit output port with the same function as
port P0
•2-bit input port
•CMOS compatible input level
•6-bit CMOS I/O port with the same function
as ports P24–P27
•CMOS compatible input level
•CMOS 3-state output
FLD automatic display pins
FLD automatic display pins
FLD automatic display pins
FLD automatic display pins
External interrupt input pins
A zero cross detection circuit input pin (P45)
Timer output pins
4
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
•8-bit output port with the same function as
port P0
P50/SIN2/AN8,
P51/SOUT2/AN9,
P52/SCLK2/AN10,
P53/SRDY2/AN11
P54/SIN3/AN12,
P55/SOUT3/AN13,
P56/SCLK3/AN14,
P57/SRDY3/AN15
P60
P61/PWM
P62/CNTR0,
P63/CNTR1
P64/SIN1,
P65/SOUT1,
P66/SCLK11,
P67/SRDY1/CS/
SCLK12
PIN DESCRIPTION (Continued)
Pin Name Function Function except a port function
I/O port P5 •8-bit CMOS I/O port with the same function
as ports P24–P27
•CMOS compatible input level
•CMOS 3-state output
•8-bit CMOS I/O port with the same function
as ports P24–P47
•CMOS compatible input level
•CMOS 3-state output
•8-bit CMOS I/O port with the same function
as ports P24–P27
•CMOS compatible input level
•CMOS 3-state output
•8-bit I/O port with the same function as ports
P24–P27
•CMOS compatible input level
•The high-breakdown-voltage P-channel
open-drain
•8-bit I/O port with the same function as ports
P24–P27
•CMOS compatible input level
•The high-breakdown voltage P-channel open-
drain
•4-bit CMOS I/O port with the same function
as ports P24–P27
•CMOS compatible input level
•CMOS 3-state output
Serial I/O2 function pins
A-D conversion input pins
Serial I/O3 function pins
A-D conversion input pins
PWM output pin (Timer output pin)
Timer input pins
Serial I/O1 function pins
A-D conversion input pins
FLD automatic display pins
I/O pins for sub-clock generating circuit (con-
nect a ceramic resonator or a quarts-crystal
oscillator)
D-A conversion output pin
P70/AN0–
P77/AN7
P80/SEG8–
P87/SEG15
P90/SEG16–
P97/SEG23
PA0/SEG0–
PA7/SEG7
PB0/XCOUT,
PB1/XCIN
PB2/DA
PB3
I/O port P6
I/O port P7
I/O port P8
Output port P9
I/O port PA
I/O port PB
5
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PART NUMBERING
Package type
FP : 100P6S-A package
FS : 100D0 package
ROM number
Omitted in some types.
ROM/PROM size
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Memory type
M
E : Mask ROM version
: EPROM or One Time PROM version
Product M3819 FPM A XXX7
6
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
GROUP EXPANSION
Mitsubishi plans to expand the 3819 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM ver-
sions
ROM/PROM capacity .................................. 40 K to 60 K bytes
RAM capacity.............................................. 1024 to 2048 bytes
(2) Packages
100P6S-A........................... 0.65 mm-pitch plastic molded QFP
100D0...........................Ceramic LCC(built-in EPROM version)
Currently supported products are listed below. As of May 1996
RAM size (bytes) RemarksPackageProduct (P) ROM size (bytes)
ROM size for User in ( )
M38197MA-XXXFP
M38197MA-XXXKP
M38198MC-XXXKP
M38199MF-XXXKP
M38198MC-XXXFP
M38198EC-XXXFP
M38198ECFP
M38198ECFS
M38199MF-XXXFP
M38199EF-XXXFP
M38199EFFP
M38199EFFS
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
1024
1536
2048
100P6S-A
100P6P-E
100P6S-A
100D0
100P6S-A
100D0
40960
(40830)
49152
(49022)
61440
(61310)
Memory Expansion Plan
Products under development : the development schedule and specifications may be revised without notice.
4K
256 512 768 1,024 1,536 2,048
ROM size (bytes)
RAM size (bytes)
Under development
8K
12K
16K
20K
24K
28K
32K
36K
40K
44K
48K
52K
56K
60K M38199MF/EF
Mass product
Mass product
M38197MA
M38198MC/EC
7
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 3819 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instruction can be used.
CPU Mode Register
The CPU mode register is allocated at address 003B16. The CPU
mode register contains the stack page selection bit and the inter-
nal system clock selection bit.
Fig. BA-1 Structure of CPU mode register
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area
X
COUT
drivability selection bit
0 : Low drive
1 : High drive
Port X
C
switch bit
0 : I/O port function
1 : X
CIN
-X
COUT
oscillating function
Main clock (X
IN
-X
OUT
) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(X
IN
)/2 (high-speed mode)
1 : f(X
IN
)/8 (middle-speed mode)
Internal system clock selection bit
0 : X
IN
-X
OUT
selected (middle/high-speed mode)
1 : X
CIN
-X
COUT
selected (low-speed mode)
b7 CPU mode register
(CPUM (CM) : address 003B
16
)
b0
8
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
192
256
384
512
640
768
896
1024
1536
2048
00FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
063F
16
083F
16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F000
16
E000
16
D000
16
C000
16
B000
16
A000
16
9000
16
8000
16
7000
16
6000
16
5000
16
4000
16
3000
16
2000
16
1000
16
F080
16
E080
16
D080
16
C080
16
B080
16
A080
16
9080
16
8080
16
7080
16
6080
16
5080
16
4080
16
3080
16
2080
16
1080
16
0100
16
0000
16
0040
16
0440
16
FF00
16
FFDC
16
FFFE
16
FFFF
16
XXXX
16
YYYY
16
ZZZZ
16
RAM
RO
M
SFR area Zero
page
Special
page
RAM area
RAM capacity
(bytes) Address XXXX
16
ROM capacity
(bytes) Address YYYY
16
Reserved area
0F00
16
0F1F
16
Not used
RAM area for serial I/O automatic transfer
Not used
0F80
16
RAM area for FLD automatic display
0FDF
16
Not used
Reserved ROM area
(common ROM area,128 bytes)
Interrupt vector area
Reserved ROM area
ROM area
Address ZZZZ
16
Memory
Special function register (SFR) area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the reset is user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. CA-1 Memory map
9
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. CA-2 Memory map of special function register (SFR)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
Port P0 (P0)
Port P1 (P1)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Serial I/O automatic transfer data pointer (SIODP)
Serial I/O1 control register (SIO1CON)
Serial I/O automatic transfer control register (SIOAC)
Serial I/O1 register (SIO1)
Serial I/O automatic transfer interval register (SIOAI)
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Timer 6 (T6)
Serial I/O3 register (SIO3)
Timer 6 PWM register (T6PWM)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
Port P0 segment/digit switch register (P0SDR)
Port P2 digit/port switch register (P2DPR)
Port P8 segment/port switch register (P8SPR)
FLDC mode register 2 (FLDM2)
Zero cross detection control register (ZCRCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
003F
16
Interrupt control register 2 (ICON2)
Port PA (PA)
Port PA direction register (PAD)
Port PB (PB)
Port PB direction register (PBD)
Serial I/O2 control register (SIO2CON)
Serial I/O3 control register (SIO3CON)
Serial I/O2 register (SIO2)
Timer 56 mode register (T56M)
D-A conversion register (DA)
AD-DA control register (ADCON)
A-D conversion register (AD)
Port PA segment/port switch register (PASPR)
FLDC mode register 1 (FLDM1)
FLD data pointer (FLDDP)
Port P9 (P9)
10
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
I/O PORTS
Direction Registers
The 3819 group has 54 programmable I/O pins arranged in 8 I/O
ports (ports P24–P27, P41–P44, P46, P47, P5–P8, PA, and PB).
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, each pin can be set to be input or
output.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set for output, the value of the
port latch is read, not the value of the pin itself. A pin which is set
for input the value of the pin itself is read because the pin is in
floating state. If a pin set for input is written to, only the port latch
is written to and the pin remains floating.
High-Breakdown-Voltage Output Ports
The 3819 group microprocessors have 7 ports with high-break-
down-voltage pins (ports P0, P1, P20–P23, P3, P8, P9, PA). The
high-breakdown-voltage ports have P-channel open-drain output
with VCC –40 V of breakdown voltage.
Each pin in ports P0, P1, P20–P23, P3, and P9 has an internal
pull-down resistor connected to VEE. Ports P8 and PA have no in-
ternal pull-down resistors, so that connect an external resistor to
each port. At reset, the P-channel output transistor of each port
latch is turned off, so it becomes VEE level (“L”) by the pull-down
resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register 1
(address 003616) shows the rising transition of the output transis-
tors for reducing transient noise. At reset, bit 7 of the FLDC mode
register 1 is set to “0” (strong drivability).
Pin Name Input/Output I/O Format Non-Port Function Related SFRSDiagram
No.
P00/SEG32/
DIG0–
P07/SEG39/
DIG7
P10/SEG40/
DIG8–
P17/DIG15
P20/DIG16–
P23/DIG19
P24–P27
P30/SEG24–
P37/SEG31
P40/INT0
P45/INT1/
ZCR
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
TTL level input
CMOS 3-state output
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
CMOS compatible
input level
P42/INT2–
P44/INT4
P46/T1OUT,
P47/T3OUT
P41
CMOS compatible
input level
CMOS 3-state output
Port P0
Port P1
Port P2
Port P3
Port P4
Output
Output
Output
Input/output,
individual bits
Output
Input
Input/output,
individual bits
FLD automatic dis-
play function
FLD automatic dis-
play function
FLD automatic dis-
play function
FLD automatic dis-
play function
External interrupt
input
Zero cross detec-
tion circuit input
(P45)
Timer output
FLDC mode register 1
FLDC mode register 2
Port P0
segment/digit
switch register
FLDC mode register 1
FLDC mode register 2
FLDC mode register 1
FLDC mode register 2
Port P2 digit/port
switch register
FLDC mode register 1
FLDC mode register 2
Interrupt edge
selection register
Zero cross detection
control register
Timer 12 mode register
Timer 34 mode register
(1)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(4)
(8)
11
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
P62/CNTR0,
P63/CNTR1
P64/SIN1
P65/SOUT1,
P66/SCLK11
P67/SRDY1/
CS/SCLK12
Port P5
Pin Name Input/Output I/O Format Non-Port Function Related SFRSDiagram
No.
P50/SIN2/
AN8
P51/SOUT2/
AN9,
P52/SCLK2/
AN10
P53/SRDY2/
AN11
P54/SIN3/
AN12
P55/SOUT3/
AN13,
P56/SCLK3/
AN14
P57/SRDY3/
AN15
P60
CMOS compatible
input level
CMOS 3-state output
Input/output,
individual bits
Serial I/O2 func-
tion I/O
A-D conversion in-
put
Serial I/O2 control
register
AD/DA control regis-
ter
(9)
Serial I/O3 func-
tion I/O
A-D conversion in-
put
Serial I/O3 control
register
AD/DA control regis-
ter
Timer 56 mode regis-
ter
PWM (timer) out-
put
P61/PWM
Timer input Interrupt edge selec-
tion register
Serial I/O1 func-
tion I/O
Serial I/O1 control
register
Serial I/O automatic
transfer control regis-
ter
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
CMOS compatible
input level
High-breakdown-
voltage P-channel
open-drain output
P70/AN0–
P77/AN7
P80/SEG8–
P87/SEG15
P90/SEG16–
P97/SEG23
PA0/SEG0–
PA7/SEG7
PB0/XCOUT,
PB1/XCIN
PB2/DA
PB3
CMOS compatible
input level
CMOS 3-state output
FLD automatic
display function
A-D conversion in-
put
I/O for sub-clock
generating circuit
D-A conversion
output
AD/DA control regis-
ter
FLDC mode register
Segment/port switch
register
FLDC mode register
FLDC mode register
Segment/port switch
register
CPU mode register
AD/DA control regis-
ter
Output
Input/output,
individual bits
Input/output,
individual bits
Port P6
Port P7
Port P8
Port P9
Port PA
(10)
(11)
(9)
(10)
(11)
(4)
(8)
(7)
(9)
(10)
(11)
(12)
(13)
(5)
(13)
(14)
(15)
(16)
Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate poten-
tial, a current will flow from VCC to VSS through the input-stage gate.
Port PB
CMOS compatible
input level
CMOS 3-state output
(4)
12
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. UA-2 Port block diagram (1)
(4) Ports P2
4
–P2
7
, P4
1
, P6
0
, PB
3
Direction
register
Port latch
Data bus
(3) Ports P2
0
–P2
3
(2) Ports P1
2
–P1
7
(1) Ports P0, P1
0
, P1
1
Port latch
D/P switch register
Dimmer signal
(Note)
Shift signal to next stage
Blanking signal
for key-scan
Data bus
Shift signal from previous stage
Port latch
V
EE
Shift signal from previous stage
Data bus
Shift signal to next stage
Dimmer signal
(Note)
Shift signal to next stage
Data bus
Shift signal from previous stage
Port latch
S/D switch register
Local data bus
Blanking signal
for key-scan Dimmer signal
(Note)
V
EE
V
EE
✽
✽
✽
✽ : High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
13
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. UA-3 Port block diagram (2)
Direction
register
Port latch
Data bus
Port latch
Dimmer signal
(Note)
Data bus
V
EE
✽
Direction
register
Port latch
Data bus
(6) Ports P4
0
, P4
5
Data bus
INT
0
, INT
1
interrupt input
Zero cross
detection
circuit
input
(only P4
5
)
Local data bus
(5) Ports P3, P9
INT
2
–INT
4
interrupt input
CNTR
0
,CNTR
1
input
Timer 1 output selection bit
Timer 3 output selection bit
Timer 6 output selection bit
Timer 1 output
Timer 3 output
Timer 6 output
✽ : High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
(7) Ports P4
2
–P4
4
, P6
2
, P6
3
(8) Ports P4
6
, P4
7
, P6
1
14
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. UA-4 Port block diagram (3)
(10) Ports P5
1
, P5
2
, P5
5
, P5
6
, P6
5
, P6
6
(11) Ports P5
3
, P5
7
, P6
7
Direction
register
Port latch
Data bus
Serial I/O input
Direction
register
Port latch
Data bus
Direction
register
Port latchData bus
Direction
register
Port latch
Data bus
(9) Ports P5
0
, P5
4
, P6
4
(12) Port P7
A-D conversion input
Analog input pin selection bit
Serial I/O port selection bit
P-channel output disable signal
Output OFF control signal
A-D conversion input
Analog input pin selection bit
S
OUT
or S
CLK
(only P5
2
, P5
6
, P6
6
)
Serial clock input
S
RDY
output enable bit
Serial ready output
or S
CLK
CS input
A-D conversion input
Analog input pin selection bit
(only P6
7
)
A-D conversion input
Analog input pin selection bit
15
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. UA-5 Port block diagram (4)
read
Data bus ✽
Local
data bus
(13) Ports P8, PA
✽ : High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
Direction
register
Port latch
Data bus
D-A conversion output
D-A output enable bit
Direction
register
Port latch
Data bus
Sub-clock generating circuit input
Direction
register
Port latch
Data bus
Directionregister
Port latch
S/P switch register
Dimmer signal
(Note)
Port XC switch
bit
Port XC switch bit
Port PB1
Oscillation circuit
Port XC switch
bit
(14) Port PB0
(15) Port PB1
(16) Port PB2
16
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INTERRUPTS
Interrupts occur by 20 sources: 5 external, 14 internal, and 1 soft-
ware.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit.
The I (interrupt disable) flag disables all interrupts except the BRK
instruction interrupt.
Interrupt Operation
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering. The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
Notes on Use
When the active edge of an external interrupt (INT0 to INT4) is
changed or when switching interrupt sources in the same vector
address, the corresponding interrupt request bit may also be set.
Therefore, please take following sequence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 1. Interrupt vector addresses and priority
Interrupt Request
Generating Conditions
High
FFFD16
Interrupt Source Priority Low
FFFC16
Remarks
Reset (Note 2) Non-maskable
External interrupt (active edge
selectable)
External interrupt (active edge
selectable)
External interrupt (active edge
selectable)
Valid when interrupt interval
determination is operating
Valid when serial I/O ordinary
mode is selected
Valid when serial I/O automatic
transfer mode is selected
Valid when serial I/O2 is se-
lected
Valid when serial I/O3 is se-
lected
STP release timer underflow
1
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
Vector Addresses (Note 1)
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1/ZCR input
At detection of either rising or
falling edge of INT2 input
INT0
INT1/ZCR
INT2
Remote control/
counter overflow
Serial I/O1
Serial I/O
automatic transfer
Serial I/O2
Serial I/O3
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
INT3
2
3
At 8-bit counter overflow
At completion of data transfer
At completion of the last data
transfer
At completion of data transfer
At completion of data transfer
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At detection of either rising or
falling edge of INT3 input External interrupt (active edge
selectable)
Valid when INT4 interrupt is
selected
External interrupt (active
edge selectable)
Valid when A-D conversion in-
terrupt is selected
At detection of either rising or
falling edge of INT4 input
At completion of A-D conver-
sion
At falling edge of the last digit
immediately before blanking
period starts
At rising edge of each digit
At BRK instruction execution
Valid when FLD blanking in-
terrupt is selected
Valid when FLD digit interrupt
is selected
Non-maskable software inter-
rupt
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
4
5
6
7
8
9
10
11
12
13
14
15
16
17
INT4
A-D conversion
FLD blanking
FLD digit
BRK instruction
17
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
b7 Interrupt edge selection register
(INTEDGE : address 003A
16
)
INT
0
interrupt edge selection bit
INT
1
/ZCR interrupt edge selection bit
INT
2
interrupt edge selection bit
INT
3
interrupt edge selection bit
INT
4
interrupt edge selection bit
INT
4
/AD conversion interrupt switch bit
CNTR
0
pin active edge switch bit
CNTR
1
pin active edge switch bit
b0
0 : Falling edge active
1 : Rising edge active
0 : No interrupt request issued
1 : Interrupt request issued
0 : INT
4
interrupt
1 : A-D conversion interrupt
0 : Rising edge count
1 : Falling edge count
b7 Interrupt request register 1
(IREQ1 : address 003C
16
)
INT
0
interrupt request bit
INT
1
/ZCR interrupt request bit
INT
2
interrupt request bit
Remote control/counter overflow
interrupt request bit
Serial I/O1 interrupt request bit
Serial I/O automatic transfer
interrupt request bit
Serial I/O2 interrupt request bit
Serial I/O3 interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
b0 b7 Interrupt request register 2
(IREQ2 : address 003D
16
)
Timer 3 interrupt request bit
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
INT
3
interrupt request bit
INT
4
interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
b0
0 : Interrupts disabled
1 : Interrupts enabled
b7 Interrupt control register 1
(ICON1 : address 003E
16
)
INT
0
interrupt enable bit
INT
1
/ZCR interrupt enable bit
INT
2
interrupt enable bit
Remote control/counter overflow
interrupt enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer
interrupt enable bit
Serial I/O2 interrupt enable bit
Serial I/O3 interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
b0 b7 Interrupt control register 2
(ICON2 : address 003F
16
)
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
INT
3
interrupt enable bit
INT
4
interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(do not write “1” to this bit)
b0
Fig. DD-1 Interrupt control
Fig. DD-2 Structure of interrupt-related registers
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
18
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
TIMERS
The 3819 group has 6 built-in timers: timer 1, timer 2, timer 3,
timer 4, timer 5, and timer 6.
Each timer has the 8-bit timer latch. The timers count down.
Once a timer reaches 0016, at the next count pulse the contents of
each timer latch is loaded into the corresponding timer, and sets
the corresponding interrupt request bit to “1”.
The count can be stopped by setting the stop bit of each timer to
“1”. The internal clock φ can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
timer internal count source is switched to either f(XIN) or f(XCIN).
Timer 1 and Timer 2
The count sources of timer 1 and timer 2 can be selected by set-
ting the timer 12 mode register. A rectangular waveform of timer 1
underflow signal divided by 2 is output from the P46/T1OUT pin.
The waveform polarity changes each time timer 1 overflows. The
active edge of the external clock CNTR0 can be switched with the
bit 6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer
12 mode register are cleared to “0”, timer 1 is set to “FF16”, and
timer 2 is set to “0116”.
Timer 3 and Timer 4
The count sources of timer 3 and timer 4 can be selected by set-
ting the timer 34 mode register. A rectangular waveform of timer 3
underflow signal divided by 2 is output from the P47/T3OUT pin.
The waveform polarity changes each time timer 3 overflows.
The active edge of the external clock CNTR1 can be switched with
the bit 7 of the interrupt edge selection register.
Timer 5 and Timer 6
The count sources of timer 5 and timer 6 can be selected by set-
ting the timer 56 mode register.
A rectangular waveform of timer 6 underflow signal divided by 2 is
output from the P61/PWM pin. The waveform polarity changes
each time timer 6 overflows.
Timer 6 PWM Mode
Timer 6 can output a rectangular waveform with duty cycle n/(n +
m) from the P61/PWM pin by setting the timer 56 mode register
(refer to fig. FB-3). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0”, the PWM output is “L”, if m is “0”, the PWM out-
put is “H”(n=0 is prior than m=0). In the PWM mode, interrupts
occur at the rising edge of the PWM output.
19
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. FB-1 Timer block diagram
XCIN
1/16
P46/T1OUT
Internal system
clock selection
bit
P62/CNTR0
P61/PWM
XIN
P46 direction register
P46 latch
“10”
“01”
“00”
Timer 1
count
source
selection bit
Timer 3 interrupt request
Timer 1 interrupt request
Timer 2 interrupt request
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Timer 3 latch (8)
Timer 3 (8)
“0”
“1”
1/2
Timer 1 output
selection bit
Timer 1
count stop
bit
FF16
Data bus
RESET
STP instruction
Timer 4 interrupt request
Timer 5 interrupt request
Timer 6 interrupt request
Timer 2
count
source
selection bit
Timer 2
count stop
bit
“10”
“01”
“00”
Timer 3
count
source
selection bit
Timer 3
count stop bit
Timer 4
count
source
selection bit
Timer 4
count stop
bit
Timer 5
count
source
selection bit
Timer 5
count stop bit
Timer 6
count
source
selection bit
Timer 6
count stop
bit
“10”
“01”
“00”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
P47 direction register
P47 latch
Timer 3 output
selection bit
P61 direction register
P61 latch
Timer 6 output
selection bit
P47/T3OUT
P63/CNTR1
Timer 4 latch (8)
Timer 4 (8)
Timer 5 latch (8)
Timer 5 (8)
Timer 6 latch (8)
Timer 6 (8)
Timer 6 PWM register (8)
PWM
1/2
Timer 6 operating
mode selection bit
Rising/falling
edge switch
Rising/falling
edge switch
0116
1/2
20
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Timer 1 count stop bit
0 : Operating
1 : Stopped
Timer 2 count stop bit
0 : Operating
1 : Stopped
Timer 1 count source selection bit
0 : f(X
IN
)/16 or f(X
CIN
)/16
1 : f(X
CIN
)
Not used (returns “0” when read)
Timer 2 count source selection bits
b5 b4
0 0 : Timer 1 underflow
0 1 : f(X
CIN
)
1 0 : External count input CNTR
0
1 1 : Not available
Timer 1 output selection bit (P4
6
)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
b7 Timer 12 mode register
(T12M : address 0028
16
)
b0
Timer 3 count stop bit
0 : Operating
1 : Stopped
Timer 4 count stop bit
0 : Operating
1 : Stopped
Timer 3 count source selection bit
0 : f(X
IN
)/16 or f(X
CIN
)/16
1 : Timer 2 underflow
Not used (returns “0” when read)
Timer 4 count source selection bits
b5 b4
0 0 : f(X
IN
)/16 or f(X
CIN
)/16
0 1 : Timer 3 underflow
1 0 : External count input CNTR
1
1 1 : Not available
Timer 3 output selection bit (P4
7
)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
Timer 34 mode register
(T34M : address 0029
16
)
b7 b0
Timer 5 count stop bit
0 : Operating
1 : Stopped
Timer 6 count stop bit
0 : Operating
1 : Stopped
Timer 5 count source selection bit
0 : f(X
IN
)/16 or f(X
CIN
)/16
1 : Timer 4 underflow
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
b5 b4
0 0 : f(X
IN
)/16 or f(X
CIN
)/16
0 1 : Timer 5 underflow
1 0 : Timer 4 underflow
1 1 : Not available
Timer 6 (PWM) output selection bit (P6
1
)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(do not write “1”)
b7 Timer 56 mode register
(T56M : address 002A
16
)
b0
Fig. FB-2 Structure of timer-related registers
21
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. FB-3 Timing in timer 6 PWM mode
ts
n ✕ tsm ✕ ts
(n + m) ✕ ts
Timer 6
count
source
Timer 6
PWM output
Timer 6 interrupt request Timer 6 interrupt request
Note: If the value set in timer 6 is n and the value set in the timer 6 PWM register is m, a PWM waveform with
duty cycle n/(n + m) and period (n + m) 5 ts (ts : the frequency of the timer 6 count source) is output.
22
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
SERIAL I/O
The 3819 group has built-in 8-bit clock synchronized serial I/O ✕ 3
channels (serial I/O1, serial I/O2, and serial I/O3).
Serial I/O1 builds in the automatic transfer function. The function
can be switched to the serial I/O ordinary mode with the serial I/O
automatic transfer control register (address 001A16).
Serial I/O2 and Serial I/O3 can be used only in the serial I/O ordi-
nary mode.
The I/O pins of the serial I/O function are also used as I/O ports
P5 and P64–P67, and their operation is selected with the serial I/O
control registers (addresses 001916, 001D16, and 001E16).
Serial I/O Control Registers
(SIO1CON, SIO2CON, SIO3CON)
001916, 001D16, 001E16
Each of the serial I/O control registers (addresses 001916,
001D16, and 001E16) consists of 8 selection bits which control the
serial I/O function.
23
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. GA-1 Serial I/O block diagram
S
CLK1
1/8
1/128
1/64
1/32
1/16
SI/O automatic
transfer RAM
(0F0016 to 0F1F16)
Main data
bus Local data
bus
Main
address bus Local
address bus
SI/O automatic
transfer
controller
SI/O automatic
transfer data
pointer Serial I/O automatic
transfer interrupt request
SI/O automatic transfer
interval register
1/256
Internal synchronous
clock selection bit
Synchronous
clock selection
bit “1”
“0”
Internal
system clock
selection bit
External clock
(Note) SRDY1
P67 latch
CS
Serial I/O counter 1(3)
Serial I/O shift register 1(8)
“0”
P66 latch
“1”
Serial I/O1 port selection bit
P65 latch
“0”
“1”
Serial I/O1 port selection bit
Address decorder
Synchronization
circuit
Frequency divider
Serial I/O1
interrupt request
“0”
“1”
XIN
XCIN
P66/SCLK11
P65/SOUT1
P64/SIN1
P67/SRDY1/
CS/SCLK12
S
CLK2
1/8
1/128
1/64
1/32
1/16
1/256
Internal synchronous
clock selection bit
Synchronous
clock selection
bit “1”
“0”
External clock
SRDY2
P53 latch
SRDY2 output selection bit
Serial I/O counter 2(3)
Serial I/O shift register 2(8)
“0”
“1”
Serial I/O2 port selection bit
P51 latch
“0”
“1”
Serial I/O2 port selection bit
Frequency divider
Serial I/O2
interrupt request
“0”
P52/SCLK2
P51/SOUT2
P50/SIN2
P53/SRDY2 “1” Synchronization
circuit
P52 latch
S
CLK3
1/8
1/128
1/64
1/32
1/16
1/256
Internal synchronous
clock selection bit
“1”
“0”
External clock
SRDY3
P57 latch
SRDY2 output selection bit
Serial I/O counter 3(3)
Serial I/O shift register 3(8)
“0”
“1”
Serial I/O3 port selection bit
P55 latch
“0”
“1”
Serial I/O3 port selection bit
Frequency divider
Serial I/O3
interrupt request
“0”
P56/SCLK3
P55/SOUT3
P54/SIN3
P57/SRDY3 “1” Synchronization
circuit
P56 latch
Note: Selected with the synchronous clock selection bit, SRDY1 output selection bit, serial I/O1 port selection bit (these 3 bits are of the serial
I/O1 control register), automatic transfer control bit, and synchronous clock output pin selection bit (these 2 bits are ofthe serial I/O
automatic transfer register).
24
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
b0
Internal synchronous clock selection bits
b2 b1 b0
0 0 0 : f(X
IN
)/8 or f(X
CIN
)/8
0 0 1 : f(X
IN
)/16 or f(X
CIN
)/16
0 1 0 : f(X
IN
)/32 or f(X
CIN
)/32
0 1 1 : f(X
IN
)/64 or f(X
CIN
)/64
1 1 0 : f(X
IN
)/128 or f(X
CIN
)/128
1 1 1 : f(X
IN
)/256 or f(X
CIN
)/256
Serial I/O1 port selection bit (P6
5
, P6
6
, and P6
7 ✽
)
0 : I/O port
1 : S
OUT1
,S
CLK11
,and S
CLK12 ✽
output pins
S
RDY1
output selection bit (P6
7
)
0 : I/O port
1 : S
RDY1
/CS
✽
output pin (Note)
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P6
5
/S
OUT1
P-channel output disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
b7 Serial I/O1 control register
(SIO1CON(SC1) : address 0019
16
)
b0
Internal synchronous clock selection bits
b2 b1 b0
0 0 0 : f(X
IN
)/8 or f(X
CIN
)/8
0 0 1 : f(X
IN
)/16 or f(X
CIN
)/16
0 1 0 : f(X
IN
)/32 or f(X
CIN
)/32
0 1 1 : f(X
IN
)/64 or f(X
CIN
)/64
1 1 0 : f(X
IN
)/128 or f(X
CIN
)/128
1 1 1 : f(X
IN
)/256 or f(X
CIN
)/256
Serial I/O2 port selection bit (P5
1
, and P5
2
)
0 : I/O port
1 : S
OUT2
and S
CLK2
output pins
S
RDY2
output selection bit (P5
3
)
0 : I/O port
1 : S
RDY2
output pin
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P5
1
/S
OUT2
P-channel output disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
b7 Serial I/O2 control register
(SIO2CON(SC2) : address 001D
16
)
b0
Internal synchronous clock selection bits
b2 b1 b0
0 0 0 : f(X
IN
)/8 or f(X
CIN
)/8
0 0 1 : f(X
IN
)/16 or f(X
CIN
)/16
0 1 0 : f(X
IN
)/32 or f(X
CIN
)/32
0 1 1 : f(X
IN
)/64 or f(X
CIN
)/64
1 1 0 : f(X
IN
)/128 or f(X
CIN
)/128
1 1 1 : f(X
IN
)/256 or f(X
CIN
)/256
Serial I/O3 port selection bit (P5
5
and P5
6
)
0 : I/O port
1 : S
OUT3
and S
CLK3
output pins
S
RDY3
output selection bit (P5
7
)
0 : I/O port
1 : S
RDY3
and S
CLK3
output pins
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P5
5
/S
OUT3
P-channel output disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
b7 Serial I/O3 control register
(SIO3CON(SC3) : address 001E
16
)
✽
: Valid only in serial I/O automatic transfer mode.
Note: When the external clock is selected in the serial I/O1 automatic transfer mode, the S
RDY1
signal pin becomes the CS signal input pin.
Fig. GA-2 Structure of serial I/O control registers
25
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(1) Serial I/O Ordinary Mode
Either an internal clock or an external clock can be selected
as the synchronous clock for serial I/O transfer. A dedicated
divider is built in as the internal clock for selecting of 6 clocks.
If internal clock is selected, transfer starts with a write signal
to a serial I/O register (addresses 001B16, 001F16, or
002616). After 8 bits have been transferred, the SOUT pin goes
to high impedance state.
If external clock is selected, control the clock externally be-
cause the contents of the serial I/O register continue to shift
during inputting the transfer clock. In this case, note that the
SOUT pin does not go to high impedance state at the comple-
tion of data transfer.
The interrupt request bit is set at the completion of the trans-
fer of 8 bits, regardless of whether the internal or external
clock is selected.
Fig. GA-3 Serial I/O timing in the serial I/O ordinary mode (for LSB first)
(2) Serial I/O Automatic Transfer Mode
The serial I/O1 has the automatic transfer function. For auto-
matic transfer, switch to the automatic transfer mode by
setting the serial I/O automatic transfer control register (ad-
dress 001A16).
The following memory spaces and registers used to enable
automatic transfer mode:
• 32-byte serial I/O automatic transfer RAM
• A serial I/O automatic transfer control register
• A serial I/O automatic transfer interval register
• A serial I/O automatic transfer data pointer
When using serial I/O automatic transfer, set the serial I/O1
control register (address 001916) in the same way as the se-
rial I/O ordinary mode. However, note that when external
clock is selected, port P67 becomes the CS input pin by set-
ting the bit 4 (the SRDY1 output selection bit ) of the serial I/O1
control register to “1”.
Serial I/O A utomatic Transfer Control Register
(SIOAC) 001A16
The serial I/O automatic transfer control register (address 001A16)
consists of 4 bits which control automatic transfer.
Fig. GA-4 Structure of serial I/O automatic transfer control register
D
1
Synchronous
clock
Interrupt request bit set
If internal clock is selected, the S
OUT
pin goes to high impedance state
at the completion of data transfer.
Note :
D
0
D
2
D
3
D
4
D
5
D
6
D
7
(Note)
Transfer clock
Serial I/O register
write signal
Serial I/O output
S
OUT
Serial I/O input
S
IN
Receive enable
signal
S
RDY
Automatic transfer control bit
0 : Serial I/O ordinary mode
(serial I/O1 interrupt)
1 : Automatic transfer mode
(serial I/O1 automatic transfer interrupt)
Automatic transfer start bit
0 : Transfer completion
1 : Transferring(starts by writing “1”)
Transfer mode switch bit
0 : Fullduplex(transmit and receive)
mode
1 : Transmit-only mode
Synchronous clock output
pin selection bit
0 : S
CLK11
1 : S
CLK12
Not used (return “0” when read)
b7 Serial I/O automatic transfer control register
(SIOAC : address 001A
16
)
b0
26
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Serial I/O Automatic Transfer Data Pointer
(SIODP) 001816
The serial I/O automatic transfer data pointer (address 001816)
consists of 5 bits which indicate addresses in serial I/O automatic
transfer RAM (the value which adds 0F0016 to the serial I/O auto-
matic transfer data pointer is actual address in memory).
Set the value (the number of transfer data-1) to the serial I/O au-
tomatic transfer data pointer for specifying the storage address of
first data.
●Serial I/O Automatic Transfer RAM
The serial I/O automatic transfer RAM is the 32 bytes from ad-
dress 0F0016 to address 0F1F16.
●Setting of Serial I/O Automatic Transfer
Data
When data is stored in the serial I/O automatic transfer RAM,
store the first data at the address set with the serial I/O auto-
matic transfer data pointer so that the last data can be stored
at address 0F0016.
Serial I/O Automatic Transfer Interval Register
(SIOAI) 001C16
The serial I/O automatic transfer interval register (address
001C16) consists of a 5-bit counter that determines the transfer in-
terval Ti during automatic transfer.
When writing the value n to the serial I/O automatic transfer inter-
val register, Ti=(n+2) ✕ Tc (Tc: the length of one bit of the transfer
clock) occurs. However, note that this transfer interval setting is
valid only when selecting the internal clock as the clock source.
Fig. GA-5 Bit allocation of serial I/O automatic transfer RAM
Fig. GA-6 Serial I/O automatic transfer interval timing
Bit
Address
0F00
16
0F01
16
0F02
16
0F1D
16
0F1E
16
0F1F
16
76543210
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
T
C
T
i
1-byte data
Transfer clock
Serial I/O output
S
OUT
Serial I/O input
S
IN
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
27
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
●Setting of Serial I/O Automatic Transfer
Timing
The timing of serial I/O automatic transfer is set with the serial
I/O1 control register (address 001916) and the serial I/O auto-
matic transfer interval register (address 001C16).
The serial I/O1 control register sets the transfer clock speed,
and the serial I/O automatic transfer interval register sets the
serial I/O automatic transfer interval. This setting of transfer in-
terval is valid only when selecting the internal clock as the
clock source.
●Start of Serial I/O Automatic Transfer
Automatic transfer mode is set by writing “1” to the bit 0 of the
serial I/O automatic transfer control register (address 001A16),
then automatic transfer starts by writing “1” to the bit 1.
The bit 1 of the serial I/O automatic transfer control register is
always “1” during automatic transfer; writing “0” can complete
the serial I/O automatic transfer.
●Operation in Serial I/O Automatic Transfer
Modes
There are two modes for serial I/O automatic transfer: full du-
plex mode and transmit-only mode. Either internal or external
clock can be selected for each of these modes.
(2.1) Operation in Full Duplex Mode
In full duplex mode, data can be transmitted and received at the
same time. Data in the automatic transfer RAM is transmitted in
sequence in accordance with the serial I/O automatic transfer data
pointer and simultaneously reception data is written to the auto-
matic transfer RAM.
The transfer timing of each bit is the same as that in ordinary op-
eration mode, and the transfer clock stops at “H” after eight
transfer clocks are counted.
When selecting the internal clock, the transfer clock remains at “H”
for the time set with the serial I/O automatic transfer interval regis-
ter, then the data at the next address (the address is indicated with
the serial I/O automatic transfer data pointer) are transferred.
If when selecting the external clock, the setting of the automatic
transfer interval register is invalid, so control the transfer clock ex-
ternally.
The last data transfer completes when the contents of the serial
I/O automatic transfer pointer reach “0016”. At that point, the serial
I/O automatic transfer interrupt request bit is set to “1” and the bit
1 of the serial I/O automatic transfer control register is cleared to
“0” to complete the serial I/O automatic transfer.
(2.2) Operation in Transmit-Only Mode
The operation in transmit-only mode is the same as that in full du-
plex mode, except for that data is not transferred from the serial
I/O1 register to the serial I/O automatic transfer RAM.
Fig. GA-7 Serial I/O1 register transfer operation in full duplex mode
•
•
•
DO
7
DO
6
DO
5
DO
4
DO
3
DO
2
DO
1
DO
0
Transfer clock
DI
1
DI
0
DO
7
DO
6
DO
5
DO
4
DO
3
DO
2
DI
2
DI
1
DI
7
DI
6
DI
5
DI
4
DI
3
DI
2
DI
1
DI
0
DO
7
DO
6
DO
5
DO
4
DO
3
DO
7
DO
6
DO
5
DO
4
DO
3
DO
2
DO
1
DI
0
Transfer direction selection bit LSB first (SC1
5
= “0” ) : MSB
MSB first (SC1
5
= “1” ) : LSB LSB
MSB
S
OUT
S
IN
Serial I/O1 register
DI
0
28
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(2.3) When Selecting the Internal Clock
When selecting the internal clock, the P67/SRDY1/CS/SCLK12 pin
can be used as the SRDY1 pin by setting SC14 to “1”.
When selecting the internal clock, the P67 pin can be used as the
synchronous clock output pin SCLK12 by setting SIOAC3 to “1”. In
this case, the SCLK11 pin goes to high impedance state.
Select the function of the P67/SRDY1/CS/SCLK12 and P66/SCLK11
with the following registers (refer to Table GA-1):
●the bit 3 (SC13), the bit 4(SC14), and the bit 6(SC16) of the se-
rial I/O1 control register
●the bit 3 (SIOAC3) of the serial I/O automatic transfer control
register
When using both the SCLK11 and SCKL12 by switching, switch the
P67/SRDY1/CS/SCLK12 to the P67 (SC14=0) and set the P67 direc-
tion register to input mode. Note that switch SIOAC3 during “H” of
transfer clock at the completion of automatic transfer.
Table GA-1. SCLK11 and SCLK12 selection
SC16
1
SC14
0
SC33
1
SIOAC3
0
1
P6
6
/S
CLK11
SCLK11
High
impedance
P6
7
/S
CLK12
P67
SCLK12
Note : SC13: Serial I/O1 port selection bit
SC14: SRDY1 output selection bit
SC16: Synchronous clock selection bit
SIOAC3: Synchronous clock output pin selection bit
Fig. GA-8 Timing diagram during serial I/O automatic transfer (internal clock selected, SRDY used)
Fig. GA-9 Timing during serial I/O automatic transfer (internal clock selected, SCLK11 and SCLK12 used)
DI
6
DI
0
DO
0
DO
7
Bit 1 write signal of serial I/O
automatic transfer control
register
Serial I/O output
S
out
Serial I/O input
S
IN
DI
0
Transfer interval
Bit 1 of serial I/O automatic
transfer control register
Write signal from RAM to
serial I/O1 register
Write signal from serial I/O1
register to RAM
Transfer clock
Data pointer
(internal or S
CLK
output)
Receive
enabled signal
S
RDY
n-1 0n
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
6
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
7
DO
0
DI7
Bit 1 write signal of serial I/O
automatic transfer control
register
Serial I/O output
S
out
Serial I/O input
S
IN
Transfer interval
Bit 1 of serial I/O automatic
transfer control register
Write signal from RAM to
serial I/O1 register
Write signal from serial I/O1
register to RAM Data pointer m-1 0
m
DO0
Bit 3 of serial I/O automatic
transfer control register
Transfer clock
(internal)
S
CLK11
output
S
CLK12
output
n
DO1DO2DO3DO4DO5DO6DO7DO0DO6DO7DO0DO1DO2DO3
DI0DI1DI2DI3DI4DI5DI6DI
7DI0DI0DI1DI2DI
3
DI6
29
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table GA-2. P67/SRDY1/CS selection
(2.4) When Selecting the External Clock
When selecting the external clock, the internal clock and the set-
ting of transfer interval with the serial I/O automatic transfer
interval register are invalid, but the serial I/O output pin SOUT1 and
the internal transfer clock can be controlled from the outside by
setting the SRDY1 pin to the CS (input) pin.
When the CS input is “L”, the SOUT1 pin and the internal transfer
clock are enabled.
When the CS input is “H”, the SOUT1 pin goes to high impedance
state and the internal transfer clock goes to “H”.
Select the function of the P67/SRDY1/CS/SCLK12 with the following
registers (refer to Table GA-2):
●the bit 4 (SC14) and the bit 6 (SC16) of the serial I/O1 control
register
●the bit 0 (SIOAC0) of the serial I/O automatic transfer control
register
Switch the CS pin from “L” to “H” or from “H” to “L” during “H” of the
transfer clock (SCLK11 input) after transferring 1-byte data.
When selecting the external clock, set the external clock to “L” af-
ter 9 cycles or more of the internal clock φ after setting the start
bit. After transferring 1-byte data, leave 11 cycles or more of the
internal clock φ free for the transfer interval.
When not using the CS input, note that the SOUT pin will not go to
high impedance state, even after transfer is completed.
When not using the CS input, or when CS is “L”, control the exter-
nal clock because the data in the serial I/O register will continue to
shift while the external clock is input, even after the completion of
automatic transfer (Note that the automatic transfer interrupt re-
quest bit is set and the bit 1 of the serial I/O automatic transfer
register is cleared at the point when the specified number of bytes
of data have been transferred.)
SC16
0
SC14
0
1
SIOAC0
✕
0
1
P67/SRDY1/CS
P67
SRDY1
CS
Note : SC14: SRDY1 output selection bit
SC16: Synchronous clock selection bit
SIOAC0: Automatic transfer control bit
Fig. GA-10 Timing during serial I/O automatic transfer (external clock selected)
X
Bit 1 write signal of serial I/O
automatic transfer control
register
Serial I/O output
S
OUT
Serial I/O input
S
IN
Note: Data marked with X is invalid.
Bit 1 of serial I/O automatic
transfer control register
Write signal from RAM to
serial I/O1 register
Write signal from serial I/O1
register to RAM
Transfer clock
(internal)
Data pointer
CS
n-1
n
DO
0
X
Transfer clock
S
CLK
input
External input
XDO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
XXX
30
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
A-D CONVER TER
The functional blocks of the A-D converter are described below.
A-D Conversion Register (AD) 002D16
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. This register should not be read dur-
ing A-D conversion.
AD/DA Control Register (ADCON) 002C16
The AD/DA control register controls the A-D and the D-A conver-
sion process. Bits 0 to 3 of this register select analog input pins.
Bit 4 is the AD conversion completion bit. The value of this bit re-
mains at “0” during an A-D conversion, then changes to “1” when
the A-D conversion is completed.
The A-D conversion starts by writing “0” to this bit. Bit 6 controls
the output of D-A converter.
Comparison V oltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P77/AN7–P70/
AN0, P57/SRDY3/AN15–P50/SIN2/AN8, and inputs to the compara-
tor.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
conversion interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to 500 kHz or more during A-D conversion.
Note : When using the A-D conversion interrupt, set the INT4/AD conver-
sion interrupt switch bit (the bit 5 of the interrupt selection register)
to “1”.
Fig. JA-1 Structure of A-D control register
Analog input pin selection bits
b3 b2 b1 b0
0 0 0 0 : P7
0
/AN
0
0 0 0 1 : P7
1
/AN
1
0 0 1 0 : P7
2
/AN
2
0 0 1 1 : P7
3
/AN
3
0 1 0 0 : P7
4
/AN
4
0 1 0 1 : P7
5
/AN
5
0 1 1 0 : P7
6
/AN
6
0 1 1 1 : P7
7
/AN
7
1 0 0 0 : P5
0
/S
IN2
/AN
8
1 0 0 1 : P5
1
/S
OUT2
/AN
9
1 0 1 0 : P5
2
/S
CLK2
/AN
10
1 0 1 1 : P5
3
/S
RDY2
/AN
11
1 1 0 0 : P5
4
/S
IN3
/AN
12
1 1 0 1 : P5
5
/S
OUT3
/AN
13
1 1 1 0 : P5
6
/S
CLK3
/AN
14
1 1 1 1 : P5
7
/S
RDY3
/AN
15
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
DA output enable bit
0 : Disable
1 : Enable
Not used (returns “0” when read)
b7 AD/DA control register
(ADCON : address 002C
16
)
b0
31
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. JA-2 A-D converter block diagram
D-A CONVERTER
The 3819 group has internal D-A converter with 8-bit resolutions ✕
1 channel.
D-A conversion is performed by setting the value in the D-A con-
version register. The result of D-A conversion is output from the
DA pin by setting the DA output enable bit to “1” . At this time, the
corresponding bit (PB2/DA) of the port PB direction register should
be set to “0” (input status).
The output analog voltage V is determined with the value n
(n: decimal number) in the D-A conversion register as follows:
V=VREF ✕ n/256 (n=0 to 255)
✽VREF: the reference voltage
At reset, the D-A conversion register is cleared to “0016”, the DA
output enable bits are cleared to “0”, and the PB2/DA pin goes to
high impedance state. The D-A output does not build in a buffer, so
connect an external buffer when driving a low-impedance load.
Set VCC to 3.0 V or more when using the D-A converter.
Fig. JB-1 D-A converter block diagram
Fig. JB-2 Equivalent connection circuit of D-A converter
Channel selector
A-D control circuit
A-D conversion register
Resistor ladder
V
REF
AV
SS
Comparator
A-D conversion interrupt request
b7 b0
4
8
P7
0
/AN
0
(Address 002D
16
)
AD-DA control register
(address 002C
16
)
P7
1
/AN
1
P7
2
/AN
2
P7
3
/AN
3
P7
4
/AN
4
P7
5
/AN
5
P7
6
/AN
6
P7
7
/AN
7
P5
0
/S
IN2
/AN
8
P5
1
/S
out2
/AN
9
P5
2
/S
CLK2
/AN
10
P5
3
/S
RDY2
/AN
11
P5
4
/S
IN3
/AN
12
P5
5
/S
OUT3
/AN
13
P5
6
/S
CLK3
/AN
14
P5
7
/S
RDY3
/AN
15
Data bus
Data bus
PB
2
/DA
D-A conversion register (8)
R-2R resistor ladder
DA output enable bit
AV
SS
V
REF
"0"
"1"
MSB
"0" "1"
R
2R LSB
PB
2
/DA
D-A conversion
register
DA output enable bit
2R 2R 2R 2R 2R 2R 2R
RR RRRR2R
32
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
G1 (SEG PA)
0F80
16
FLD automatic
display RAM
G2 (SEG PA)
G15 (SEG PA)
G16 (SEG PA)
G1 (SEG P8)
G2 (SEG P8)
0F8F
16
0F90
16
G15 (SEG P8)
G16 (SEG P8)
G1 (SEG P9)
G2 (SEG P9)
0F9F
16
0FA0
16
G15 (SEG P9)
G16 (SEG P9)
G1 (SEG P3)
G2 (SEG P3)
0FAF
16
0FB0
16
G15 (SEG P3)
G16 (SEG P3)
G1 (SEG P0)
G2 (SEG P0)
0FBF
16
0FC0
16
G15 (SEG P0)
G16 (SEG P0)
G1 (SEG P1)
G2 (SEG P1)
0FCF
16
0FD0
16
G15 (SEG P1)
G16 (SEG P1)
0FDF
16
Local
address bus
Main
address bus
Address
decoder FLD data pointer
(address 0038
16
)
FLD data pointer
reload register
(address 0038
16
)
Timing
generator FLD blanking interrupt
FLD digit interrupt
PA
1
/SEG
1
S/P PA
0
/SEG
0
S/P
PA
2
/SEG
2
S/P PA
3
/SEG
3
S/P PA
4
/SEG
4
S/P PA
5
/SEG
5
S/P PA
6
/SEG
6
S/P PA
7
/SEG
7
S/P
0014
16
0035
16
8
P8
1
/SEG
9
S/P P8
0
/SEG
8
S/P
P8
2
/SEG
10
S/P P8
3
/SEG
11
S/P P8
4
/SEG
12
S/P P8
5
/SEG
13
S/P P8
6
/SEG
14
S/P P8
7
/SEG
15
S/P
0010
16
0034
16
8
P9
1
/SEG
17
P9
0
/SEG
16
P9
2
/SEG
18
P9
3
/SEG
19
P9
4
/SEG
20
P9
5
/SEG
21
P9
6
/SEG
22
P9
7
/SEG
23
0012
16
8
P0
1
/SEG
33
/DIG
1
S/D P0
0
/SEG
32
/DIG
0
S/D
P0
2
/SEG
34
/DIG
2
S/D P0
3
/SEG
35
/DIG
3
S/D P0
4
/SEG
36
/DIG
4
S/D P0
5
/SEG
37
/DIG
5
S/D P0
6
/SEG
38
/DIG
6
S/D P0
7
/SEG
39
/DIG
7
S/D
0000
16
0032
16
8
P2
1
/DIG
17
D/P P2
0
/DIG
16
D/P
P2
2
/DIG
18
D/P P2
3
/DIG
19
D/P
4
FLDC mode
register 1
(address 0036
16
)
P1
1
/SEG
41
/DIG
9
S/D P1
0
/SEG
40
/DIG
8
S/D
P1
2
/DIG
10
P1
3
/DIG
11
P1
4
/DIG
12
P1
5
/DIG
13
P1
6
/DIG
14
P1
7
/DIG
15
0002
16
0037
16
8
P3
1
/SEG
25
P3
0
/SEG
24
P3
2
/SEG
26
P3
3
/SEG
27
P3
4
/SEG
28
P3
5
/SEG
29
P3
6
/SEG
30
P3
7
/SEG
31
0006
16
8
Main
data bus Local
data bus
0004
16
0033
16
FLD CONTROLLER
The 3819 group has fluorescent display (FLD) drive and control
circuits.
The FLD controller consists of the following components:
• 42 pins for segments
• 20 pins for digits
• FLDC mode register 1
• FLDC mode register 2
• FLD data pointer
• FLD data pointer reload register
• Port P0 segment/digit switch register
• Port P2 digit/port switch register
• Port PA segment/port switch register
• Port P8 segment/port switch register
• 96-byte FLD automatic display RAM
The segment pins can be used from 16 up to 42 pins (maximum)
and the digit pins can be used from 6 up to 16 pins (maximum).
The segment and the digit pins can be used up to 52 pins (maxi-
mum) in total.
In the FLD automatic display mode ports P12 to P17 become digit
pins DIG10 to DIG15 automatically.
Fig. KA-1 FLD control circuit block diagram
33
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
FLDC Mode Registers (FLDM 1, FLDM 2)
003616, 003716
The FLDC mode register 1 (address 003616) and FLDC mode reg-
ister 2 (address 003716) are a seven bit register and an eight bit
register respectively which are used to control the FLD automatic
display and set the blanking time Tscan for key-scan.
Fig. KA-2 Structure of FLDC mode register 1
Fig. KA-3 Structure of FLDC mode register 2
T
scan
control bits
b1
b0
0 0 : 0 FLD digit interrupt (at rising edge of each digit)
0 1 : 1 ✕ T
disp
1 0 : 2 ✕ T
disp
1 1 : 3 ✕ T
disp
T
off
control bits
(Setting of digit/segment OFF time)
b5
b4
b3
b2
0 0 0 0 : 1/16 ✕ T
disp
0 0 0 1 : 2/16 ✕ T
disp
0 0 1 0 : 3/16 ✕ T
disp
0 0 1 1 : 4/16 ✕ T
disp
0 1 0 0 : 5/16 ✕ T
disp
0 1 0 1 : 6/16 ✕ T
disp
0 1 1 0 : 7/16 ✕ T
disp
0 1 1 1 : 8/16 ✕ T
disp
1 0 0 0 : 9/16 ✕ T
disp
1 0 0 1 : 10/16 ✕ T
disp
1 0 1 0 : 11/16 ✕ T
disp
1 0 1 1 : 12/16 ✕ T
disp
1 1 0 0 : 13/16 ✕ T
disp
1 1 0 1 : 14/16 ✕ T
disp
1 1 1 0 : 15/16 ✕ T
disp
1 1 1 1 : 16/16 ✕ T
disp
Not used (returns “0” when read)
High-breakdown-voltage drivability selection bit
0 : Strong drivability
1 : Weak drivability
b7 FLDC mode register 1
(FLDM 1 : address 0036
16
)
b0
FLD blanking interrupt
(at falling edge of the last digit)
Automatic display control bit(P0, P1, P2
0
–P2
3
, P3, P8, P9, PA)
0 : Ordinary mode
1 : Automatic display mode
Display start bit
0 : Display stopped
1 : Display in progress
(display starts by writing “1” to this bit which is set to “0”)
T
disp
control bits
(digit time setting, at 8 MHz oscillation frequency)
b5
b4
b3
b2
0 0 0 0 : 128 µs
0 0 0 1 : 256 µs
0 0 1 0 : 384 µs
0 0 1 1 : 512 µs
0 1 0 0 : 640 µs
0 1 0 1 : 768 µs
0 1 1 0 : 896 µs
0 1 1 1 : 1024 µs
1 0 0 0 : 1152 µs
1 0 0 1 : 1280 µs
1 0 1 0
1 1 1 1
Pl
0
segment/digit switch bit
0 : Digit
1 : Segment
Pl
1
segment/digit switch bit
0 : Digit
1 : Segment
b7 FLDC mode register 2
(FLDM 2 : address 0037
16
)
b0
Not available
34
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
DIG
10
G
10
DIG
9
G
11
DIG
10
G
10
PA
7
PA
1
PA
0
PA
3
PA
2
PA
5
PA
4
PA
6
P8
7
P8
1
P8
0
P8
3
P8
2
P8
5
P8
4
P8
6
SEG
23
SEG
17
SEG
16
SEG
19
SEG
18
SEG
21
SEG
20
SEG
22
Port PA
(has the segment/port
switch register)
Number of segments
Number of digits
0
0
0
0
0
0
0
0
24
8
Port P8
(has the segment/port
switch register)
0
0
0
0
0
0
0
0
Port P9
(segment only)
PA
7
PA
1
PA
0
PA
3
PA
2
PA
5
PA
4
PA
6
SEG
15
P8
1
P8
0
P8
3
P8
2
SEG
13
SEG
12
SEG
14
SEG
23
SEG
17
SEG
16
SEG
19
SEG
18
SEG
21
SEG
20
SEG
22
0
0
0
0
0
0
0
0
30
10
1
0
0
0
0
1
1
1
SEG
7
SEG
1
SEG
0
SEG
3
SEG
2
SEG
5
SEG
4
SEG
6
SEG
15
SEG
9
SEG
8
SEG
11
SEG
10
SEG
13
SEG
12
SEG
14
SEG
23
SEG
17
SEG
16
SEG
19
SEG
18
SEG
21
SEG
20
SEG
22
1
1
1
1
1
1
1
1
36
16
1
1
1
1
1
1
1
1SEG
39
SEG
33
SEG
32
SEG
35
SEG
34
SEG
37
SEG
36
SEG
38
DIG
8
G
8
Port P3
(segment only)
Number of segments
Number of digits 24
8
Port P0
(has the segment/digit
switch register)
1
1
1
1
1
1
1
1
Port P1
(has the segment/digit
switch register)
SEG
39
SEG
33
SEG
32
SEG
35
SEG
34
SEG
37
SEG
36
SEG
38
30
10
1
1
1
1
1
1
1
1DIG
7
G
13
SEG
33
SEG
32
SEG
35
SEG
34
DIG
5
G
15
DIG
4
G
16
DIG
6
G
14
36
16
0
1
1
1
1
0
0
0
SEG
31
SEG
25
SEG
24
SEG
27
SEG
26
SEG
29
SEG
28
SEG
30
SEG
31
SEG
25
SEG
24
SEG
27
SEG
26
SEG
29
SEG
28
SEG
30
SEG
31
SEG
25
SEG
24
SEG
27
SEG
26
SEG
29
SEG
28
SEG
30
0
0DIG
9
G
7
DIG
10
G
6
DIG
11
G
5
DIG
12
G
4
DIG
13
G
3
DIG
14
G
2
DIG
15
G
1
SEG
40
1
1SEG
41
DIG
11
G
9
DIG
12
G
8
DIG
13
G
7
DIG
14
G
6
DIG
15
G
5
DIG
8
G
12
0
0
DIG
11
G
9
DIG
12
G
8
DIG
13
G
7
DIG
14
G
6
DIG
15
G
5
Port P2
(has the digit/port
switch register) 1
1
1
1
DIG
16
G
4
DIG
17
G
3
DIG
18
G
2
DIG
19
G
1
1
1
1
1
DIG
16
G
4
DIG
17
G
3
DIG
18
G
2
DIG
19
G
1
0
0
0
0
P2
0
P2
1
P2
2
P2
3
●Pins for FLD Automatic Display
Ports P0, P1, P20–P23, P3, P8, P9, and PA is selected for the
FLD automatic display function by setting the automatic display
control bit of the FLDC mode register 2 (address 003716) to
“1”.
When using the FLD automatic display mode, set the number
of segments and digits for each port.
Table L-1. Pins in FLD automatic display mode
Port Name
PA0–PA7
P80–P87
P90–P97
P30–P37
P00–P07
P10, P11
P12–P17
P20–P23
Automatic Display Pins
SEG0–SEG7
or
PA0–PA7
SEG8–SEG15
or
P80–P87
SEG16–SEG23
SEG24–SEG31
SEG32–SEG41
or
DIG0–DIG9
DIG10–DIG15
DIG16–DIG19
or
P20–P23
Setting Method
The individual bits of the segment/port switch register (address 003516) can be set each pin
to either segment (“1”) or general-purpose I/O port (“0”).
The individual bits of the segment/port switch register (address 003416) can be used to set
each pin to either segment (“1”) or general-purpose I/O port (“0”).
None (segment only)
None (segment only)
The individual bits of the segment/digit switch register (address 003216) and the bit 6, 7 of
the FLDC mode register 2 can be used to set each pin to segment (“1”) or digit (“0”). (Note)
None (digit only)
The individual bits of the digit/port switch register (address 003316) can be used to set each
pin to digit (“1”) or general-purpose output port (“0”). (Note)
Note : Be sure to set digits in sequence.
Fig. KA-4 Segment/digit setting example
35
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
●FLD Automatic Display RAM
The FLD automatic display RAM area is the 96 bytes from ad-
dresses 0F8016 to 0FDF16. The FLD automatic display RAM
area can store 6-byte segment data up to 16 digits (maximum).
Addresses 0F8016 to 0F8F16 are used for PA segment data,
addresses 0F9016 to 0F9F16 are used for P8 segment data,
addresses 0FA016 to 0FAF16 are used for P9 segment data,
addresses 0FB016 to 0FBF16 are used for P3 segment data,
addresses 0FC016 to 0FCF16 are used for P0 segment data,
and addresses 0FD0 to 0FDF16 are used for P1 segment data.
FLD Data Pointer and FLD Data Pointer
Reload Register (FLDDP) 003816
Both the FLD data pointer and FLD data pointer reload register
are 7-bit registers allocated at address 003816. When writing data
to this address, the data is written to the FLD data pointer reload
register, when reading data from this address, the value in the
FLD data pointer is read.
The FLD data pointer indicates the data address in the FLD auto-
matic display RAM to be transferred to a segment. The FLD data
pointer reload register indicates the first digit address of the most
significant segment.
The value which adds 0F8016 to these data is actual address in
memory.
The contents of the FLD data pointer indicate the first address of
segment P1(the contents of the FLD data pointer reload register)
at the start of automatic display. The FLDC data pointer content
changes repeatedly as follows: when transferring the segment P1
data to the segment, the content decreases by –16; when transfer-
ring the segment P0 data, it decreases by –16; when transferring
the segment P3 data, it decreases by –16; when transferring the
segment P9 data, it decreases by –16; when transferring the seg-
ment P8 data, it decreases by –16; when transferring the segment
PA data, it increases by +79. Once it reaches “00”, at the next tim-
ing the value in the FLD data pointer reload register is transferred
to the FLD data pointer. In this way, the 6-byte data of P1, P0, P3,
P9, P8 and PA segments for 1 digit are transferred.
36
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0F80
16
7
Bit
Address SEG
7
6
SEG
6
5
SEG
5
4
SEG
4
3
SEG
3
2
SEG
2
1
SEG
1
0
SEG
0
The last digit
(The last data of segment PA)
0F81
16
SEG
7
SEG
6
SEG
5
SEG
4
SEG
3
SEG
2
SEG
1
SEG
0
0F8E
16
SEG
7
SEG
6
SEG
5
SEG
4
SEG
3
SEG
2
SEG
1
SEG
0
0F8F
16
SEG
7
SEG
6
SEG
5
SEG
4
SEG
3
SEG
2
SEG
1
SEG
0
0F90
16
SEG
15
SEG
14
SEG
13
SEG
12
SEG
11
SEG
10
SEG
9
SEG
8
0F91
16
SEG
15
SEG
14
SEG
13
SEG
12
SEG
11
SEG
10
SEG
9
SEG
8
Segment PA
data area
The last digit
(The last data of segment P8)
Segment P8
data area
0F9E
16
SEG
15
SEG
14
SEG
13
SEG
12
SEG
11
SEG
10
SEG
9
SEG
8
0F9F
16
SEG
15
SEG
14
SEG
13
SEG
12
SEG
11
SEG
10
SEG
9
SEG
8
0FA0
16
SEG
23
SEG
22
SEG
21
SEG
20
SEG
19
SEG
18
SEG
17
SEG
16
0FA1
16
SEG
23
SEG
22
SEG
21
SEG
20
SEG
19
SEG
18
SEG
17
SEG
16
The last digit
(The last data of segment P9)
Segment P9
data area
0FAE
16
SEG
23
SEG
22
SEG
21
SEG
20
SEG
19
SEG
18
SEG
17
SEG
16
0FAF
16
SEG
23
SEG
22
SEG
21
SEG
20
SEG
19
SEG
18
SEG
17
SEG
16
0FB0
16
SEG
31
SEG
30
SEG
29
SEG
28
SEG
27
SEG
26
SEG
25
SEG
24
0FB1
16
SEG
31
SEG
30
SEG
29
SEG
28
SEG
27
SEG
26
SEG
25
SEG
24
The last digit
(The last data of segment P3)
Segment P3
data area
0FBE
16
SEG
31
SEG
30
SEG
29
SEG
28
SEG
27
SEG
26
SEG
25
SEG
24
0FBF
16
SEG
31
SEG
30
SEG
29
SEG
28
SEG
27
SEG
26
SEG
25
SEG
24
0FC0
16
SEG
39
SEG
38
SEG
37
SEG
36
SEG
35
SEG
34
SEG
33
SEG
32
0FC1
16
SEG
39
SEG
38
SEG
37
SEG
36
SEG
35
SEG
34
SEG
33
SEG
32
The last digit
(The last data of segment P0)
Segment P0
data area
0FCE
16
SEG
39
SEG
38
SEG
37
SEG
36
SEG
35
SEG
34
SEG
33
SEG
32
0FCF
16
SEG
39
SEG
38
SEG
37
SEG
36
SEG
35
SEG
34
SEG
33
SEG
32
0FD0
16
SEG
41
SEG
40
0FD1
16
SEG
41
SEG
40
The last digit
(The last data of segment P1)
Segment P1
data area
0FDE
16
SEG
41
SEG
40
0FDF
16
SEG
41
SEG
40
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fig. KA-5 FLD automatic display RAM and bit allocation
37
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
●Data Setup
When data is stored in the FLD automatic display RAM, the
last data of segment PA is stored at address 0F8016, the last
data of segment P8 is stored at address 0F9016, the last data
of segment P9 is stored at address 0FA016, the last data of
segment P3 is stored at address 0FB016, the last data of seg-
ment P0 is stored at address 0FC016, and the last data of
segment P1 is stored at address 0FD016 to allocate in se-
quence from the last data respectively. The first data of the
segment PA, P8, P9, P3, P0, and P1 is stored at an address
which adds the value of (the digit number–1) to the corre-
sponding address 0F8016, 0F9016, 0FA016, 0FB016, 0FC016,
and 0FD016.
Set the low-order 4 bits of the FLD data pointer reload register
to the value given by the number of digits–1. “1” is always writ-
ten to bit 6 and bit 4, and “0” is always written to bit 5. Note that
“0” is always read from bits 6, 5 and 4 when reading.
Fig. KA-6 Example of using the FLD automatic display RAM (1)
For 30 segments and 15 digits
(FLD data pointer reload register = 14)
0F80
16
7
Bit
Address 6543210
0F81
16
0F82
16
0F83
16
0F84
16
0F85
16
0F86
16
0F87
16
0F88
16
0F89
16
0F8A
16
0F8B
16
0F8C
16
0F8D
16
0F8E
16
0F8F
16
0F90
16
0F91
16
0F92
16
0F93
16
0F94
16
0F95
16
0F96
16
0F97
16
0F98
16
0F99
16
0F9A
16
0F9B
16
0F9C
16
0F9D
16
0F9E
16
0F9F
16
0FA0
16
0FA1
16
0FA2
16
0FA3
16
0FA4
16
0FA5
16
0FA6
16
0FA7
16
0FA8
16
0FA9
16
0FAA
16
0FAB
16
0FAC
16
0FAD
16
0FAE
16
0FAF
16
Note : Shaded areas are used.
For 30 segments and 15 digits
(FLD data pointer reload register = 14)
0FB0
16
7
Bit
Address 6543210
0FB1
16
0FB2
16
0FB3
16
0FB4
16
0FB5
16
0FB6
16
0FB7
16
0FB8
16
0FB9
16
0FBA
16
0FBB
16
0FBC
16
0FBD
16
0FBE
16
0FBF
16
0FC0
16
0FC1
16
0FC2
16
0FC3
16
0FC4
16
0FC5
16
0FC6
16
0FC7
16
0FC8
16
0FC9
16
0FCA
16
0FCB
16
0FCC
16
0FCD
16
0FCE
16
0FCF
16
0FD0
16
0FD1
16
0FD2
16
0FD3
16
0FD4
16
0FD5
16
0FD6
16
0FD7
16
0FD8
16
0FD9
16
0FDA
16
0FDB
16
0FDC
16
0FDD
16
0FDE
16
0FDF
16
38
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. KA-6 Example of using the FLD automatic display RAM (2) (continued)
For 42 segments and 8 digits
(FLD data pointer reload register = 7)
0F80
16
7
Bit
Address 6543210
0F81
16
0F82
16
0F83
16
0F84
16
0F85
16
0F86
16
0F87
16
0F88
16
0F89
16
0F8A
16
0F8B
16
0F8C
16
0F8D
16
0F8E
16
0F8F
16
0F90
16
0F91
16
0F92
16
0F93
16
0F94
16
0F95
16
0F96
16
0F97
16
0F98
16
0F99
16
0F9A
16
0F9B
16
0F9C
16
0F9D
16
0F9E
16
0F9F
16
0FA0
16
0FA1
16
0FA2
16
0FA3
16
0FA4
16
0FA5
16
0FA6
16
0FA7
16
0FA8
16
0FA9
16
0FAA
16
0FAB
16
0FAC
16
0FAD
16
0FAE
16
0FAF
16
Note : Shaded areas are used.
For 42 segments and 8 digits
(FLD data pointer reload register = 7)
0FB0
16
7
Bit
Address 6543210
0FB1
16
0FB2
16
0FB3
16
0FB4
16
0FB5
16
0FB6
16
0FB7
16
0FB8
16
0FB9
16
0FBA
16
0FBB
16
0FBC
16
0FBD
16
0FBE
16
0FBF
16
0FC0
16
0FC1
16
0FC2
16
0FC3
16
0FC4
16
0FC5
16
0FC6
16
0FC7
16
0FC8
16
0FC9
16
0FCA
16
0FCB
16
0FCC
16
0FCD
16
0FCE
16
0FCF
16
0FD0
16
0FD1
16
0FD2
16
0FD3
16
0FD4
16
0FD5
16
0FD6
16
0FD7
16
0FD8
16
0FD9
16
0FDA
16
0FDB
16
0FDC
16
0FDD
16
0FDE
16
0FDF
16
39
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
G n
G n-1
G n-2
G 1
T
scan
T
disp
Segment
output
FLD digit interrupt occurs
at the rising edge of each digit FLD blanking interrupt occurs
at the falling edge of the last digit
Segment setting by software
T
off
T
disp
Digit
Segment
●Timing Setting
The digit time (Tdisp) can be set with the FLDC mode register 2
(address 003716). The Tscan and digit/segment OFF time (Toff)
can be set with the FLDC mode register 1 (address 003616).
Note that flickering will occur if the repetition frequency (1/
(Tdisp ✕ number of digits + Tscan)) is an integral multiple of the
digit timing Tdisp.
●FLD Automatic Display Start
To perform FLD automatic display, set the following registers.
• Port P0 segment/digit switch register
• Port P2 digit/port switch register
• Port P8 segment/port switch register
• Port PA segment/port switch register
• FLDC mode register 1
• FLDC mode register 2
• FLD data pointer
Automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register 2 (address 003716), and the auto-
matic display is started by writing “1” to the bit 1.
During automatic display bit 1 of the FLDC mode register 2 al-
ways keeps “1”, automatic display can be interrupted by writing
“0” to the bit 1.
●Key-scan
If key-scan is performed with the segment during the key-scan
blanking period Tscan, take the following sequence:
1. Write “0” to the bit 0 (automatic display control bit) of the
FLDC mode register 2 (address 003716).
2. Set the port corresponding to the segment for key-scan to
the output port.
3. Perform the key-scan.
4. After the key-scan is performed, write “1” (automatic display
mode) to the bit 0 of FLDC mode register 2 (address
003716).
Note on performance of key-scan in the above 1 to 4 sequence.
1. Do not write “0” to the bit 1 of FLDC mode register 2 (ad-
dress 003716).
2. Do not write “1” to the port corresponding to the digit.
Fig. KA-7 FLDC timing
40
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INTERRUPT INTERVAL DETERMINATION
FUNCTION
The 3819 group builds in an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from
the rising transition (falling transition) of an input signal pulse on
the P42/INT2 pin to the rising transition (falling transition) of the
signal pulse that is input next.
How to determine the interrupt interval is described below.
➀Enable the INT2 interrupt by setting the bit 2 of the interrupt con-
trol register 1 (address 003E16). Select the rising interval or
falling interval by setting the bit 2 of the interrupt edge selection
register (address 003A16).
➁Set the bit 0 of the interrupt interval determination control regis-
ter (address 003116) to “1” (interrupt interval determination
operating).
➂Select the sampling clock of 8-bit binary up counter by setting
the bit 1 of the interrupt interval determination control register.
When writing “0”, f(XIN)/256 is selected (the sampling interval:
32 µs at f(XIN) = 8.38 MHz) ; when “1”, f(XIN)/512 is selected (the
sampling interval: 64 µs at f(XIN) = 8.38 MHz).
➃When the signal of polarity which is set on the INT2 pin (rising or
falling transition) is input, the 8-bit binary up counter starts
counting up of the selected counter sampling clock.
➄When the signal of polarity above ➃ is input again, the value of
the 8-bit binary up counter is transferred to the interrupt interval
determination register (address 003016), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter is cleared to “0016”. The 8-bit binary up counter con-
tinues to count up again from “0016”.
➅When count value reaches “FF16”, the 8-bit binary up counter
stops counting up. Then, simultaneously when the next counter
sampling clock is input, the counter sets value “FF16” to the in-
terrupt interval determination register to generate the counter
overflow interrupt request.
Noise filter
The P42/INT2 pin builds in the noise filter.
The noise filter operation is described below.
➀Select the sampling clock of the input signal with the bits 2 and
3 of the interrupt interval determination control register. When
not using the noise filter, set “002”.
➁The P42/INT2 input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in series,
the signal is recognized as the interrupt signal, and the interrupt
request occurs.
When setting the bit 4 of interrupt interval determination control
register to “1”, the interrupt request can occur at both rising and
falling edges.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 2 cycles or more.
Note : In the low-speed mode (CM7=1), the interrupt interval determination
function can not operate.
Fig. DE-1 Block diagram of interrupt interval datermination circuit
INT2 interrupt input
The counter
sampling clock
selection bit f(XIN)/256
f(XIN)/512
Noise filter sampling
clock selection bit
One-sided/both-sided
detection selection bit
Noise filter
8-bit binary up counter
Interrupt interval
determination register
The counter overflow
interrupt request or
remote control interrupt request
address 003016
Data bus
Divider
1/256
1/64 1/128
f(XIN)
41
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. DE-2 Structure of interrupt interval determination control register
Fig. DE-3 Interrupt interval determination operation example (at rising edge active)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(X
IN
)/256
1 : f(X
IN
)/512
Noise filter sampling clock selection bits(INT
2
)
0 0 : Filter stop
0 1 : f(X
IN
)/64
1 0 : f(X
IN
)/128
1 1 : f(X
IN
)/256
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection
Not used (return “0” when read)
b7 Interrupt interval determination control register
(IIDCON : address 0031
16
)
b0
Noise filter
Sampling clock
(When IIDCON
4
= “0”)
INT
2
pin
Acceptance
of interrupt
Counter
sampling clock
6 3 FF
6 3 FF
1
8-bit binary
up counter value
Interrupt interval
determination
register value Remote control
interrupt request Remote control
interrupt request Counter overflow
interrupt request
Remote control
interrupt request
N
23456
012301
FE FF
0 0
N
42
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. DE-4 Interrupt interval determination operation example (at both-sided edge active)
Noise filter
Sampling clock
(When IIDCON4 = “1”)
INT2 pin
Acceptance
of interrupt
Counter
sampling clock
FF
N
1
8-bit binary
up counter value
Interrupt interval
determination
register value Remote
control
interrupt
request
N
N
0101
FE FF
0 0
01234010
1
Remote
control
interrupt
request
1
4
Remote
control
interrupt
request
1
Remote
control
interrupt
request
4
1
Remote
control
interrupt
request
1
1
Remote
control
interrupt
request
1 1
FF
Counter
overflow
interrupt
request
43
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
ZERO CROSS DETECTION CIRCUIT
The zero cross detection circuit compares the voltage applied to
P45/INT1/ZCR pin and VSS. The result can be read from the zero
cross detection circuit input bit (bit 7) of the zero cross detection
control register. It is set to “1” when the input voltage is higher than
VSS and to “0” when it is lower than VSS. The input signal to P45/
INT1/ZCR pin can select to either pass through the zero cross de-
tection comparator or not to do.
When using 100 V AC as input signal, insert an external circuit be-
tween it and P45/INT1/ZCR pin. Set the input current limiting
resistors used in the external circuit to a value which satisfies the
absolute maximum rating of port P45.
Fig. JE-1 External circuit example for zero cross detection
Fig. JE-3 Block diagram of zero cross detection circuit
Fig. JE-2 Structure of zero cross detection control register
V
CC
R
1
R
2
P4
5
/INT
1
/ZCR
V
SS
100V AC
Zero cross detection ON/OFF selection bit
0 : Without passing through zero cross detection comparator
1 : Passing through zero cross detection comparator
Not used (returns “0” when read)
Noise filter sampling clock selection bits (INT
1
)
b3 b2
0 0 : Not use noise filter
0 1 : f(X
IN
)/64 or f(X
CIN
)/64
1 0 : f(X
IN
)/128 or f(X
CIN
)/128
1 1 : f(X
IN
)/256 or f(X
CIN
)/256
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection
Not used (return “0” when read)
Zero cross detection circuit input bit (read only)
0 : Less than 0 V
1 : 0 V or more
b7 Zero cross detection control register
(ZCRCON : address 0039
16
)
b0
P4
5
/INT
1
/ZCR Zero cross detection
ON/OFF selection bit
“0”
“1”
Zero cross detection
circuit input bit
Rising/falling
edge switch
Noise filter
When not using
the filter
When using
the filter
INT
1
/ZCR
interrupt request
One-sided/both-sided edge
detection selection bit
Noise filter sampling clock
selection bit
Zero cross detection comparator
f(X
CIN
)
f(X
IN
)Divider
1/64
1/256
1/28
44
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
NOISE FILTER
The noise filter uses a sampling clock to remove the noise compo-
nent digitally from the input signal of P45/INT1/ZCR pin. The
sampling clock can be selected from 8 µs, 16 µs, or 32 µs (at
f(XIN)= 8.38 MHz) and this is used to change the noise component
to be removed. It is also possible to generate an internal trigger
and INT1/ZCR interrupt request directly without passing through
the noise filter. When passing through the noise filter, either both-
sided edge detection or one-sided edge detection can be selected
as the interrupt request generating source. The zero cross detec-
tion control register is used for this selection. Furthermore, switch
between rising edge and falling edge is performed with the bit 1 of
the interrupt edge selection register (address 003A16).
Fig. JE-4 Noise filter circuit diagram
Fig. JE-5 Timing of noise filter circuit
Input signal from
P4
5
/INT
1
/ZCR pin
Sampling clock
RESET
R
QD
C
R
QD
C
QS
R
R
QD
C
“1”
“0”
One-sided/both-sided edge
detection selection bit
(bit 4 of ZCRCON)
INT
1
/ZCR
interrupt request
C
BA
RESET
Sampling clock
Input signal from
P4
5
/INT
1
/ZCR pin
A
B
C
(one-sided edge)
(both-sided edge)
INT
1
/ZCR
interrupt request
P4
5
/INT
1
/ZCR (Note 1) 0 V
(Note 2) Switched with
bit 4 of ZCRCON
: Ignored this because of treating this as noise
: INT
1
/ZCR interrupt request occurs
Notes 1
2
45
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between 2.8 V and 5.5
V, and XIN oscillation is stable), reset is released. In order to give
the XIN clock time to stabilize, internal operation does not begin
until after about 4000 XIN clock cycles (256 cycles of f(XIN)/16) are
completed. After the reset is completed, the program starts from
the address contained in address FFFD16 (high-order) and ad-
dress FFFC16 (low-order). Make sure that the reset input voltage
is 0.5 V or less for 2.8 V of VCC.
Fig. VB-2 Example of reset circuit
Fig. VB-2 Reset sequence
Note : Reset release voltage : VCC = 2.8 V
Power source
voltage
Poweron
(Note)
VCCRESET
VCCRESET Power source voltage
detection circuit
0 V
Reset input
voltage 0.2VCC
0 V
about 4000
X
IN
clock cycles
RESET
Internal reset
f(X
IN
) and f(φ) are in the relationship : f(X
IN
) = 8
•
f(φ)
A question mark (?) indicates an undefined state that depends on the previous state.
Notes 1 :
2 :
?
??
SYNC
Data
Address
φ
X
IN
Reset address from
vector table
? ? FFFC FFFD AD
H
, AD
L
???AD
L
AD
H
46
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. VB-3 Internal status at reset
01001000
00
16
(0000
16
)
• • •
(1) Port P0
✕ : Undefined
The contents of all other registers and RAM are undefined at reset, so set their initial values.
Note :
Register contentsAddress
00
16
(0002
16
)
• • •
(2) Port P1
00
16
(0004
16
)
• • •
(3) Port P2
0F
16
(0005
16
)
• • •
(4) Port P2 direction register
00
16
(0006
16
)
• • •
(5) Port P3
00
16
(0008
16
)
• • •
(6) Port P4
00
16
(0009
16
)
• • •
(7) Port P4 direction register
00
16
(000A
16
)
• • •
(8) Port P5
00
16
(000B
16
)
• • •
(9) Port P5 direction register
00
16
(000C
16
)
• • •
(10) Port P6
00
16
(000D
16
)
• • •
(11) Port P6 direction register
00
16
(000E
16
)
• • •
(12) Port P7
00
16
(000F
16
)
• • •
(13) Port P7 direction register
00
16
(0010
16
)
• • •
(14) Port P8
00
16
(0011
16
)
• • •
(15) Port P8 direction register
00
16
(0012
16
)
• • •
(16) Port P9
00
16
(0014
16
)
• • •
(17) Port PA
00
16
(0015
16
)
• • •
(18) Port PA direction register
00
16
(0016
16
)
• • •
(19) Port PB
00
16
(0017
16
)
• • •
(20) Port PB direction register
00
16
(0019
16
)
• • •
(21) Serial I/O1 control register
00
16
(001A
16
)
• • •
(22) Serial I/O automatic transfer
00
16
(001C
16
)
• • •
(23) Serial I/O automatic transfer
00
16
(001D
16
)
• • •
(24) Serial I/O2 control register
00
16
(001E
16
)
• • •
(25) Serial I/O3 control register
FF
16
(0020
16
)
• • •
(26) Timer 1
01
16
(0021
16
)
• • •
(27) Timer 2
FF
16
(0022
16
)
• • •
(28) Timer 3
FF
16
(0023
16
)
• • •
(29) Timer 4
FF
16
(0024
16
)
• • •
(30) Timer 5
FF
16
(0025
16
)
• • •
(31) Timer 6
Register contentsAddress
00
16
(0028
16
)
• • •
(32) Timer 12 mode register
00
16
(0029
16
)
• • •
(33) Timer 34 mode register
00
16
(002A
16
)
• • •
(34) Timer 56 mode register
00
16
(002B
16
)
• • •
(35) D-A conversion register
10
16
(002C
16
)
• • •
(36) AD/DA control register
00
16
(0031
16
)
• • •
(37) Interrupt interval determination
control register
00
16
(0032
16
)
• • •
(38) Port P0 segment/digit
switch register
00
16
(0033
16
)
• • •
(39) Port P2 digit/port switching
register
00
16
(0034
16
)
• • •
(40) Port P8 segment/port
switch register
00
16
(0035
16
)
• • •
(41) Port PA segment/port switch
00
16
(0036
16
)
• • •
(42) FLDC mode register 1
00
16
(0037
16
)
• • •
(43) FLDC mode register 2
00
16
(0039
16
)
• • •
(44) Zero cross detection control
register
00
16
(003A
16
)
• • •
(45) Interrupt edge selection register
(003B
16
)
• • •
(46) CPU mode register
00
16
(003C
16
)
• • •
(47) Interrupt request register 1
00
16
(003D
16
)
• • •
(48) Interrupt request register 2
00
16
(003E
16
)
• • •
(49) Interrupt control register 1
00
16
(003F
16
)
• • •
(50) Interrupt control register 2
✕
(PS)
• • •
(51) Processor status register
Contents of address FFFD16
(PC
H
)
• • •
(52) Program counter
control register
interval register
Contents of address FFFC16
(PC
L
)
• • •
✕✕✕✕1✕✕
47
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CLOCK GENERATING CIRCUIT
The 3819 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
Immediately after poweron, only the XIN oscillation circuit starts
oscillation, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
Middle-speed mode
The internal clock φ is the frequency of X IN divided by 8. After re-
set, this mode is selected.
High-speed mode
The internal clock φ is half the frequency of XIN.
Low-speed mode
The internal clock φ is half the frequency of XCIN.
Note : If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is re-
quired for the XCIN oscillation to stabilize, especially immediately
after poweron and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the frequency
on condition that f(XIN) > 3·f(XCIN).
Low-power dissipation mode
When stopping the main clock XIN in the low-speed mode, the low-
power dissipation operation starts. To stop the main clock, set the
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted, set enough time for oscillation to stabilize by program-
ming.
The low-power dissipation operation 200 µA or less (at f(XIN) = 32
kHz) can be realized by reducing the XCIN–XCOUT drivability. To re-
duce the XCIN–XCOUT drivability, clear the bit 3 of the CPU mode
register to “0”. At reset or when executing the STP instruction, this
bit is set to “1” and strong drivability is selected to help the oscilla-
tion to start.
Oscillation Control
Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is in-
put to timer 1, and the output of timer 1 is connected to timer 2.
The bits of the timer 12 mode register are cleared to “0”. Set the
timer 1 and timer 2 interrupt enable bits to disabled (“0”) before ex-
ecuting the STP instruction.
Oscillator restarts at reset or when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU until
timer 1 underflows. When using an external resonator, it is neces-
sary for oscillating to stabilize.
Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore executing the WIT instruction. The internal clock restarts at
reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
Fig. WA-1 Ceramic resonator external circuit
Fig. WA-2 External clock input circuit
X
CIN
X
COUT
C
CIN
C
COUT
R
d
R
f
X
IN
X
OUT
C
IN
C
OUT
X
CIN
X
COUT
X
IN
X
OUT
Open Open
External oscillation
circuit or pulse External oscillation
circuit
V
CC
V
SS
V
CC
V
SS
48
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Notes
Main clock stop bit (Note 3)
Middle/
High-speed mode
High-speed mode
or Low-speed mode
Main clock division ratio selection bit (Note 3)
Middle-speed mode
Timing φ
(Internal clock)
WIT
instruction
QS
R STP instruction
X
IN
X
OUT
Port X
C
switch bit (Note 3)
Internal system clock selection bit
Low-speed mode
(Note 1, 3)
Timer 1 count
source selection
bit (Note 2)
X
CIN
X
COUT
“1” “0”
Reset
Interrupt disable flag I
Interrupt request
1/41/2 1/2 Timer 1
“1”
“0”
“1”
“0”
“1”
“0”
SQ
R
QS
R STP instruction
1 : When selecting the low-speed mode, set the port X
C
switch bit to “1”.
2 : Refer to the structume of timer 12 mode register.
3 : Refer to the structume of CPU mode register (next page).
Fig. WA-3 Clock generating circuit block diagram
49
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. WA-4 State transitions of system clock
Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode
is ended.
Timer operates in the wait mode.
When the stop mode is released in middle/high-speed mode, a delay of approximately 0.5 ms occurs automatically by timer 1.
When the stop mode is released in low-speed mode, a delay of approximately 0.125 s occurs automatically by timer 1.
The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Low power dissipation mode (φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM5 = 1 (XIN stopped)
CM4 = 1 (32 kHz oscillating)
CM
6
“1” “0”
CM
4
“0” “1”
b7 CPU mode register
(CPUM (CM) : address 003B16)
CM4 : Port XC switch bit
0 : I/O port function
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN-XOUT) stop bit
0 : Oscillating
1 : Stopped
CM6 : Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
CM7 : Internal system clock selection bit
0 : XIN-XOUT selected
(middle/high-speed mode)
1 : XCIN-XCOUT selected
(low-speed mode)
b0
Notes 1 :
2 :
3 :
4 :
5 :
Reset
CM
6
“1” “0”
CM
4
“1” “0”
CM4
“1” “0”
CM6
“1” “0”
CM4
“1” “0”
CM7
“1” “0”
CM6
“1” “0”
CM7
“1” “0”
CM5
“1” “0”
CM6
“1” “0”
CM5
“1” “0”
High-speed mode (φ = 4 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (XIN oscillating)
CM4 = 1 (32 kHz oscillating)
CM6
“1” “0”
Middle-speed mode (φ =1 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (XIN oscillating)
CM4 = 1 (32 kHz oscillating)
Middle-speed mode (φ =1 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (XIN oscillating)
CM4 = 0 (32 kHz stopped)
High-speed mode (φ = 4 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (XIN oscillating)
CM4 = 0 (32 kHz stopped)
Low-speed mode (φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (XIN oscillating)
CM4 = 1 (32 kHz oscillating)
Low-speed mode (φ = 16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (XIN oscillating)
CM4 = 1 (32 kHz oscillating)
Low power dissipation mode (φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 1 (XIN stopped)
CM4 = 1 (32 kHz oscillating)
CM
6
“1” “0”
CM
5
“0” “1”
CM
6
“1” “0”
CM
5
“1” “0”
50
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing
a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. Only the ADC
and SBC instructions yield proper decimal results. After execut-
ing an ADC or SBC instruction, execute at least one instruction
before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flag are invalid.
The carry flag can be used to indicate whether a carry or borrow
has occurred. Initialize the carry flag before each calculation.
Clear the carry flag before an ADC and set the flag before an
SBC.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• the data transfer instruction (LDA, etc.)
• the operation instruction when the index X mode flag (T) is “1”
• the addressing mode which uses the value of a direction register
as an index
• the bit-test instruction (BBC or BBS, etc.) to a direction register
• the read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
When using the internal clock, set the synchronous clock to inter-
nal clock, then clear the serial I/O interrupt request bit before
executing a serial I/O transfer and serial I/O automatic transfer.
A-D Conver ter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500 kHz or more during an A-D conver-
sion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions. The frequency of the internal
clock φ is half of the XIN or XCIN frequency.
At the STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode regis-
ter are cleared.
The XCOUT drivability selection bit (the CPU mode register) is set
to “1” (high drive) in order to start oscillating.
51
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical
copies)
PROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter.
Set the address of PROM programmer in the user ROM area.
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after writing, the procedure shown in Figure
XC-1 is recommended to verify programming.
Package
100P6S-A
100D0
Name of Programming Adapter
PCA4738F-100A
PCA4738L-100A
Fig. XC-1 Programming and testing of One Time PROM version
The screening temperature is far higher than
the storage temperature. Never expose to
150°C exceeding 100 hours.
Caution :
Functional check in target device
Programming with
PROM Programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM Programmer
52
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
ABSOLUTE MAXIMUM RATINGS
Conditions
Symbol Ratings Unit
Parameter
Power source voltage
Pull-down power source voltage
Input voltage P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77, PB0–PB3
Input voltage P40, P45
Input voltage P80–P87, PA0–PA7
Input voltage RESET, XIN
Input voltage XCIN
Output voltage P00–P07, P10–P17, P20–P23,
P30–P37, P80–P87, P90–P97, PA0–PA7
Output voltage P24–P27, P41–P44, P46, P47, P50–P57,
P60–P67, P70–P77, PB0–PB3, XOUT,
XCOUT
Power dissipation
Operating temperature
Storage temperature
VCC
VEE
VI
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
–0.3 to 7.0
V
CC
–40 to V
CC
+0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
V
CC
–40 to V
CC
+0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
V
CC
–40 to V
CC
+0.3
–0.3
to V
CC
+
0.3
600
–10 to 85
–40 to 125
V
V
V
V
V
V
V
V
V
mW
°C
°C
All voltages are based on VSS.
Output transistors are cut off.
Ta = 25°C
RECOMMENDED OPERATING CONDITIONS (Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
Min.
4.0
2.8
VCC–38
2.0
3.0
0
0.75VCC
0.4VCC
0.8VCC
0.8VCC
0.8VCC
0
0
0
0
0
Typ.
5.0
5.0
0
0
Max.
5.5
5.5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.25VCC
0.16VCC
0.2VCC
0.2VCC
0.2VCC
Symbol
VCC
VSS
VEE
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Parameter
Power source voltage
Power source voltage
Pull-down power source voltage
Analog reference voltage (when using A-D converter)
Analog reference voltage (when using D-A converter)
Analog power source voltage
Analog input voltage AN0–AN15
“H” input voltage P40–P47, P50–P57, P60–P67,
P70–P77, PB0–PB3
“H” input voltage P24–P27
“H” input voltage P80–P87, PA0–PA7
“H” input voltage RESET
“H” input voltage XIN, XCIN
“L” input voltage P40–P47, P50–P57, P60–P67,
P70–P77, PB0–PB3
“L” input voltage P24–P27
“L” input voltage P80–P87, PA0–PA7
“L” input voltage RESET
“L” input voltage XIN, XCIN
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
High-speed mode
Middle/Low-speed mode
Limits
53
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
“H” total peak output current P00–P07, P10–P17, P20–P27,
P30–P37, P80–P87, P90–P97,
(Note 1) PA6, PA7
RECOMMENDED OPERATING CONDITIONS (Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
kHz
MHz
kHz
–240
–60
100
–120
–30
50
–40
–10
10
–18
–5.0
5.0
250
8.4
50
Min. Typ. Max.
Symbol Parameter Unit
ΣIOH(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Limits
“H” total peak output current P41–P44, P46, P47, P50–P57,
P60–P67, P70–P77, PA0–PA5,
(Note 1) PB0–PB3
“L” total peak output current P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
(Note 1) PB0–PB3
“H” total average output current P00–P07, P10–P17, P20–P27,
P30–P37, P80–P87, P90–P97,
(Note 1) PA6, PA7
“H” total average output current P41–P44, P46, P47, P5 0–P57,
P60–P67, P70–P77, PA0–PA5,
(Note 1) PB0–PB3
“L” total average output current P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
(Note 1) PB0–PB3
“H” peak output current P00–P07, P10–P17, P20–P23,
P30–P37, P80–P87, P90–P97,
(Note 2) PA0–PA7
“H” peak output current P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
(Note 2) PB0–PB3
“L” peak output current P24–P27, P41–P44, P4 6, P47,
P50–P57, P60–P67, P70–P77,
(Note 3) PB0–PB3
“H” average output current P00–P07, P10–P17, P20–P23,
P30–P37, P80–P87, P90–P97,
(Note 3) PA0–PA7
“H” average output current P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
(Note 3) PB0–PB3
“L” average output current P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
(Note 3) PB0–PB3
Clock input frequency for timers 2 and 4
(duty cycle 50%)
Main clock input oscillation frequency (Note 4)
Sub-clock input oscillation frequency (Note 4, 5)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports.The total average
current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2:The peak output current is the peak current flowing in each port.
3:The average output current in an average value measured over 100 ms.
4:When the oscillation frequency has a 50% duty cycle.
5:When using the microcomputer in low-speed operation mode, set the sub-clock input oscillation frequency on
condition that f(XCIN) < f(XIN)/3.
32.768
54
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
ELECTRICAL CHARACTERISTICS (Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
Min. Typ. Max.
Symbol Parameter Limits Unit
Test conditions
VOH
VOH
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IH
IH
IH
IH
IL
IL
IL
IL
ILOAD
ILEAK
VRAM
“H” output voltage P00–P07, P1 0–P17, P20–P23,
P30–P37, P80–P87, P90–P97,
PA0–PA7
“H” output voltage P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
PB0–PB3
“L” output voltage P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
PB0–PB3
Hysteresis INT0–INT4, SIN1, SIN2, SIN3, SCLK11,
SCLK2, SCLK3, CS, CNTR0, CNTR1
Hysteresis RESET, XIN
Hysteresis XCIN
“H” input current P24–P27, P40–P47, P50–P57,
P60–P67, P70–P77, PB0–PB3
“H” input current P80–P87, PA0–PA7 (Note)
“H” input current RESET, XCIN
“H” input current XIN
“L” input current P24–P27, P4 0–P47, P50–P57,
P60–P67, P70–P77, PB0–PB3
“L” input current P80–P87, PA0–PA7 (Note)
“L” input current RESET, XCIN
“L” input current XIN
IOH=–18 mA
IOH=–10 mA
IOL=10 mA
When using a non-port
function
VI=VCC
VI=VCC
VI=VCC
VI=VCC
VI=VSS
VI=VSS
VI=VSS
VI=VSS
VCC–2.0
VCC–2.0
150
2
0.4
0.5
0.5
4.0
–4.0
500
2.0
5.0
5.0
5.0
–5.0
–5.0
–5.0
900
–10
5.5
Output load current P00–P07, P1 0–P17, P20–P23,
P30–P37, P90–P97
Output leakage current P00–P07, P10–P17,
P20–P23, P30–P37,
P80–P87, P90–P97,
PA0–PA7
RAM hold voltage
VEE=VCC–36 V, VOL=VCC,
Output transistors “off”
VEE=VCC–38 V,
VOL=VCC–38 V,
Output transistors “off”
When clock is stopped
Note : Except when reading ports P8 or PA.
55
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol Test conditions
• High-speed mode
f(XIN) = 8.4 MHz
f(XCIN) = 32 kHz
Output transistors “off”
• High-speed mode
f(XIN) = 8.4 MHz (in WIT state)
f(XCIN) = 32 kHz
Output transistors “off”
• Middle-speed mode
f(XIN) = 8.4 MHz
f(XCIN) = stopped
Output transistors “off”
• Middle-speed mode
f(XIN) = 8.4 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
• Low-speed mode
f(XIN) = stopped, f(XCIN) = 32 kHz
Low-power dissipation mode set
(CM3) = 0
Output transistors “off”
• Low-speed mode
f(XIN) = stopped
f(XCIN) = 32 kHz (in WIT state)
Low-power dissipation mode set
(CM3) = 0
Output transistors “off”
Increase at A-D converter operating
f(XIN) = 8.4 MHz
Increase at zero cross detection
(P45 = VCC)
All oscillation stopped
(in STP state)
Output transistors “off”
Limits
Min. Typ.
7.5
1
3
1
60
20
0.6
1
0.1
Max.
15
200
40
1
10
Unit
mA
mA
mA
mA
µA
µA
mA
mA
µA
Ta = 25°C
Ta = 85°C
ICC
Parameter
Power source current
56
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
ZERO CROSS DETECTION INPUT CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol
fZCR
∆VT
Parameter
Input frequency of zero cross detection
Voltage error of zero cross detection distinction
Test conditions
50 Hz or 60 Hz
Limits
Min.
–100
Typ.
50, 60
0
Max.
1000
100
Unit
Hz
mV
A-D CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, high-speed operation mode f(XIN) = 500 kHz to 8.4 MHz, unless otherwise noted)
Symbol
–
–
TCONV
IVREF
IIA
RLADDER
Parameter
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Reference power source input current
Analog port input current
Ladder resistor
Test conditions
VCC = VREF = 5.12 V
VREF = 5 V
Limits
Min.
49
50
Max.
8
±2.5
50
200
5.0
Unit
Bits
LSB
tc (φ)
µA
µA
kΩ
Typ.
±1
150
0.5
35
D-A CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 to VCC, Ta = –10 to 85°C, unless otherwise noted)
Symbol
–
–
Tsu
RO
IVREF
Parameter
Resolution
Absolute accuracy
Setting time
Output resistor
Reference power source input current (Note)
Test conditions Limits
Min.
1
Max.
8
1.0
2.5
3
4
3.2
Unit
Bits
%
%
µs
kΩ
mA
Typ.
2.5
VCC = 4.0 to 5.5 V
VCC = 3.0 to 5.5 V
Note : Exclude currents flowing through the A-D converter ladder resistor
Fig. ZA-1 Zero cross detection input characteristics
100V AC
P45/INT1/ZCR
clamp correction
input waveform
Zero cross detection
comparator output
5.7 V
0 V
– 0.7 V
VI
VT
1/fZCR
57
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
P5
6
/S
CLK3
,
P5
2
/S
CLK2
,
P6
6
/S
CLK11
Serial clock output port
Note : Ports P8 and PA need external resistors.
C
L
P0, P1, P2
0
–P2
3
,
P3, P8, P9, PA
High-breakdown-voltage
P-channel open-drain
output port C
L
(Note) V
EE
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XcIN)
tWH(XcIN)
tWL(XcIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SIN)
th(SCLK–SIN)
TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT4 input “H” pulse width
INT0–INT4 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
Limits
Min.
2.0
119
30
30
20
5.0
5.0
4.0
1.6
1.6
80
80
1.0
400
400
200
200
Typ. Max. Unit
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
SWITCHING CHARACTERISTICS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol
tWH(SCLK)
tWL(SCLK)
td(SCLK–SOUT)
tv(SCLK–SOUT)
tr(SCLK)
tf(SCLK)
tr(Pch–strg)
tf(Pch–weak)
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output hold time
Serial I/O clock output rising time
Serial I/O clock output falling time
High-breakdown-voltage P-channel open-
drain output rising time (Note 1)
Test conditions
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
VEE = VCC –36 V
Limits
Min.
tc(SCLK)
/2–160
tc(SCLK)
/2–160
0
Typ.
55
1.8
Max.
0.2t
c(S
CLK
)
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
µs
Notes 1: When the bit 7 of the FLDC mode register 1 (address 003616) is at “0”.
2: When the bit 7 of the FLDC mode register 1 (address 003616) is at “1”.
Fig. ZA-2 Circuit for measuring output switching characteristics
High-breakdown-voltage P-channel open-
drain output falling time (Note 2) CL = 100 pF
VEE = VCC –36 V
58
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
TIMING DIAGRAM
t
C(X
IN
)
t
WL(X
IN
)
t
WH(X
IN
)
t
W(RESET)
t
WL(CNTR)
t
WH(CNTR)
t
C(S
CLK
)
0.8V
CC
0.2V
CC
0.2V
CC
0.8V
CC
INT
0
-
INT
4
RESET
0.8V
CC
X
IN
0.2V
CC
0.2V
CC
S
CLK
0.8V
CC
t
d(S
CLK
-
S
OUT
)
t
h(S
CLK
-
S
IN
)
t
f
t
WL(S
CLK
)
t
WH(S
CLK
)
S
IN
S
OUT
t
r
0.8V
CC
0.2V
CC
CNTR
0
CNTR
1
t
C(CNTR)
t
WL(INT)
t
WH(INT)
0.8V
CC
0.2V
CC
t
C(X
CIN
)
t
WL(X
CIN
)
t
WH(X
CIN
)
0.8V
CC
X
CIN
0.2V
CC
t
su(S
IN
-
S
CLK
)
t
v(S
CLK
-
S
OUT
)
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jan. 1998.
Specifications subject to change without notice.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Rev. Rev.
No. date
1.0 First Edition 980109
REVISION DESCRIPTION LIST 3819 GROUP DATA SHEET
(1/1)
Revision Description
