LM49120
LM49120 Audio Sub-System with Mono Class AB Loudspeaker Amplifier
andStereo OCL/SE Headphone Amplifier
Literature Number: SNAS431B
July 15, 2008
LM49120
Audio Sub-System with Mono Class AB Loudspeaker
Amplifier and Stereo OCL/SE Headphone Amplifier
General Description
The LM49120 is a compact audio subsystem designed for
portable handheld applications such as cellular phones. The
LM49120 combines a mono 1.3W speaker amplifier, stereo
85mW/ch output capacitorless headphone amplifier, 32 step
volume control, and an input mixer/multiplexer into a single
16–bump micro SMD package.
The LM49120 has three input channels: two single-ended
stereo inputs and a differential mono input. Each input fea-
tures a 32-step digital volume control. The headphone output
stage features an 8 step (-18dB – 0dB) attenuator, while the
speaker output stage has two selectable (0dB/+6dB) gain
settings. The digital volume control and mode control are pro-
grammed through a two-wire I2C compatible interface.
Key Specifications
■ Output power at VDD = 5V:
Speaker:
RL = 8Ω BTL, THD+N ≤ 1% 1.3W (typ)
Headphone:
RL = 32Ω, SE, THD+N ≤ 1% 85mW (typ)
■ Output power at VDD = 3.6V:
Speaker:
RL = 8Ω, BTL, THD+N ≤ 1% 632mW (typ)
■ Output power at VDD = 3.3V:
Speaker:
RL = 8Ω, BTL, THD+N ≤ 1% 540mW (typ)
Headphone:
RL = 32Ω, OCL/SE, THD+N ≤ 1% 35mW (typ)
Features
■RF immunity
■Selectable OCL/SE headphone drivers
■32 Step volume control
■Click and Pop suppression
■Independent speaker and headphone gain settings
■Minimum external components
■Thermal over load protection
■Micro-power shutdown
■Space saving 16–bump mciro SMD package
■Thermal shutdown protection
■Micro-power shutdown
■I2C Control Interface
Applications
■Mobile Phones
■PDAs
■Portable Electronics
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2008 National Semiconductor Corporation 300375 www.national.com
LM49120 Audio Sub-System with Mono Class AB Loudspeaker Amplifier and Stereo OCL/SE
Headphone Amplifier
Typical Application
300375g1
FIGURE 1. Output Capacitor-less Configuration
300375n4
FIGURE 2. Single-Ended Configuration
Note:The 6dB speaker gain applies only to the differential input path.
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LM49120
Connection Diagrams
16 Bump micro SMD Package
300375n2
Top View
(Bump-Side Down)
See NS Package Number TLA1611A
30037549
Top View
XY - Date Code
TT - Die Traceability
G- Boomer
K2 - LM49120TL
Ordering Information
Order Number Package Package DWG # Transport Media MSL
Level Green Status
LM49120TL 16 Bump micro SMD TLA1611A 250 units on tape and reel 1 NOPB
LM49120TLX 16 Bump micro SMD TLA1611A 3000 units on tape and reel 1 NOPB
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LM49120
Pin Descriptions
Bump Name Description
A1 VOC Headphone Center Amplifier Output
A2 VDD Headphone Power Supply
A3 ROUT Right Channel Headphone Output
A4 LOUT Left Channel Headphone Output
B1 MONO_IN+ Mono Non-inverting Input
B2 BYPASS Bias Bypass
B3 LIN Left Channel Input
B4 RIN Right Channel Input
C1 MONO_IN- Mono Inverting Input
C2 I2CVDD I2C Interface Power Supply
C3 SCL I2C Clock Input
C4 SDA I2C Data Input
D1 MONO- Loudspeaker Inverting Output
D2 GND Ground
D3 VDD Power Supply
D4 MONO+ Loudspeaker Non-inverting Output
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LM49120
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Note 1) 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3 to VDD +0.3
Power Dissipation (Note 3) Internally Limited
ESD Rating (Note 4) 2000V
ESD Rating (Note 5) 200V
Junction Temperature 150°C
Solder Information
Vapor Phase (60 sec.) 215°C
Infrared (15 sec.) 220°C
Thermal Resistance
θJA (typ) - TLA 62.3°C/W
Operating Ratings
Temperature Range −40°C to 85°C
Supply Voltage (VDD)2.7V ≤ VDD ≤ 5.5V
Supply Voltage (I2CVDD)1.7V ≤ I2CVDD ≤ 5.5V
Electrical Characteristics 3.3V (Notes 1, 2)
The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol Parameter Conditions
LM49120 Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
IDD Supply Current
VIN = 0, No Load
Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15
OCL Headphone 6.2 8.0 mA (max)
Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15
SE Headphone 5.5 mA
Output mode 1, 2, 3
OCL Headphone 4.1 5.3 mA (max)
Output mode 1, 2, 3
SE Headphone 5.5 mA
Output mode 4, 8, 12
OCL Headphone 3.7 4.7 mA (max)
Output mode 4, 8, 12
SE Headphone 3.0 mA
ISD Shutdown Current Shutdown Mode 0 0.01 1 µA
VOS Output Offset Voltage
VIN = 0V, Output Mode 10, LS output 10 mV
VIN = 0V, Output Mode 10, HP output,
(OCL), 0dB (HP Output Gain) 1.5 5 mV (max)
POOutput Power
LSOUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1 540 500 mW (min)
LOUT and ROUT; RL = 32Ω
THD+N = 1%; f = 1kHz, OCL, Mode 8 35 30 mW (min)
THD+N Total Harmonic Distortion + Noise
MONOOUT
f = 1kHz
POUT = 250mW; RL = 8Ω, BTL, Mode 1
0.05 %
LOUT and ROUT, f = 1kHz
POUT = 12mW; RL = 32Ω, SE, Mode 8 0.015 %
LOUT and ROUT, f = 1kHz
POUT = 12mW; RL = 32Ω, OCL, Mode 8 0.015 %
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LM49120
Symbol Parameter Conditions
LM49120 Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
eOUT Output Noise
A-weighted,
inputs terminated to GND, Output referred
Speaker Amplifier; Mode 1 15 μV
Speaker Amplifier; Mode 2 24 μV
Speaker Amplifier; Mode 3 29 μV
Headphone Amplifier; SE, Mode 4 8 μV
Headphone Amplifier; SE, Mode 8 8 μV
Headphone Amplifier; SE, Mode 12 11 μV
Headphone Amplifier; OCL, Mode 4 8 μV
Headphone Amplifier; OCL, Mode 8 9 μV
Headphone Amplifier; OCL, Mode 12 12 μV
PSRR Power Supply Rejection Ratio
VRIPPLE = 200mVPP; fRIPPLE = 217Hz, RL = 8Ω (Speaker); RL = 32Ω (Headphone)
CB = 2.2µF, BTL
All audio inputs terminated to GND; output referred
Speaker Output; Speaker Output Gain 6dB
Speaker Amplifier; Mode 1 79 dB
Speaker Amplifier; Mode 2 63 dB
Speaker Amplifier; Mode 3 62 dB
Speaker Amplifier Output; Speaker Output Gain 0dB
Speaker Amplifier; Mode 1 84 dB
Speaker Amplifier; Mode 2 63 dB
Speaker Amplifier; Mode 3 62 dB
Headphone Amplifier Output
Headphone Amplifier; SE, Mode 4 83 dB
Headphone Amplifier; SE, Mode 8 84 dB
Headphone Amplifier; SE, Mode 12 78 dB
Headphone Amplifier; OCL, Mode 4 83 dB
Headphone Amplifier; OCL, Mode 8 80 dB
Headphone Amplifier; OCL, Mode 12 77 dB
VOL∈Volume Control Step Size Error ±0.2 dB
VOLRANGE Digital Volume Control Range
Maximum Attenuation –86 –91
–81
dB (min)
dB (max)
Maximum Gain 18 17.4
18.6
dB (min)
dB (max)
Au(HP) HP (SE) Mute Attenuation Output Mode 1, 2, 3 96 dB
ZIN
MONO_IN Input Impedance
LIN and RIN Input Impedance
Maximum gain setting 12.5 10
15
kΩ (min)
kΩ (max)
Maximum attenuation setting 110 90
130
kΩ (min)
kΩ (max)
CMRR Common-Mode Rejection Ratio
f = 217Hz, VCM = 1VPP,
Speaker, BTL, Mode 1,
RL = 8Ω
Differential Input
61 dB
f = 217Hz, VCM = 1VPP,
Headphone, OCL, Mode 4,
RL = 32Ω
Stereo Input
66 dB
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LM49120
Symbol Parameter Conditions
LM49120 Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
XTALK Crosstalk
Headphone; POUT = 12mW
f = 1kHz, OCL. Mode 8 –60 dB
Headphone; POUT = 12mW
f = 1kHz, SE, Mode 8 –72 dB
TWU Wake-Up Time from Shutdown
CB = 4.7μF, OCL 35 ms
CB = 2.2μF, SE,
Normal Turn On Mode
Turn_On_Time = 1
120 ms
CB = 2.2μF, OCL 30 ms
CB = 4.7μF, SE,
Fast Turn On Mode
Turn_On_Time = 0
130 ms
Electrical Characteristics 5.0V (Notes 1, 2)
The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol Parameter Conditions
LM49120 Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
IDD Supply Current
VIN = 0, No Load
Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15
OCL Headphone 7.2 mA
Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15
SE Headphone 6.4 mA
Output mode 1, 2, 3
OCL Headphone 6.4 mA
Output mode 1, 2, 3
SE Headphone 4.8 mA
Output mode 4, 8, 12
OCL Headphone 4.4 mA
Output mode 4, 8, 12
SE Headphone 3.5 mA
ISD Shutdown Current Shutdown Mode 0 0.01 µA
VOS Output Offset Voltage
VIN = 0V, Output Mode 10, LS output 10 mV
VIN = 0V, Output Mode 10, HP output,
(OCL), 0dB (HP Output Gain) 1.5 mV
POOutput Power
LS OUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1 1.3 W
LOUT and ROUT; RL = 32Ω
THD+N = 1%; f = 1kHz, OCL, Mode 8 85 mW
THD+N Total Harmonic Distortion + Noise
LSOUT
f = 1kHz
POUT = 250mW; RL = 8Ω, BTL, Mode 1
0.05 %
LOUT and ROUT, f = 1kHz
POUT = 12mW; RL = 32Ω, SE, Mode 8 0.015 %
LOUT and ROUT, f = 1kHz
POUT = 12mW; RL = 32Ω, OCL, Mode 8 0.015 %
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LM49120
Symbol Parameter Conditions
LM49120 Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
eOUT Output Noise
A-weighted,
inputs terminated to GND, Output referred
Speaker Amplifier; Mode 1 17 μV
Speaker Amplifier; Mode 2 27 μV
Speaker Amplifier; Mode 3 33 μV
Headphone Amplifier; SE, Mode 4 8 μV
Headphone Amplifier; SE, Mode 8 8 μV
Headphone Amplifier; SE, Mode 12 12 μV
Headphone Amplifier; OCL, Mode 4 9 μV
Headphone Amplifier; OCL, Mode 8 9 μV
Headphone Amplifier; OCL, Mode 12 12 μV
PSRR Power Supply Rejection Ratio
VRIPPLE = 200mVPP; fRIPPLE = 217Hz, RL = 8Ω
(Speaker); RL = 32Ω (Headphone)
CB = 2.2µF, BTL
All audio inputs terminated to GND; output referred
Speaker Output; Speaker Output Gain 6dB
Speaker Amplifier; Mode 1 69 dB
Speaker Amplifier; Mode 2 60 dB
Speaker Amplifier; Mode 3 58 dB
Speaker Amplifier Output; Speaker Output Gain 0dB
Speaker Amplifier; Mode 1 84 dB
Speaker Amplifier; Mode 2 63 dB
Speaker Amplifier; Mode 3 62 dB
Headphone Amplifier Output
Headphone Amplifier; SE, Mode 4 75 dB
Headphone Amplifier; SE, Mode 8 75 dB
Headphone Amplifier; SE, Mode 12 72 dB
Headphone Amplifier; OCL, Mode 4 75 dB
Headphone Amplifier; OCL, Mode 8 75 dB
Headphone Amplifier; OCL, Mode 12 72 dB
VOL∈Volume Control Step Size Error ±0.2 dB
VOLRANGE Digital Volume Control Range
Maximum Attenuation –86 –91
–81
dB
dB
Maximum Gain 18 dB
dB
Au(HP) HP (SE) Mute Attenuation Output Mode 1, 2, 3 96 dB
ZIN
MONO_IN Input Impedance
LIN and RIN Input Impedance
Maximum gain setting 12.5 kΩ
kΩ
Maximum attenuation setting 110 kΩ
kΩ
CMRR Common-Mode Rejection Ratio
f = 217Hz, VCM = 1VPP,
Speaker, BTL, Mode 1,
RL = 8Ω
Differential Input
61 dB
f = 217Hz, VCM = 1VPP,
Headphone, OCL, Mode 4,
RL = 32Ω
Stereo Input
66 dB
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LM49120
Symbol Parameter Conditions
LM49120 Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
XTALK Crosstalk
Headphone; POUT = 12mW
f = 1kHz, OCL, Mode 8 –54 dB
Headphone; POUT = 12mW
f = 1kHz, SE, Mode 8 –72 dB
TWU Wake-Up Time from Shutdown
CB = 4.7μF, OCL 28 ms
CB = 2.2μF, SE,
Normal Turn On Mode
Turn_On_Time = 1
151 ms
CB = 2.2μF, OCL 25 ms
CB = 4.7μF, SE,
Fast Turn On Mode
Turn_On_Time = 0
168 ms
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LM49120
I2C Timing Characteristics 2.2V ≤ I2C_VDD ≤ 5.5V, (Notes 1, 2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ I2C_VDD ≤ 5.5V, unless otherwise specified.
Symbol Parameter Conditions
LM49120 Units
(Limits)
Typical
(Note 6)
Limits (Note 7)
t1I2C Clock Period 2.5 µs (min)
t2I2C Data Setup Time 100 ns (min)
t3I2C Data Stable Time 0 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition Time 100 ns (min)
t6I2C Data Hold Time 100 ns (min)
VIH I2C Input Voltage High 0.7xI2CVDD V (min)
VIL I2C Input Voltage Low 0.3xI2CVDD V (max)
I2C Timing Characteristics 1.7V ≤ I2C_VDD ≤ 2.2V (Notes 1, 2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2C_VDD ≤ 2.2V, unless otherwise specified.
Symbol Parameter Conditions
LM49120 Units
(Limits)
Typical
(Note 6)
Limits (Note 7)
t1I2C Clock Period 2.5 µs (min)
t2I2C Data Setup Time 250 ns (min)
t3I2C Data Stable Time 0 ns (min)
t4Start Condition Time 250 ns (min)
t5Stop Condition Time 250 ns (min)
t6I2C Data Hold Time 250 ns (min)
VIH I2C Input Voltage High 0.7xI2CVDD V (min)
VIL I2C Input Voltage Low 0.3xI2CVDD V (max)
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.
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LM49120
Typical Performance Characteristics
Filter BW = 22kHz
Crosstalk vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW,
f = 1kHz, Mode 8, OCL
30037501
Crosstalk vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW,
f = 1kHz, Mode 8, SE
30037502
Crosstalk vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW,
f = 1kHz, Mode 8, OCL
30037503
Crosstalk vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW,
f = 1kHz, Mode 8, SE
30037504
Output Power vs Supply Voltage
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 8, OCL
30037505
Output Power vs Supply Voltage
VDD = 5V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
30037506
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LM49120
Power Dissipation vs Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 8, OCL
30037507
Power Dissipation vs Output Power
VDD = 3.3V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
30037508
Power Dissipation vs Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, Mode 8, OCL
30037509
Power Dissipation vs Output Power
VDD =5V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
30037510
Supply Current vs Supply Voltage
VIN= GND, No load
30037511
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
f = 22kHz, Mode 8, OCL
30037512
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LM49120
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
f = 22kHz, Mode 8, SE
30037513
THD+N vs Frequency
VDD = 3.3V, RL = 64Ω, PO = 24mW
f = 22kHz, Mode 4, BTL
30037514
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
f = 1kHz, Mode 1, Speaker
30037515
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
f = 22kHz, Mode 8, OCL
30037516
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
f = 22kHz, Mode 8, SE
30037517
THD+N vs Frequency
VDD = 5V, RL = 64Ω, PO = 72mW
f = 22kHz, Mode 4, BTL
30037518
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LM49120
THD+N vs Frequency
VDD = 5V, RL = 8Ω, PO = 500mW
f = 1kHz, Mode 1, Speaker
30037519
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 8, OCL
30037520
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 8, SE
30037521
THD+N vs Output Power
VDD = 3.3V, RL = 64Ω
f = 1kHz, Mode 4, BTL
30037522
THD+N vs Output Power
VDD = 3.3V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
30037523
THD+N vs Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, Mode 8, OCL
30037524
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LM49120
THD+N vs Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, Mode 8, SE
30037525
THD+N vs Output Power
VDD = 5V, RL = 64Ω
f = 1kHz, Mode 4, BTL
30037526
THD+N vs Output Power
VDD = 5V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
30037527
PSRR vs Frequency
VDD = 3.3V, RL = 8Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 1
30037531
PSRR vs Frequency
VDD = 3.3V, RL = 8Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 1
30037532
PSRR vs Frequency
VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 8, OCL
30037533
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LM49120
PSRR vs Frequency
VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 8, SE
30037534
PSRR vs Frequency
VDD = 3.3V, RL = 32Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 8, OCL
30037535
PSRR vs Frequency
VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 4, BTL
30037536
PSRR vs Frequency
VDD = 3.3V, RL = 64Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 4, BTL
30037537
PSRR vs Frequency
VDD = 3.3V, RL = 8Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 1
30037538
PSRR vs Frequency
VDD = 5V, RL = 8Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 1
30037539
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LM49120
PSRR vs Frequency
VDD = 5V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 8, OCL
30037540
PSRR vs Frequency
VDD = 5V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 8, SE
30037541
PSRR vs Frequency
VDD = 5V, RL = 64Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 4, BTL
30037542
PSRR vs Frequency
VDD = 5V, RL = 32Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 8, SE
30037543
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LM49120
Application Information
I2C COMPATIBLE INTERFACE
The LM49120 is controlled through an I2C compatible serial
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock line is uni-directional. The data line is
bi-directional (open drain). The LM49120 and the master can
communicate at clock rates up to 400kHz. Figure 3 shows the
I2C interface timing diagram. Data on the SDA line must be
stable during the HIGH period of SCL. The LM49120 is a
transmit/receive slave-only device, reliant upon the master to
generate the SCL signal. Each transmission sequence is
framed by a START condition and a STOP condition (Figure
4). Each data word, device address and data, transmitted
over the bus is 8 bits long and is always followed by an ac-
knowledge pulse (Figure 5). The LM49120 device address is
1111100.
I2C BUS FORMAT
The I2C bus format is shown in Figure 5. The START signal,
the transition of SDA from HIGH to LOW while SCL is HIGH,
is generated, alerting all devices on the bus that a device ad-
dress is being written to the bus.
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit. R/W = 0 indicates
the master is writing to the slave device, R/W = 1 indicates
the master wants to read data from the slave device. Set R/
W = 0; the LM49120 is a WRITE-ONLY device and will not
respond the R/W = 1. The data is latched in on the rising edge
of the clock. Each address bit must be stable while SCL is
HIGH. After the last address bit is transmitted, the master de-
vice releases SDA, during which time, an acknowledge clock
pulse is generated by the slave device. If the LM49120 re-
ceives the correct address, the device pulls the SDA line low,
generating and acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit reg-
ister data word is sent. Each data bit should be stable while
SCL is HIGH. After the 8-bit register data word is sent, the
LM49120 sends another ACK bit. Following the acknowl-
edgement of the register data word, the master issues a
STOP bit, allowing SDA to go high while SCL is high.
30037550
FIGURE 3. I2C Timing Diagram
30037551
FIGURE 4. Start and Stop Diagram
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LM49120
30037552
FIGURE 5. Example Write Sequence
TABLE 1. Device Address
B7 B6 B5 B4 B3 B2 B1 B0 (R/W)
Device
Address 1 1 1 1 1 0 0 0
TABLE 2. Control Registers
B7 B6 B5 B4 B3 B2 B1 B0
Shutdown Control 0 0 0 OCL/SE HP/BTL SD_I2CVDD
Turn_On
_Time PWR_On
Output Mode Control 0 1 0 0 MC3 MC2 MC1 MC0
Output Gain Control 1 0 0 0 LS_GAIN HP_GAIN2 HP_GAIN1 HP_GAIN0
Mono Input Volume
Control 1 0 1 MG4 MG3 MG2 MG1 MG0
Left Input Volume
Control 1 1 0 LG4 LG3 LG2 LG1 LG0
Right Input Volume
Control 1 1 1 RG4 RG3 RG2 RG1 RG0
TABLE 3. Shutdown Control Register
Bit Name Value Description
B4 OSC/SE 0 Single-Ended headphone mode (Capacitively Coupled)
1 Output Capacitor-less (OCL) headphone mode
B3 HP/BTL 0 Single-ended stereo headphone output mode
1 Mono, BTL output mode.
B2 SD_I2CVDD 0
I2CVDD acts as an active low RESET input. If I2CVDD drops below
1.1V, the device is reset and the I2C registers are restored to their
default state.
1Normal Operation. I2CVDD voltage does not reset the device
B1 TURN_ON_TIME 0 Fast turn on time (120ms)
1 Normal turn on time (130ms)
B0 PWR_ON 0 Device Disabled
1 Device Enabled
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LM49120
TABLE 4. Output Mode Control (HP/BTL = 0)
Output
Mode
Number
MC3 MC2 MC1 MC0 LS Output HP R Output HP L Output
0 0 0 0 0 SD SD SD
1 0 0 0 1 GM x M Mute Mute
2 0 0 1 0 2 x (GL x L + GR x R) Mute Mute
3 0 0 1 1 2 x (GL x L + GR x R)
+ GM x M Mute Mute
4 0 1 0 0 SD GM x M/2 GM x M/2
5 0 1 0 1 GM x M GM x M/2 GM x M/2
6 0 1 1 0 2 x (GL x L + GR x R) GM x M/2 GM x M/2
7 0 1 1 1 2 x (GL x L + GR x R)
+ GM x M GM x M/2 GM x M/2
8 1 0 0 0 SD GR x R GL x L
9 1 0 0 1 GM x M GR x R GL x L
10 1 0 1 0 2 x (GL x L + GR x R) GR x R GL x L
11 1 0 1 1 2 x (GL x L + GR x R)
+ GM x M GR x R GL x L
12 1 1 0 0 SD GR x R + GM x M/2 GL x L + GM x M/2
13 1 1 0 1 GM x M GR x R + GM x M/2 GL x L + GM x M/2
14 1 1 1 0 2 x (GL x L + GR x R) GR x R + GM x M/2 GL x L + GM x M/2
15 1 1 1 1 2 x (GL x L + GR x R)
+ GM x M GR x R + GM x M/2 GL x L + GM x M/2
M: Mono Differential Input
R: Right In
L: Left In
SD: Shutdown
GM: Mono Volume Control Gain
GR: Right Stereo Volume Control Gain
GL: Left Stereo Volume Control Gain
www.national.com 20
LM49120
TABLE 5. Output Mode Control (HP/BTL = 1)
Output
Mode
Number
MC3 MC2 MC1 MC0 LS Output HP R Output HP L Output
4 0 1 0 0 SD GM x M+/2 GM x M-/2
5 0 1 0 1 GM x M GM x M+/2 GM x M-/2
6 0 1 1 0 2 x (GL x L + GR x R) GM x M+/2 GM x M-/2
7 0 1 1 1 2 x (GL x L + GR x R)
+ GP x P GM x M+/2 GM x M-/2
12 1 1 0 0 SD GR x R + GM x M+/2 GL x L + GM x M-/2
13 1 1 0 1 GM x M GR x R + GM x M+/2 GL x L + GM x M-/2
14 1 1 1 0 2 x (GL x L + GR x R) GR x R + GM x M+/2 GL x L + GM x M-/2
15 1 1 1 1 2 x (GL x L + GR x R)
+ GM x M GR x R + GM x M+/2 GL x L + GM x M-/2
21 www.national.com
LM49120
TABLE 6. Volume Control Table
Volume Step _G4 _G3 _G2 _G1 _G0 Gain (dB)
1 0 0 0 0 0 Mute
2 0 0 0 0 1 –46.50
3 0 0 0 1 0 –40.50
4 0 0 0 1 1 –34.50
5 0 0 1 0 0 –30.00
6 0 0 1 0 1 –27.00
7 0 0 1 1 0 –24.00
8 0 0 1 1 1 –21.00
9 0 1 0 0 0 –18.00
10 0 1 0 0 1 –15.00
11 0 1 0 1 0 –13.50
12 0 1 0 1 1 –12.00
13 0 1 1 0 0 –10.50
14 0 1 1 0 1 –9.00
15 0 1 1 1 0 –7.50
16 0 1 1 1 1 –6.00
17 1 0 0 0 0 –4.50
18 1 0 0 0 1 –3.00
19 1 0 0 1 0 –1.50
20 1 0 0 1 1 0.00
21 1 0 1 0 0 1.50
22 1 0 1 0 1 3.00
23 1 0 1 1 0 4.50
24 1 0 1 1 1 6.00
25 1 1 0 0 0 7.50
26 1 1 0 0 1 9.00
27 1 1 0 1 0 10.50
28 1 1 0 1 1 12.00
29 1 1 1 0 0 13.50
30 1 1 1 0 1 15.00
31 1 1 1 1 0 16.50
32 1 1 1 1 1 18.00
TABLE 7. Output Gain Control (Headphone)
HP_GAIN2 HP_GAIN1 HP_GAIN0 GAIN (dB)
0 0 0 0
0 0 1 –1.2
0 1 0 –2.5
0 1 1 –4.0
1 0 0 –6.0
1 0 1 –8.5
1 1 0 –12
1 1 1 –18
www.national.com 22
LM49120
TABLE 8. Output Gain Control (Loudspeaker)
Bit Value Gain (dB)
Differential Input
Gain (dB)
Single-Ended Input
LS_GAIN 0 0 +6
1 +6 +12
BRIDGE CONFIGURATION EXPLAINED
The LM49120 loudspeaker amplifier is designed to drive a
load differentially, a configuration commonly referred to as a
bridge-tied load (BTL). The BTL configuration differs from the
single-ended configuration, where one side of the load is con-
nected to ground. A BTL amplifier offers advantages over a
single-ended device. By driving the load differentially, the out-
put voltage is doubled, compared to a single-ended amplifier
under similar conditions. This doubling of the output voltage
leads to a quadrupling of the output power, for example, the
theoretical maximum output power for a single-ended ampli-
fier driving 8Ω and operating from a 5V supply is 390mW,
while the theoretical maximum output power for a BTL ampli-
fier operating under the same conditions is 1.56W. Since the
amplifier outputs are both biased about VDD/2, there is no net
DC voltage across the load, eliminating the DC blocking ca-
pacitors required by single-ended, single-supply amplifiers.
Headphone Amplifier
The LM49120 headphone amplifier features two different op-
erating modes, output capacitor-less (OCL) and single-ended
(SE) capacitor coupled mode.
The OCL architecture eliminates the bulky, expensive output
coupling capacitors required by traditional headphone ampli-
fiers. In OCL mode, the LM49120 headphone section uses
three amplifiers. Two amplifiers drive the headphones, while
the third (VOC) is set to the internally generated bias voltage
(typically VDD/2). The third amplifier is connected to the return
terminal of the headphone jack (Figure 1). In this configura-
tion, the signal side of the headphone is biased to VDD/2, the
return is biased to VDD/2, thus there is no net DC voltage
across the headphone, eliminating the need for an output
coupling capacitor. Removing the output coupling capacitors
from the headphone signal path reduces component count,
reducing system cost and board space consumption, as well
as improving low frequency performance.
In OCL mode, the headphone return sleeve is biased to
VDD/2. When driving headphones, the voltage on the return
sleeve is not an issue. However, if the headphone output is
used as a line out, the VDD/2 can conflict with the GND po-
tential that the line-in would expect on the return sleeve. When
the return of the headphone jack is connected to GND the
VOC amplifier of the LM49120 detects an output short circuit
condition and is disabled, preventing damage to the
LM49120, and allowing the headphone return to be biased at
GND.
Single-Ended, Capacitor Coupled Mode
In single-ended mode, the VOC amplifier is disabled, and the
headphone outputs are coupled to the jack through series
capacitors, allowing the headphone return to be connected to
GND (Figure 2). In SE mode, the LM49120 requires output
coupling capacitors to block the DC component of the ampli-
fier output, preventing DC current from flowing to the load.
The output capacitor and speaker impedance form a high
pass filter with a -3dB roll-off determined by:
f–3dB = 1 / 2πRLCO (Hz) (1)
Where RL is the headphone impedance, and CO is the value
of the output coupling capacitor. Choose CO such that f-3dB is
well below the lowest frequency of interest. Setting f-3dB too
high results in poor low frequency performance. Select ca-
pacitor dielectric types with low ESR to minimize signal loss
due to capacitor series resistance and maximize power trans-
fer to the load.
Headphone Amplifier BTL Mode
The LM49120 headphone amplifiers feature a BTL mode
where the two headphone outputs, LOUT and ROUT are con-
figured to drive a mono speaker differentially. In BTL mode,
the amplifier accepts audio signals from either the differential
MONO inputs, or the single-ended stereo inputs, and con-
verts them to a mono BTL output. However, if the stereo
inputs are 180° out of phase, no audio will be present at the
amplifier outputs. Bit B3 (HP/BTL) in the Shutdown Control
Register determines the headphone output mode. Set HP/
BTL = 0 for stereo headphone mode, set HP/BTL = 1 for BTL
mode.
Input Mixer/Multiplexer
The LM49120 includes a comprehensive mixer multiplexer
controlled through the I2C interface. The mixer/multiplexer al-
lows any input combination to appear on any output of the
LM49120. Multiple input paths can be selected simultane-
ously. Under these conditions, the selected inputs are mixed
together and output on the selected channel. Tables 4 and 5
show how the input signals are mixed together for each pos-
sible input selection.
Audio Amplifier Gain Setting
Each channel of the LM49120 has two separate gain stages.
Each input stage features a 32-step volume control with a
range of -46dB to +18dB (Table 6). The loudspeaker output
stage has two additional gain settings: 0dB and +6dB (Table
8) when the differential MONO input is selected, and +6dB
and +12dB when the single-ended stereo inputs are selected.
The headphone gain is not affected by the input mode. Each
headphone output stage has 8 gain settings (Table 7). This
allows for a maximum separation of 22dB between the speak-
er and headphone outputs when both are active.
Calculate the total gain of the given signal path as follows:
AVOL + AVOS = AVTOTAL (dB) (2)
Where AVOL is the volume control level, AVOS is the output
stage gain setting, and AVTOTAL is the total gain for the signal
path.
23 www.national.com
LM49120
POWER DISSIPATION
Power dissipation is a major concern when designing a suc-
cessful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the
load by a bridge amplifier is higher internal power dissipation.
The LM49120 has a pair of bridged-tied amplifiers driving a
handsfree speaker, MONO. The maximum internal power
dissipation operating in the bridge mode is twice that of a sin-
gle-ended amplifier. From Equation (2), assuming a 5V power
supply and an 8Ω load, the maximum MONO power dissipa-
tion is 633mW.
PDMAX-SPKROUT = 4(VDD)2 / (2π2 RL): Bridge Mode (3)
The LM49120 also has a pair of single-ended amplifiers driv-
ing stereo headphones, ROUT and LOUT. The maximum inter-
nal power dissipation for ROUT and LOUT is given by equation
(3) and (4). From Equations (3) and (4), assuming a 5V power
supply and a 32Ω load, the maximum power dissipation for
LOUT and ROUT is 40mW, or 80mW total.
PDMAX-LOUT = (VDD)2 / (2π2 RL): Single-ended Mode (4)
PDMAX-ROUT = (VDD)2 / (2π2 RL): Single-ended Mode (5)
The maximum internal power dissipation of the LM49120 oc-
curs when all three amplifiers pairs are simultaneously on;
and is given by Equation (5).
PDMAX-TOTAL =
PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT (6)
The maximum power dissipation point given by Equation (5)
must not exceed the power dissipation given by Equation (6):
PDMAX = (TJMAX - TA) / θJA (7)
The LM49120's TJMAX = 150°C. In the SQ package, the
LM49120's θJA is 46°C/W. At any given ambient temperature
TA, use Equation (6) to find the maximum internal power dis-
sipation supported by the IC packaging. Rearranging Equa-
tion (6) and substituting PDMAX-TOTAL for PDMAX' results in
Equation (7). This equation gives the maximum ambient tem-
perature that still allows maximum stereo power dissipation
without violating the LM49120's maximum junction tempera-
ture.
TA = TJMAX - PDMAX-TOTAL θJA (8)
For a typical application with a 5V power supply and an 8Ω
load, the maximum ambient temperature that allows maxi-
mum mono power dissipation without exceeding the maxi-
mum junction temperature is approximately 121°C for the SQ
package.
TJMAX = PDMAX-TOTAL θJA + TA(9)
Equation (8) gives the maximum junction temperature
TJMAX. If the result violates the LM49120's 150°C, reduce the
maximum junction temperature by reducing the power supply
voltage or increasing the load resistance. Further allowance
should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount
part operating around the maximum power dissipation point.
Since internal power dissipation is a function of output power,
higher ambient temperatures are allowed as output power or
duty cycle decreases. If the result of Equation (5) is greater
than that of Equation (6), then decrease the supply voltage,
increase the load impedance, or reduce the ambient temper-
ature. If these measures are insufficient, a heat sink can be
added to reduce θJA. The heat sink can be created using ad-
ditional copper area around the package, with connections to
the ground pin(s), supply pin and amplifier output pins. Ex-
ternal, solder attached SMT heatsinks such as the Thermalloy
7106D can also improve power dissipation. When adding a
heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the
junction-to-case thermal impedance, θCS is the case-to-sink
thermal impedance, and θSA is the sink-to-ambient thermal
impedance). Refer to the Typical Performance Characteris-
tics curves for power dissipation information at lower output
power levels.
PROPER SELECTION OF EXTERNAL COMPONENTS
Power Supply Bypassing/Filtering
Proper power supply bypassing is critical for low noise per-
formance and high PSRR. Place the supply bypass capaci-
tors as close to the device as possible. Place a 1μF ceramic
capacitor from VDD to GND. Additional bulk capacitance may
be added as required.
Input Capacitor Selection
Input capacitors may be required for some applications, or
when the audio source is single-ended. Input capacitors block
the DC component of the audio signal, eliminating any conflict
between the DC component of the audio source and the bias
voltage of the LM49120. The input capacitors create a high-
pass filter with the input resistors RIN. The -3dB point of the
high pass filter is found using Equation (3) below.
f = 1 / (2πRINCIN) (Hz) (10)
Where the value of RIN is given in the Electrical Characteris-
tics Table.
High pass filtering the audio signal helps protect the speakers.
When the LM49120 is using a single-ended source, power
supply noise on the ground is seen as an input signal. Setting
the high-pass filter point above the power supply noise fre-
quencies, 217Hz in a GSM phone, for example, filters out the
noise such that it is not amplified and heard on the output.
Capacitors with a tolerance of 10% or better are recommend-
ed for impedance matching and improved CMRR and PSRR.
Bias Capacitor Selection
The LM49120 internally generates a VDD/2 common-mode
bias voltage. The BIAS capacitor CBIAS, improves PSRR and
THD+N by reducing noise at the BIAS node. Use a 2.2µF ce-
ramic placed as close to the device as possible.
www.national.com 24
LM49120
PCB LAYOUT GUIDELINES
Minimize trace impedance of the power, ground and all output
traces for optimum performance. Voltage loss due to trace
resistance between the LM49120 and the load results in de-
creased output power and efficiency. Trace resistance be-
tween the power supply and ground has the same effect as a
poorly regulated supply, increased ripple and reduced peak
output power. Use wide traces for power supply inputs and
amplifier outputs to minimize losses due to trace resistance,
as well as route heat away from the device. Proper grounding
improves audio performance, minimizes crosstalk between
channels and prevents digital noise from interfering with the
audio signal. Use of power and ground planes is recommend-
ed.
Place all digital components and route digital signal traces as
far as possible from analog components and traces. Do not
run digital and analog traces in parallel on the same PCB lay-
er. If digital and analog signal lines must cross either over or
under each other, ensure that they cross in a perpendicular
fashion.
Revision History
Rev Date Description
1.0 06/26/08 Initial release.
1.01 07/15/08 Edited the Ordering Information table.
25 www.national.com
LM49120
Physical Dimensions inches (millimeters) unless otherwise noted
16 – Bump micro SMD Package
Order Number LM49120TL
NS Package Number TLA00016
X1 = 2000μm±30m, X2 = 2000μm±30μm, X3 = 600μm
www.national.com 26
LM49120
Notes
27 www.national.com
LM49120
Notes
LM49120 Audio Sub-System with Mono Class AB Loudspeaker Amplifier and Stereo OCL/SE
Headphone Amplifier
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