LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Datasheet
The LXT972A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T app lications. It p rov ides a Media Ind epend ent In terface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs).
This document also supports the LXT972.
The LXT972A supports full-duplex operation at 10Mbps and 100Mbps. Its operating condition
can be set using auto-negotiat ion, parallel detection, or manual control.
The LXT972A is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
Product Features
■Combination 10BASE-T/100BASE-TX
Network Interface Cards (NICs) ■10/100 PCMCIA Cards
■Cable Modems and Set-Top Boxes
■3.3V Operation.
■Low powe r consumption (300 mW
typical).
■10BASE-T and 100BASE-TX using a
single RJ-45 connection.
■Supports auto-negotiation and parallel
detection.
■MII interface with extended register
capability.
■Robust baseline wander co rrection
performance.
■Standard CSMA/CD or full-dup lex
operation.
■Configurable via MDIO seria l port or
hardware control pins.
■Integrated, programmable LED drivers.
■64-pin Low-profile Quad Flat Package
(LQFP).
—LXT972ALC - Commercial (0 ° to 70°C
ambient).
As of January 15, 2001, this document replaces the Level One document Order Number: 249186-002
LXT972A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet. January 2001
Datasheet
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or lif e sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT972A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet 3
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Contents
1.0 Pin Assig nments............................................................................................................10
2.0 Signal Descriptions........................................................................................................13
3.0 Functional Description ..................................................................................................16
3.1 Introduction..........................................................................................................16
3.1.1 Compreh ens ive Fu nctio nal ity................ ................... ....... ...... ....... ..........16
3.1.2 OSP™ Architect ure..................................... ....... ...... ....... ...... ....... ..........16
3.2 Network Media / Protocol Support.......................................................................17
3.2.1 10/100 Network Interface.......................................................................17
3.2.1.1 Twisted-Pair Interface ...............................................................17
3.2.1.2 Fault Detection and Reporting...................................................17
3.2.2 MII Data Interface...................................................................................18
3.2.3 Configur ation Man age men t Inter face................. ...... ....... ...... ....... ...... ....1 8
3.2.3.1 MDIO Management Interface....................................................18
3.2.3.2 MII Interrupts .............................................................................19
3.2.3.3 Hardware Control Interface .......................................................19
3.3 Operating Requirements.....................................................................................20
3.3.1 Power Requirements..............................................................................20
3.3.2 Clock Requir em ents................. ...... ....... ...... ....... ...... .................... ...... ....20
3.3.2.1 External Crystal/Oscillator.........................................................20
3.3.2.2 MDIO Clock...............................................................................20
3.4 Initialization..........................................................................................................21
3.4.1 MDIO Control Mode ...............................................................................21
3.4.2 Hardware Control Mode.........................................................................21
3.4.3 Reduced Po wer Modes.................. ....... ...... ....... ...... ....... ...... ....... ...... ....2 2
3.4.3.1 Hardware Power Down .............................................................22
3.4.3.2 Software Power Down...............................................................22
3.4.4 Reset......................................................................................................23
3.4.5 Hardware Configuration Settings ...........................................................23
3.5 Establishing Link .................................................................................................24
3.5.1 Auto-Negotiation.....................................................................................24
3.5.1.1 Base Page Exchange................................................................24
3.5.1.2 Next Page Excha nge......... ....... ...... ....... ...... ....... ................... ....24
3.5.1.3 Controlling Auto-Negotiation .....................................................25
3.5.2 Parallel Detection...................................................................................25
3.6 MII Operation.......................................................................................................25
3.6.1 MII Clocks...............................................................................................26
3.6.2 Transmit Enable .....................................................................................26
3.6.3 Receive Data Valid.................................................................................26
3.6.4 Carrier Sense .........................................................................................26
3.6.5 Error Signals...........................................................................................26
3.6.6 Collision..................................................................................................26
3.6.7 Loopback................................................................................................28
3.6.7.1 Operational Loopback ...............................................................28
3.6.7.2 Test Loopback...........................................................................28
3.7 100Mbps Operation.............................................................................................29
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
4 Datasheet
3.7.1 100BASE-X Network Operations ...........................................................29
3.7.2 Collision Indication .................................................................................31
3.7.3 100BASE-X Protocol Sublayer Operations............................................31
3.7.3.1 PCS Sublayer............................................................................31
3.7.3.2 PMA Sublayer ...........................................................................34
3.7.3.3 Twisted-Pair PMD Sublayer......................................................34
3.8 10Mbps Operation...............................................................................................35
3.8.1 10T Preamble Handling .........................................................................35
3.8.2 10T Carrier Sense..................................................................................36
3.8.3 10T Dribble Bits......................................................................................36
3.8.4 10T Link Integrity Test............................................................................36
3.8.4.1 Link Failure................................................................................36
3.8.5 10T SQE (Heartbeat).............................................................................36
3.8.6 10T Jabber.............................................................................................36
3.8.7 10T Polarity Correction ..........................................................................37
3.9 Monitoring Operations.........................................................................................37
3.9.1 Monitoring Auto-Negotiation...................................................................37
3.9.1.1 Monitoring Next Page Exchange...............................................37
3.9.2 LED Functio ns.......... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ..............37
3.9.2.1 LED Pulse Stretching................................................................38
3.10 Boundary Scan (JTAG1149.1) Functions ...........................................................38
3.10.1 Boundary Scan Interface........................................................................38
3.10.2 State Machin e .. ....... ...... ....... ...... ................... ....... ...... ....... ...... ....... .......39
3.10.3 Instruction Register................................................................................39
3.10.4 Boundary Scan Register (BSR)..............................................................39
4.0 Application Information.................................................................................................40
4.1 Magnetics Information.........................................................................................40
4.2 Typical Twisted-Pair Interface.............................................................................40
5.0 Test Specifications ........................................................................................................44
5.1 Electrical Parameters..........................................................................................44
5.2 Timing Diag rams................................ ...... ...... ....... ...... ....... ................... ....... ...... .47
6.0 Register Definitions.......................................................................................................55
7.0 P ac kage Sp ec ificat ion ...................................................................................................70
Datasheet 5
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Figures 1 LXT972A Bl oc k Diagram.......... ....... ...... ................... ....... ...... ....... ...... ....... ............9
2 LXT972A 64-Pin LQFP Assignments..................................................................10
3 Management Interface Read Frame Structure ...................................................19
4 Management Interface Write Frame Structure ...................................................19
5 Interrupt Logic ....................................................................................................20
6 Initialization Sequence .......................................................................................22
7 Hardware Configuration Settings .......................................................................23
8 Link Establishment Overview .............................................................................25
9 10BASE-T Clocking ............................................................................................27
10 100BASE-X Clocking .........................................................................................27
11 Link Down Clock Transition ................................................................................27
12 Loopback Paths ..................................................................................................28
13 100BASE-X Frame Format ................................................................................29
14 100BAS E-TX Data Path ................. ...... ................... ....... ...... ....... ...... ....... ..........29
15 100BASE-TX Reception with no Errors ..............................................................30
16 100BASE-TX Reception with Invalid Symbol .....................................................30
17 100BASE-TX Transmission with no Errors .......................................................31
18 100BASE-TX Transmission with Collision .........................................................31
19 Protocol Sublayers .............................................................................................32
20 LED Pulse Stretching .........................................................................................38
21 Typical Twisted-Pair Interface - Switch ...............................................................41
22 Typical Twisted-Pair Interface - NIC ...................................................................42
23 Typical MII Interface ...........................................................................................43
24 100BAS E-TX Rec ei ve Timing - 4B Mode ................ ....... ...... ....... ...... .................47
25 100BAS E-TX Tra nsmit Timing - 4B Mode .. ....... ...... ....... ...... ....... ...... ....... ..........48
26 10BASE-T Receive Timing .................................................................................49
27 10BASE-T Transmit Timing ................................................................................50
28 10BASE -T Jabbe r and Unjabbe r Timing ................. ....... ................... ....... ...... ....5 1
29 10BASE-T SQE (Heartbeat) Timing ...................................................................51
30 Auto Negotiation and Fast Link Pulse Timing ....................................................52
31 Fast Link Pulse Timing .......................................................................................52
32 MDIO Input Timing .............................................................................................53
33 MDIO Output Timing ..........................................................................................53
34 Power-Up Timi ng .. ...... ....... ...... ....... ...... ................... ....... ...... ....... ...... ....... ..........54
35 RESET Pulse Width and Recovery Timing ........................................................54
36 PHY Identifier Bit Mapping .................................................................................60
37 LXT972A LQFP Package Specifications ............................................................70
Tables 1 LQFP Numeric Pin List.......................................................................................11
2 LXT972A MII Signal Descriptions........................................................................13
3 LXT972A Network Interface Signal Descriptions ................................................14
4 LXT972A Miscellaneous Signal Descriptions......................................................14
5 LX T97 2A Power Supply Si gnal Descr ipt ion s ........................ ....... ...... .................15
6 LX T97 2A JTA G Test Signa l Descr ip tio ns .......... ................... ....... ...... ....... ..........15
7 LXT972A LED Signal Descriptions......................................................................15
8 Hardware Configuration Settings ........................................................................24
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
6 Datasheet
9 Carrier Sense, Loopback, and Collision Conditions............................................28
10 4B/5B Codi ng.... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ................... ....... ...... .33
11 BSR Mode of Operation......................................................................................39
12 Supported JTAG Instructions..............................................................................39
13 Device ID Register ..............................................................................................39
14 Magnetics Requirements ....................................................................................40
15 RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces ....................40
16 Absolute Maximum Ratings ................................................................................44
17 Operating Conditions ..........................................................................................44
18 Digital I/O Characteristics 1.................................................................................45
19 Digital I/O Characteristics - MII Pins ...................................................................45
20 I/O Characteristics - REFCLK/XI and XO Pins....................................................45
21 I/O Characte ris tics - LED /CFG Pins......... ...... ....... ...... ....... ...... ....... ...... ..............45
22 100BASE-TX Transceiver Characteristics ..........................................................46
23 10BASE-T Transceiver Characteristics...............................................................46
24 10BASE-T Link Integrity Timing Characteristics .................................................46
25 100BASE-TX Receive Timing Parameters - 4B Mode........................................47
26 100BASE-TX Transmit Timing Parameters - 4B Mode.......................................48
27 10BASE-T Receive Timing Parameters..............................................................49
28 10BASE-T Transmit Timing Parameters.............................................................50
29 10BASE-T Jabber and Unjabber Timing Parameters .........................................51
30 10BASE-T SQE Timing Parameters...................................................................51
31 Auto Negotiation and Fast Link Pulse Timing Parameters..................................52
32 MDIO Timing Parameters ...................................................................................53
33 Power-Up Timing Parameters............................................................................54
34 RESET Pulse Width and Recovery Timing Parameters ....................................54
35 Register Set ........................................................................................................55
36 Register Bit Map..................................................................................................56
37 Control Register (Address 0)...............................................................................58
38 MII Status Register #1 (Address 1).....................................................................58
39 PHY Identification Register 1 (Address 2)...........................................................59
40 PHY Identification Register 2 (Address 3)...........................................................60
41 Auto Negotiation Advertisement Register (Address 4)........................................61
42 Auto Negotiation Link Partner Base Page Ability Register (Address 5)..............62
43 Auto Negotiation Expansion (Address 6) ............................................................63
44 Auto Negotiation Next Page Transmit Register (Address 7)...............................63
45 Auto Negotiation Link Partner Next Page Receive Register (Address 8) ...........64
46 Configuration Register (Address 16, Hex 10) .....................................................64
47 Status Register #2 (Address 17).........................................................................65
48 Interrupt Enable Register (Address 18)...............................................................66
49 Interrupt Status Register (Address 19, Hex 13) ..................................................66
50 LED Configuration Register (Address 20, Hex 14) .............................................68
51 Transmit Control Register #2 (Address 30).........................................................69
Datasheet 7
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Revision History
Revision Date Description
002 January 2001 Clock Requirements: Modified language under Clock Requirements heading.
I/O Characteristics REFCLK (table): Changed values for Input Clock Duty
Cycle under Min from 40 to 35 and under Max from 60 to 65.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 9
Figure 1. LXT972A Block Diagram
TX_EN
RX_ER
CRS
Pwr Supply
Management /
Mode Select
Logic
ADDR0
MDIO
MDC
MDINT
TX_ER
RXDV
TPON
TPOP
TPIN
TPIP
REFCLK
VCC
GND
COL
RX_CLK
TX_CLK
RESET
LED/CFG<3:1>
TXD<3:0>
Decoder &
Descrambler
+
-
Serial-to-
Parallel
Converter
Scrambler
& Encoder
Parallel/Serial
Converter
Carrier Sense
Data Valid
Error Detect
Auto
Negotiation
Manchester
Decoder
Manchester
Encoder
10
100
10
100
Media
Select
TP
Driver
TP Out
Register
Set
Register Set Clock
Generator
+
-
10BT
Collision
Detect Clock
Generator
TX PCS
OSP
™
Adaptive EQ with
Baseline Wander
Cancellation
OSP
™
Slicer
OSP
™
Pulse
Shaper
RXD<3:0>
+
-
100TX
TP In
MDDIS TxSLEW<1:0>
RX PCS
PWRDWN
JTAG
TDI,
TDO,
TMS,
TCK,
TRST
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
10 Datasheet
1.0 Pin Assignments
Figure 2. LXT972A 64-Pin LQFP Assignments
Package Topside Markings
Marking Definition
Part # LXT972A is the unique identifier for this product family.
Rev # Identifies the particular silicon “stepping” (Refer to Specification Update for additional stepping
information.)
Lot # Identifies the batch.
FPO # Identifies the Finish Process Order.
RXD0
RBIAS 17 64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REFCLK/XI
XO
MDDIS
RESET
TXSLEW0
TXSLEW1
GND
VCCIO
N/C
N/C
GND
ADDR0
GND
GND
GND
GND
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
TPOP
TPON
VCCA
VCCA
TPIP
TPIN
GND
GND
TDI
TDO
TMS
TCK
TRST
GND
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RXD1
RXD2
RXD3
N/C
MDC
MDIO
GND
VCCIO
PWRDWN
LED/CFG1
LED/CFG2
LED/CFG3
TEST1
TEST0
PAUSE
MDINT
CRS
COL
GND
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
TX_ER
RX_ER
RX_CLK
VCCD
GND
RX_DV
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
LXT972A XX
XXXXXX
XXXXXXXX
Part #
LOT #
FPO #
Rev #
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 11
Table 1. LQFP Numeric Pin List
Pin Symbol Type Reference for
Full Description
1 REFCLK/XI Input Table 4 on page 14
2 XO Output Table 4 on page 14
3 MDDIS Input Table 2 on page 13
4 RESET Input Table 4 on page 14
5 TxSLEW0 Input Table 4 on page 14
6 TxSLEW1 Input Table 4 on page 14
7GND –Table 5 on page 15
8 VCCIO –Table 5 on page 15
9N/C –Table 4 on page 14
10 N/C –Table 4 on page 14
11 GND –Table 5 on page 15
12 ADDR0 Input Table 4 on page 14
13 GND –Table 5 on page 15
14 GND –Table 5 on page 15
15 GND –Table 5 on page 15
16 GND –Table 5 on page 15
17 RBIAS Analog Input Table 4 on page 14
18 GND –Table 5 on page 15
19 TPOP Output Table 3 on page 14
20 TPON Output Table 3 on page 14
21 VCCA –Table 5 on page 15
22 VCCA –Table 5 on page 15
23 TPIP Input Table 3 on page 14
24 TPIN Input Table 3 on page 14
25 GND –Table 5 on page 15
26 GND –Table 5 on page 15
27 TDI Input Table 6 on page 15
28 TDO Output Table 6 on page 15
29 TMS Input Table 6 on page 15
30 TCK Input Table 6 on page 15
31 TRST Input Table 6 on page 15
32 GND –Table 5 on page 15
33 PAUSE Input Table 4 on page 14
34 TEST0 Input Table 4 on page 14
35 TEST1 Input Table 4 on page 14
36 LED/CFG3 I/O Table 7 on page 15
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
12 Datasheet
37 LED/CFG2 I/O Table 7 on page 15
38 LED/CFG1 I/O Table 7 on page 15
39 PWRDWN Input Table 4 on page 14
40 VCCIO –Table 5 on page 15
41 GND –Table 5 on page 15
42 MDIO I/O Table 2 on page 13
43 MDC Input Table 2 on page 13
44 N/C –Table 4 on page 14
45 RXD3 Output Table 2 on page 13
46 RXD2 Output Table 2 on page 13
47 RXD1 Output Table 2 on page 13
48 RXD0 Output Table 2 on page 13
49 RX_DV Output Table 2 on page 13
50 GND –Table 5 on page 15
51 VCCD –Table 5 on page 15
52 RX_CLK Output Table 2 on page 13
53 RX_ER Output Table 2 on page 13
54 TX_ER Input Table 2 on page 13
55 TX_CLK Output Table 2 on page 13
56 TX_EN Input Table 2 on page 13
57 TXD0 Input Table 2 on page 13
58 TXD1 Input Table 2 on page 13
59 TXD2 Input Table 2 on page 13
60 TXD3 Input Table 2 on page 13
61 GND –Table 5 on page 15
62 COL Output Table 2 on page 13
63 CRS Output Table 2 on page 13
64 MDINT Open Drain Table 2 on page 13
Table 1. LQFP Numeric Pin List (Continued)
Pin Symbol Type Reference for
Full Description
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 13
2.0 Signal Descriptions
Table 2. LXT972A MII Signal Descriptions
LQFP
Pin# Symbol Type1Sign al Description
Data Interface Pins
60
59
58
57
TXD3
TXD2
TXD1
TXD0
ITran smit Dat a. TXD is a bundle of parallel data signals that are driven by the MAC.
TXD<3:0> shall transition synchronously with respect to the TX_CLK. TXD<0> is the least
significant bit.
56 TX_EN I Transmit Enable. The MAC asserts this signal when it drives valid data on TXD. This
signal must be synchronized to TX_CLK.
55 TX_CLK O Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100Mbps operations. 2.5
MHz for 10Mbps operation, 25 MHz for 100Mbps operation.
45
46
47
48
RXD3
RXD2
RXD1
RXD0
OReceive Data. RXD is a bundle of parallel signals that transition synchronously with
respect to the RX_CLK. RXD<0> is the least significant bit.
49 RX_DV O Receive Data Valid. The LXT972A asserts this signal when it drives valid data on RXD.
This output is synchronous to RX_CLK.
53 RX_ER O Receive Error. Signals a receive error condition has occurred. This output is synchronous
to RX_CLK.
54 TX_ER I Transmit Error. Signals a transmit error condition. This signal must be synchronized to
TX_CLK.
52 RX_CLK O Receive Clock. 25 MHz for 100Mbps operation, 2.5 MHz for 10Mbps operation. Refer to
“Clock Requirements” on page 20 in the Functional Description section.
62 COL O Collision Detected. The LXT972A asserts this output when a collision is detected. This
output remains High for the duration of the collision. This signal is asynchronous and is
inactive during full-duplex operation.
63 CRS O
Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT972A asserts this output
when either transmitting or receiving data packets. During full-duplex operation (bit 0.8 = 1),
CRS is asserted during receive. CRS assertion is asynchronous with respect to RX_CLK.
CRS is de-asserted on loss of carrier, sync hronous to RX_C LK.
MII Control Interface Pins
3 MDDIS I
Management Dis a ble. When MDDIS is High, the MDIO is disabled from read and write
operations.
When MDDIS is Low at power up or reset, the Hardware Control Interface pins control only
the initial or “default” values of their respective register bits. After the power-up/reset cycle
is complete, bit control reverts to the MDIO serial channel.
43 MDC I Management Data Clo c k . Clock for the MDIO serial data channel. Maximum frequency is
8 MHz.
42 MDIO I/O Manageme nt Data Input/O utput. Bidirectional serial data channel for PHY/STA
communication.
64 MDINT OD Management Dat a Interr upt. When bit 18.1 = 1, an active Low output on this pin indicates
status change. Interrupt is cleared by reading Register 19.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
14 Datasheet
Table 3. LXT972A Network Interface Signal Descriptions
LQFP
Pin# Symbol Type1Signal Description
19
20 TPOP
TPON OTwis ted-Pair Outputs, Positive & Negative.
During 100BASE-TX or 10BA SE- T operation, TPOP/N pins drive 802.3 compliant
pulses onto the line.
23
24 TPIP
TPIN ITwis ted-Pair Inputs, Positive & Negative.
During 100BASE-TX or 10BA SE- T operation, TPIP/N pins receive differential
100BASE-TX or 10BASE-T signals from the line.
1. T y pe Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Table 4. LXT972A Miscellaneous Signal Descriptions
LQFP
Pin# Symbol Type1Signal Description
5
6TxSLEW0
TxSLEW1 I
Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate (rise
and fall time) as follows:
TxSLEW1 TxSL EW0 Slew Rate (Rise and Fall Time)
002.5 ns
013.1 ns
103.7 ns
114.3 ns
4 RESET I
Reset. This active Low input is OR’ed with the control register Reset bit (0.15). The
LXT972A reset cycle is extended to 258 µs (nominal) after reset is deasserted.
12 ADDR0 I Address0. Sets device address.
17 RBIAS AI Bias. This pin provides bias current for the internal circuitry. Must be tied to ground
through a 22.1 kΩ, 1% re sistor.
33 PAUSE I Pause. When set High, the LXT972A advertises Pause capabilities during auto
negotiation.
34 TEST0 I Test. Tie Low.
35 TEST1 I Test. Tie Low.
39 PWRDWN I Power Down. When set High, this pin puts the LXT972A in a power-down mode.
1
2REFCLK/XI
XO I
O
Crystal Input and Output. A 25 MHz crystal oscillator circuit can be connected
across XI and XO. A clock can also be used at XI. Refer to Functional Description for
detailed clock requirements.
9, 10,
44 N/C - No Connection. These pins are not used and should not be terminated.
1. T y pe Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 15
Table 5. LXT972A Power Supply Signal Descriptions
LQFP
Pin# Symbol Type Signal Description
51 VCCD - Digital Power. Requires a 3.3V power supply.
7, 11, 13,
14, 15,
16, 18,
25, 26,
32, 41,
50, 61
GND - Ground.
8, 40 VCCIO - MII Power. Requires either a 3.3V or a 2.5V supply. Must be supplied from the same
source used to power the MAC on the other side of the MII.
21, 22 VCCA - Analog Power. Requires a 3.3V power supply.
Table 6. LXT972A JTAG Test Signal Descriptions
LQFP
Pin# Symbol Type1Signal Descript ion
27 TDI2ITest Data Input. Test data sampled with respect to the rising edge of TCK.
28 TDO2OTest Data Outp u t. Test data driven with respect to the falling edge of TCK.
29 TMS2ITest Mo de Select.
30 TCK2ITest Clock. Test clock input sourced by ATE.
31 TRST2ITest Reset. Test reset input sourced by AT E.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
2. If JTAG port is not used, these pins do not need to be terminated.
Table 7. LXT972A LED Signal Descriptions
LQFP
Pin# Symbol Type1Signal Description
38
37
36
LED/CFG1
LED/CFG2
LED/CFG3 I/O
LED Drivers 1 -3. These pins drive LED indicators. Each LED can display one of
several available status conditions as selected by the LED Configuration Register
(refer to Table 50 on page 68 for details).
Configura tion Inp uts 1-3. These pins also provide initial configuration settings (refer
to Table 8 on page 24 for details).
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
16 Datasheet
3.0 Functional Description
3.1 Introduction
The LXT972A is a single-port Fast Ethernet 10/100 Transceiver that supports 10Mbps and
100Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT972A
can directly drive either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185
meters).
3.1.1 Comprehensive Functionality
The LXT972A provides a standard Media Independent Interface (MII) for 10/100 MACs. The
LXT972A performs all functions of the Physical Coding Sublayer (PCS) and Physical Media
Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. This device also
performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections.
On power-up, the LXT972A reads its configuration pins to check for forced operation settin gs. If
not configured for forced operation, it uses auto-negotiation/parallel detectio n to automatically
determine line operating condi tions. If the PHY device on the other side of the link support s auto-
negotiation, the LX T97 2A auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY
partner does not sup por t auto- negotiation, the LXT972A automatically d e tects the presence of
either link pulses (10Mbps PHY) or Idle symbols (100Mbps PHY) and set its operating conditions
accordingly.
The LXT972A provides half-duplex and f ull- duple x operation at 10 0Mbp s and 10Mbps .
3.1.2 OSP™ Architecture
Intel’s LXT972A incorporates high-efficiency Optimal Signal Processing™ design tech niques,
combining the best properties of digital and analog signal processing to produce a truly optimal
device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equa lizer. Using OSP mixed-signal processing techni ques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). This
results in improved receiver noise and cross-talk performance.
The OSP signal processin g s c heme also requires substantially less computational logic than
traditional DSP-based designs. This lowers power consumption and also reduces the logic
switching noise generated by DSP engines. This logic switching noise can be a considerable
source of EMI generated on the device’s power supplie s .
The OSP-based LXT972A provides improved data recovery, EMI performance and low power
consumption.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 17
3.2 Network Media / Protocol Support
The LXT972A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair.
3.2.1 10/100 Network Interface
The network interf ace port co nsists of two dif fer ential signal pair s. Refer to Table 3 for s pecific pin
assignments.
The LXT972A output drivers generate either 100BASE-TX or 10BASE-T. When not transmitting
data, the LXT972A generates 802.3-compliant link pulses or idle code. Input signals are decoded
either as a 100BASE-TX or 10BAS E-T in put, depen ding on the mode s elected. Auto -neg otia tio n/
parallel detection or manual control is used to determine the speed of this interface.
3.2.1.1 Twisted-Pair Interface
The LXT972A supports either 100BASE-TX or 10BASE-T connections over 100Ω, Category 5,
Unshielded Twisted Pair (UTP) cable. When operating at 100Mbps, the LXT972 A contin uously
transmits and receives MLT3 symbols. When not transmittin g data, the LX T972A generat es
“IDLE” symbols.
During 1 0Mbp s operation, Manchester-enc oded data is exc hanged. When no data is bein g
exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link
up.
Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete
this interface. On the transmit side, the LXT972A has an active internal termination and does not
require external termination resistors. Intel's patented waveshaping technology shapes the outgoing
signal to help reduce the need for external EMI filters. Four slew rate settin gs (refer to Table 4 on
page 14) allow the designer to match the output waveform to the magnetic characteristics. On the
receive side, the internal impedance is high enough that it has no practical effect on the external
termination circu it.
3.2.1.2 Fault Detection and Reporting
The LXT972A supports one fault detection and reporting mechani sm. “Remote Fault” refers to a
MAC-to-MAC commu nication fun ction that is essentially transparent to PHY layer d e vices. It is
used only during Auto-Negotiation, and therefore is applicable only to twisted-pair links. “Far-End
Fault”, on the other hand, is an optional PMA-layer function th at may b e embedded within PHY
devices. The LXT972A supports only the Remote Fault Function, explained in the paragraph that
follows.
Remote Fault
Bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault indications.
It is typically used when re-starting the auto-negotiation sequence to indicate to the link partner
that the link is down because the advertising device detected a fault.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
18 Datasheet
When the LXT972A receives a Remote Fault indication fro m its partn er du ring au to-neg otiation it:
•sets bit 5.13 in the Link Partner Base Page Ability Reg ister, and
•sets the Remo te Fault bit 1.4 in the MII Status Register to pass this information to the local
controller.
3.2.2 MII Data Interface
The LXT972A supports a standard Media Independent Interface (MII). The MII consists of a data
interface and a management interface. The MII Data Interface passes data between the LXT972A
and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and
receive. This interf ace o perates at either 1 0Mb ps or 100Mbps. Th e s peed is set autom atically, once
the operating conditio ns of the netwo rk lin k have been determined. Refer to “MII Operation” on
page 25 for additional details.
3.2.3 Configuration Management Interface
The LXT972A provides both an MDIO interface and a Hardware Control Interface for device
configurati on an d manageme nt.
3.2.3.1 MDIO Management Interface
The LXT972A supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT972A. The MDIO interface consists of a physical
connection, a specific protocol that runs across the connection, and an internal set of addressable
registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT972A also supports additio nal register s for expanded functionality. The LXT972A supports
multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using
an “X.Y” notation, where X is the register number (0-31) and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write
operations are disabled and the Hardware Control Interf ace provides primary configuration contr ol.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
MDIO Addressing
The protocol allows one controller to communicate between two LXT972A chips. Pin ADDR0 is
set high or low to determine the chip address .
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 19
MDIO Frame Structure
The physical interf ace consists of a data line (MDI O) and clock line (MDC). The frame stru cture is
shown in Figure 3 and Figure 4 (read and write). MDIO Interface timing is shown in Table 32 on
page 53.
3.2.3.2 MII Interrupts
The LXT972A provides a single interrupt pin (MDINT). Interrupt lo gic is shown in Figure 5. The
LXT972A also provides two dedicated interrupt registers. Register 18 provides interrupt enable
and mask functions and Register 19 provides interrupt status. Setting bit 18.1 = 1, enables the
device to request interru pt via the MDINT p in. An active Low on th is pin indicates a st atus chang e
on the LXT972A. Interrupts may be caused by four conditions:
•Auto-negotiatio n com plete
•Speed status change
•Duplex status change
•Link status change
3.2.3.3 Hardware Control Interface
The LXT972A provides a Hardware Control Interface for applications where the MDIO is not
desired. The Har dware Control Interface uses the three LED driver pin s to set device configuration .
Refer to Secti on 3. 4.5, “Hardware Configuration Settings” on page 23 for additio nal d e tails.
Figure 3. Management Interface Read Frame Structure
Figure 4. Management Interface Write Frame Structure
MDC
MDIO
(Read)
32 "1"s 0110
Preamble ST Op Code PHY Address Turn
Around
Z0
A4 A3 A0 R4 R3 R0
Register Address
D15 D14 D1
Data
Write Read
D15 D14 D1 D0
Idle
High Z
MDC
MDIO
(Write)
32 "1"s 0101
Preamble ST Op Code PHY Address Turn
Around
10
A4 A3 A0 R4 R3 R0
Register Address
D15 D14 D1 D0
Data Idle
Idle
Write
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
20 Datasheet
3.3 O per ating Requirements
3.3.1 Power Requirements
The LXT972A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and
analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied from a
single source. Each supply input must be decoupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either +2.5V or
+3.3V. Also, the inputs on the MII interface are tolerant to 5V signals from the controller on the
other side of the MII interface. Refer to Tab l e 19 on page 45 for MII I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible.
3.3.2 Clock Requirement s
3.3.2.1 External Crystal/Oscil lator
The LXT972A r equires a reference clock inp ut that is u sed to g enerate trans mit signals a nd recov er
receive signals. It may be provided by either of two methods: by connecting a crystal across the
oscillator pins (XI and XO), or by conn ecting an external clock sou rce to pin XI . The co nnectio n of
a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is
recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the
LXT971A/972A Design and Layout Guide for a list of recommended clock sources.
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a
crystal, is frequently used in switch applications. Refer to Table 20 on page 45 for clock timing
requirements
3.3.2.2 MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. Refer to Table 32 on page 53 for details.
Figure 5. Interrupt Logic
Force Interrupt Int erru pt Ena ble
Event X Mask Reg
Event X Status Reg
Interrupt Pin
.
.
.
AND
OR
NAND
Per Event
1. Interrupt (Event) Status Register is cleared on read.
(MDINT)
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 21
3.4 Initialization
When the LXT972A is first powered on, reset, or encounters a link failu r e state, it checks the
MDIO register configuration bits to determine the line speed and operating conditions to use for
the network link. The con figur ation b i ts m ay b e s et by the Hardware Co ntrol or MDIO interf ace as
shown in Figure 6.
3.4.1 MD IO Control Mode
In the MDIO Control mode, the LXT972A reads the Hardware Control Interface pins to set the
initial (default) values of th e MDIO reg ister s. Once the initial values are set, bit control reverts to
the MDIO interface.
3.4.2 Hardware Control Mode
In the Hardware Control Mode, LXT972A disables direct write operations to the MDIO registers
via the MDIO Interface. On po wer- up or hardware r eset the LXT972A reads the Hardware Control
Interface pins and sets the MDIO registers accordingly.
The following modes are available using either Hardware Control or MDIO Control:
•Force network l ink ope ration to:
100TX, Full-Duplex.
100TX, Half-Duplex.
10BAS E-T, Full- Dup le x.
10BASE-T, Half-Duplex .
•Allow auto-negotiation / parallel-detection.
When the network link is forced to a specific configuration, the LXT972A immediately begins
operating the network interface as commanded. When auto-negotiation is enabled, the LXT972A
begins the auto-negotiation / parallel-detection operation.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
22 Datasheet
3.4.3 Reduced Power Modes
The LXT972A offers two power-down modes.
3.4.3.1 Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,
the following conditions are true :
•The LXT972A network port and clock are shut down.
•All outputs are tri-stated.
•All weak pad pull-up and pull-down resistors are disabled.
•The MDIO registers are not accessible.
3.4.3.2 S oftware Power Down
Software power-down control is provided by bit 0.11 in the Control Register (refer to Table 37 on
page 58). During soft power-down, the following conditions are true:
•The network po rt is sh ut dow n.
•The MDIO registers remain accessible.
Figure 6. Initialization Sequence
MDDIS Voltage
Level?
HighLow
MDIO Control
Mode Hardware Control
Mode
Disable MDIO Read and
Write Operations
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
MDIO Controlled Operation
(MDIO Writes Enabled)
Power-up or Reset
Initialize MDIO Registers
Read H/W Control
Interface
Software
Reset?
Yes
No
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 23
3.4.4 Reset
The LXT972A provides both hardware and software resets. Configuration control of Auto-
Negotiation, speed and duplex mode selection is handled differently for each. During a hardware
reset, Auto-Negotiation and Speed are read in from pins (refer to Table 8 on page 24 for pin
settings and to Table 37 on page 58 for register bit definitions).
During a software re set (0 .15 = 1), th ese bit se ttings are no t re-r ead from the p ins. They revert back
to the values that were read in during the last hardware reset. Therefore, any changes to pin values
made since the last hardware reset are not detected during a software reset.
During a hardware res et, register infor mation is unavailab le for 1 ms after de-asser tion of the reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0).
3.4.5 Hardware Configuration Settings
The LXT972A provides a hardware option to set th e initial device configuration. The hardware
option uses the three LED driver pins. This provides three control bits, as listed in Table 8. The
LED drivers can operate as either open-drain or open-source circuits as shown in Figure 7.
.
Figure 7. Hardware Configuration Settings
Configur ation Bit = 1
Configuration Bit = 0
LED/CFG Pin
LED/CFG Pin
1. The LED/CFG pins automatically
adjust their polarity upon power-
up or reset.
3.3V
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
24 Datasheet
3.5 Establishing Link
See Figure 8 for an overview of link establishment.
3.5.1 Auto-Negotiation
If not configured for forced operation, the LXT972A attempts to auto-negotiate with its li nk
partner by sending Fast Lin k Pulse (FLP) b ursts. Each b urst con sists of up to 33 link pulses spaced
62.5 µs apart. Odd link pulses (clock pulses) are always pr esent. Even link pulses (data pu lses) may
be present or absent to indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data, which are
referred to as a “link code word”. All devices that support auto-negotiation must implement the
“Base P age” defined by IEEE 802.3 (registers 4 and 5). LXT972A also supports the optional “Next
Page” function as descr ibed in Table 44 and Table 45 (registers 7 and 8).
3.5.1.1 B ase Page Exchange
By exchanging Base Pages, the LX T972A and its link partner communicate their capabilities to
each other. Both sides must receive at least three identical base pages for negotiation to continue.
Each side identifies the hig hes t comm on capabilities that both sides support and configures itself
accordingly.
3.5.1.2 Next Page Exchange
Additional information, above that required by base page exchange, is also sent via “Next Page s’.
The LXT972A fully supports the IEEE 802.3ab method of negotiation via Next Page exchange.
Table 8. Hardware Configuration Settings
Desired Mode LED/CFGn
Pin Settings1
Resulting Register Bit Values
Control Register Auto-Neg Advertisement
Auto-Neg Speed
(Mbps) Duplex 1 2 3 AutoNeg
0.12 Speed
0.13 FD
0.8 100FD
4.8 100TX
4.7 10FD
4.6 10T
4.5
Disabled
10 Half Low Low Low
0
00
N/A
Auto-Negotiation Advertis emen t
Full Low Low High 1
100 Half Low High Low 10
Full Low High High 1
Enabled
100 Only Half High Low Low
11
00 1 00
Full High Low High 1 1 1 0 0
10/100 Half Only High High Low 0 0 1 0 1
Full or
Half High High High 1 1 1 1 1
1. Refer to Table 7 on page 15 for LED/CFG pin assignments.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 25
3.5.1.3 Controlling Auto-Negotiation
When auto-negotiation is controlled by software, the following steps are recommended:
•After power- up, power -down, or reset, the power -down recovery time, as specified in Table 34
on page 54, must be exhausted before proceeding.
•Set the auto-negotiation advertisement register bits.
•Enable auto-negotiation (set MDIO bit 0.12 = 1).
3.5.2 Parallel Detection
For the parallel detection featu re of auto-negotiation, the LXT972A also monitors for 10BASE-T
Normal Link Pulses (NLP) and 100BASE-TX Idle symbols. If either is detected, the device
automatically reverts to the corresponding operating mode. Parallel detection allows the LXT972A
to communicate with devices th at do not su pport auto-negotiation.
3.6 MII Operation
The LXT972A device implements the Media Independent Interface (MII) as defined in the IEEE
802.3 standard. Separate channels ar e pro vided for transm itting data from the MAC to the
LXT972A (TXD), and for passing data received from the line (RXD) to the MAC. Each channel
has its own clock, data bus, and control signals. Nine signals are used to pass received data to the
MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL, and CRS. Seven signals are used to transmit
data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and TX_ER.
Figure 8. Link Establishment Overview
Check Value
0.12
Start
Done
Enable
Auto-Neg/Parallel Detection
Go To Forced
Settings Attempt Auto-
Negotiation Listen for 10T
Link Pulses
Listen for 100TX
Idle Symbols
Link Up?
NOYES
Power-Up, Reset,
or Link Failure
Disable
Auto-Negotiation 0.12 = 0 0.12 = 1
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
26 Datasheet
The LXT972A supplies both clock signals as well as separate outputs for carrier sense and
collision. Data tran smission across the MII is normally im plemented in 4-bit-wide nibbles.
3.6.1 MII Clocks
The LXT972A is the master clock source for data transmission and supplies both MII clocks
(RX_CLK and TX_CLK). It autom atically sets the clock speeds to match link condi tions. When
the link is operating at 100Mbps, the clocks are set to 25 MHz. When the link is operating at
10Mbps, the clocks are set to 2.5 MHz. Figure 9 throu gh Figure 11 show the clock cycles for each
mode. The transmit data and control signals must always be synchronized to TX_CLK by the
MAC. The LXT972A samples these signals on the rising edge of TX_CLK.
3.6.2 Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, an d de-as s ert TX_EN
after the last bit of the packet.
3.6.3 Recei ve Data Valid
The LXT972A asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
•For 100TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the
data packet.
•For 10BT links, the entire p reamble is truncated. RX_DV is asserted with the first nibble of the
Start of Frame Delim iter (S FD) “5D” and remains asserted until the end of the packet.
3.6.4 Carri er Sense
Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received
from the line and in half-duplex when a packet is transmitted.
Carrier sense is not generated when a packet is transmitted and in full-duplex mod e. Table 9
summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
3.6.5 Error Signals
When LXT972A is in 100Mbps mode and receives an invalid symbol from the network, it asserts
RX_ER and drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT972A drives “H” symbols out on the TPOP/N pins.
3.6.6 Collision
The LXT972A asserts its collision signal, asynchronously to any clock, whenever the line state is
half-duplex and the transmitter and receiver are active at the same tim e. Table 9 summarizes the
conditions for assertion of carrier sense, collision, and data loopback signals.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 27
Figure 9. 10BASE-T Clocking
Figure 10. 100BASE-X Clocking
Figure 11. Link Down Clock Transition
RX_CLK
(Sourced by LXT972)
2.5 MHz during Auto-Negotiation and 10BASE-T Data & Idle
TX_CLK
(Sourced by LXT972)
2.5 MHz during Auto-Negotiation and 10BASE-T Data & Idle
Constant 25 MHz
XI
RX_CLK
(Sourced by LXT972)
2.5 MHz during Auto-Negotiation
TX_CLK
(Sourced by LXT972)
Constant 25 MHz
XI
25 MHz once 100BASE-X
Link Established
2.5 MHz during Auto-Negotiation 25 MHz once 100BASE-X
Link Established
Any Clock 2.5MHz Clock
Clock transition time will not exceed 2X the
Link Down condition/Auto Negotiate Enabled
RX_CLK
TX_CLK
nominal clock period: (10Mbps = 2.5 MHz; 100Mbps = 25 MHz)
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
28 Datasheet
3.6.7 Loopback
The LXT972A provides two loopback functions, operational and test (see Table 9). Loopback
paths are shown in Figure 12.
3.6.7.1 O perational Loopback
Operational loopback is provided for 10Mbps half-duplex links when bit 16.8 = 0. Data transmitted
by the MAC (TXData) is looped back on the receive side of the MII (RXData). Operational
loopback is not provided for 100Mbps links, full-duplex links, or when 16.8 = 1.
3.6.7.2 Test Loopback
A test loopback function is provided for diagnostic testing of the LXT972A. During test loopback,
the twisted-pair interface is disabled. Data transmitted by the MAC is internally looped back by the
LXT972A and returned to the MAC.
Test loopback is available for both 100TX and 10T operation. Test loopback is enabled by setting
bits as follows :
• 0.14 = 1
•0.8 = 1 (full-duplex)
•0.12 = 0 (disable auto-negotiati on).
Figure 12. Loopback Paths
Table 9. Carrier Sense, Loopback, and Collision Conditions
Speed Duplex Condition Carrier Sense Test1
Loopback Operational
Loopback Collision
100Mbps Full-Duplex Receive Only Yes No None
Half-Duplex Transmit or Receive No No Transmit and Receive
10Mbps
Full-Duplex Receive Only Yes No None
Half-Duplex, 16.8 = 0 Transmit or Receive Yes Yes Transmit and Receive
Half-Duplex, 16.8 = 1 Transmit or Receive No No Transmit and Receive
1. Tes t Loopback is enabled when 0.14 = 1
10T
Loopback
Digital
Block
MII
TX Drive r
100X
Loopback
Analog
Block
LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 29
3.7 100Mbps Operation
3.7.1 100BASE-X Network Operations
During 100BASE-X operation, the LXT972A transmits and receives 5-bit symbols across the
network link. Figure 13 shows the structure of a standard frame packet. When the MAC is not
actively transmittin g da ta, the LXT972A sends out Idle symbols o n the lin e.
In 100TX mode, the LXT972A scrambles and transmits the data to the network using MLT-3 line
code (Figure 14 on page 29). MLT-3 signals received from the network are descrambled, decoded,
and sent across the MII to the MAC.
.
Figure 13. 100BASE-X Fr ame Format
Figure 14. 100BASE-TX Data Path
P0 P1 P6
SFD
64-Bit Preamble
(8 Octets)
Start-of-Frame
Delimiter (SFD)
DA DA SA SA
Destination and Source
Address (6 Octets each)
L1 L2
Packet Length
(2 Octets)
D0 D1 Dn
Data Field
(Pad to minimum packet size) Frame Check Field
(4 Octets)
CRC I0
InterFrame Gap / Idle Code
(> 12 Octets)
Replaced by
/T/R/ code-groups
End-of-Stream Delimiter (ESD)
IFG
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
S0
S1
S2
S3
S4
Parallel
to
Serial
Serial
to
Parallel
MLT3
0
+1
-1
00
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Scrambler Bypass Data Flow
S0 S1 S2 S3 S4
Standard Data Flow
D0
D1
D2
D3
Parallel
to
Serial
Serial
to
Parallel
D0 D1 D2 D3
4B/5B
S0 S1 S2 S3 S4
MLT3
0
+1
-1
00
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Scramble
De-
Scramble
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
30 Datasheet
As shown in Figure 13 on page 29, the MAC starts each transmission with a preamble pattern. As
soon as the LXT972A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then enco des and transmits the rest of the pack et, includ ing th e
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT972A transmits the End-of Stream-Delimiter (ESD, symbols T and
R) and then returns to transmitting Idle sy mbols. 4B/5B coding is shown in Table 10 on page 33.
Figure 15 shows normal reception with no errors. When the LXT972A receives invalid symbols
from the line, it asserts RX_ER as shown in Figure 16.
Figure 15. 100BASE-TX Reception with no Errors
Figure 16. 100BASE-TX Reception with Invalid Symbol
RX_CLK
RX_DV
RXD<3:0>
RX_ER
preamble SFD SFD DA DA DA DA CRC CRC CRC CRC
RX_CLK
RX_DV
RXD<3:0>
RX_ER
preamble SFD SFD DA DA XX XX XX XX XX XX XX XX XX XX
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 31
3.7.2 Collision Indication
Figure 17 shows normal transmission. Upon detection of a collision, the COL outp ut is asserted
and remains asserted for the duration of the collision as shown in Figure 18.
3.7.3 100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT972A is a Physical Layer 1 (PHY)
device. The LXT972A implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 80 2.3 u stan dard . The fo llowing p aragrap hs discu ss LXT97 2A op eration fr om
the reference model point of view.
3.7.3.1 PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function.
For 100TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as lo ng
as TX_EN is de-asserted.
Figure 17. 100BASE-TX Transmission with no Errors
Figure 18. 100BASE-TX Transmission with Collision
DA DA DA DA DA DADA DA DA
TX_CLK
TX_EN
TXD<3:0>
CRS
COL
PR EAMB LE
JAM
TX_CLK
TX_EN
TXD<3:0>
CRS
COL
PR EA MB LE JAM JAM JAM
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
32 Datasheet
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-
Stream Delimiter (SSD), for the firs t two nibbles receiv ed across the MII. The PC S layer continues
to encode th e rem aini ng MII d at a, f ol lowi ng th e co ding in Table 10 on page 33, until TX_EN is de-
asserted. It then returns to suppl ying IDLE symbols to the line driver.
In the receive direction, the PCS layer performs the opposite function, substituting two preamble
nibbles for the SSD.
Dribble Bits
The LXT972A handles dribbles b its in all modes. If between one through four dribble bits are
received, the nibble is passed across the MII, padded with 1s if necessary. If between five through
seven dribble bits are received, the second nibble is not sent onto the MII bus.
Figure 19. Protocol Sublayers
Encoder/Decoder
Serializer/De-serializer
Link/Carrier Detect
PCS
Sublayer
PMA
Sublayer
MII Interface
LXT972A
100BASE-TX
Scrambler/
De-scrambler
PMD
Sublayer
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 33
Table 10. 4B/5B Coding
Code Type 4B Code
3 2 1 0 Name 5B Code
4 3 2 1 0 Interpretation
0 0 0 0 0 1 1 1 1 0 Data 0
0 0 0 1 1 0 1 0 0 1 Data 1
0 0 1 0 2 1 0 1 0 0 Data 2
0 0 1 1 3 1 0 1 0 1 Data 3
0 1 0 0 4 0 1 0 1 0 Data 4
0 1 0 1 5 0 1 0 1 1 Data 5
0 1 1 0 6 0 1 1 1 0 Data 6
DATA 0 1 1 1 7 0 1 1 1 1 Data 7
1 0 0 0 8 1 0 0 1 0 Data 8
1 0 0 1 9 1 0 0 1 1 Data 9
1 0 1 0 A 1 0 1 1 0 Data A
1 0 1 1 B 1 0 1 1 1 Data B
1 1 0 0 C 1 1 0 1 0 Data C
1 1 0 1 D 1 1 0 1 1 Data D
1 1 1 0 E 1 1 1 0 0 Data E
1 1 1 1 F 1 1 1 0 1 Data F
IDLE undefined I 1 1 1 1 11 Idle. Used as inter-stream fill code
0 1 0 1 J 2 1 1 0 0 0 Start-of-Stream Delimiter (SSD), part 1 of 2
CONTROL 0 1 0 1 K 2 1 0 0 0 1 Start-of-Stream Delimiter (SSD), part 2 of 2
undefined T 3 0 1 1 0 1 End-of-Stream Delimiter (ESD), part 1 of 2
undefined R 3 0 0 1 1 1 End-of-Stream Delimiter (ESD), part 2 of 2
undefined H 4 0 0 1 0 0 Transmit Error. Used to force signaling errors
undefined Invalid 0 0 0 0 0 Invalid
undefined Invalid 0 0 0 0 1 Invalid
undefined Invalid 0 0 0 1 0 Invalid
INVALID undefined Invalid 0 0 0 1 1 Invalid
undefined Invalid 0 0 1 0 1 Invalid
undefined Invalid 0 0 1 1 0 Invalid
undefined Invalid 0 1 0 0 0 Invalid
undefined Invalid 0 1 1 0 0 Invalid
undefined Invalid 1 0 0 0 0 Invalid
undefined Invalid 1 1 0 0 1 Invalid
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
34 Datasheet
3.7.3.2 PMA Sublayer
Link
In 100Mbps mode, the LXT972A establishes a link whenever the scrambler becomes locked and
remains locked for approx imately 50ms. Whenever the scrambler lose s lock (receiving less than 12
consecutive idle symbols during a 2ms window), the link are taken down. This provides a very
robust link, ess e ntial ly filter in g out any small noise hits that may otherwise disrupt the link.
Furthermore, 100M idle pa tter ns will not bring up a 10M link.
The LXT972A reports link failure via the MII statu s bits (1.2 and 17.1 0) and interru pt function s. If
auto-negotiation is enabled, link failure causes the LXT972A to re-negotiate.
Link Failure Overrid e
The LXT972A normally transmits data packets only if it detects the link is up. Setting bit 16.14 = 1
overrides this function, allowing the LXT972A to transmit d a ta packets even when the link is
down. This feature is provided as a diagnostic tool. Note that auto- negotiation must be disabled to
transmit data packets in the absence of link. If auto-negotiation is enabled, the LXT972A
automatically tr ans mits FLP bursts if the link is d own.
Carrier Sense
For 100TX links, a start-of-str eam delimiter (SSD) or /J/K symbol p air causes assertion of carrier
sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of CRS.
The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R; however, in this
case RX_ER is asserted for one clock cycle when CRS is de-asserted.
Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:
•De-assertion time for CRS is slightly long er than assertion time. This causes IFG in ter vals to
appear somewhat shorter to the MAC than it actually is on the wire.
•CRS de-assertion is not aligned with TX _EN d e -as sertion on transmit loopback s in half-
duplex mode.
Receive Data Valid
The LXT972A asserts RX_DV to indicate that the received data maps to valid symbols. However,
RXD outputs zeros until the received data is decoded and available for transfer to the controller.
3.7.3.3 Twisted-Pair PMD Sublayer
The twisted-pair Phys ical Medium Dependent (PMD) layer provides the sign al scr ambling and
descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as
receiving, polarity correction, and baseline wander correction functions.
Scrambler/Descrambler
The purpose of the s crambler is to spread the signal power spectrum and fur the r redu ce EMI using
an 11 -bit, data-independent polynomial. The receiver automatically decodes the polynomial
whenever IDLE symbols are received.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 35
Scrambler Seeding. Once the transmit data (or Idle symbols) are properly encoded, they are
scrambled t o furth e r r educe EMI and to spread the po wer spect ru m u sing an 11-bit scram bler s eed.
Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the
design.
Scrambler Bypass. The scrambler/descrambler can be bypassed by setting bit 16.12 = 1.
Scrambler bypass is provided for diagnostic and test support.
Baseline Wander Correction
The LXT972A provides a baseline wander correction function which makes the device robust
under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by
definition “unbalanced”. This means that the average value of the signal voltage can “wander”
significantly over short time inte rvals (tenths of s econds ). This wander can caus e receiver error s at
long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are
completely data dependent.
The LXT972A baseline wander correction characteristics allow the device to recover error-free
data while receiving worst-case “killer” packets over all cable lengths.
Polarity Correction
The 100BASE-TX descrambler automatically detects and corrects for the condition where the
receive signal at TPIP and TPIN is inverted.
Programmable Slew Rate Control
The LXT972A de vice s upports a slew r a te mechan ism whereb y o ne of fou r p re-selected s l ew rates
can be used. This allows the des ign er to o ptimize the ou tput wavef orm to match the ch aracteris tics
of the magnetics. The slew rate is determined by the TxSLEW pins as shown in T able 4 on page 14.
3.8 10Mbps Operation
The LXT972A operates as a standard 10BASE-T transceiver. The LXT972A supports all the
standard 10Mbps functions. During 10BASE-T (10T) operation, the LXT972A transmits and
receives Manchester-encoded data across the network link. When the MAC is not actively
transmitting data, th e LX T972A drives link pulses on to the line.
In 10T mode, th e polynomi al scr ambl er/de scrambler is inacti ve. Ma nchester-encoded signals
received from the network are decoded by the LXT972A and sent across the MII to the MAC.
3.8.1 10T Pr eamble Handling
The LXT972A offers two opti ons for preamble handling, sel ected by bit 16. 5. In 10T Mode whe n
16.5 = 0, the LXT972A strips the entire preamble off of received packets. CRS is asserted
coincident with SFD. RX_DV is held Low for the duration of the preamble. When RX_DV is
asserted, the very first two nibbles driven by the LXT972A are the SFD “5D” hex followed by the
body of the packet.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
36 Datasheet
In 10T mode with 16.5 = 1, the LXT972A passes the preamble through the MII and asserts
RX_DV and CRS simultaneously. In 10T loopback, the LXT972A loops back whatever the MAC
transmits to it, including the preamble.
3.8. 2 10T Carrier Sense
For 10T links, CRS ass ertion is based on reception of valid preamble, and de-as sertion on r eception
of an end-of-frame (EOF) marker. Bit 16.7 allows CRS de-asser tion to be synchronized with
RX_DV de-assertio n. Refer to Table 46 on page 64.
3.8.3 10T Dribble Bits
The LXT972A device handles dribbles bits in all modes. If between one through four dribble bits
are received, the nibble is passed across the MII, padded with 1s if necessary. If between five
through seven dribble bits are received, the second nibble is not sent onto the MII bus.
3.8.4 10T Link Integrity Test
In 10T mode, the LXT972A always transmits link pulses. When the Link Integrity Test function is
enabled (the normal configuration) , it monitors the connection for link pulses. Once link pulses are
detected, data transmission is enabled and remains enabled as long as either the link pulses or data
transmissio n continue. If the link pulses stop, th e data transmission is disabled.
If the Link Integrity Test function is disabled, the LXT972A transmits to the connection regardless
of detected link pulses. The Link Integrity Test f unctio n can be disabled by setting bit 16.14 = 1.
3.8.4.1 Link Failure
Link failure occurs if Link Integrity Test is enabled and link pu lses or pack ets stop being received .
If this condition occurs, the LXT972A returns to the auto-negotiatio n phase if auto -neg oti ation is
enabled. If the Link Integrity Test fu ncti on is disabled by setting 16.14 = 1 in the Configuration
Register, the LXT972A transmits packets, regardless of link status.
3.8.5 10T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972A. To
enable this function, set bit 16.9 = 1. When this function is enabled, the LXT972A asserts its C OL
output for 5-15 BT after each packet. See Figure 29 on page 51 for SQE timing parameters.
3.8.6 10T Jabber
If a transmission exceeds the jabber timer, the LXT972A disables the transmit and loopback
func tions. See Figure 28 on pa ge 51 for jabber timing parameters.
The LXT972A automatically exits jab ber m ode after the u njabb er time ha s ex pired . This fu nction
can be disabled by set ting bit 16 .10 = 1.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 37
3.8.7 10T Polarity Correction
The LXT972A automatically detects and corrects for the condition where the receive signal (TPIP/
N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-of-
frame (EOF) markers, are received consecutively. If link pulses or data are not received by the
maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted state.
3.9 Monitorin g Operations
3.9.1 Monitoring Auto-Negotiation
Auto-negotiatio n can be monito r e d as follo ws:
•Bit 17.7 is set to 1 once the Auto-Neg otiation process is completed.
•Bits 1.2 and 17.10 are set to 1 once the link is established.
•Bits 17.14 and 17.9 can be used to determin e the link operating cond itions (speed and duplex).
3.9.1.1 Monitoring Next Page Exchange
The LXT972A offers an Alternate Next Page mode to simplify the next page exchange process.
Normally, bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is
enabled (16.1 = 1), bit 6.1 is automatically cleared whenever a new negotiation process takes place.
This prevents the user from reading an old value in 6.1 and assuming that Registers 5 and 8
(Partner Ability) contain valid inform ation. Additionally, the LXT972A uses bit 6 .5 to indicate
when the current received page is the base page. This information is useful for recognizing when
next pages must be resent due to a new negotiation process starting. Bits 6.1 and 6.5 are cleared
when read.
3.9.2 LED Functions
The LXT972A incorporates three direct LED drivers. On power up all the drivers are asserted for
approximately 1 seco nd after reset d e-asserts. Each LED dr iver can be programme d using the LED
Configuration Register (refer to Table 50 on page 68) to indicate one the following conditions:
•Operating Speed
•Transmit Activity
•Receive Activity
•Collision Condition
•Link Status
•Duplex Mode
The LED drivers can also be programmed to display various combined status conditions. For
example, setting bits 20.15:12 = 1101 produces the following combination of Link and Activity
indications:
•If Link is down LED is off.
•If Link is up LED is on.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
38 Datasheet
•If Link is up and activity is detected, the LED blinks at the stretch inter val s elected by bits
20.3:2 and continues to blink as long as activity is present.
The LED driver pins also provide initial configur ation settings. The LED pins are sensitive to
polarity and automatically pulls up or pulls down to conf igure fo r either op en drain or open source
circuits (10 mA Max current rating) as required by the hardware configuration. Refer to the
discussi on of “Hardware Configuration Settings” on page 23 for details.
3.9.2.1 LED Pulse Stretching
The LED Configuration Register also prov ides optional LED pulse stretching to 30, 60, or 100 ms.
If during this pu lse stretch period the event o ccurs ag ain, th e pu lse st retch time is f urther exten ded.
When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer.
The LED driver remains asserted until the stretch timer expires. If another event occurs before the
stretch timer expires, the stre tch timer is reset and the stretch time is extended.
When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer.
When the stretch timer expires the ed ge detector is reset so that a long event causes another pulse to
be generated from the edge detector, which resets the stretch timer and causes the LED driver to
remain asserted. Figure 20 shows how the stretch op er ation functions.
3.10 Boundary Scan (JTAG1149.1) Functions
LXT972A includes a IEEE 1 149.1 boundary scan test port for board level testing. All digital input,
output, and input/output pins are accessible. The BSDL file is available by contacting your local
sales office (see the back page) or by accessing the Intel web site (developer.intel.com/design/
network/).
3.10.1 Boundary Scan Interface
This interface consists of f ive pins (TMS, TDI, TDO, TRST, and TCK). I t includes a state machine,
data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is
internally pulled down . TDO do es not h ave an internal pull-up or pull-down.
Figure 20. LED Pulse Stretching
Event
LED
Note: The direct drive LED outputs in this diagram are shown as active Low.
stretch stretch stretch
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 39
3.10.2 State Machine
The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset the
TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are
high for five TCK periods.
3.10.3 Instructi on Registe r
After the state machine resets, the IDCODE instruction is always invoked. The decode logic
ensures the correct data flow to the Data registers according to the current instruction. Valid
instructions are li sted in Table 12.
3.10.4 Boundary Scan Register (BSR)
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage. There are four modes of operation as listed in Table
11.
Table 11. BSR Mode of Operation
Mode Description
1 Capture
2Shift
3 Update
4 System F unct ion
Table 12. Supported JTAG Instructions
Name Code Description Mode Data Register
EXTEST 0000 Externa l Tes t Test BSR
IDCODE 0001 ID Code Inspection Normal ID REG
SAMPLE 0010 Sample Boundary Normal BSR
TRIBYP 0011 F orce Float Normal Bypass
SETBYP 0100 Control Boundary to 1/0 Tes t Bypass
BYPA SS 1111 Bypass Scan Normal Bypass
Table 13. Device ID Register
31:28 27:12 11:8 7:1 0
Version Part ID (hex) Jedec Continuation Characters JEDEC ID1Reserved
0001 03CB 1110 111 1110 1
1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC ID is FE (1111 1110) which becomes
111 1110
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
40 Datasheet
4.0 Application Information
4.1 Magnetics Information
The LXT972A requires a 1:1 ratio for both the receive and transmit transformers. The transformer
isolation voltage should be rate d at 2kV to protect th e circuitry from static voltages across the
connectors and cables. Refer to Table 14 for transformer requirements.
A cross-reference list of magnetic manufacturers and par t numbers is available in Application Note
073, Magnetic Manufacturers, which can be found on the Intel web site (developer.intel.com/
design/network/). Before committing to a specific component, designers should contact the
manufacturer for current product specifications, and validate the magnetics for the specific
application.
4.2 Typical Twisted-Pair Interface
Table 15 provides a comparison of the RJ-45 connections for NIC and switch applications in a
typical twisted-pair interface setting.
Figure 21 on page 41 shows a typical twisted-pair interface with the RJ-45 connections crossed
over for a swit ch configur atio n. Figure 22 on page 42 provides a typical twisted-pair interface with
the RJ-45 connections configured for a NIC application.
Table 14. Magnetics Requirements
Parameter Min Nom Max Units Test Condition
Rx turns ratio –1 : 1 ––
Tx turns ratio –1 : 1 ––
Insertion loss 0.0 0.6 1.1 dB
Primary inductance 350 ––
µH
Transformer isolat ion –1.5 –kV
Differential to common mo de rejection 40 ––dB .1 to 60 MHz
35 ––dB 60 to 100 MHz
Return Loss -16 ––dB 30 MHz
-10 ––dB 80 MHz
Table 15. RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces
Symbol RJ-45
Switch NIC
TPIP 1 3
TPIN 2 6
TPOP 3 1
TPON 6 2
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 41
Figure 21. Typical Twisted-Pair Interface - Switch
TPIP
TPIN
RJ-45
* = 0.001
µ
F / 2.0 kV
To Twisted-Pair Network
3
6
1
2
1:1
LXT972A
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
4
5
8
7
1:1
1
TPOP
TPON
VCCA
GND
0.1
µ
F.01
µ
F
2
270 pF 5%
270 pF 5%
0.01
µ
F
50
Ω 1%
50
Ω 1%
**
3
4
0.1
µ
F
1. Center tap current may be supplied from 3.3V VCCA as shown. Additional power savings may be realized by supplying
the center tap from a 2.5V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center tap
current.
2. The 100Ω transmit load termination resistor typically required is integrated in the LXT972A.
3. Magnetics without a receive pair center tap do not require a 2 kV termination.
4. RJ-45 connec tions show n are for a standard switch application. For a standard NIC RJ-45 setup, see Figure 22.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
42 Datasheet
Figure 22. Typical Twisted-Pair Interface - NIC
1. Center tap current may be supplied from 3.3V VCCA as shown. Additional power savings may be realized by supplying the
center tap from a 2.5V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center tap current.
2. The 100Ω transmit load termination resistor typically required is integrated in the LXT972A.
3. Magnetics without a receive pair center tap do not require a 2kV termination.
4. R J-45 connec tions shown are for a standard NIC. Tx/Rx crosso ver may be required for repeater & switch applications.
TPIP
TPIN
* = 0.001
µ
F / 2.0 kV
To Twisted-Pair Network
1:1
LXT972A
1:1
1
TPOP
TPON
VCCA
GND
0.1
µ
F.01
µ
F
2
270 pF 5%
270 pF 5%
0.01
µ
F
50
Ω 1%
50
Ω 1%
**
3
6
3
8
7
5
4
1
2
50
Ω
50
Ω
50
Ω
RJ-45
50
Ω
50
Ω
50
Ω
4
0.1
µ
F
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 43
Figure 23. Typical MII Interface
MAC
TX_EN
TX_ER
TXD<3:0>
TX_CLK
RX_DV
RX_ER
RXD<3:0>
CRS
COL
LXT972A X RJ-45
F
M
R
RX_CLK
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
44 Datasheet
5.0 Test Specifications
Note: Table 16 through Table 34 and Figure 24 th r ough Figure 35 represent the target specifications of
the LXT972A. These specifications are guaranteed by test except where noted “by design.”
Minimum and maximum values listed in Table 18 through Table 34 apply over the recommended
operating conditions specified in Table 17.
5.1 Electrical Parameters
Table 16. Absolute Maximum Ratings
Parameter Sym Min Max Units
Supply voltage VCC -0.3 4.0 V
Operating temperature TOPA 0+70 ºC
Storage temperature TST -65 +150 ºC
Caution: Exceeding these values may cause permanent damage.
Functional operation under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 17. Operating Conditions
Parameter Sym Min Typ1Max Units
Recommended operating temperature LXT972A_C
(Commercial) TOPA 0–70 ºC
Recommended supply voltage2Analog & Digital Vcca, Vccd 3.14 3.3 3.45 V
I/O Vccio 2.35 –3.45 V
VCC current
100BASE-TX ICC ––110 mA
10BASE-T ICC ––82 mA
Power Down ICC ––1mA
Auto-Negotiation ICC ––110 mA
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Voltages with respect to ground unless otherwise specified.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 45
Table 18. Digital I/O Characteristics 1
Parameter Symbol Min Typ2Max Units Test Conditions
Input Low voltage VIL ––0.8 V –
Input High voltage VIH 2.0 ––V–
Input current II-10 –10 µA0.0 < VI < VCC
Output Low voltage VOL ––0.4 V IOL = 4 mA
Output High voltage VOH 2.4 ––VIOH = -4 mA
1. Applies to all pins except MII, LED and XI/XO pins. Refer to Table 19 for MII I/O Charact erist ics, Table 20 for XI/XO and Table
21 for LED Characteristics.
2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 19. Digital I/O Characteristics - MII Pins
Parameter Symbol Min Typ1Max Uni t s Test Conditio ns
Input Low voltage VIL ––0.8 V –
Input High voltage VIH 2.0 –– V–
Input current II-10 –10 µA0.0 < VI < VCCIO
Output Low voltage VOL ––0.4 V IOL = 4 mA
Output High voltage VOH 2.2 –– VIOH = -4 mA, VCCIO = 3.3V
VOH 2.0 –– VIOH = -4 mA, VCCIO = 2.5V
Driver output resistance
(Line driver output enabled) RO2–100 –ΩVCCIO = 2.5V
RO2–100 –ΩVCCIO = 3.3V
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Para met er is guaranteed by design; not subject to production testing.
Table 20. I/O Characteristics - REFCLK/XI and XO Pins
Parameter Sym Min Typ1Max Units Test Conditions
Input Low Voltage VIL ––0.8 V
Input High Voltage VIH 2.0 ––V
Input Clock Frequency Tolerance2∆f–– ±100 ppm
Input Clock Duty Cycle2Tdc 35 –65 %
Input Capacitance CIN –3.0 –pF
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.
Table 21. I/O Characteristics - LED/CFG Pins
Parameter Sym Min Typ Max Units Test Co ndition s
Output Low V oltage Vol ––0.4 V IOL = 10 mA
Output High V oltage V oh 2.4 ––VI
OH = -10 mA
Input Current II-10 –10 µA0 < VI < V CCIO
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
46 Datasheet
Table 22. 100BASE-TX Transceiver Characteristics
Parameter Sym Min Typ1Max Units Test Conditions
Peak differential output voltage VP0.95 –1.05 V Note 2
Signal amplitude symmetry Vss 98 –102 % Note 2
Signal rise/fall time TRF 3.0 –5.0 ns Note 2
Rise/fall time symmetry TRFS ––0.5 ns Note 2
Duty cycle distortion DCD 35 50 65 % Of fset from 16ns pulse width at
50% of pulse peak
Overshoot/Undershoot VOS –– 5% –
Jitter (measured differentially) –––1.4 ns –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Measured at the line side of the transformer , line replaced by 100Ω(+/-1%) resist or.
Table 23. 10BASE-T Transceiver Characteristics
Parameter Sym Min Typ Max Un its Test Conditions
Transmitter
Peak differential output voltage V OP 2.2 2.5 2.8 V Wi th trans former, line
replaced by 100 Ω
resistor
Transition timing jitter added by the
MAU and PLS sections -0211ns
After line model
specified by IEEE 802.3
for 10BASE-T MAU
Receiver
Receive Input Impedance ZIN --22kΩ
Differential Squelch Threshold VDS 300 420 585 mV
Table 24. 10BASE-T Link Integrity Timing Characteristics
Parameter Sym Min Typ Max Units Test Conditions
Time Link Loss Receive TLL 50 –150 ms –
Link Pulse TLP 2–7 Link Pulses –
Link Min Receive Timer TLR MIN 2–7ms –
Link Max Receive Ti mer TLR MAX 50 –150 ms –
Link Transmit Period Tlt 8 –24 ms –
Link Pulse Width Tlpw 60 –150 ns –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 47
5.2 Timing Diagrams
Figure 24. 100BASE-TX Receive Timing - 4B Mode
Table 25. 100BASE-TX Receive Timing Parameters - 4B Mode
Parameter Sym Min Typ1Max Units2Test Conditions
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High t1 10 –– ns –
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High t2 10 –– ns –
CRS asserted to RXD<3:0>, RX_DV t3 3 –5BT –
Receive start of “J” to CRS asserted t4 12 –16 BT –
Receive start of “T” to CRS de-asserted t5 10 –17 BT –
Receive start of “J” to COL asserted t6 16 –22 BT –
Receive start of “T” to COL de-asserted t7 17 –20 BT –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10-
8 s or 10 ns.
t4 t5
t3
t6 t7
0ns 250ns
CRS
RX_DV
RXD<3:0>
RX_CLK
COL
t1t2
TPI
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
48 Datasheet
Figure 25. 100BASE-TX Transmit Timing - 4B Mode
Table 26. 100BASE-TX Transmit Timing Parameters - 4B Mode
Parameter Sym Min Typ1Max Units2Test Conditions
TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High t1 12 –– ns –
TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High t2 0 –– ns –
TX_EN sampled to CRS asserted t3 20 –24 BT –
TX_EN sampled to CRS de-asserted t4 24 –28 BT –
TX_EN sampled to TPO out (Tx latency) t5 5.3 –5.7 BT –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10-
8 s or 10 ns.
t1
t2
t5
t3 t4
0ns 250ns
TXCLK
TX_EN
TXD<3:0>
TPO
CRS
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 49
Figure 26. 10BASE-T Receive Timing
Table 27. 10BASE-T Receive Timing Parameters
Parameter Sym Min Typ1Max Units2Test Conditions
RXD, RX_DV, RX_ER Setup to RX_CLK High t1 10 –– ns –
RXD, RX_DV, RX_ER Hold from RX_CLK High t2 10 –– ns –
TPIP /N in to R XD o u t ( R x l a te n cy) t3 5 .8 –6.0 BT –
CRS asserted to RXD, RX_DV, RX_ER
asserted t4 5 –32 BT –
RXD, RX_DV, RX_ER de-asserted to CRS de-
asserted t5 0.3 –0.5 BT –
TPI in to CRS asserted t6 2 –28 BT –
TPI quiet to CRS de-asserted t7 6 –10 BT –
TPI in to COL asserted t8 1 –31 BT –
TPI quiet to COL de-asserted t9 5 –10 BT –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10-
7 s or 100 ns.
RX_CLK
RXD,
RX_DV,
RX_ER
CRS
TPI
t
3
t
4
t
2
t
6
t
1
t
7
t
5
COL t
8
t
9
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
50 Datasheet
Figure 27. 10BASE-T Transmit Timing
Table 28. 10BASE-T Transmit Timing Parameters
Parameter Sym Min Typ1Max Units2Test Conditions
TXD, TX_EN, TX_ER setup to TX_CLK High t1 10 –– ns –
TXD, TX_EN, TX_ER hold from TX_CLK High t2 0 –– ns –
TX_EN sampled to CRS asserted t3 –2–BT –
TX_EN sampled to CRS de-asserted t4 –1–BT –
TX_EN sampled to TPO out (Tx latency) t5 –72.5 –BT –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. B T is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10-
7 s or 100 ns.
TX_CLK
TXD,
TX_EN,
TX_ER
CRS
TPO
t
1
t
3
t
4
t
5
t
2
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 51
Figure 28. 10BASE-T Jabber and Unjabber Timing
Table 29. 10BASE-T Jabber and Unjabber Timing Parameters
Parameter Sym Min Typ1Max Units Test Conditions
Maximum transmit time t1 20 –150 ms –
Unjab time t2 250 –750 ms –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Figure 29. 10BASE-T SQE (Heartbeat) Timing
Table 30. 10BASE-T SQE Timing Parameters
Parameter Sym Min Typ1Max Units Test Conditions
COL (SQE) Delay after TX_EN off t1 0.65 –1.6 us –
COL (SQE) Pulse duration t2 0.5 –1.5 us –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
TXD
COL
t
1
t
2
TX_EN
TX_CLK
TX_EN
t
1
t
2
COL
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
52 Datasheet
Figure 30. Auto Negotiation and Fast Link Pulse Timing
Figure 31. Fast Link Pulse Timing
Table 31. Auto Negotiation and Fast Link Pulse T iming Parameters
Parameter Sym Min Typ1Max Units Test Conditions
Clock/Data pulse width t1 –100 –ns –
Clock pulse to Data pulse t2 55.5 –63.8 µs–
Clock pulse to Clock pulse t3 123 –127 µs–
FLP burst width t4 –2–ms –
FLP burst to FLP burst t5 8 12 24 ms –
Clock/Data pulses per burst –17 –33 ea –
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
TPO
t1 t1
t2 t3
Clock Pulse Data Pulse Clock Pulse
TPO
t4 t5
FLP Burst FLP Burst
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 53
Figure 32. MDIO Input Timing
Figure 33. MDIO Output Timing
Table 32. MDIO Timing Parameters
Parameter Sym Min Typ1Max Units Test Condi t ions
MDIO setup before MDC, sourced
by STA t1 10 ––ns –
MDIO hold after MDC, sourced by
STA t2 5 ––ns –
MDC to MDIO output delay, source
by PHY t3 ––150 ns –
MDC period t4 125 ––ns MDC = 8 MHz
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
t1
MDC
MDIO
t2
t3
MDC
MDIO
t4
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
54 Datasheet
Figure 34. Power-Up Timing
Table 33. Power-Up Timing Parameters
Parameter Sym Min Typ1Max Units Test Conditions
Voltage threshold v1 –2.9 –V–
Power Up delay2t1 ––300 µs–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. P ower Up Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY com es
out of reset after a delay of No MORE Than 300 µs. System designers should consider this as a minimum value - After
threshold v1 is reached, the MAC should delay No LESS Than 300 µs before accessing the MDIO port.
Figure 35. RESET Pulse Width and Recovery Timing
Table 34. RESET Pulse Width and Recovery Timing Parameters
Parameter Sym Min Typ1Max Units Test Conditions
RESET pulse width t1 10 ––ns –
RESET recovery delay2t2 ––300 µs–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY
comes out of reset after a delay of No MORE Than 300 µs. System designers should consider this as a minimum value -
After de-asserting RESET*, the MAC should delay No LESS Than 300 µs before accessing the MDIO port.
t1
VCC
M
DIO,etc
v1
t2
RESET
MDIO,etc
t1
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 55
6.0 Register Definitions
The LXT972A register set includes multiple 16-bit registers. Refer to Table 35 for a complete
register l isting.
•Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublay er and
Media Independent Interface” and “Physical Layer Link Signaling for 10/1 00Mb ps Auto-
Negotiation” sections of the IEEE 802.3 standard.
•Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique
chip functions.
Table 35. Register Set
Address Register Name Bit Assignments
0 Control Register Refer to Table 37 on page 58
1 Status Register #1 Refer to Table 38 on page 58
2 PHY Identification Register 1 Refer to Table 39 on page 59
3 PHY Identification Register 2 Refer to Table 40 on page 60
4 Auto-Negot iation Advertisement Register Refer to Table 41 on page 61
5 Auto-Negotiation Link Partner Base Page Ability Register Refer to Table 42 on page 62
6 Auto-Negot iation Expansion Register Refer to Table 43 on page 63
7 Auto-Negotiation Next Page Transmit Register Refer to Table 44 on page 63
8 Auto-Negotiation Link Partner Received Next Page Register Refer to Table 45 on page 64
9 1000BA SE -T/100BAS E-T 2 Control Register Not Implemented
10 1000BASE -T/100BAS E-T 2 St atus Register Not Implemented
15 Extended Status Register Not Implemented
16 Port Configuration Register Refer to Table 46 on page 64
17 Status Register #2 Refer to Table 47 on page 65
18 Interrupt Enable Register Refer to Table 48 on page 66
19 Interrupt Status Register Refer to Table 49 on page 66
20 LED Configuration Register Refer to Table 50 on page 68
21- 29 Reserved
30 Transmit Control Register Refer to Table 51 on page 69
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
56 Datasheet
Table 36. Register Bit Map
Reg Title Bit Fields Addr
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Control Register
Control Reset Loopback Speed
Select A/N
Enable Power
Down Isolate Re-start
A/N Duplex
Mode COL Test Speed
Select Reserved 0
Status Register
Status 100Base-
T4 100Base-
X Full
Duplex
100Base-
X Half
Duplex
10Mbps
Full
Duplex
10Mbps
Half
Duplex
100Base-
T2 Full
Duplex
100Base-
T2 Half
Duplex Extended
Status Reserved MF
Preamble
Suppress A/N
Complete Remote
Fault A/N Ability Link
Status Jabber
Detect Extended
Capability 1
PHY ID Registers
PHY ID 1 15141312111098765432102
PHY ID2 PHY ID No MFR Model No MFR Rev No 3
Auto-Negotiation Advertisement Register
A/N
Advertise Next
Page Reserved Remote
Fault Reserved Asymm
Pause Pause 100Base-
T4 100Base-
TX Full
Duplex 100Base-
TX 10Base-T
Full
Duplex 10Base-T IEEE Selector Field 4
Auto-Negotiation Link Partner Base Page Ability Register
A/N Link
Ability Next
Page Ack Remote
Fault Reserved Asymm
Pause Pause 100Base-
T4 100Base-
TX Full
Duplex 100Base-
TX 10Base-T
Full
Duplex 10Base-T IEEE Selector Field 5
Auto-Negotiation E x pansion Register
A/N
Expansion Reserved Base
Page Parallel
Detect
Fault
Link
Partner
Next
Page Able
Next
Page Able Page
Received Link
Partner
A/N Able 6
Auto-Negotiation Next Page Transmit Register
A/N Next
Page Txmit Next
Page Reserved Message
Page Ack 2 Toggle Message / Unformatted Code Field 7
Auto-Negotiation Link Partner Next Page Receive Register
A/N Link Next
Page Next
Page Ack Message
Page Ack 2 Toggle Message / Unformatted Code Field 8
Configuration Reg ister
Port Config Reserved Force
Link Pass Txmit
Disable Bypass
Scrambler
(100TX) Reserved
)Jabber
(10T) SQE
(10T) TP
Loopback
(10T)
CRS
Select
(10T) Reserved PRE_EN Reserved Reserved Alternate
Next
Page Reserved 16
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 57
Status Register #2
Status
Register #2 Reserved 10/100
Mode Transmit
Status Receive
Status Collision
Status Link Duplex
Mode Auto-Neg Auto-Neg
Complete Reserved Polarity Pause Error Reserved Reserved 17
Interrupt Enable Register
Interrupt
Enable Reserved Reserved Auto-Neg
Mask Speed
Mask Duplex
Mask Link Mask Reserved Reserved Interrupt
Enable Test
Interrupt 18
Interrupt Status Register
Interrupt
Status Reserved Reserved Auto-Neg
Done Speed
Change Duplex
Change Link
Change Reserved MD
Interrupt Reserved Reserved 19
LED Configuration Register
LED Config LED1 LED2 LED3 LED Freq Pulse
Stretch Reserved 20
Transmit Control Register
Trans.
Control Reserved Transmit
Low Pwr Port Rise Time
Control Reserved 30
Table 36. Register Bit Map (Continued)
Reg Title Bit Fields Addr
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
58 Datasheet
Table 37. Control Register (Address 0)
Bit Name Description Type 1Default
0.15 Reset 1 = PHY reset
0 = Normal operation R/W
SC 0
0.14 Loopback 1 = Enable loopback mode
0 = Disable loopback mode R/W 0
0.13 Speed Selection
0.6 0.13 Speed Selected
R/W Note 2
1
1
0
0
1
0
1
0
Reserved
1000Mbps (not supported)
100Mbps
10Mbps
0.12 Auto-Negotiation
Enable 1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process R/W Note 2
0.11 Power-Down 1 = Power-down
0 = Normal operation R/W 0
0.10 Isolate 1 = Electrically isolate PHY from MII
0 = Normal operation R/W 0
0.9 Restart
Auto-Negotiation 1 = Restart Auto-Negotiation Process
0 = Normal operation R/W
SC 0
0.8 Duplex Mode 1 = Full Duplex
0 = Half Duplex R/W Note 2
0.7 Collision Test 1 = Enable COL signal test
0 = Disable COL signal test R/W 0
0.6 Speed Selection
0.6 0.13 Speed Selected
R/W 0
1
1
0
0
1
0
1
0
Reserved
1000Mbps (not supported)
100Mbps
10Mbps
0.5:0 Reserved Write as 0, ignore on Read R/W 00000
1. R/W = Read/Write
RO = Read Only
SC = Self Clearing
2. Default value of bits 0.12, 0.13 and 0.8 are determined by the LED/CFG pins (refer to Table 8 on page 24).
Table 38. MII Status Register #1 (Address 1)
Bit Name Description Type 1Default
1.15 100BASE-T4
Not Supported 1 = PHY able to perform 100BASE-T4
0 = PHY not able to perfor m 100BA SE- T4 RO 0
1.14 100BASE-X Fu ll-
Duplex 1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform full-duplex 100BA SE-X RO 1
1.13 100BASE-X Half-
Duplex 1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to perfor m half-duplex 100BASE -X RO 1
1. RO = Read Only
LL = Latching Low
LH = Latching High
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 59
1.12 10Mbps Full-D uplex 1 = PHY able to operate at 10Mbps in full-duplex mode
0 = PHY not able to operate at 10Mbps full-duplex mode RO 1
1.11 10Mbps Half-Duplex 1 = PHY able to operate at 10Mbps in half-duplex mode
0 = PHY not able to operate at 10Mbps in half-duplex RO 1
1.10 100BASE-T2 Full-
Duplex
Not Supported
1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform full-duplex 100BASE-T2 RO 0
1.9 100BASE-T2 Half-
Duplex
Not Supported
1 = PHY able to perform half duplex 100BASE-T2
0 = PHY not able to perform half-duplex 100BASE-T2 RO 0
1.8 Extended Status 1 = Extended status information in register 15
0 = No extended status information in register 15 RO 0
1.7 Reserved 1 = ignore when read RO 0
1.6 MF Preamble
Suppression
1 = PHY accepts management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed RO 0
1.5 Auto-Negotiation
Complete 1 = Auto-negotiation complete
0 = Auto-negotiation not complete RO 0
1.4 Remote Fault 1 = Remote fault condition detected
0 = No remote fault condition detected RO/LH 0
1.3 Auto-Negotiation
Ability 1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto-Negotiation RO 1
1.2 Link Status 1 = Link is up
0 = Link is down RO/LL 0
1.1 Jabber Detect 1 = Jabber condition detected
0 = Jabber condition not detected RO/LH 0
1.0 Extended Capability 1 = Extended register capabilities
0 = Basic register capabilities RO 1
Table 39. PHY Identification Register 1 (Address 2)
Bit Name Description Type 1Default
2.15:0 PHY ID
Number The PHY identifier composed of bits 3 through 18 of the OUI. RO 0013 hex
1. RO = Read Only
Table 38. MII Status Register #1 (Address 1)
Bit Name Description Type 1Default
1. RO = Read Only
LL = Latching Low
LH = Latching High
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
60 Datasheet
Table 40. PHY Identification Register 2 (Address 3)
Bit Name Description Type 1Default
3.15:10 PHY ID number The PHY identifier composed of bits 19 through 24 of the
OUI. RO 011110
3.9:4 Manufacturer’s
model number 6 bits containing manufacturer’s part number. RO 001110
3.3:0 Manufacturer’s
revision number 4 bits containing manufacturer ’s revision number . RO xxxx
(See LXT971A/972A
Specification Update)
1. RO = Read Only
Figure 36. PHY Identifier Bit Mapping
0 0000000 00 0001001101111000111000
abc rs x
15015 10 9 4 3 0
00
The Intel OUI is 00207B hex
PHY ID Regi ster #1 (address 2) = 0013 PHY ID Register #2 (Address 3)
Manufacturer’s
Model Num be r Revision
Number
Organizationally Unique Identifier
00 20 7B 5030
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 61
Table 41. Auto Negotiation Advertisement Register (Address 4)
Bit Name Description Type 1Default
4.15 Next Page 1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages. R/W 0
4.14 Reserved Ignore. RO 0
4.13 Remote Fault 1 = Remote fault.
0 = No remote fault. R/W 0
4.12 Reserved Ignore. R/W 0
4.11 Asymmetric
Pause Pause operation defined in Clause 40 and 27. R/W 0
4.10 Pause 1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled. R/W Note 2
4.9 100BASE-T4
1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT972A does not support 100BASE-T4 but allows this bit t o be set to
advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An
external 100BASE-T4 transceiver could be switched in if this capability is
desired.)
R/W 0
4.8 100BASE-TX
full-duplex 1 = Port is 100BAS E-TX fu ll-duplex capable.
0 = Port is not 100BASE-TX full-duplex capable. R/W Note 3
4.7 100BASE-TX 1 = Port is 100BASE-T X capable.
0 = Port is not 100BASE-TX capable. R/W Note 3
4.6 10BASE-T
full-duplex 1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BAS E-T full-duplex capable. R/W Note 3
4.5 10BASE-T 1 = Port is 10BASE-T capable.
0 = Port is not 10BASE-T capable. R/W Note 3
4.4:0 Selector Field,
S<4:0>
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation development.
<11111> = Reserved for future Auto-Negot iation development.
Unspecified or reserved combinations should not be transmitted.
R/W 00001
1. R/W = Read/Write
RO = Read Only
2. Default value of bit 4.10 is determined by pin 33/H8.
3. Default values of bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFGn pins at reset. Refer to Table 8 for details.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
62 Datasheet
Table 42. Auto Negotiation Link Partner Base Page Ability Register (Address 5)
Bit Name Description Type 1 Default
5.15 Next Page 1 = Link Partner has ability to send multiple pages.
0 = Link Partner has no ability to send multiple pages. RO N/A
5.14 Acknowledge 1 = Link Partner has received Link Code Word from LXT972A.
0 = Link Partner has not received Link Code Word from the
LXT972A. RO N/A
5.13 Remote Fault 1 = Remote fault.
0 = No remote fault. RO N/A
5.12 Reserved Ignore. RO N/A
5.11 Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
1 = Link Partner is Pause capable.
0 = Link Partner is not Pause capable. RO N/A
5.10 Pause 1 = Link Partner is Pause capable.
0 = Link Partner is not Pause capable. RO N/A
5.9 100BASE-T4 1 = Link Partner is 100BASE-T4 capable.
0 = Link Partner is not 100BASE-T4 capable. RO N/A
5.8 100BASE-TX
full-duplex 1 = Link Partner is 100BASE-TX full-duplex capable.
0 = Link Partner is not 100BASE-TX full-duplex capable. RO N/A
5.7 100BASE-TX 1 = Link Partner is 100BASE-TX capable.
0 = Link Partner is not 100BASE-TX capable. RO N/A
5.6 10BASE-T
full-duplex 1 = Link Partner is 10BASE-T full-duplex capable.
0 = Link Partner is not 10BASE-T full-duplex capable. RO N/A
5.5 10BASE-T 1 = Link Partner is 10BASE- T capable.
0 = Link Partner is not 10BASE-T capable. RO N/A
5.4:0 Selector Field
S<4:0>
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation development.
<11111> = Reserved for future Auto-Negotiation development.
Unspecified or reserved combinations shall not be transmitted.
RO N/A
1. RO = Read Only
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 63
Table 43. Auto Negotiation Expansion (Address 6)
Bit Name Description Type 1Default
6.15:6 Reserved Ignore on read. RO 0
6.5 Base Page
This bit indicates the status of the Auto-Negotiation variable, base page. It
flags synchronization with the Auto-Negotiation state diagram allowing
detection of interrupted links. This bit is only used if bit 16.1 (Alternate NP
feature) is set.
1 = basepage = true
0 = basepage = false
RO/
LH 0
6.4 Parallel
Detection Fault 1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred. RO/
LH 0
6.3 Link Partner
Next Page Able 1 = Link partner is next page able.
0 = Link partner is not next page able. RO 0
6.2 Next Page Able 1 = Local device is next page able.
0 = Local device is not next page able. RO 1
6.1 Page Received
1 = Indicates that a new page has been received and the received code
word has been loaded into register 5 (base pages) or register 8 (next
pages) as specified in clause 28 of 802.3. This bit is cleared on read. If bit
16.1 is set, the Page Received bit is also cleared when mr_page_rx = false
or transmit_disable = true.
RO
LH 0
6.0 Link Partner A/
N Able 1 = Link partner is auto-negotiation able.
0 = Link partner is not auto-negotiation able. RO 0
1. RO = Read Only LH = Latching High
Table 44. Auto Negotiation Next Page Transmit Register (Address 7)
Bit Name Description Type 1Default
7.15 Next Page
(NP) 1 = Additional next pages follow
0 = Last page R/W 0
7.14 Reserved Write as 0, ignore on read RO 0
7.13 Message Page
(MP) 1 = Message page
0 = Unformatted page R/W 1
7.12 Acknowledge 2
(ACK2) 1 = Complies with message
0 = Can not comply with message R/W 0
7.11 Toggle
(T)
1 = Previous value of the transmitted Link Code Word equalled logic
zero
0 = Previous value of the transmitted Link Code Word equalled logic
one
R/W 0
7.10:0 Message/
Unformatted Code
Field R/W 00000000
001
1. RO = Read Only. R/W = Read/Write
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
64 Datasheet
Table 45. Auto Negotiation Link Partner Next Page Receive Register (Address 8)
Bit Name D escripti on Type 1Default
8.15 Next Page
(NP) 1 = Link Partner has additional next pages to send
0 = Link Partner has no additional next pages to send RO 0
8.14 Acknowledge
(ACK) 1 = Link Partner has received Link Code Word from LXT972A
0 = Link Partner has not received Link Code Word from LXT972A RO 0
8.13 Message Page
(MP) 1 = Page sent by the Link Partner is a Message Page
0 = Page sent by the Link Partner is an Unformatted Page RO 0
8.12 Acknowledge 2
(ACK2) 1 = Link Partner complies with the message
0 = Link Partner can not comply with the message RO 0
8.11 Toggle
(T)
1 = Previous value of the transmitted Link Code Word equalled logic
zero
0 = Previous value of the transmitted Link Code Word equalled logic
one
RO 0
8.10:0 Message/
Unformatted Code
Field User definable RO 0
1. RO = Read Only.
Table 46. Configuration Register (Address 16, Hex 10)
Bit Name Description Type 1Default
16.15 Reserved Write as zero, ignore on read. R/W 0
16.14 Force Link Pass 1 = Force Link pass
0 = Normal operation R/W 0
16.13 Transmit Disable 1 = Disable Twiste d Pair transmitter
0 = Normal Operation R/W 0
16.12 Bypass Scr a mbler
(100BASE-TX) 1 = Bypass Scrambler and Descrambler
0 = Normal Operation R/W 0
16.11 Reserved Ignore R/W 0
16.10 Jabber
(10BASE-T) 1 = Disable Jabber Correction
0 = Normal operation R/W 0
16.9 SQE
(10BASE-T) 1 = Enable Heart Beat
0 = Disable Heart Beat R/W 0
16.8 TP Loopback
(10BASE-T) 1 = Disable TP loopback during half-duplex operation
0 = Normal Operation R/W 0
16.7 CRS Sel ect
(10BASE-T) 1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation R/W 1
16.6 Reserved Write as zero, ignore on read. R/W 0
16.5 PRE_EN Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when CRS is asserted. R/W 0
16.4:3 Reserved Write as zero, ignore on read. R/W 00
1. R/W = Read /Write, LHR = Latches High on Reset
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 65
16.2 Reserved Write as zero, ignore on read. R/W 0
16.1 Alternate NP
feature 1 = Enable alternate auto negotiate next page feature.
0 = Disable alternate auto negotiate next page feature R/W 0
16.0 Reserved Write as zero, ignore on read. R/W 0
Table 47. Status Register #2 (Address 17)
Bit Name Description Type 1Default
17.15 Reserved Always 0. RO 0
17.14 10/100 Mode 1 = LXT972A is operating in 100BASE-TX mode.
0 = LXT972A is not operating 100BASE-TX mode. RO 0
17.13 Transmit Status 1 = LXT972A is transmitting a packet.
0 = LXT972A is not transmitting a packet. RO 0
17.12 Receive Status 1 = LXT972A is receiving a packet.
0 = LXT972A is not receiving a packet. RO 0
17.11 Collision Status 1 = Collision is occurring.
0 = No collision. RO 0
17.10 Link 1 = Link is up.
0 = Link is down. RO 0
17.9 Duplex Mode 1 = Full-duplex.
0 = Half-duplex. RO 0
17.8 Auto-Negotiation 1 = LXT972A is in Auto-Negotiation Mode.
0 = LXT972A is in manual mode. RO 0
17.7 Auto-Negotiation
Complete
1 = Auto-negotiation process completed.
0 = Auto-negotiation process not completed.
This bit is only valid when auto negotiate is enabled, and i s equi valent
to bit 1.5.
RO 0
17.6 Reserved Reserved. RO 0
17.5 Polarity 1 = Polarity is reversed.
0 = Polarity is not reversed. RO 0
17.4 Pause 1 = Device Pause capable.
0 = Device Not Pause capable. RO 0
17:3 Error 1 = Error Occurred (Remote Fault, X,Y,Z).
0 = No error occurred. RO 0
17:2 Reserved Always 0. RO 0
17:1 Reserved Always 0. RO 0
17.0 Reserved Always 0. RO 0
1. RO = Read Only. R/W = Read/Write
Table 46. Configuration Register (Address 16, Hex 10) (Continued)
Bit Name Description Type 1Default
1. R/W = Read /Write, LHR = Latches High on Reset
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
66 Datasheet
Table 48. Interrupt Enable Register (Address 18)
Bit Name Description Type 1 Default
18.15:9 Reserved Write as 0; ignore on read. R/W N/A
18.8 Reserved Write as 0; ignore on read. R/W 0
18.7 ANMSK Mask for Auto Negotiate Complete
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt. R/W 0
18.6 SPEEDMSK Mask for Speed Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt. R/W 0
18.5 DUPLEXMSK Mask for Duplex Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt. R/W 0
18.4 LINKMSK Mask for Link Status Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt. R/W 0
18.3 Reserved Write as 0, ignore on read. R/W 0
18.2 Reserved Write as 0, ignore on read. R/W 0
18.1 INTEN 1 = Enable interrupts.
0 = Disable interrupts. R/W 0
18.0 TINT 1 = Force interrupt on MDINT.
0 = Normal operation. R/W 0
1. R/W = Read /Write
Table 49. Interrupt Status Register (Address 19, Hex 13)
Bit Name Description Type 1 Default
19.15:9 Reserved Ignore RO N/A
19.8 Reserved Ignore RO 0
19.7 ANDONE Auto Negotiation Status
1 = Auto Negotiation has completed.
0 = Auto Negotiation has not completed. RO/SC N/A
19.6 SPEEDCHG Speed Change Status
1 = A Speed Change has occurred since last reading this register.
0 = A Speed Change has not occurred since last reading this register. RO/SC 0
19.5 DUPLEXCHG Duplex Change Status
1 = A Duplex Change has occurred since last reading this register .
0 = A Duplex Change has not occurred since last reading this register. RO/SC 0
19.4 LINKCHG Link Status Change Status
1 = A Link Change has occurred since last reading this register .
0 = A Link Change has not occurred since last reading this register. RO/SC 0
19.3 Reserved Ignore RO 0
1. R/W = Read/Write, SC = Self Clearing.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 67
19.2 MDINT 1 = MII interrupt pending.
0 = No MII interrupt pending. RO
19.1 Reserved Ignore. RO N/A
19.0 Reserved Ignore RO 0
Table 49. Interrupt Status Register (Address 19, Hex 13) (Continued)
Bit Name Description Type 1 Default
1. R/W = Read/Write, SC = Self Clearing.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
68 Datasheet
Table 50. LED Configuration Register (Address 20, Hex 14)
Bit Name Description Type 1Default
20.15:12 LED1
Programming
bits
0000 = Display Speed Status (Continuous, Default)
0001 = Display Transmit Status (Stretched)
0010 = Display Receive Status (Stretched)
0011 = Display Collision Status (Stretched)
0100 = Display Link Status (Continuous)
0101 = Display Duplex Status (Continuous)
0110 = Unused
0111 = Display Receive or Trans mit Activity (Stretched)
1000 = Test mode- turn LED on (Continuous)
1001 = Test mode- turn LED off (Continuous)
1010 = Test mode- blink LED fast (Continuous)
1011 = Test mode- blink LED slow (Continuous)
1100 = Display Link and Receive Status combined 2 (Stretched)3
1101 = Display Link and Activity Status combined 2 (Stretched)3
1110 = Display Duplex and Collision Status combined 4 (Stretched)3
1111 = Unused
R/W 0000
20.11:8 LED2
Programming
bits
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status
0011 = Display Collision Status
0100 = Display Link Status (Default)
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Trans mit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2 (Stretched)3
1101 = Display Link and Activity Status combined 2 (Stretched)3
1110 = Display Duplex and Collision Status combined 4 (Stretched)3
1111 = Unused
R/W 0100
20.7:4 LED3
Programming
bits
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status (Default)
0011 = Display Collision Status
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Trans mit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2 (Stretched)3
1101 = Display Link and Activity Status combined 2 (Stretched)3
1110 = Display Duplex and Collision Status combined 4 (Stretched)3
1111 = Unused
R/W 0010
1. R/W = Read /Write
RO = Read Only
LH = Latching High
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
3. Com bined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of
the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
5. Values are relative approximations. Not guaranteed or production tested.
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Datasheet 69
20.3:2 LEDFREQ500 = Stretch LED events to 30 ms.
01 = Stretch LED events to 60 ms.
10 = Stretch LED events to 100 ms.
11 = Reserved.
R/W 00
20.1 PULSE-
STRETCH 0 = Disable pulse stretching of all LEDs.
1 = Enable pulse stretching of all LEDs. R/W 1
20.0 Reserved Ignore. R/W N/A
Table 51. Transmit Control Register #2 (Address 30)
Bit Name Description Type2Default
30.15:11 Reserved Ignore R/W 0
30.12 Transmit Low Power 1 = Forces the transmitter into low power mode. Also
forces a zero-differential transmission.
0 = Normal transmission. R/W 0
30.11:10 Port Rise Time Control100 = 2.7 ns (default is pins TXSLEW<1:0>)
01 = 3.5 ns
10 = 2.3 ns
11 = 2.0 ns
R/W N/A
30.9:0 Reserved Ignore R/W 0
1. Values are relative approximations. Not guaranteed or production tested.
2. R/W = Read/Write
Table 50. LED Configuration Register (Address 20, Hex 14) (Continued )
Bit Name Description Type 1Default
1. R/W = Read /Write
RO = Read Only
LH = Latching High
2. Link status is the primary LED driver . The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of
the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
5. Values are relative approximations. Not guaranteed or production tested.
LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
70 Datasheet
7.0 Package Specification
Figure 37. LXT972A LQFP Package Specifications
D
D
1
A
1
A
2
L
A
B
L
1
θ
3
θ
3
θ
E
E
1
e
/
2
e
64-Pin Low Profil e Quad Flat Pack
• Part Number - LXT972ALC Commercial Temperature Range (0ºC to +70ºC)
Dim Millimeters
Min Max
A–1.60
A10.05 0.15
A21.35 1.45
B0.170.27
D 11.85 12.15
D19.9 10.1
E 11.85 12.15
E1 9.9 10.1
e 0.50 BSC1
L0.450.75
L11.00 REF
θ311o13o
θ0o7o
1. B asic Spac ing between Centers
