General Description
The MAX4721/MAX4722/MAX4723 low-voltage, low on-
resistance (RON), dual single-pole/single throw (SPST)
analog switches operate from a single +1.8V to +5.5V
supply. These devices are designed for USB 1.1 and
audio switching applications.
The MAX4721/MAX4722/MAX4723 feature 4.5ΩRON
(max) with 1.2Ωflatness and 0.3Ωmatching between
channels. These new switches feature guaranteed
operation from +1.8V to +5.5V and are fully specified at
3V and 5V. These switches offer break-before-make
switching (1ns) with tON <80ns and tOFF <40ns at
+2.7V. The digital logic inputs are +1.8V logic compati-
ble with a +2.7V to +3.6V supply.
These switches are packaged in a chip-scale package
(UCSP™), significantly reducing the required PC board
area. The chip occupies only a 1.52mm ✕1.52mm area
and has a 3 ✕3 bump array with a bump pitch of
0.5mm. These switches are also available in an 8-pin
µMAX package.
Applications
Battery-Operated Equipment
Audio/Video-Signal Routing
Low-Voltage Data-Acquisition Systems
Sample-and-Hold Circuits
Communications Circuits
Features
♦USB 1.1 Signal Switching
♦<2ns Differential Skew
♦-3dB Bandwidth: >300MHz
♦Low 15pF On-Channel Capacitance
♦Low RON (max) Switches
4.5Ω(max) (+3V Supply)
3Ω(max) (+5V Supply)
♦0.3Ω(max) RON Match (+3V Supply)
♦1.2Ω(max) RON Flatness (+3V Supply)
♦<0.5nA Leakage Current at TA= +25°C
♦High Off-Isolation: -55dB (10MHz)
♦Low Crosstalk: -80dB (10MHz)
♦Low Distortion: 0.03%
♦+1.8V CMOS-Logic Compatible
♦Single-Supply Operation from +1.8V to +5.5V
♦Rail-to-Rail®Signal Handling
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2632; Rev 0; 10/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN/BUMP-
PACKAGE
TOP
MARK
MAX4721EUA -40°C to +85°C 8 µMAX —
MAX4721EBL-T* -40°C to +85°C 9 UCSP-9 ABP
MAX4722EUA -40°C to +85°C 8 µMAX —
MAX4722EBL-T* -40°C to +85°C 9 UCSP-9 ABQ
MAX4723EUA -40°C to +85°C 8 µMAX —
MAX4723EBL-T* -40°C to +85°C 9 UCSP-9 ABR
MAX4721
UCSP
TOP VIEW
(BUMP SIDE DOWN)
IN_
LOW
HIGH
NO_
OFF
ON
NC_
ON
OFF
C
B
A
123
IN2
COM1
NO1
GND
V+
NO2
COM2
IN1
MAX4722
C
B
A
123
IN2
COM1
NC1
GND
V+
NC2
COM2
IN1
MAX4723
C
B
A
123
IN2
COM1
NO1
GND
V+
NC2
COM2
IN1
UCSP
UCSP
Pin Configurations/Functional Diagrams/Truth Tables
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
UCSP is a trademark of Maxim Integrated Products, Inc.
Note: UCSP package requires special solder temperature pro-
file described in the Absolute Maximum Ratings section.
*UCSP reliability is integrally linked to the user’s assembly meth-
ods, circuit board material, and environment. See the UCSP reli-
ability notice in the UCSP Reliability section of this data sheet for
more information.
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +2.7V to +3.6V, VIH = +1.4V, VIL = +0.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3.0V,
TA= +25°C, unless otherwise noted.) (Notes 3, 4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All Voltages Referenced to GND, Unless Otherwise Noted.)
V+, IN_...................................................................-0.3V to +6.0V
COM_, NO_, NC_ (Note 1) ...........................-0.3V to (V+ + 0.3V)
Continuous Current COM_, NO_, NC_ ...........................±100mA
Peak Current COM_, NO_, NC_
(pulsed at 1ms, 10% duty cycle)................................±200mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 4.5mW/°C above +70°C) .............362mW
9-Bump UCSP (derate 4.7mW/°C above +70°C).........379mW
ESD Method 3015.7 .............................................................>2kV
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Bump Temperature (soldering) (Note 2)
Infrared (15s) ...............................................................+220°C
Vapor Phase (60s) .......................................................+215°C
Note 1: Signals on COM_, NO_, or NC_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maxi-
mum current rating.
Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device
can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recom-
mended in the industry standard specification, JEDEC 020A, paragraph 7.6, table 3 for IR/VPR and convection reflow.
Preheating is required. Hand or wave soldering is not allowed.
PARAMETER SYMBOL CONDITIONS TAMIN TYP MAX UNITS
Analog Signal Range VCOM_,
VNO_, VNC_ 0V+V
ANALOG SWITCH
+25°C 3.0 4.5
On-Resistance (Note 5) RON V+ = 2.7V, ICOM_ = 10mA;
VNO_ or VNC_ = 1.5V TMIN to
TMAX 5Ω
+25°C 0.1 0.3
On-Resistance Match Between
Channels (Notes 5, 6) ∆RON V+ = 2.7V, ICOM_ = 10mA;
VNO_ or VNC_ = 1.5V TMIN to
TMAX 0.4 Ω
+25°C 0.6 1.2
On-Resistance Flatness (Note 7) RFLAT
(
ON
)
V+ = 2.7V, ICOM_ = 10mA;
VNO_ or VNC_ = 1.0V, 1.5V, 2.0V TMIN to
TMAX 1.5 Ω
+25°C -0.5 +0.01 +0.5
NO_, NC_ Off-Leakage Current
(Note 8)
INO_
(
OFF
),
INC_
(
OFF
)
V+ = 3.6V, VCOM_ = 0.3V, 3.3V;
VNO_ or VNC_ = 3.3V, 0.3V TMIN to
TMAX -1.5 +1.5 nA
+25°C -0.5 +0.01 +0.5
COM_ Off-Leakage Current
(Note 8)
IC OM _ (OF F) ,
IC OM _
(
OF F
)
V+ = 3.6V, VCOM_ = 0.3V, 3.3V;
VNO_ or VNC_ = 3.3V, 0.3V TMIN to
TMAX -1.5 +1.5 nA
+25°C -1 +0.01 +1
COM_ On-Leakage Current
(Note 8) ICOM_
(
ON
)
V+ = 3.6V, VCOM_ = 0.3V, 3.3V;
VNO_ or VNC_ = 0.3V, 3.3V, or
floating
TMIN to
TMAX -2 +2 nA
+25°C4080
Turn-On Time tON VNO_, VNC_ = 1.5V;
RL = 300Ω, CL = 35pF, Figure 1 TMIN to
TMAX 100 ns
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = +2.7V to +3.6V, VIH = +1.4V, VIL = +0.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3.0V,
TA= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER SYMBOL CONDITIONS TAMIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS
+25°C2040
Turn-Off Time tOFF VNO_, VNC_ = 1.5V;
RL = 300Ω, CL = 35pF, Figure 1 TMIN to
TMAX 50 ns
+25°C8
Break-Before-Make Time Delay
(MAX4723 Only) (Note 8) tBBM VNO_, VNC_ = 1.5V;
RL = 300Ω, CL = 35pF, Figure 2 TMIN to
TMAX 1ns
Skew (Note 8) tSKEW RS = 39Ω, CL = 50pF, Figure 3 TMIN to
TMAX 0.15 0.2 ns
Charge Injection Q VGEN = 2V, RGEN = 0Ω,
CL = 1.0nF, Figure 4 +25°C5 pC
f = 10MHz; VNO_, VNC_ = 1VP-P;
RL = 50Ω, CL = 5pF, Figure 5a -55
Off-Isolation (Note 9) VISO f = 1MHz; VNO_, VNC_ = 1VP-P;
RL = 50Ω, CL = 5pF, Figure 5a
+25°C
-80
dB
f = 10MHz; VNO_, VNC_ = 1VP-P;
RL = 50Ω, CL = 5pF, Figure 5b -80
Crosstalk (Note 10) VCT f = 1MHz; VNO_, VNC_ = 1VP-P;
RL = 50Ω, CL = 5pF, Figure 5b
+25°C
-110
dB
On-Channel -3dB Bandwidth BW Signal = 0dBm, CL = 5pF,
RL = 50Ω, Figure 5a +25°C >300 MHz
Total Harmonic Distortion THD RL = 600Ω+25°C 0.03 %
NO_, NC_ Off-Capacitance CNO_
(
OFF
)
CNC_
(
OFF
)
f = 1MHz, Figure 6 +25°C9 pF
Switch On-Capacitance C(ON) f = 1MHz, Figure 6 +25°C15 pF
DIGITAL I/O
Input Logic High Voltage VIH TMIN to
TMAX 1.4 V
Input Logic Low Voltage VIL TMIN to
TMAX 0.5 V
Input Leakage Current IIN V+ = +3.6V, VIN_ = 0 or 5.5V TMIN to
TMAX -0.1 +0.1 µA
SUPPLY
Supply Voltage Range V+ TMIN to
TMAX 1.8 5.5 V
Positive Supply Current I+ V+ = 5.5V, VIN_ = 0V or V+ TMIN to
TMAX 1µA
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +4.2V to +5.5V, VIH = +2.0V, VIL = +0.8V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5.0V,
TA= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER SYMBOL CONDITIONS TAMIN TYP MAX UNITS
Analog Signal Range VCOM_,
VNO_, VNC_
TMIN to
TMAX 0V+V
ANALOG SWITCH
+25°C 1.7 3.0
On-Resistance (Note 5) RON V+ = 4.2V, ICOM_ = 10mA;
VNO_ or VNC_ = 3.5V TMIN to
TMAX 3.5 Ω
+25°C 0.1 0.3
On-Resistance Match Between
Channels (Notes 5, 6) ∆RON V+ = 4.2V, ICOM_ = 10mA;
VNO_ or VNC_ = 3.5V TMIN to
TMAX 0.4 Ω
+25°C 0.4 1.2
On-Resistance Flatness (Note 7) RFLAT
(
ON
)
V+ = 4.2V, ICOM_ = 10mA;
VNO_ or VNC_ = 1.0V, 2.0V, 3.5V TMIN to
TMAX 1.5 Ω
+25°C -0.5 +0.01 +0.5
NO_, NC_ Off-Leakage Current
(Note 8)
INO_
(
OFF
),
INC_
(
OFF
)
V+ = 5.5V, VCOM_ = 1.0V, 4.5V;
VNO_ or VNC_ = 4.5V, 1.0V TMIN to
TMAX -1.5 +1.5 nA
+25°C -0.5 +0.01 +0.5
COM _ Off-Leakage Current
(Note 8) IC OM _
(
OF F
)
V+ = 5.5V, VCOM_ = 1V, 4.5V;
VNO_ or VNC_ = 4.5V, 1V TMIN to
TMAX -1.5 +1.5 nA
+25°C -1 +0.01 +1
COM_ On-Leakage Current
(Note 8) ICOM_
(
ON
)
V+ = 5.5V, VCOM_ = 1.0V, 4.5V;
VNO_ or VNC_ = 1.0V, 4.5V, or
floating
TMIN to
TMAX -2 +2 nA
DYNAMIC CHARACTERISTICS
+25°C3080
Turn-On Time tON VNO_, VNC_ = 3.0V;
RL = 300Ω, CL = 35pF, Figure 1 TMIN to
TMAX 90 ns
+25°C2040
Turn-Off Time tOFF VNO_, VNC_ = 3.0V;
RL = 300Ω, CL = 35pF, Figure 1 TMIN to
TMAX 50 ns
+25°C8
Break-Before-Make Time Delay
(MAX4723 Only) (Note 8) tBBM VNO_, VNC_ = 3.0V;
RL = 300Ω, CL = 35pF, Figure 2 TMIN to
TMAX 1ns
Skew (Note 8) tSKEW RS = 39Ω, CL = 50pF, Figure 3 TMIN to
TMAX 1.5 2 ns
DIGITAL I/O
Input Logic High Voltage VIH TMIN to
TMAX 2.0 V
Input Logic Low Voltage VIL TMIN to
TMAX 0.8 V
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = +4.2V to +5.5V, VIH = +2.0V, VIL = +0.8V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5.0V,
TA= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER SYMBOL CONDITIONS TAMIN TYP MAX UNITS
Input Leakage Current IIN V+ = 5.5V, VIN_ = 0V or V+ TMIN to
TMAX -0.1 +0.1 µA
POWER SUPPLY
Power-Supply Range V+ TMIN to
TMAX 1.8 5.5 V
Positive Supply Current I+ V+ = 5.5V, VIN_ = 0V or V+ TMIN to
TMAX 1µA
Note 3: UCSP parts are 100% tested at +25°C only, and guaranteed by design over the specified temperature range. µMAX parts
are 100% tested at TMAX and guaranteed by design over the specified temperature range.
Note 4: The algebraic convention used in this data sheet is where the most negative value is a minimum and the most positive
value is a maximum.
Note 5: Guaranteed by design for UCSP parts.
Note 6: ∆RON = RON(MAX) - RON(MIN).
Note 7: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
Note 8: Guaranteed by design.
Note 9: Off-Isolation = 20log10 (VCOM / VNO), VCOM = output, VNO = input to off switch.
Note 10: Between any two switches.
ON-RESISTANCE vs. VCOM
MAX4721/22/23 toc01
VCOM (V)
RON (Ω)
4321
2
4
6
8
10
0
05
V+ = 1.8V
V+ = 2.5V
V+ = 3V V+ = 4.2V
V+ = 5V
ON-RESISTANCE vs. VCOM
MAX4721/22/23 toc02
VCOM (V)
RON (Ω)
2.52.01.51.00.5
2
3
4
5
6
1
0 3.0
TA = +85°C
TA = +25°C
TA = -40°C
V+ = 3V
ON-RESISTANCE vs. VCOM
MAX4721/22/23 toc03
VCOM (V)
RON (Ω)
4321
1
2
3
4
5
0
05
V+ = 5V
TA = +85°C
TA = -40°CTA = +25°C
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
LEAKAGE CURRENT vs. TEMPERATURE
MAX4721/22/23 toc04a
TEMPERATURE (°C)
LEAKAGE CURRENT (pA)
603510-15
100
200
300
400
500
0
-40 85
V+ = 3V
COM ON-LEAKAGE
COM OFF-LEAKAGE
LEAKAGE CURRENT vs. TEMPERATURE
MAX4721/22/23 toc04b
TEMPERATURE (°C)
LEAKAGE CURRENT (pA)
603510-15
200
400
600
800
1000
0
-40 85
V+ = 5V
COM ON-LEAKAGE
COM OFF-LEAKAGE
CHARGE INJECTION vs. VCOM
MAX4721/22/23 toc05
VCOM (V)
CHARGE INJECTION (pC)
4321
10
20
30
40
50
0
05
CL = 1nF
V+ = 5V
CL = 1nF
V+ = 3V
SUPPLY CURRENT vs. TEMPERATURE
MAX4721/22/23 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (nA)
603510-15
1
2
3
4
5
6
0
-40 85
V+ = 5V
V+ = 3V
SUPPLY CURRENT vs. LOGIC LEVEL
MAX4721/22/23 toc07
LOGIC LEVEL (V)
SUPPLY CURRENT (µA)
4321
20
40
60
80
100
0
05
V+ = 5V
V+ = 3V
TURN-ON/OFF TIME
vs. SUPPLY VOLTAGE
MAX4721/22/23 toc08
SUPPLY VOLTAGE (V)
tON/tOFF (ns)
4.53.52.5
20
40
60
80
100
0
1.5 5.5
tON
tOFF
TURN-ON/OFF TIME
vs. TEMPERATURE
MAX4721/22/23 toc09
TEMPERATURE (°C)
tON/tOFF (ns)
603510-15
0
-40 85
tOFF, V+ = 3.0V tOFF, V+ = 5.0V
tON, V+ = 5.0V
10
20
30
40
50
60
tON, V+ = 3.0V
RISE/FALL-TIME DELAY
vs. SUPPLY VOLTAGE
MAX4721/22/23 toc10
SUPPLY VOLTAGE (V)
OUTPUT RISE/FALL-TIME DELAY (ps)
4.53.52.5
0.5
1.0
1.5
2.0
2.5
3.0
0
1.5 5.5
INPUT RISE/FALL TIME = 15ns
FIGURE 3, CL = 50pF
RISE DELAY
FALL DELAY
RISE/FALL-TIME DELAY
vs. TEMPERATURE
MAX4721/22/23 toc11
TEMPERATURE (°C)
OUTPUT RISE/FALL-TIME DELAY (ns)
603510-15
0.5
1.0
1.5
2.0
0
-40 85
INPUT RISE/FALL TIME = 15ns
FIGURE 3, CL = 50pF
V+ = 4.2V
RISE DELAY FALL DELAY
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
_______________________________________________________________________________________ 7
RISE TIME TO FALL TIME MISMATCH
vs. SUPPLY VOLTAGE
MAX4721/22/23 toc12
SUPPLY VOLTAGE (V)
MISMATCH (ps)
4.53.52.5
100
200
300
400
0
1.5 5.5
INPUT RISE/FALL TIME = 15ns
FIGURE 3, CL = 50pF
RISE TIME TO FALL TIME MISMATCH
vs. TEMPERATURE
MAX4721/22/23 toc13
TEMPERATURE (°C)
MISMATCH (ps)
603510-15
50
100
150
200
0
-40 85
INPUT RISE/FALL TIME = 15ns
FIGURE 3, CL = 50pF
V+ = 4.2V
SKEW vs. SUPPLY VOLTAGE
MAX4721/22/23 toc14
SUPPLY VOLTAGE (V)
SKEW (ps)
4.53.52.5
100
200
300
400
0
1.5 5.5
INPUT RISE/FALL TIME = 15ns
FIGURE 3, CL = 50pF
SKEW vs. TEMPERATURE
MAX4721/22/23 toc15
TEMPERATURE (°C)
SKEW (ps)
603510-15
50
100
150
200
0
-40 85
INPUT RISE/FALL TIME = 15ns
FIGURE 3, CL = 50pF
V+ = 4.2V
FREQUENCY RESPONSE
MAX4721/22/23 toc16
FREQUENCY (MHz)
ON-LOSS (dB)
10.01
-120
-100
-80
-60
-40
-20
0
20
-140
0.0001 100
V+ = 3V/5V
ON-LOSS
OFF-ISOLATION
CROSSTALK
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
MAX4721/22/23 toc17
FREQUENCY (Hz)
THD (%)
10k1k100
0.1
10 100k
1
0.01
V+ = 3V
RL = 600Ω
LOGIC THRESHOLD vs. SUPPLY VOLTAGE
MAX4721/22/23 toc18
SUPPLY VOLTAGE (V)
LOGIC THRESHOLD (V)
5.04.54.03.53.02.52.0
0.4
0.8
1.2
1.6
2.0
0
1.5 5.5
VTH+
VTH-
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
8 _______________________________________________________________________________________
Detailed Description
The MAX4721/MAX4722/MAX4723 dual SPST analog
switches operate from a single +1.8V to +5.5V supply.
The MAX4721/MAX4722/MAX4723 offer excellent AC
characteristics, <0.5nA leakage current, less than 2ms
differential skew, and 15pF on-channel capacitance. All
of these devices are CMOS-logic compatible with rail-
to-rail signal handling capability.
The MAX4721/MAX4722/MAX4723 are USB-compliant
switches that provide 4.5Ω(max) on-resistance, and
15pF on-channel capacitance to maintain signal integri-
ty. At 12Mbps (USB full-speed data rate specification)
the MAX4721/MAX4722/MAX4723 introduce less than
2ns propagation delay between input and output sig-
nals and less than 0.5ns change in skew for the output
signals (see Figure 3 for more details).
The MAX4721 has two normally open (NO) switches, the
MAX4722 has two normally closed (NC) switches, and
the MAX4723 has one NO switch and one NC switch.
Applications Information
Digital Control Inputs
The MAX4721/MAX4722/MAX4723 logic inputs accept
up to +5.5V regardless of supply voltage. For example,
with a +3.3V supply, IN_ can be driven low to GND and
high to +5.5V allowing for mixing of logic levels in a
system. Driving the control logic inputs rail-to-rail mini-
mizes power consumption. For a +3.0V supply voltage,
the logic thresholds are 0.5V (low) and 1.4V (high); for
a +5V supply voltage, the logic thresholds are 0.8V
(low) and 2.0V (high).
Analog Signal Levels
Analog signals that range over the entire supply voltage
(V+ to GND) are passed with very little change in on-resis-
tance (see the Typical Operating Characteristics). The
switches are bidirectional, so the NO_, NC_, and COM_
pins can be either inputs or outputs.
PIN
MAX4721 MAX4722 MAX4723
UCSP µMAX UCSP µMAX UCSP µMAX
NAME FUNCTION
A1 3 A1 3 A1 3 IN2 Logic-Control Digital Input
A2 4 A2 4 A2 4 GND Ground. Connect to digital ground.
A3 5 —— — —NO2 Analog-Switch Normally Open Terminal
B1 2 B1 2 B1 2 COM1 Analog-Switch Common Terminal
B3 6 B3 6 B3 6 COM2 Analog-Switch Common Terminal
C1 1 ——C1 1 NO1 Analog-Switch Normally Open Terminal
C2 8 C2 8 C2 8 V+ Positive Analog Supply
C3 7 C3 7 C3 7 IN1 Logic-Control Digital Input
——C1 1 ——NC1 Analog-Switch Normally Closed Terminal
——A3 5 A3 5 NC2 Analog-Switch Normally Closed Terminal
Pin Description
Power-Supply Bypassing
Power-supply bypassing improves noise margin and
prevents switching noise from propagating from the V+
supply to other components. A 0.1µF capacitor connect-
ed from V+ to GND is adequate for most applications.
Power-Supply Sequencing
and Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings may
cause permanent damage to the device.
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Chip-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
_______________________________________________________________________________________ 9
Test Circuits/Timing Diagrams
50%
VIL
LOGIC
INPUT
RL
COM_
GND
IN_
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VCOM
VN_
VIH
tOFF
0V
NO_
OR NC_
0.9 x V0UT 0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
CL
V+
VOUT
MAX4721/
MAX4722/
MAX4723
(RL
RL - RON )
Figure 1. Switching Time
LOGIC
INPUT
RL2
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_ VOUT2
V+
V+
CL2
MAX4723
RL1 CL1
VOUT1
VCOM1
VCOM2
50%
0.9 x V0UT1
VIH
VIL
0V
LOGIC
INPUT
SWITCH
OUTPUT 2
(VOUT2)
0V
0.9 x VOUT2
tDtD
SWITCH
OUTPUT 1
(VOUT1)
COM2
COM1
Figure 2. Break-Before-Make Interval
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
10 ______________________________________________________________________________________
tskew_i
90%
50%
10%
90%
50%
10%
tfi
INPUT A
INPUT A-
tri
tskew_o
90%
50%
10%
90%
50%
10%
tfo
OUTPUT B
OUTPUT B-
tro
B-
CL
A-
Rs
AB
CL
TxD+
TxD-
Rs
Rs = 39Ω
CL = 50pF
DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
|tskew_i|
|tskew_o|
|tfo - tfi|
|tro - tri|
Figure 3. Input/Output Skew Timing Diagram
Test Circuits/Timing Diagrams (continued)
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
______________________________________________________________________________________ 11
VGEN GND
COM_
CL
VOUT
V+ VOUT
IN
OFF ON OFF
∆VOUT
Q = (∆VOUT)(CL)
NC_
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
OFF ON OFF
IN
VIL TO VIH
V+
RGEN
IN_
MAX4721/
MAX4722/
MAX4723
OR NO_
Figure 4. Charge Injection
MAX4721/
MAX4722/
MAX4723
V+
C = 0.1µF
NC_ or NO_
V+
IN_
0V OR V+
GND
COM_
50Ω*
ANALYZER
*USED ONLY FOR OFF-ISOLATION TEST.
SIGNAL
GENERATOR
0dBm
Figure 5a. On-Loss, Off-Isolation, and Crosstalk
MAX4721/
MAX4722/
MAX4723
V+
C = 0.1µF
V+
0V OR V+
GND
ANALYZER
SIGNAL GENERATOR
0dBm COM1
IN1
NO2
0V TO V+
NO1
IN2
COM2
50Ω
N.C.
Figure 5b. Crosstalk Test Circuit
CAPACITANCE
METER
NC_ or NO_
COM_
GND
IN_ 0V OR V+
C = 0.1µFV+
f = 1MHz
V+
MAX4721/
MAX4722/
MAX4723
Figure 6. Channel Off/On-Capacitance
Test Circuits/Timing Diagrams (continued)
Chip Information
TRANSISTOR COUNT: 181
PROCESS: BiCMOS
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
12 ______________________________________________________________________________________
Pin Configurations/Functional Diagrams/Truth Tables (continued)
1
2
3
4
8
7
6
5
V+
IN1
COM2
NO2GND
IN2
COM1
NO1
MAX4721
µMAX
TOP VIEW
LOGIC SWITCH
0
1
OFF
ON
1
2
3
4
8
7
6
5
V+
IN1
COM2
NC2GND
IN2
COM1
NC1
MAX4722
µMAX
LOGIC SWITCH
0
1
ON
SWITCHES SHOWN FOR LOGIC "0" INPUT
OFF
1
2
3
4
8
7
6
5
V+
IN1
COM2
NC2GND
IN2
COM1
NO1
MAX4723
µMAX
LOGIC SWITCH1
0
1
OFF
ON
SWITCH2
ON
OFF
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
______________________________________________________________________________________ 13
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX4721/MAX4722/MAX4723
4.5
Ω
Dual SPST Analog Switches in UCSP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
PACKAGE OUTLINE, 8L uMAX/uSOP
1
1
21-0036 J
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
MAX
0.043
0.006
0.014
0.120
0.120
0.198
0.026
0.007
0.037
0.0207 BSC
0.0256 BSC
A2 A1
c
eb
A
L
FRONT VIEW SIDE VIEW
E H
0.6±0.1
0.6±0.1
ÿ 0.50±0.1
1
TOP VIEW
D
8
A2 0.030
BOTTOM VIEW
16∞
S
b
L
H
E
D
e
c
0∞
0.010
0.116
0.116
0.188
0.016
0.005
8
4X S
INCHES
-
A1
A
MIN
0.002
0.950.75
0.5250 BSC
0.25 0.36
2.95 3.05
2.95 3.05
4.78
0.41
0.65 BSC
5.03
0.66
6∞0∞
0.13 0.18
MAX
MIN
MILLIMETERS
- 1.10
0.05 0.15
α
α
DIM
