SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 D Extremely Low Offset Voltage . . . 1 V Max D Extremely Low Change on Offset Voltage D008, JG, OR P PACKAGE (TOP VIEW) With Temperature . . . 0.003 V/C Typ CXA IN - IN + VDD - D Low Input Offset Current D D D D D D 500 pA Max at TA = - 55C to 125C AVD . . . 135 dB Min CMRR . . . 120 dB Min kSVR . . . 110 dB Min Single-Supply Operation Common-Mode Input Voltage Range Includes the Negative Rail No Noise Degradation With External Capacitors Connected to VDD - 1 8 2 7 3 6 4 5 CXB VDD + OUT CLAMP D014, J, OR N PACKAGE (TOP VIEW) CXB CXA NC IN - IN + NC VDD - description 1 14 2 13 3 12 4 11 5 10 6 9 INT/EXT CLK IN CLK OUT VDD + OUT CLAMP C RETURN 8 The TLC2652 and TLC2652A are high-precision chopper-stabilized operational amplifiers using FK PACKAGE Texas Instruments Advanced LinCMOS pro(TOP VIEW) cess. This process, in conjunction with unique chopper-stabilization circuitry, produces operational amplifiers whose performance matches or exceeds that of similar devices available today. Chopper-stabilization techniques make possible 3 2 1 20 19 NC 18 CLK OUT 4 extremely high dc precision by continuously NC 17 NC 5 nulling input offset voltage even during variations IN - 6 16 VDD + in temperature, time, common-mode voltage, and 15 NC NC 7 power supply voltage. In addition, low-frequency 14 OUT 8 IN + noise voltage is significantly reduced. This high 9 10 11 12 13 precision, coupled with the extremely high input impedance of the CMOS input stage, makes the TLC2652 and TLC2652A an ideal choice for low-level signal processing applications such as strain gauges, thermocouples, and other transducer amplifiers. For applications that NC - No internal connection require extremely low noise and higher usable bandwidth, use the TLC2654 or TLC2654A device, which has a chopping frequency of 10 kHz. The TLC2652 and TLC2652A input common-mode range includes the negative rail, thereby providing superior performance in either single-supply or split-supply applications, even at power supply voltage levels as low as 1.9 V. Two external capacitors are required for operation of the device; however, the on-chip chopper-control circuitry is transparent to the user. On devices in the 14-pin and 20-pin packages, the control circuitry is made accessible to allow the user the option of controlling the clock frequency with an external frequency source. In addition, the clock threshold level of the TLC2652 and TLC2652A requires no level shifting when used in the single-supply configuration with a normal CMOS or TTL clock input. NC VDD- NC C RETURN CLAMP V XA V XB NC INT/EXT CLK IN 7 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinCMOS is a trademark of Texas Instruments. Copyright 1988-2005, Texas Instruments Incorporated !"#$ %" & '## % & "! (')* %" %+ #" '%& " !"#$ %" &(! %" & (# %, %#$& "! - & &%#'$ %& &% # . ## %/+ #" '%" (#"&& 0 "& "% && #*/ *' %&% 0 "! ** ( # $%#&+ (#" '%& "$(* % %" 121 ** ( # $%#& # %&% ' *&& "%,#.& "% + ** "%,# (#" '%& (#" '%" (#"&& 0 "& "% && #*/ *' %&% 0 "! ** ( # $%#&+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 description (continued) Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload recovery time. If desired, an output clamp pin is available to reduce the recovery time even further. The device inputs and output are designed to withstand 100-mA surge currents without sustaining latch-up. Additionally the TLC2652 and TLC2652A incorporate internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance. The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized for operation from - 40C to 85C. The Q-suffix devices are characterized for operation from - 40C to125C. The M-suffix devices are characterized for operation over the full military temperature range of -55C to125C. AVAILABLE OPTIONS(1) PACKAGED DEVICES TA VIOmax AT 25C 0C 0 C to 70 C 70C 8 PIN 14 PIN 20 PIN CHIP FORM (Y) SMALL OUTLINE (D008) CERAMIC DIP (JG) PLASTIC DIP (P) SMALL OUTLINE (D014) CERAMIC DIP (J) PLASTIC DIP (N) CHIP CARRIER (FK) 1 V 3 V TLC2652AC-8D TLC2652C-8D -- -- TLC2652ACP TLC2652CP TLC2652AC-14D TLC2652C - 14D -- -- TLC2652ACN TLC2652CN -- -- TLC2652Y 40C - 40 C to 85 C 85C 1 V 3 V TLC2652AI-8D TLC2652A-8D -- -- TLC2652AIP TLC2652IP TLC2652AI-14D TLC2652I-14D -- -- TLC2652AIN TLC2652IN -- -- -- 40C - 40 C to 125 C 125C 3.5 V TLC2652Q-8D -- -- -- -- -- -- -- - 55C to 125C 3 V 3.5 V TLC2652AM-8D TLC2652M-8D TLC2652AMJG TLC2652MJG TLC2652AMP TLC2652MP TLC2652AM-14D TLC2652M-14D TLC2652AMJ TLC2652MJ TLC2652AMN TLC2652MN TLC2652AMFK TLC2652MFK -- The D008 and D014 packages are available taped and reeled. Add R suffix to the device type (e.g., TLC2652AC-8DR). Chips are tested at 25C. NOTE (1): For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. functional block diagram DISTRIBUTION OF TLC2652 INPUT OFFSET VOLTAGE VDD + 7 36 IN + IN - 3 6 + - 2 B B Main CIC A B CompensationBiasing Circuit OUT A + - A Null CXA CXB 150 Units Tested From 1 Wafer Lot 32 VDD = 5 V TA = 25C 28 N Package CLAMP External Components Percentage of Units - % 5 Clamp Circuit 24 20 16 12 8 4 4 VDD - 8 0 C RETURN -3 Pin numbers shown are for the D (14 pin), JG, and N packages. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 -2 -1 0 1 2 VIO - Input Offset Voltage - V 3 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TLC2652Y chip information This chip, when properly assembled, displays characteristics similar to the TLC2652C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (13) (12) (11) (10) (9) (14) (8) CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 x 4 MINIMUM TJmax = 150C TOLERANCES ARE 10%. 80 ALL DIMENSIONS ARE IN MILS. (1) PIN (7) IS INTERNALLY CONNECTED TO BACK SIDE OF CHIP. FOR THE PINOUT, SEE THE FUNCTIONAL BLOCK DIAGRAM. (2) (4) (5) (7) 90 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage VDD + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Supply voltage VDD - (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Input voltage, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Voltage range on CLK IN and INT/EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - to VDD - + 5.2 V Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Duration of short-circuit current at (or below) 25C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Current into CLK IN and INT/EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 150 C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or P package . . . . . . . . . . . . . 260 C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JG package . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD + and VDD - . 2. Differential voltages are at IN+ with respect to IN -. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. DISSIPATION RATING TABLE PACKAGE TA 25C 25 C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70 70C C POWER RATING TA = 85 85C C POWER RATING TA = 125 125C C POWER RATING D008 725 mV 5.8 mW/C 464 mW 377 mW 145 mW D014 950 mV 7.6 mW/C 608 mW 494 mW 190 mW FK 1375 mV 11.0 mW/C 880 mW 715 mW 275 mW J 1375 mV 11.0 mW/C 880 mW 715 mW 275 mW JG 1050 mV 8.4 mW/C 672 mW 546 mW 210 mW N 1575 mV 12.6 mW/C 1008 mW 819 mW 315 mW P 1000 mV 8.0 mW/C 640 mW 520 mW 200 mW recommended operating conditions C SUFFIX Supply voltage, VDD Common-mode input voltage, VIC Clock input voltage Operating free-air temperature, TA 4 I SUFFIX Q SUFFIX M SUFFIX MIN MAX MIN MAX MIN MAX MIN MAX 1.9 8 1.9 8 1.9 8 1.9 8 VDD - VDD - 0 VDD + - 1.9 VDD - + 5 70 VDD - VDD - -40 POST OFFICE BOX 655303 VDD + - 1.9 VDD - VDD - + 5 VDD - 85 -40 * DALLAS, TEXAS 75265 VDD + - 1.9 VDD - VDD - + 5 VDD - 125 -55 UNIT V VDD + - 1.9 VDD - + 5 V 125 C V SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC2652C MIN 25C VIO Input offset voltage VIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) TYP 0.6 Full range VIC = 0, RS = 50 IIO Input offset current IIB Input bias current VICR Common-mode input voltage range RS = 50 VOM + Maximum positive peak output voltage swing RL = 10 k k, See Note 5 VOM - Maximum negative peak output voltage swing RL = 10 k k, See Note 5 AVD Large-signal differential voltage amplification VO = 4 V, RL = 10 k fch Internal chopping frequency TLC2652AC MAX MIN 3 TYP 0.5 4.35 MAX 1 2.35 UNIT V V Full range 0.003 0.03 0.003 0.03 V/C V/C 25C 0.003 0.06 0.003 0.02 V/mo 25C 2 60 2 Full range 100 25C 4 Full range 60 4 100 Full range -5 to 3.1 25C 4.7 Full range 4.7 25C -4.7 Full range -4.7 25C 120 Full range 120 25C 60 100 60 100 -5 to 3.1 4.8 4.7 -4.7 4.8 V -4.9 V -4.7 150 135 150 dB 130 450 450 25C 25 25 25 25 Hz A A Clamp on-state current RL = 100 k Full range 25C 100 100 Clamp off-state current VO = - 4 V to 4 V Full range 100 100 Common-mode rejection ratio VO = 0, VIC = VICRmin, RS = 50 25C 120 CMRR Full range 120 Supply-voltage rejection ratio (VDD /VIO) VDD = 1.9 V to 8 V, VO = 0, RS = 50 25C 110 kSVR Full range 110 IDD Supply current 25C Full range 140 120 110 dB 135 dB 110 1.5 2.4 2.5 pA 140 120 135 pA V 4.7 -4.9 pA 1.5 2.4 2.5 mA Full range is 0 to 70C. NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150C extrapolated at TA = 25 using the Arrhenius equation and assuming an activation energy of 0.96 eV. 5. Output clamp is not connected. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 operating characteristics specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA 25C TLC2652C MIN TYP 2 2.8 TLC2652AC MAX MIN TYP 2 2.8 MAX SR + Positive slew rate at unity gain SR - Negative slew rate at unity gain VO = 2.3 V, RL = 10 k, CL = 100 pF Equivalent input noise voltage (see Note 6) f = 10 Hz 25C 94 94 140 Vn f = 1 kHz 25C 23 23 35 Peak-to-peak equivalent input noise voltage f = 0 to 1 Hz 25C 0.8 0.8 VN(PP) f = 0 to 10 Hz 25C 2.8 2.8 In Equivalent input noise current f = 10 kHz 25C 0.004 0.004 25C 25 C 1.9 1.9 25C 48 48 Gain-bandwidth product m Phase margin at unity gain Full range 1.5 25C 2.3 Full range 1.8 f = 10 kHz, RL = 10 k, CL = 100 pF RL = 10 k, CL = 100 pF V/ s V/s 1.5 3.1 2.3 UNIT 3.1 V/ s V/s 1.8 nV/Hz V V fA/Hz MHz Full range is 0 to 70C. NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TA TEST CONDITIONS TLC2652I MIN TYP 25C VIO Input offset voltage VIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) 0.6 Full range IIO Input offset current IIB Input bias current VICR Common-mode input voltage range RS = 50 VOM + Maximum positive peak output voltage swing k RL = 10 k, See Note 5 VOM - Maximum negative peak output voltage swing k RL = 10 k, See Note 5 AVD Large-signal differential voltage amplification VO = 4 V, RL = 10 k MIN 3 TYP 0.5 4.95 MAX 1 2.95 V V 0.003 0.03 0.003 0.03 V/C V/C 25C 0.003 0.06 0.003 0.02 V/mo 25C 2 60 2 Full range 150 25C 4 Full range -5 to 3.1 25C 4.7 Full range 4.7 25C -4.7 Full range -4.7 25C 120 Full range 120 25C 60 150 60 4 150 Full range Internal chopping frequency 150 -5 to 3.1 4.8 4.7 -4.7 4.8 V -4.9 V -4.7 150 135 150 dB 125 450 450 25C 25 25 25 25 Hz A A RL = 100 k Full range 25C 100 100 Clamp off-state current VO = - 4 V to 4 V Full range 100 100 Common-mode rejection ratio VO = 0, VIC = VICRmin, RS = 50 25C 120 CMRR Full range 120 Supply-voltage rejection ratio (VDD /VIO) VDD = 1.9 V to 8 V, VO = 0, RS = 50 25C 110 kSVR Full range 110 IDD Supply current VO = 0, 25C Full range 140 120 110 dB 135 dB 110 1.5 2.4 2.5 pA 140 120 135 pA V 4.7 -4.9 pA 60 Clamp on-state current No load UNIT Full range RS = 50 VIC = 0, TLC2652AI MAX 1.5 2.4 2.5 mA Full range is - 40 to 85C. NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150C extrapolated at TA = 25 using the Arrhenius equation and assuming an activation energy of 0.96 eV. 5. Output clamp is not connected. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA 25C TLC2652I MIN TYP 2 2.8 TLC2652AI MAX MIN TYP 2 2.8 MAX SR + Positive slew rate at unity gain SR - Negative slew rate at unity gain VO = 2.3 V, RL = 10 k, CL = 100 pF Equivalent input noise voltage (see Note 6) f = 10 Hz 25C 94 94 140 Vn f = 1 kHz 25C 23 23 35 Peak-to-peak equivalent input noise voltage f = 0 to 1 Hz 25C 0.8 0.8 VN(PP) f = 0 to 10 Hz 25C 2.8 2.8 In Equivalent input noise current f = 1 kHz 25C 0.004 0.004 25C 25 C 1.9 1.9 25C 48 48 Gain-bandwidth product m Phase margin at unity gain Full range 1.4 25C 2.3 Full range 1.7 f = 10 kHz, RL = 10 k, CL = 100 pF RL = 10 k, CL = 100 pF V/ s V/s 1.4 3.1 2.3 UNIT 3.1 V/ s V/s 1.7 nV/Hz V V pA/Hz MHz Full range is - 40 to 85C. NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TA TEST CONDITIONS TLC2652Q TLC2652M MIN VIO Input offset voltage (see Note 7) VIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) 25C TYP MAX 0.6 3.5 Full range IIO Input offset current IIB Input bias current VICR Common-mode input voltage range RS = 50 VOM + Maximum positive peak output voltage swing k RL = 10 k, See Note 5 VOM - Maximum negative peak output voltage swing k RL = 10 k, See Note 5 AVD Large-signal differential voltage amplification VO = 4 V, RL = 10 k fch Internal chopping frequency MIN UNIT TYP MAX 0.5 3 10 8 0.003 0.03 0.003 0.03 V/C V/C 25C 0.003 0.06 0.003 0.02 V/mo 25C 2 60 2 60 Full range 500 25C 4 Full range 500 60 4 500 Full range -5 to 3.1 25C 4.7 Full range 4.7 25C -4.7 Full range -4.7 25C 120 Full range 120 25C -5 to 3.1 4.8 4.7 -4.7 4.8 V -4.9 V -4.7 150 135 150 dB 120 450 450 25C 25 25 25 25 Hz A A VO = - 5 V to 5 V Full range 25C 100 100 Clamp off-state current RL = 100 k Full range 500 500 Common-mode rejection ratio VO = 0, VIC = VICRmin, RS = 50 25C 120 CMRR Full range 120 Supply-voltage rejection ratio (VDD /VIO) VDD = 1.9 V to 8 V, VO = 0, RS = 50 25C 110 kSVR Full range 110 IDD Supply current VO = 0, 25C Full range 140 120 110 dB 135 dB 110 1.5 2.4 2.5 pA 140 120 135 pA V 4.7 -4.9 pA 60 500 Clamp on-state current No load V V Full range RS = 50 VIC = 0, TLC2652AM 1.5 2.4 2.5 mA On products compliant to MIL-PRF-38535, this parameter is not production tested. Full range is - 40 to 125C for Q suffix, - 55 to 125C for M suffix. NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150C extrapolated at TA = 25 using the Arrhenius equation and assuming an activation energy of 0.96 eV. 5. Output clamp is not connected. 7. This parameter is not production tested. Thermocouple effects preclude measurement of the actual VIO of these devices in high speed automated testing. VIO is measured to a limit determined by the test equipment capability at the temperature extremes. The test ensures that the stabilization circuitry is performing properly. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA 25C SR + Positive slew rate at unity gain SR - Negative slew rate at unity gain Vn Equivalent input noise voltage VN(PP) Peak-to-peak equivalent input noise voltage In m VO = 2.3 V, RL = 10 k, CL = 100 pF MIN TYP 2 2.8 Full range 1.3 25C 2.3 Full range 1.6 V/ s V/s 25C 94 25C 23 f = 0 to 1 Hz 25C 0.8 f = 0 to 10 Hz 25C 2.8 Equivalent input noise current f = 1 kHz 25C 0.004 Gain-bandwidth product f = 10 kHz, RL = 10 k, CL = 100 pF 25C 1.9 Phase margin at unity gain RL = 10 k, CL = 100 pF 25C 48 * DALLAS, TEXAS 75265 MAX 3.1 f = 1 kHz POST OFFICE BOX 655303 UNIT V/ s V/s f = 10 Hz Full range is - 40 to 125C for the Q suffix, - 55 to 125C for the M suffix. 10 TLC2652Q TLC2652M TLC2652AM nV/Hz V V pA/Hz MHz SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 electrical characteristics at VDD = 5 V, TA = 25C (unless otherwise noted) PARAMETER VIO TEST CONDITIONS TLC2652Y MIN Input offset voltage Input offset voltage long-term drift (see Note 4) VIC = 0, RS = 50 UNIT TYP MAX 0.6 3 0.003 0.006 2 60 pA 4 60 pA V V/mo IIO IIB Input offset current VICR Common-mode input voltage range RS = 50 VOM + VOM - Maximum positive peak output voltage swing RL = 10 k, See Note 5 4.7 4.8 Maximum negative peak output voltage swing RL = 10 k, See Note 5 -4.7 -4.9 V AVD fch Large-signal differential voltage amplification VO = 4 V, RL = 10 k 120 150 dB Input bias current -5 to 3.1 Internal chopping frequency V V 450 Clamp on-state current RL = 100 k Clamp off-state current VO = - 4 V to 4 V VO = 0, VIC = VICRmin, RS = 50 CMRR Common-mode rejection ratio kSVR Supply-voltage rejection ratio (VDD /VIO) Hz A 25 VDD = 1.9 V to 8 V, RS = 50 VO = 0, VO = 0, No load 100 pA 120 140 dB 110 135 dB IDD Supply current 1.5 2.4 mA NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150C extrapolated at TA = 25 using the Arrhenius equation and assuming an activation energy of 0.96 eV. 5. Output clamp is not connected. operating characteristics at VDD = 5 V, TA = 25C PARAMETER SR + Positive slew rate at unity gain SR - Negative slew rate at unity gain TEST CONDITIONS VO = 2.3 V, CL = 100 pF RL = 10 k, TLC2652Y TYP 2 2.8 V/s 2.3 3.1 V/s f = 10 Hz 94 f = 1 kHz 23 f = 0 to 1 Hz 0.8 f = 0 to 10 Hz 2.8 Vn Equivalent input noise voltage VN(PP) Peak-to-peak equivalent input noise voltage In Equivalent input noise current f = 1 kHz Gain-bandwidth product f = 10 kHz, CL = 100 pF RL = 10 k, 1.9 Phase margin at unity gain RL = 10 k, CL = 100 pF 48 m POST OFFICE BOX 655303 MAX UNIT MIN nV/Hz V V pA/Hz * DALLAS, TEXAS 75265 MHz 11 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Normalized input offset voltage vs Chopping frequency 1 IIB Input bias current vs Common-mode input voltage vs Chopping frequency vs Free-air temperature 2 3 4 IIO Input offset current vs Chopping frequency vs Free-air temperature 5 6 Clamp current vs Output voltage 7 Maximum peak-to-peak output voltage vs Frequency VOM Maximum peak output voltage vs Output current vs Free-air temperature 9, 10 11, 12 AVD Large-signal differential voltage amplification vs Frequency vs Free-air temperature 13 14 Chopping frequency vs Supply voltage vs Free-air temperature 15 16 IDD Supply current vs Supply voltage vs Free-air temperature 17 18 IOS Short-circuit output current vs Supply voltage vs Free-air temperature 19 20 SR Slew rate vs Supply voltage vs Free-air temperature 21 22 Voltage-follower pulse response Small-signal Large-signal 23 24 Peak-to-peak equivalent input noise voltage vs Chopping frequency Equivalent input noise voltage vs Frequency 27 Gain-bandwidth product vs Supply voltage vs Free-air temperature 28 29 Phase margin vs Supply voltage vs Free-air temperature vs Load capacitance 30 31 32 Phase shift vs Frequency 13 V(OPP) VN(PP) Vn m 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 8 25, 26 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS NORMALIZED INPUT OFFSET VOLTAGE vs CHOPPING FREQUENCY INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE 70 IIB I IB - Input Bias Current - pA 60 VIO uV VIO - Normalized Input Offset - V 25 VDD = 5 V VIC = 0 TA = 25C 50 40 30 20 10 VDD = 5 V TA = 25C 20 15 10 5 0 -10 100 1k 10 k Chopping Frequency - Hz 0 -5 100 k -4 -3 -2 1 2 3 4 5 Figure 2 INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE INPUT BIAS CURRENT vs CHOPPING FREQUENCY 100 70 VDD = 5 V VIC = 0 TA = 25C IIB I IB - Input Bias Current - pA IIB I IB - Input Bias Current - pA 0 VIC - Common-Mode Input Voltage - V Figure 1 60 -1 50 40 30 20 VDD = 5 V VO = 0 VIC = 0 10 10 0 100 1k 10 k 100 k 1 25 45 65 85 105 125 TA - Free-Air Temperature - C Chopping Frequency - Hz Figure 4 Figure 3 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS INPUT OFFSET CURRENT vs CHOPPING FREQUENCY INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE 10 VDD = 5 V VIC = 0 VDD = 5 V VIC = 0 TA = 25C 20 IIIO IO - Input Offset Current - pA IIIO IO - Input Offset Current - pA 25 15 10 5 8 6 4 2 0 0 100 1k 10 k 105 45 65 85 TA - Free-Air Temperature - C 25 100 k Chopping Frequency - Hz Figure 5 Figure 6 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY VO(PP) V O(PP)- Maximum Peak-to-Peak Output Voltage - V CLAMP CURRENT vs OUTPUT VOLTAGE 100 A VDD = 5 V TA = 25C 10 A |Clamp Current| 1 A Positive Clamp Current 100 nA 10 nA 1 nA 100 pA Negative Clamp Current 10 pA 1 pA 4 4.2 4.4 4.6 4.8 5 10 8 TA = - 55C 6 TA = 125C 4 2 VDD = 5 V RL = 10 k 0 100 1k 10 k f - Frequency - Hz |VO| - Output Voltage - V Figure 7 Figure 8 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 14 125 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1M SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT 7.5 VDD = 5 V TA = 25C 4.8 VOM + VDD = 7.5 V TA = 25C |VOM| |VOM - Maximum Peak Output Voltage - V |VOM| |VOM - Maximum Peak Output Voltage - V 5 VOM - 4.6 4.4 4.2 7.3 7.1 6.9 4 6.7 0 0.4 0.8 1.2 1.6 2 0 0.4 |IO| - Output Current - mA 0.8 1.2 1.6 2 |IO| - Output Current - mA Figure 9 Figure 10 MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 5 8 VOM VOM - Maximum Peak Output Voltage - V VOM VOM - Maximum Peak Output Voltage - V VOM - VOM + 2.5 VDD = 5 V RL = 10 k 0 -2.5 -5 4 VDD = 7.5 V RL = 10 k 0 -4 -8 -75 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C -75 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C 125 Figure 12 Figure 11 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 120 60 AA AA AA Phase Shift 80 80 100 AVD 60 120 40 140 20 160 0 -20 -40 10 180 VDD = 5 V RL = 10 k CL = 100 pF TA = 25C 100 Phase Shift AVD AVD- Large-Signal Differential Voltage Amplification - dB 100 200 1k 10 k 100 k 1M 220 10 M f - Frequency - Hz Figure 13 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE AVD AVD- Large-Signal Differential Voltage Amplification - dB 155 AA AA AA VDD = 7.5 V RL = 10 k VO = 4 V 150 145 140 135 -75 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C Figure 14 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS CHOPPING FREQUENCY vs FREE-AIR TEMPERATURE CHOPPING FREQUENCY vs SUPPLY VOLTAGE 460 540 VDD = 5 V TA = 25C 450 Chopping Frequency - kHz Chopping Frequency - kHz 520 500 480 460 440 430 420 410 440 400 -75 420 0 1 6 2 3 4 5 |VDD | - Supply Voltage - V 7 8 75 100 0 25 50 -50 -25 TA - Free-Air Temperature - C Figure 15 Figure 16 SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 2 2 VO = 0 No Load VDD = 7.5 V IIDD DD - Supply Current - mA 1.6 IIDD DD - Supply Current - mA 125 TA = 25C 1.2 TA = - 55C 0.8 TA = 125C 1.6 VDD = 5 V 1.2 VDD = 2.5 V 0.8 0.4 0.4 VO = 0 No Load 0 0 1 2 3 4 5 6 7 8 0 -75 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C |VDD | - Supply Voltage - V Figure 18 Figure 17 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE SHORT-CIRCUIT OUTPUT CURRENT vs FREE-AIR TEMPERATURE 15 VO = 0 TA = 25C IOS I OS - Short-Circuit Output Current - mA IOS I OS - Short-Circuit Output Current - mA 12 8 4 VID = - 100 mV 0 -4 -8 VID = 100 mV -12 0 1 6 2 3 4 5 |VDD | - Supply Voltage - V 7 10 5 VID = - 100 mV 0 -5 VID = 100 mV -10 -15 -75 8 VDD = 5 V VO = 0 75 100 0 25 50 -50 -25 TA - Free-Air Temperature - C Figure 19 Figure 20 SLEW RATE vs FREE-AIR TEMPERATURE SLEW RATE vs SUPPLY VOLTAGE 4 4 SR - SR - VDD = 5 V RL = 10 k CL = 100 pF 3 SR - Slew Rate - V?us V/ s 3 SR - Slew Rate - V?us V/ s 125 SR + 2 1 SR + 2 1 RL = 10 k CL = 100 pF TA = 25C 0 0 1 6 2 3 4 5 |VDD | - Supply Voltage - V 7 8 0 75 100 -75 -50 -25 0 25 50 TA - Free-Air Temperature - C Figure 21 Figure 22 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 125 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE 100 4 75 3 50 2 VO VO - Output Voltage - V VO VO - Output Voltage - mV VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE VDD = 5 V RL = 10 k CL = 100 pF TA = 25C 25 0 -25 -50 VDD = 5 V RL = 10 k CL = 100 pF TA = 25C 1 0 -1 -2 -3 -75 -100 0 1 2 3 4 5 6 -4 7 0 Figure 23 VN(PP) - Peak-to-Peak Input Noise Voltage - V VN(PP) uV VN(PP) VN(PP) - Peak-to-Peak Input Noise Voltage -uV V VDD = 5 V RS = 20 f = 0 to 1 Hz TA = 25C 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 4 15 20 25 30 35 40 PEAK-TO-PEAK INPUT NOISE VOLTAGE vs CHOPPING FREQUENCY 1.8 2 10 Figure 24 PEAK-TO-PEAK INPUT NOISE VOLTAGE vs CHOPPING FREQUENCY 0 5 t - Time - s t - Time - s 6 8 10 fch - Chopping Frequency - kHz 5 VDD = 5 V RS = 20 f = 0 to 10 Hz TA = 25C 4 3 2 1 0 0 8 2 4 6 fch - Chopping Frequency - kHz 10 Figure 26 Figure 25 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 100 2.1 80 Gain-Bandwidth Product - MHz V Vn nV/HzHz n - Equivalent Input Noise Voltage - nV/ EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 60 40 20 VDD = 5 V RS = 20 TA = 25C 0 1 10 100 RL = 10 k CL = 100 pF TA = 25C 2 1.9 1.8 1k 0 1 f - Frequency - Hz 2 3 Figure 27 6 7 8 7 8 PHASE MARGIN vs SUPPLY VOLTAGE 50 2.6 VDD = 5 V RL = 10 k CL = 100 pF 2.4 RL = 10 k CL = 100 pF TA = 25C 48 om m - Phase Margin Gain-Bandwidth Product - MHz 5 Figure 28 GAIN-BANDWIDTH PRODUCT vs FREE-AIR TEMPERATURE 2.2 2 1.8 46 44 42 1.4 1.2 -75 4 |VCC | - Supply Voltage - V 40 -50 -25 0 25 50 75 100 125 0 1 TA - Free-Air Temperature - C 2 3 4 5 6 |VCC | - Supply Voltage - V Figure 29 Figure 30 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS PHASE MARGIN vs LOAD CAPACITANCE PHASE MARGIN vs FREE-AIR TEMPERATURE 50 60 50 om m - Phase Margin om m - Phase Margin 48 46 44 42 VDD = 5 V RL = 10 k TA = 25C 30 20 10 VDD = 5 V RL = 10 k CL = 100 pF 40 -75 -50 -25 40 0 0 25 50 75 100 125 0 200 TA - Free-Air Temperature - C 400 600 800 1000 CL - Load Capacitance - pF Figure 31 Figure 32 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. APPLICATION INFORMATION capacitor selection and placement The two important factors to consider when selecting external capacitors CXA and CXB are leakage and dielectric absorption. Both factors can cause system degradation, negating the performance advantages realized by using the TLC2652. Degradation from capacitor leakage becomes more apparent with the increasing temperatures. Low-leakage capacitors and standoffs are recommended for operation at TA = 125C. In addition, guard bands are recommended around the capacitor connections on both sides of the printed circuit board to alleviate problems caused by surface leakage on circuit boards. Capacitors with high dielectric absorption tend to take several seconds to settle upon application of power, which directly affects input offset voltage. In applications where fast settling of input offset voltage is needed, it is recommended that high-quality film capacitors, such as mylar, polystyrene, or polypropylene, be used. In other applications, however, a ceramic or other low-grade capacitor can suffice. Unlike many choppers available today, the TLC2652 is designed to function with values of CXA and CXB in the range of 0.1 F to 1 F without degradation to input offset voltage or input noise voltage. These capacitors should be located as close as possible to the CXA and CXB pins and returned to either VDD - or C RETURN. On many choppers, connecting these capacitors to VDD - causes degradation in noise performance. This problem is eliminated on the TLC2652. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 APPLICATION INFORMATION internal/external clock When large differential input voltage conditions are applied to the TLC2652, the nulling loop attempts to prevent the output from saturating by driving CXA and CXB to internally-clamped voltage levels. Once the overdrive condition is removed, a period of time is required to allow the built-up charge to dissipate. This time period is defined as overload recovery time (see Figure 33). Typical overload recovery time for the TLC2652 is significantly faster than competitive products; however, if required, this time can be reduced further by use of internal clamp circuitry accessible through CLAMP if required. VII - Input Voltage - mV V overload recovery/output clamp VO V O - Output Voltage - V The TLC2652 has an internal clock that sets the chopping frequency to a nominal value of 450 Hz. On 8-pin packages, the chopping frequency can only be controlled by the internal clock; however, on all 14-pin packages and the 20-pin FK package, the device chopping frequency can be set by the internal clock or controlled externally by use of the INT/EXT and CLK IN pins. To use the internal 450-Hz clock, no connection is necessary. If external clocking is desired, connect INT/EXT to VDD - and the external clock to CLK IN. The external clock trip point is 2.5 V above the negative rail; however, CLK IN can be driven from the negative rail to 5 V above the negative rail. If this level is exceeded, damage could occur to the device unless the current into CLK IN is limited to 5 mA. When operating in the single-supply configuration, this feature allows the TLC2652 to be driven directly by 5-V TTL and CMOS logic. A divide-by0 two frequency divider interfaces with CLK IN and VDD = 5 V sets the clock chopping frequency. The duty cycle TA = 25 C of the external clock is not critical but should be kept between 30% and 60%. -5 0 -50 0 10 20 30 40 50 60 70 80 t - Time - ms Figure 33. Overload Recovery The clamp is a switch that is automatically activated when the output is approximately 1 V from either supply rail. When connected to the inverting input (in parallel with the closed-loop feedback resistor), the closed-loop gain is reduced, and the TLC2652 output is prevented from going into saturation. Since the output must source or sink current through the switch (see Figure 7), the maximum output voltage swing is slightly reduced. thermoelectric effects To take advantage of the extremely low offset voltage drift of the TLC2652, care must be taken to compensate for the thermoelectric effects present when two dissimilar metals are brought into contact with each other (such as device leads being soldered to a printed circuit board). Dissimilar metal junctions can produce thermoelectric voltages in the range of several microvolts per degree Celsius (orders of magnitude greater than the 0.01-V/C typical of the TLC2652). To help minimize thermoelectric effects, careful attention should be paid to component selection and circuit-board layout. Avoid the use of nonsoldered connections (such as sockets, relays, switches, etc.) in the input signal path. Cancel thermoelectric effects by duplicating the number of components and junctions in each device input. The use of low-thermoelectric-coefficient components, such as wire-wound resistors, is also beneficial. 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 APPLICATION INFORMATION latch-up avoidance Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs and output are designed to withstand -100-mA surge currents without sustaining latch-up; however, techniques to reduce the chance of latch-up should be used whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltages should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 F typical) located across the supply rails as close to the device as possible. The current path established if latch-up occurs is usually between the supply rails and is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up occurring increases with increasing temperature and supply voltage. electrostatic discharge protection The TLC2652 incorporates internal ESD-protection circuits that prevent functional failures at voltages at or below 2000 V. Care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance. theory of operation Chopper-stabilized operational amplifiers offer the best dc performance of any monolithic operational amplifier. This superior performance is the result of using two operational amplifiers, a main amplifier and a nulling amplifier, plus oscillator-controlled logic and two external capacitors to create a system that behaves as a single amplifier. With this approach, the TLC2652 achieves submicrovolt input offset voltage, submicrovolt noise voltage, and offset voltage variations with temperature in the nV/C range. The TLC2652 on-chip control logic produces two dominant clock phases: a nulling phase and an amplifying phase. The term chopper-stabilized derives from the process of switching between these two clock phases. Figure 34 shows a simplified block diagram of the TLC2652. Switches A and B are make-before-break types. During the nulling phase, switch A is closed shorting the nulling amplifier inputs together and allowing the nulling amplifier to reduce its own input offset voltage by feeding its output signal back to an inverting input node. Simultaneously, external capacitor CXA stores the nulling potential to allow the offset voltage of the amplifier to remain nulled during the amplifying phase. Main Amplifier IN + + IN - - VO B B A CXB + VDD - - Null Amplifier A CXA Figure 34. TLC2652 Simplified Block Diagram POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 SLOS019E - SEPTEMBER 1988 - REVISED FEBRUARY 2005 APPLICATION INFORMATION theory of operation (continued) During the amplifying phase, switch B is closed connecting the output of the nulling amplifier to a noninverting input of the main amplifier. In this configuration, the input offset voltage of the main amplifier is nulled. Also, external capacitor CXB stores the nulling potential to allow the offset voltage of the main amplifier to remain nulled during the next nulling phase. This continuous chopping process allows offset voltage nulling during variations in time and temperature over the common-mode input voltage range and power supply range. In addition, because the low-frequency signal path is through both the null and main amplifiers, extremely high gain is achieved. The low-frequency noise of a chopper amplifier depends on the magnitude of the component noise prior to chopping and the capability of the circuit to reduce this noise while chopping. The use of the Advanced LinCMOS process, with its low-noise analog MOS transistors and patent-pending input stage design, significantly reduces the input noise voltage. The primary source of nonideal operation in chopper-stabilized amplifiers is error charge from the switches. As charge imbalance accumulates on critical nodes, input offset voltage can increase, especially with increasing chopping frequency. This problem has been significantly reduced in the TLC2652 by use of a patent-pending compensation circuit and the Advanced LinCMOS process. The TLC2652 incorporates a feed-forward design that ensures continuous frequency response. Essentially, the gain magnitude of the nulling amplifier and compensation network crosses unity at the break frequency of the main amplifier. As a result, the high-frequency response of the system is the same as the frequency response of the main amplifier. This approach also ensures that the slewing characteristics remain the same during both the nulling and amplifying phases. 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 23-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE LCCC FK 20 1 TBD Call TI 5962-9089501MCA ACTIVE CDIP J 14 1 TBD A42 5962-9089501MPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI 5962-9089503M2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI 5962-9089503MCA ACTIVE CDIP J 14 1 TBD Call TI Call TI 5962-9089503MPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI TLC2652AC-14D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AC-14DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AC-8D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AC-8DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AC-8DR OBSOLETE SOIC D 0 TLC2652ACN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652ACNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Call TI Call TI N / A for Pkg Type Call TI TLC2652ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652AI-14D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AI-14DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AI-8D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AI-8DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AI-8DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AI-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) Addendum-Page 1 Samples (Requires Login) 5962-9089501M2A TBD (3) CU NIPDAU N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 23-May-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) TLC2652AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type TLC2652AMJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type TLC2652AMJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type 1 TBD A42 N / A for Pkg Type TBD Call TI TLC2652AMJGB ACTIVE CDIP JG 8 TLC2652C-14D OBSOLETE SOIC D 14 TLC2652C-8D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652C-8DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652C-8DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652C-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Call TI TLC2652CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652I-8D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652I-8DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652I-8DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652I-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC2652M-8D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652M-8DG4 ACTIVE SOIC D 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 (3) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 23-May-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan TLC2652MFKB ACTIVE LCCC FK 20 1 TBD (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) POST-PLATE N / A for Pkg Type TLC2652MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type TLC2652MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type TLC2652Q-8D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2652Q-8DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF TLC2652, TLC2652A, TLC2652AM, TLC2652M : * Catalog: TLC2652A, TLC2652 Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 23-May-2012 * Military: TLC2652M, TLC2652AM NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC2652AI-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC2652C-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC2652I-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC2652AI-8DR SOIC D 8 2500 340.5 338.1 20.6 TLC2652C-8DR SOIC D 8 2500 340.5 338.1 20.6 TLC2652I-8DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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