SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DExtremely Low Offset Voltage ...1 µV Max
DExtremely Low Change on Offset Voltage
With Temperature . . . 0.003 µV/°C Typ
DLow Input Offset Current
500 pA Max at TA = − 55°C to 125°C
DAVD . . . 135 dB Min
DCMRR . . . 120 dB Min
DkSVR ...110 dB Min
DSingle-Supply Operation
DCommon-Mode Input Voltage Range
Includes the Negative Rail
DNo Noise Degradation With External
Capacitors Connected to VDD−
description
The TLC2652 and TLC2652A are high-precision
chopper-stabilized operational amplifiers using
Texas Instruments Advanced LinCMOS pro-
cess. This process, in conjunction with unique
chopper-stabilization circuitry, produces opera-
tional amplifiers whose performance matches or
exceeds that of similar devices available today.
Chopper-stabilization techniques make possible
extremely high dc precision by continuously
nulling input offset voltage even during variations
in temperature, time, common-mode voltage, and
power supply voltage. In addition, low-frequency
noise voltage is significantly reduced. This high
precision, coupled with the extremely high input
impedance of the CMOS input stage, makes the
TLC2652 and TLC2652A an ideal choice for
low-level signal processing applications such as
strain gauges, thermocouples, and other
transducer amplifiers. For applications that
require extremely low noise and higher usable
bandwidth, use the TLC2654 or TLC2654A
device, which has a chopping frequency of
10 kHz.
The TLC2652 and TLC2652A input common-mode range includes the negative rail, thereby providing superior
performance in either single-supply or split-supply applications, even at power supply voltage levels as low as
±1.9 V.
Two external capacitors are required for operation of the device; however, the on-chip chopper-control circuitry
is transparent to the user. On devices in the 14-pin and 20-pin packages, the control circuitry is made accessible
to allow the user the option of controlling the clock frequency with an external frequency source. In addition, the
clock threshold level of the TLC2652 and TLC2652A requires no level shifting when used in the single-supply
configuration with a normal CMOS or TTL clock input.
Copyright 1988−2005, Texas Instruments Incorporated
!"#$%" & '##% & "! (')*%" %+
#"'%& "!"#$ %" &(!%"& (# %, %#$& "! -& &%#'$%&
&%# .##%/+ #"'%" (#"&&0 "& "% &&#*/ *'
%&%0 "! ** (#$%#&+
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
1
2
3
4
8
7
6
5
CXB
VDD+
OUT
CLAMP
D008, JG, OR P PACKAGE
NC − No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
INT/EXT
CLK IN
CLK OUT
VDD+
OUT
CLAMP
C RETURN
D014, J, OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
CLK OUT
NC
VDD+
NC
OUT
FK PACKAGE
(TOP VIEW)
INT/EXT
NC
CLAMP CLK IN
NC
NC
XA
V
C RETURN
XB
V
DD−
V
(TOP VIEW)
NC
NC
IN−
NC
IN+
CXB
CXA
NC
IN−
IN+
NC
VDD−
CXA
IN−
IN+
VDD−
(#"'%& "$(*% %" 121 ** (#$%#& # %&%
'*&& "%,#.& "%+ ** "%,# (#"'%& (#"'%"
(#"&&0 "& "% &&#*/ *' %&%0 "! ** (#$%#&+
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload
recovery time. If desired, an output clamp pin is available to reduce the recovery time even further.
The device inputs and output are designed to withstand ±100-mA surge currents without sustaining latch-up.
Additionally the TLC2652 and TLC2652A incorporate internal ESD-protection circuits that prevent functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be
exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric
performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The Q-suffix devices are characterized for operation from −40°C to125°C.
The M-suffix devices are characterized for operation over the full military temperature range of −55°C to125°C.
AVAILABLE OPTIONS(1)
PACKAGED DEVICES
VIOmax
8 PIN 14 PIN 20 PIN CHIP
FORM
TA
VIOmax
AT 25°CSMALL
OUTLINE
(D008)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
SMALL
OUTLINE
(D014)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
CHIP
CARRIER
(FK)
CHIP
FORM
(Y)
0
°
C
1 µV
TLC2652AC-8D
—
TLC2652ACP
TLC2652AC-14D
—
TLC2652ACN
—
0 C
to
70 C
1 µV
3 µV
TLC2652AC-8D
TLC2652C-8D
—
—
TLC2652ACP
TLC2652CP
TLC2652AC-14D
TLC2652C-14D
—
—
TLC2652ACN
TLC2652CN
—
—
TLC2652Y
to
70°C
3
µ
V
TLC2652C-8D
—
TLC2652CP
TLC2652C-14D
—
TLC2652CN
—
TLC2652Y
−40
°
C
1 µV
TLC2652AI-8D
—
TLC2652AIP
TLC2652AI-14D
—
TLC2652AIN
—
−40 C
to
85 C
1 µV
3 µV
TLC2652AI-8D
TLC2652A-8D
—
—
TLC2652AIP
TLC2652IP
TLC2652AI-14D
TLC2652I-14D
—
—
TLC2652AIN
TLC2652IN
—
—
—
to
85°C
3
µ
V
TLC2652A-8D
—
TLC2652IP
TLC2652I-14D
—
TLC2652IN
—
—
−40
°
C
−40 C
to
125 C
3.5 µV TLC2652Q-8D — — — — — — —
to
125°C
3.5 µV
TLC2652Q-8D
—
—
—
—
—
—
—
−55°C
to
3 µV
TLC2652AM-8D
TLC2652AMJG
TLC2652AMP
TLC2652AM-14D
TLC2652AMJ
TLC2652AMN
TLC2652AMFK
—
to
125°C
3 µV
3.5 µV
TLC2652AM-8D
TLC2652M-8D
TLC2652AMJG
TLC2652MJG
TLC2652AMP
TLC2652MP
TLC2652AM-14D
TLC2652M-14D
TLC2652AMJ
TLC2652MJ
TLC2652AMN
TLC2652MN
TLC2652AMFK
TLC2652MFK —
The D008 and D014 packages are available taped and reeled. Add R suffix to the device type (e.g., TLC2652AC-8DR). Chips are tested at 25°C.
NOTE (1):For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
functional block diagram
Clamp
Circuit CLAMP
OUT
C RETURN
VDD−
Compensation-
Biasing
Circuit
VDD+
A
BBA
IN+
IN−
CXA CXB External Components
Null
Main
+
−
+
−
AB
DISTRIBUTION OF TLC2652
INPUT OFFSET VOLTAGE
Percentage of Units − %
V
IO
− Input Offset Voltage − µV
−3 −2 −1 0 1 2
3
0
4
8
12
16
20
24
28
32
36 150 Units Tested From 1 Wafer Lot
VDD± = ±5 V
TA = 25°C
N Package
CIC
5
4
2
36
7
8
Pin numbers shown are for the D (14 pin), JG, and N packages.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2652Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC2652C. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (7) IS INTERNALLY CONNECTED
TO BACK SIDE OF CHIP.
FOR THE PINOUT, SEE THE FUNCTIONAL
BLOCK DIAGRAM.
90
80
(13) (12) (11) (10) (9)
(8)
(1)
(7)(5)(4)
(2)
(14)
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage VDD+ (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage VDD− (see Note 1) −8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (any input, see Note 1) ±8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range on CLK IN and INT/EXT V
DD − to VDD− + 5.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (each input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into CLK IN and INT/EXT ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q suffix −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or P package 260°C. . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JG package 300°C. . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD−.
2. Differential voltages are at IN+ with respect to IN−.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA
≤
25
°
C
DERATING FACTOR
TA = 70
°
C
TA = 85
°
C
TA = 125
°
C
PACKAGE
TA ≤ 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70 C
POWER RATING
TA = 85 C
POWER RATING
TA = 125 C
POWER RATING
D008 725 mV 5.8 mW/°C464 mW 377 mW 145 mW
D014 950 mV 7.6 mW/°C 608 mW 494 mW 190 mW
FK 1375 mV 11.0 mW/°C 880 mW 715 mW 275 mW
J1375 mV 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mV 8.4 mW/°C 672 mW 546 mW 210 mW
N1575 mV 12.6 mW/°C 1008 mW 819 mW 315 mW
P1000 mV 8.0 mW/°C640 mW 520 mW 200 mW
recommended operating conditions
C SUFFIX I SUFFIX Q SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
Supply voltage, VDD±±1.9 ±8±1.9 ±8±1.9 ±8±1.9 ±8 V
Common-mode input voltage, VIC VDD− VDD+ −1.9 VDD− VDD+ −1.9 VDD− VDD+ −1.9 VDD− VDD+ −1.9 V
Clock input voltage VDD− VDD− +5 VDD− VDD− +5 VDD− VDD− +5 VDD− VDD− +5 V
Operating free-air temperature, TA0 70 −40 85 −40 125 −55 125 °C
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC2652C TLC2652AC
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 0.6 3 0.5 1
V
VIO Input offset voltage Full range 4.35 2.35 µV
VIO
Temperature coefficient of
Full range
0.003
0.03
0.003
0.03
V/°C
αVIO
Temperature coefficient of
input offset voltage Full range 0.003 0.03 0.003 0.03 µV/°C
Input offset voltage long-term
drift (see Note 4) VIC = 0, RS = 50 Ω25°C0.003 0.06 0.003 0.02 µV/mo
IIO
Input offset current
25°C 2 60 2 60
pA
IIO Input offset current Full range 100 100 pA
IIB
Input bias current
25°C 4 60 4 60
pA
IIB Input bias current Full range 100 100 pA
Common-mode input voltage
−5
−5
VICR
Common-mode input voltage
range
RS = 50
Ω
Full range
−5
to
−5
to
V
VICR
range
RS = 50 Ω
Full range
to
3.1
to
3.1
V
VOM+
Maximum positive peak
RL = 10 kΩ
See Note 5
25°C 4.7 4.8 4.7 4.8
V
VOM+
Maximum positive peak
output voltage swing RL = 10 kΩ, See Note 5 Full range 4.7 4.7 V
VOM−
Maximum negative peak
RL = 10 kΩ
See Note 5
25°C −4.7 −4.9 −4.7 −4.9
V
VOM−
Maximum negative peak
output voltage swing RL = 10 kΩ, See Note 5 Full range −4.7 −4.7 V
AVD
Large-signal differential
VO = ±4 V,
RL = 10 kΩ
25°C 120 150 135 150
dB
AVD
Large-signal differential
voltage amplification VO = ±4 V, RL = 10 kΩFull range 120 130 dB
fch Internal chopping frequency 25°C 450 450 Hz
Clamp on-state current
RL = 100 kΩ
25°C 25 25
A
Clamp on-state current RL = 100 kΩFull range 25 25 µA
Clamp off-state current
VO = −4 V to 4 V
25°C 100 100
pA
Clamp off-state current VO = −4 V to 4 V Full range 100 100 pA
CMRR
Common-mode rejection
VO = 0, VIC = VICRmin,
25°C 120 140 120 140
dB
CMRR
Common-mode rejection
ratio
VO = 0, VIC = VICRmin,
RS = 50 ΩFull range 120 120 dB
kSVR
Supply-voltage rejection ratio
VDD± = ±1.9 V to ±8 V, 25°C110 135 110 135
dB
kSVR
Supply-voltage rejection ratio
(∆VDD±/∆VIO)VO = 0, RS = 50 ΩFull range 110 110 dB
IDD
Supply current
25°C 1.5 2.4 1.5 2.4
mA
I
DD
Supply current
Full range 2.5 2.5
mA
†Full range is 0° to 70°C.
NOTES: 4. Typical values are based on the input of fset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics specified free-air temperature, VDD± = ±5 V
PARAMETER
TEST
TA†
TLC2652C TLC2652AC
UNIT
PARAMETER
TEST
CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
SR+
Positive slew rate at unity gain
V = 2.3 V,
25°C 2 2.8 2 2.8
V/ s
SR+ Positive slew rate at unity gain VO = ±2.3 V,
RL = 10 kΩ,
Full range 1.5 1.5 V/µs
SR−
Negative slew rate at unity gain
O
R
L
= 10 k
Ω
,
CL = 100 pF
25°C 2.3 3.1 2.3 3.1
V/ s
SR− Negative slew rate at unity gain
CL = 100 pF
Full range 1.8 1.8 V/µs
Vn
Equivalent input noise voltage
f = 10 Hz 25°C 94 94 140
nV/√Hz
Vn
Equivalent input noise voltage
(see Note 6) f = 1 kHz 25°C 23 23 35
nV/√Hz
VN(PP)
Peak-to-peak equivalent input
f = 0 to 1 Hz 25°C 0.8 0.8
V
VN(PP)
Peak-to-peak equivalent input
noise voltage f = 0 to 10 Hz 25°C 2.8 2.8 µV
InEquivalent input noise current f = 10 kHz 25°C 0.004 0.004 fA/√Hz
f = 10 kHz,
Gain-bandwidth product
f = 10 kHz,
R
L
= 10 kΩ,
25
°
C
1.9
1.9
MHz
Gain-bandwidth product
RL = 10 kΩ,
C
L
= 100 pF
25 C
1.9
1.9
MHz
φmPhase margin at unity gain RL = 10 kΩ,
CL = 100 pF 25°C 48°48°
†Full range is 0° to 70°C.
NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement
has no bearing on testing or nontesting of other parameters.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC2652I TLC2652AI
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 0.6 3 0.5 1
V
VIO Input offset voltage Full range 4.95 2.95 µV
VIO
Temperature coefficient of
Full range
0.003
0.03
0.003
0.03
V/°C
αVIO
Temperature coefficient of
input offset voltage Full range 0.003 0.03 0.003 0.03 µV/°C
Input offset voltage
long-term drift (see Note 4) VIC = 0, RS = 50 Ω25°C0.003 0.06 0.003 0.02 µV/mo
IIO
Input offset current
25°C 2 60 2 60
pA
IIO Input offset current Full range 150 150 pA
IIB
Input bias current
25°C 4 60 4 60
pA
IIB Input bias current Full range 150 150 pA
Common-mode input
−5
−5
VICR
Common-mode input
voltage range
RS = 50
Ω
Full range
−5
to
−5
to
V
VICR
voltage range
RS = 50 Ω
Full range
to
3.1
to
3.1
V
VOM+
Maximum positive peak
RL = 10 kΩ
See Note 5
25°C 4.7 4.8 4.7 4.8
V
VOM+
Maximum positive peak
output voltage swing RL = 10 kΩ, See Note 5 Full range 4.7 4.7 V
VOM−
Maximum negative peak
RL = 10 kΩ
See Note 5
25°C −4.7 −4.9 −4.7 −4.9
V
VOM−
Maximum negative peak
output voltage swing RL = 10 kΩ, See Note 5 Full range −4.7 −4.7 V
AVD
Large-signal differential
VO = ±4 V,
RL = 10 kΩ
25°C 120 150 135 150
dB
AVD
Large-signal differential
voltage amplification VO = ±4 V, RL = 10 kΩFull range 120 125 dB
Internal chopping frequency 25°C 450 450 Hz
Clamp on-state current
RL = 100 kΩ
25°C 25 25
A
Clamp on-state current RL = 100 kΩFull range 25 25 µA
Clamp off-state current
VO = −4 V to 4 V
25°C 100 100
pA
Clamp off-state current VO = −4 V to 4 V Full range 100 100 pA
CMRR
Common-mode rejection
VO = 0, VIC = VICRmin,
25°C 120 140 120 140
dB
CMRR
Common-mode rejection
ratio
VO = 0, VIC = VICRmin,
RS = 50 ΩFull range 120 120 dB
kSVR
Supply-voltage rejection
VDD± = ±1.9 V to ±8 V, 25°C110 135 110 135
dB
kSVR
Supply-voltage rejection
ratio (∆VDD±/∆VIO)VO = 0, RS = 50 ΩFull range 110 110 dB
IDD
Supply current
VO = 0,
No load
25°C 1.5 2.4 1.5 2.4
mA
I
DD
Supply current
V
O
= 0,
No load
Full range 2.5 2.5
mA
†Full range is −40° to 85°C.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER
TEST
TA†
TLC2652I TLC2652AI
UNIT
PARAMETER
TEST
CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
SR+
Positive slew rate at unity gain
V = 2.3 V,
25°C 2 2.8 2 2.8
V/ s
SR+ Positive slew rate at unity gain VO = ±2.3 V,
RL = 10 kΩ,
Full range 1.4 1.4 V/µs
SR−
Negative slew rate at unity gain
O
R
L
= 10 k
Ω
,
CL = 100 pF
25°C 2.3 3.1 2.3 3.1
V/ s
SR− Negative slew rate at unity gain
CL = 100 pF
Full range 1.7 1.7 V/µs
Vn
Equivalent input noise voltage
f = 10 Hz 25°C 94 94 140
nV/√Hz
Vn
Equivalent input noise voltage
(see Note 6) f = 1 kHz 25°C 23 23 35
nV/√Hz
VN(PP)
Peak-to-peak equivalent input
f = 0 to 1 Hz 25°C 0.8 0.8
V
VN(PP)
Peak-to-peak equivalent input
noise voltage f = 0 to 10 Hz 25°C 2.8 2.8 µV
InEquivalent input noise current f = 1 kHz 25°C 0.004 0.004 pA/√Hz
f = 10 kHz,
Gain-bandwidth product
f = 10 kHz,
R
L
= 10 kΩ,
25
°
C
1.9
1.9
MHz
Gain-bandwidth product
RL = 10 kΩ,
C
L
= 100 pF
25 C
1.9
1.9
MHz
φmPhase margin at unity gain RL = 10 kΩ,
CL = 100 pF 25°C 48°48°
†Full range is −40° to 85°C.
NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement
has no bearing on testing or nontesting of other parameters.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
†TLC2652Q
TLC2652M TLC2652AM
UNIT
PARAMETER
TEST CONDITIONS
TA†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 0.6 3.5 0.5 3
V
VIO
Input offset voltage
(see Note 7) Full range 10 8 µV
VIO
Temperature coefficient of
Full range
0.003
0.03∗
0.003
0.03∗
V/°C
αVIO
Temperature coefficient of
input offset voltage Full range 0.003 0.03∗0.003 0.03∗µV/°C
Input offset voltage
long-term drift (see Note 4) VIC = 0, RS = 50 Ω25°C0.003 0.06∗0.003 0.02∗µV/mo
IIO
Input offset current
25°C 2 60 2 60
pA
IIO Input offset current Full range 500 500 pA
IIB
Input bias current
25°C 4 60 4 60
pA
IIB Input bias current Full range 500 500 pA
Common-mode input
−5
−5
VICR
Common-mode input
voltage range
RS = 50
Ω
Full range
−5
to
−5
to
V
VICR
voltage range
RS = 50 Ω
Full range
to
3.1
to
3.1
V
VOM+
Maximum positive peak
RL = 10 kΩ
See Note 5
25°C 4.7 4.8 4.7 4.8
V
VOM+
Maximum positive peak
output voltage swing RL = 10 kΩ, See Note 5 Full range 4.7 4.7 V
VOM−
Maximum negative peak
RL = 10 kΩ
See Note 5
25°C −4.7 −4.9 −4.7 −4.9
V
VOM−
Maximum negative peak
output voltage swing RL = 10 kΩ, See Note 5 Full range −4.7 −4.7 V
AVD
Large-signal differential
VO = ±4 V,
RL = 10 kΩ
25°C 120 150 135 150
dB
AVD
Large-signal differential
voltage amplification VO = ±4 V, RL = 10 kΩFull range 120 120 dB
fch Internal chopping frequency 25°C 450 450 Hz
Clamp on-state current
VO = −5 V to 5 V
25°C 25 25
A
Clamp on-state current VO = −5 V to 5 V Full range 25 25 µA
Clamp off-state current
RL = 100 kΩ
25°C 100 100
pA
Clamp off-state current RL = 100 kΩFull range 500 500 pA
CMRR
Common-mode rejection
VO = 0, VIC = VICRmin,
25°C 120 140 120 140
dB
CMRR
Common-mode rejection
ratio
VO = 0, VIC = VICRmin,
RS = 50 ΩFull range 120 120 dB
kSVR
Supply-voltage rejection
VDD± = ±1.9 V to ±8 V, 25°C110 135 110 135
dB
kSVR
Supply-voltage rejection
ratio (∆VDD±/∆VIO)VO = 0, RS = 50 ΩFull range 110 110 dB
IDD
Supply current
VO = 0,
No load
25°C 1.5 2.4 1.5 2.4
mA
I
DD
Supply current
V
O
= 0,
No load
Full range 2.5 2.5
mA
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†Full range is −40° to 125°C for Q suffix, −55° to 125°C for M suffix.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.
7. This parameter is not production tested. Thermocouple effects preclude measurement of the actual VIO of these devices in high
speed automated testing. VIO is measured to a limit determined by the test equipment capability at the temperature extremes. The
test ensures that the stabilization circuitry is performing properly.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER TEST CONDITIONS TA†
TLC2652Q
TLC2652M
TLC2652AM UNIT
A
MIN TYP MAX
SR+
Positive slew rate at unity gain
V = 2.3 V,
25°C 2 2.8
V/ s
SR+ Positive slew rate at unity gain VO = ±2.3 V,
RL = 10 kΩ,
Full range 1.3 V/µs
SR−
Negative slew rate at unity gain
O
R
L
= 10 k
Ω
,
CL = 100 pF
25°C 2.3 3.1
V/ s
SR− Negative slew rate at unity gain
CL = 100 pF
Full range 1.6 V/µs
Vn
Equivalent input noise voltage
f = 10 Hz 25°C 94
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 25°C 23
nV/√Hz
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0 to 1 Hz 25°C 0.8
V
VN(PP) Peak-to-peak equivalent input noise voltage f = 0 to 10 Hz 25°C 2.8 µV
InEquivalent input noise current f = 1 kHz 25°C 0.004 pA/√Hz
Gain-bandwidth product f = 10 kHz,
RL = 10 kΩ,
CL = 100 pF 25°C 1.9 MHz
φmPhase margin at unity gain RL = 10 kΩ,
CL = 100 pF 25°C 48°
†Full range is −40° to 125°C for the Q suffix, −55° to 125°C for the M suffix.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at VDD± = ±5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC2652Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VIO Input offset voltage 0.6 3 µV
Input offset voltage long-term drift (see Note 4)
VIC = 0,
RS = 50 Ω
0.003 0.006 µV/mo
IIO Input offset current VIC = 0, RS = 50 Ω2 60 pA
IIB Input bias current 4 60 pA
−5
VICR
Common-mode input voltage range
RS = 50
Ω
−5
to
V
VICR
Common-mode input voltage range
RS = 50 Ω
to
3.1
V
VOM+ Maximum positive peak output voltage swing RL = 10 kΩ, See Note 5 4.7 4.8 V
VOM− Maximum negative peak output voltage swing RL = 10 kΩ, See Note 5 −4.7 −4.9 V
AVD Large-signal differential voltage amplification VO = ±4 V, RL = 10 kΩ120 150 dB
fch Internal chopping frequency 450 Hz
Clamp on-state current RL = 100 kΩ25 µA
Clamp off-state current VO = −4 V to 4 V 100 pA
CMRR Common-mode rejection ratio VO = 0,
RS = 50 ΩVIC = VICRmin, 120 140 dB
kSVR
Supply-voltage rejection ratio (∆VDD /∆VIO)
VDD± = ±1.9 V to ±8 V,
110
135
dB
kSVR Supply-voltage rejection ratio (∆VDD±/∆VIO)RS = 50 ΩVO = 0, 110 135 dB
IDD Supply current VO = 0, No load 1.5 2.4 mA
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.
operating characteristics at VDD± = ±5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC2652Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
SR+ Positive slew rate at unity gain
VO =
±
2.3 V,
RL = 10 k
Ω
,
2 2.8 V/µs
SR− Negative slew rate at unity gain
VO = ±2.3 V,
CL = 100 pF
RL = 10 kΩ,
2.3 3.1 V/µs
Vn
Equivalent input noise voltage
f = 10 Hz 94
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 23
nV/√Hz
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0 to 1 Hz 0.8
V
VN(PP) Peak-to-peak equivalent input noise voltage f = 0 to 10 Hz 2.8 µV
InEquivalent input noise current f = 1 kHz pA/√Hz
Gain-bandwidth product f = 10 kHz,
CL = 100 pF RL = 10 kΩ,1.9 MHz
φmPhase margin at unity gain RL = 10 kΩ, CL = 100 pF 48°
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Normalized input offset voltage vs Chopping frequency 1
vs Common-mode input voltage
2
IIB
Input bias current
vs Common-mode input voltage
vs Chopping frequency
2
3
IIB
Input bias current
vs Chopping frequency
vs Free-air temperature
3
4
IIO
Input offset current
vs Chopping frequency
5
IIO Input offset current
vs Chopping frequency
vs Free-air temperature
5
6
Clamp current vs Output voltage 7
V(OPP) Maximum peak-to-peak output voltage vs Frequency 8
VOM
Maximum peak output voltage
vs Output current
9, 10
VOM Maximum peak output voltage
vs Output current
vs Free-air temperature
9, 10
11, 12
AVD
Large-signal differential voltage amplification
vs Frequency
13
AVD Large-signal differential voltage amplification
vs Frequency
vs Free-air temperature
13
14
Chopping frequency
vs Supply voltage
15
Chopping frequency
vs Supply voltage
vs Free-air temperature
15
16
IDD
Supply current
vs Supply voltage
17
IDD Supply current
vs Supply voltage
vs Free-air temperature
17
18
IOS
Short-circuit output current
vs Supply voltage
19
IOS Short-circuit output current
vs Supply voltage
vs Free-air temperature
19
20
SR
Slew rate
vs Supply voltage
21
SR Slew rate
vs Supply voltage
vs Free-air temperature
21
22
Voltage-follower pulse response
Small-signal
23
Voltage-follower pulse response
Small-signal
Large-signal
23
24
VN(PP) Peak-to-peak equivalent input noise voltage vs Chopping frequency 25, 26
VnEquivalent input noise voltage vs Frequency 27
Gain-bandwidth product
vs Supply voltage
28
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
28
29
vs Supply voltage
30
φm
Phase margin
vs Supply voltage
vs Free-air temperature
30
31
φm
Phase margin
vs Free-air temperature
vs Load capacitance
31
32
Phase shift vs Frequency 13
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
NORMALIZED INPUT OFFSET VOLTAGE
vs
CHOPPING FREQUENCY
−10
0
10
20
30
40
50
60
70
100 1 k 10 k 100 k
Chopping Frequency − Hz
VDD± = ±5 V
VIC = 0
TA = 25°C
VIO − Normalized Input Offset − uV
V
IO Vµ
Figure 1
−5 VIC − Common-Mode Input Voltage − V
IIB − Input Bias Current − pA
10
5
001
15
20
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
25
2345
IIB
VDD± = ±5 V
TA = 25°C
−4 −3 −2 −1
Figure 2
Figure 3
Chopping Frequency − Hz
30
10
0
60
20
IIB − Input Bias Current − pA
50
40
70
INPUT BIAS CURRENT
vs
CHOPPING FREQUENCY
100 1 k 10 k 100 k
IB
I
VDD± = ±5 V
VIC = 0
TA = 25°C
TA − Free-Air Temperature − °C
1
100
25 45 65 105 125
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
85
10
VDD± = ±5 V
VO = 0
VIC = 0
IIB − Input Bias Current − pA
IB
I
Figure 4
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
INPUT OFFSET CURRENT
vs
CHOPPING FREQUENCY
Chopping Frequency − Hz
20
10
5
0
25
15
100 1 k 10 k 100 k
IIO − Input Offset Current − pA
IIO
VDD± = ±5 V
VIC = 0
TA = 25°C
Figure 5 Figure 6
IIO − Input Offset Current − pA
IIO
TA − Free-Air Temperature − °C
6
4
2
025 45 65 85
8
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
10
105 125
VDD± = ±5 V
VIC = 0
|VO| − Output Voltage − V
1 nA
100 pA
10 pA
1 pA 4 4.2 4.4 4.6
CLAMP CURRENT
vs
OUTPUT VOLTAGE
4.8 5
100 nA
10 nA
VDD± = ±5 V
TA = 25°C
Negative Clamp Current
100 µA
10 µA
1 µAPositive Clamp Current
|Clamp Current|
Figure 7
8
4
2
0
10
6
100 1 k 10 k 1 M
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
f − Frequency − Hz
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE
vs
FREQUENCY
VO(PP)
VDD± = ±5 V
RL = 10 kΩ
TA = 125°C
TA = −55°C
Figure 8
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 9
|IO| − Output Current − mA
4.6
4.4
4.2
40 0.4 0.8 1.2
4.8
MAXIMUM PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5
1.6 2
VDD± = ±5 V
TA = 25°C
VOM+ VOM−
|VOM| − Maximum Peak Output Voltage − V
|V
OM
Figure 10
|IO| − Output Current − mA
7.1
6.9
6.7 0 0.4 0.8 1.2
7.3
MAXIMUM PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
7.5
1.6 2
VDD± = ±7.5 V
TA = 25°C
VOM+ VOM−
|VOM| − Maximum Peak Output Voltage − V
|V
OM
Figure 11
TA − Free-Air Temperature − °C
0
−75 0 25 50
2.5
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
75 100 125
VDD± = ±5 V
RL = 10 kΩ
−2.5
VOM − Maximum Peak Output Voltage − V
V
OM
−5 −50 −25
Figure 12
VOM − Maximum Peak Output Voltage − V
0
4
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
8
TA − Free-Air Temperature − °C
−75 0 25 50 75 100 125
VDD± = ±7.5 V
RL = 10 kΩ
VOM
−50 −25
−8
−4
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
20
0
40
60
80
10 100 1 k 10 k 100 k
f − Frequency − Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
1 M 10 M
100
120
220°
200°
180°
160°
140°
120°
100°
80°
60°
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AVD
−20
−40
Phase Shift
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
Figure 13
Phase Shift
Figure 14
−50 −25
145
140
135
−75 0 25 50
150
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION
vs
FREE-AIR TEMPERATURE
155
75 100 125
TA − Free-Air Temperature − °C
VDD± = ±7.5 V
RL = 10 kΩ
VO = ±4 V
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 15
|VDD±| − Supply Voltage − V
480
460
440
420012345
500
520
CHOPPING FREQUENCY
vs
SUPPLY VOLTAGE
540
678
TA = 25°C
Chopping Frequency − kHz
Figure 16
−50 −25
TA − Free-Air Temperature − °C
430
420
410
400
−75 0 25 50
440
450
CHOPPING FREQUENCY
vs
FREE-AIR TEMPERATURE
460
75 100 125
VDD± = ±5 V
Chopping Frequency − kHz
Figure 17
|VDD ±| − Supply Voltage − V
IDD − Supply Current − mA
IDD
1.2
0.8
0.4
00235
1.6
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
2
78146
TA = 25°C
TA = −55°C
TA = 125°C
VO = 0
No Load
−50 −25
TA − Free-Air Temperature − °C
1.2
0.8
0.4
0
−75 0 50
1.6
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
2
100 125
25 75
VDD± = ±5 V
VDD± = ±7.5 V
VDD± = ±2.5 V
VO = 0
No Load
IDD − Supply Current − mA
IDD
Figure 18
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 19
−4
0
−12012345
IOS − Short-Circuit Output Current − mA
4
8
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
12
678
|VDD ±| − Supply Voltage − V
IOS
VO = 0
TA = 25°C
−8
VID = −100 mV
VID = 100 mV
Figure 20
−50 −25
0
−10
−15
−75 0 25 50
5
10
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
15
75 100 125
TA − Free-Air Temperature − °C
VID = 100 mV
VID = −100 mV
VDD± = ±5 V
VO = 0
IOS − Short-Circuit Output Current − mA
IOS
−5
Figure 21
2
1
0012 3 45
3
4
678
|VDD±| − Supply Voltage − V
SLEW RATE
vs
SUPPLY VOLTAGE
RL = 10 kΩ
CL = 100 pF
TA = 25°C
SR−
SR+
SR − Slew Rate − V?us
sµ
V/
Figure 22
−50 −25
2
1
0
−75 0 25 50
SR − Slew Rate − V?us
3
SLEW RATE
vs
FREE-AIR TEMPERATURE
4
75 100 125
TA − Free-Air Temperature − °C
sµ
V/
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
SR+
SR−
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 23
−25
t − Time − µs
VO − Output Voltage − mV
0
−75
−100 0123
25
75
VOLTAGE-FOLLOWER
SMALL-SIGNAL
PULSE RESPONSE
100
4567
50
VO
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
−50
Figure 24
t − Time − µs
VO − Output Voltage − V
VO
0
−1
−3
−4 0 5 10 15 20
1
3
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
4
25 30 35 40
−2
2
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
Figure 25
fch − Chopping Frequency − kHz
PEAK-TO-PEAK INPUT NOISE VOLTAGE
vs
CHOPPING FREQUENCY
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0246810
VN(PP) − Peak-to-Peak Input Noise Voltage −uV
N(PP)
V
VDD± = ±5 V
RS = 20 Ω
f = 0 to 1 Hz
TA = 25°C
µV
Figure 26
fch − Chopping Frequency − kHz
3
2
1
00246
VN(PP) − Peak-to-Peak Input Noise Voltage − uV
4
PEAK-TO-PEAK INPUT NOISE VOLTAGE
vs
CHOPPING FREQUENCY
5
810
N(PP)
V
VDD± = ±5 V
RS = 20 Ω
f = 0 to 10 Hz
TA = 25°C
µV
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Vn − Equivalent Input Noise Voltage − nV/Hz
80
40
20
0
100
60
1 10 100 1 k
f − Frequency − Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
Vn
VDD± = ±5 V
RS = 20 Ω
TA = 25°C
nV/ Hz
Figure 27 Figure 28
|VCC±| − Supply Voltage − V
1.9
1.8012345
Gain-Bandwidth Product − MHz
2
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
2.1
678
RL = 10 kΩ
CL = 100 pF
TA = 25°C
Figure 29
−50
TA − Free-Air Temperature − °C
2
1.8
1.4
1.2
−75 0 25 50
Gain-Bandwidth Product − MHz
2.2
2.4
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
2.6
75 100 125
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
−25
Figure 30
|VCC±| − Supply Voltage − V
om − Phase Margin
0235
PHASE MARGIN
vs
SUPPLY VOLTAGE
78146
RL = 10 kΩ
CL = 100 pF
TA = 25°C
φm
50°
48°
46°
44°
42°
40°
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 31
−50 −25
50°
48°
46°
44°
42°
40°
TA − Free-Air Temperature − °C
−75 0 50
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
100 12525 75
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
om − Phase Margin
φm
Figure 32
0 200 400 600
PHASE MARGIN
vs
LOAD CAPACITANCE
800 1000
VDD± = ±5 V
RL = 10 kΩ
TA = 25°C
CL − Load Capacitance − pF
om − Phase Margin
φm
60°
50°
40°
30°
20°
10°
0°
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
APPLICATION INFORMATION
capacitor selection and placement
The two important factors to consider when selecting external capacitors CXA and CXB are leakage and
dielectric absorption. Both factors can cause system degradation, negating the performance advantages
realized by using the TLC2652.
Degradation from capacitor leakage becomes more apparent with the increasing temperatures. Low-leakage
capacitors and standoffs are recommended for operation at TA = 125°C. In addition, guard bands are
recommended around the capacitor connections on both sides of the printed circuit board to alleviate problems
caused by surface leakage on circuit boards.
Capacitors with high dielectric absorption tend to take several seconds to settle upon application of power, which
directly affects input offset voltage. In applications where fast settling of input offset voltage is needed, it is
recommended that high-quality film capacitors, such as mylar, polystyrene, or polypropylene, be used. In other
applications, however, a ceramic or other low-grade capacitor can suffice.
Unlike many choppers available today, the TLC2652 is designed to function with values of CXA and CXB in the
range of 0.1 µF to 1 µF without degradation to input offset voltage or input noise voltage. These capacitors
should be located as close as possible to the CXA and CXB pins and returned to either VDD− or C RETURN. On
many choppers, connecting these capacitors to VDD− causes degradation in noise performance. This problem
is eliminated on the TLC2652.
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
internal/external clock
The TLC2652 has an internal clock that sets the chopping frequency to a nominal value of 450 Hz. On 8-pin
packages, the chopping frequency can only be controlled by the internal clock; however, on all 14-pin packages
and the 20-pin FK package, the device chopping frequency can be set by the internal clock or controlled
externally by use of the INT/EXT and CLK IN pins. To use the internal 450-Hz clock, no connection is necessary.
If external clocking is desired, connect INT/EXT to VDD− and the external clock to CLK IN. The external clock
trip point is 2.5 V above the negative rail; however, CLK IN can be driven from the negative rail to 5 V above
the negative rail. If this level is exceeded, damage could occur to the device unless the current into CLK IN is
limited t o ±5 mA. When operating in the single-supply configuration, this feature allows the TLC2652 to be driven
directly by 5-V TTL and CMOS logic. A divide-by-
two frequency divider interfaces with CLK IN and
sets the clock chopping frequency. The duty cycle
of the external clock is not critical but should be
kept between 30% and 60%.
overload recovery/output clamp
When large differential input voltage conditions
are applied to the TLC2652, the nulling loop
attempts to prevent the output from saturating by
driving C XA and CXB to internally-clamped voltage
levels. Once the overdrive condition is removed,
a period of time is required to allow the built-up
charge to dissipate. This time period is defined as
overload recovery time (see Figure 33). Typical
overload recovery time for the TLC2652 is
significantly faster than competitive products;
however, if required, this time can be reduced
further by use of internal clamp circuitry
accessible through CLAMP if required.
The clamp is a switch that is automatically activated when the output is approximately 1 V from either supply
rail. When connected to the inverting input (in parallel with the closed-loop feedback resistor), the closed-loop
gain is reduced, and the TLC2652 output is prevented from going into saturation. Since the output must source
or sink current through the switch (see Figure 7), the maximum output voltage swing is slightly reduced.
thermoelectric effects
To take advantage of the extremely low offset voltage drift of the TLC2652, care must be taken to compensate
for the thermoelectric effects present when two dissimilar metals are brought into contact with each other (such
as device leads being soldered to a printed circuit board). Dissimilar metal junctions can produce thermoelectric
voltages in the range of several microvolts per degree Celsius (orders of magnitude greater than the 0.01-µV/°C
typical of the TLC2652).
To help minimize thermoelectric effects, careful attention should be paid to component selection and
circuit-board layout. Avoid the use of nonsoldered connections (such as sockets, relays, switches, etc.) in the
input signal path. Cancel thermoelectric e ffects by duplicating the number of components and junctions in each
device input. The use of low-thermoelectric-coefficient components, such as wire-wound resistors, is also
beneficial.
0
0 10203040
VI − Input Voltage − mV VO − Output Voltage − V
t − Time − ms
0
50 60 70 80
VIVO
VDD± = ±5 V
TA = 25°C
Figure 33. Overload Recovery
−5
−50
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
latch-up avoidance
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs
and output are designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques
to reduce the chance of latch-up should be used whenever possible. Internal protection diodes should not, by
design, be forward biased. Applied input and output voltages should not exceed the supply voltage by more than
300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients
should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close
to the device as possible.
The current path established if latch-up occurs is usually between the supply rails and is limited only by the
impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up
occurring increases with increasing temperature and supply voltage.
electrostatic discharge protection
The TLC2652 incorporates internal ESD-protection circuits that prevent functional failures at voltages at or
below 2000 V. Care should be exercised in handling these devices, as exposure to ESD may result in
degradation of the device parametric performance.
theory of operation
Chopper-stabilized operational amplifiers offer the best dc performance of any monolithic operational amplifier.
This superior performance is the result of using two operational amplifiers, a main amplifier and a nulling
amplifier, plus oscillator-controlled logic and two external capacitors to create a system that behaves as a single
amplifier. With this approach, the TLC2652 achieves submicrovolt input offset voltage, submicrovolt noise
voltage, and offset voltage variations with temperature in the nV/°C range.
The TLC2652 on-chip control logic produces two dominant clock phases: a nulling phase and an amplifying
phase. The term chopper-stabilized derives from the process of switching between these two clock phases.
Figure 34 shows a simplified block diagram of the TLC2652. Switches A and B are make-before-break types.
During the nulling phase, switch A is closed shorting the nulling amplifier inputs together and allowing the nulling
amplifier to reduce its own input offset voltage by feeding its output signal back to an inverting input node.
Simultaneously, external capacitor CXA stores the nulling potential to allow the of fset voltage of the amplifier to
remain nulled during the amplifying phase.
Null
Amplifier
IN+
IN−
Main Amplifier
VO
VDD−
CXA
CXB
B
A
B
A
+
+
−
−
Figure 34. TLC2652 Simplified Block Diagram
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUAR Y 2005
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
theory of operation (continued)
During the amplifying phase, switch B is closed connecting the output of the nulling amplifier to a noninverting
input of the main amplifier. In this configuration, the input offset voltage of the main amplifier is nulled. Also,
external capacitor CXB stores the nulling potential to allow the offset voltage of the main amplifier to remain
nulled during the next nulling phase.
This continuous chopping process allows offset voltage nulling during variations in time and temperature over
the common-mode input voltage range and power supply range. In addition, because the low-frequency signal
path is through both the null and main amplifiers, extremely high gain is achieved.
The low-frequency noise of a chopper amplifier depends on the magnitude of the component noise prior to
chopping and the capability of the circuit to reduce this noise while chopping. The use of the Advanced LinCMOS
process, with its low-noise analog MOS transistors and patent-pending input stage design, significantly reduces
the input noise voltage.
The primary source of nonideal operation in chopper-stabilized amplifiers is error charge from the switches. As
charge imbalance accumulates on critical nodes, input offset voltage can increase, especially with increasing
chopping frequency. This problem has been significantly reduced in the TLC2652 by use of a patent-pending
compensation circuit and the Advanced LinCMOS process.
The TLC2652 incorporates a feed-forward design that ensures continuous frequency response. Essentially, th e
gain magnitude of the nulling amplifier and compensation network crosses unity at the break frequency of the
main amplifier. As a result, the high-frequency response of the system is the same as the frequency response
of the main amplifier. This approach also ensures that the slewing characteristics remain the same during both
the nulling and amplifying phases.
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9089501M2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9089501MCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
5962-9089501MPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI
5962-9089503M2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9089503MCA ACTIVE CDIP J 14 1 TBD Call TI Call TI
5962-9089503MPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI
TLC2652AC-14D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AC-14DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AC-8D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AC-8DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AC-8DR OBSOLETE SOIC D 0 TBD Call TI Call TI
TLC2652ACN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652ACNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652AI-14D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AI-14DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AI-8D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AI-8DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AI-8DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AI-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC2652AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLC2652AMJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
TLC2652AMJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLC2652AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLC2652C-14D OBSOLETE SOIC D 14 TBD Call TI Call TI
TLC2652C-8D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652C-8DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652C-8DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652C-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652I-8D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652I-8DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652I-8DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652I-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC2652M-8D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652M-8DG4 ACTIVE SOIC D 8 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC2652MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLC2652MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLC2652MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLC2652Q-8D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2652Q-8DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2652, TLC2652A, TLC2652AM, TLC2652M :
•Catalog: TLC2652A, TLC2652
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC2652AI-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC2652C-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC2652I-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC2652AI-8DR SOIC D 8 2500 340.5 338.1 20.6
TLC2652C-8DR SOIC D 8 2500 340.5 338.1 20.6
TLC2652I-8DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2010
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
