19-1641; Rev 2; 11/04 Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 Features 8-Bit Accuracy in a Miniature 5-Pin SOT23 Wide +2.7V to +5.5V Supply Range (MAX5382) Low 230A max Supply Current 1A Shutdown Mode Buffered Output Drives Resistive Loads Low-Glitch Power-On Reset to Zero DAC Output Fast I2C-Compatible Serial Interface <5% Full-Scale Error (MAX5382) <1LSB max INL/DNL Ordering Information PART MAX5380_EUK-T MAX5381_EUK-T MAX5382_EUK-T TEMP RANGE -40C to +85C -40C to +85C -40C to +85C Selector Guide Applications Automatic Tuning (VCO) Power-Amplifier Bias Control Programmable Threshold Levels Automatic Gain Control Automatic Offset Adjustment Typical Operating Circuit +2.7V TO +5.5V VDD C VDD PX.0/SDA SDA PX.1/SCL SCL GND MAX5382 GND PART ADDRESS REFERENCE (V) TOP MARK MAX5380LEUK MAX5380MEUK MAX5380NEUK MAX5380PEUK MAX5381LEUK MAX5381MEUK MAX5381NEUK MAX5381PEUK MAX5382LEUK MAX5382MEUK MAX5382NEUK MAX5382PEUK 0x60 0x62 0x64 0x66 0x60 0x62 0x64 0x66 0x60 0x62 0x64 0x66 +2.0 +2.0 +2.0 +2.0 +4.0 +4.0 +4.0 +4.0 0.9 x VDD 0.9 x VDD 0.9 x VDD 0.9 x VDD ADMN ADMZ ADNF ADMP ADMV ADNB ADNH ADMR ADMX ADND ADNJ ADMT Pin Configuration OUT TOP VIEW OUT Ps, Ia line I2s. PIN-PACKAGE 5 SOT23 5 SOT23 5 SOT23 1 GND 2 5 SCL 4 SDA MAX5380 MAX5381 MAX5382 VDD 3 SOT23-5 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5380/MAX5381/MAX5382 General Description The MAX5380/MAX5381/MAX5382 are low-cost, 8-bit digital-to-analog converters (DACs) in miniature 5-pin SOT23 packages, with a simple 2-wire serial interface that allows communication with multiple devices. The MAX5380 has an internal +2V reference and operates from a +2.7V to +3.6V supply. The MAX5381 has an internal +4V reference and operates from a +4.5V to +5.5V supply. The MAX5382 operates over the full +2.7V to +5.5V supply range and has an internal reference equal to 0.9 x VDD. The fast-mode I2C*-compatible serial interface allows communication at data rates up to 400kbps, minimizing board space and reducing interconnect complexity in many applications. Each device is available with one of four factory-preset addresses (see Selector Guide). These DACs also include an output buffer, a low-power shutdown mode, and a power-on reset that ensures the DAC outputs are at zero when power is initially applied. In shutdown mode, supply current is reduced to less than 1A and the output is pulled down to GND with a 10k resistor. MAX5380/MAX5381/MAX5382 Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUT, SCL, SDA to GND ...........................................-0.3V to +6V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 5-Pin SOT23 (derate 7.1mW/C above +70C).............571mW Operating Temperature Ranges MAX538_ _EUK-T .............................................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k; CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 LSB 1 LSB 25 mV STATIC ACCURACY Resolution 8 Integral Linearity Error INL (Note 1) Differential Linearity Error DNL Guaranteed monotonic Offset Error (Note 2) Offset Error Supply Rejection MAX5382 (Notes 2, 3) Offset Error Temperature Coefficient (Note 2) Full-Scale Error Code = 255 Full-Scale Error Supply Rejection Code = 255, MAX5380/MAX5281 (Note 4) Full-Scale Error Temperature Coefficient Code = 255 Bits 1 60 dB MAX5380/MAX5381 3 MAX5382 1 ppm/C MAX5380/MAX5381 10 MAX5382 5 % of ideal FS 50 dB MAX5380/MAX5381 40 MAX5382 10 ppm/C DAC OUTPUT MAX5380 Internal Reference (Note 5) REF 1.8 2 2.2 MAX5381 3.6 4 4.4 MAX5382 0.85 x VDD 0.9 x VDD 0.95 x VDD V Code = 255, 0 to 100A 0.5 Code = 0, 0 to 100A 0.5 VOUT = 0 to VDD, power-down mode 10 k Voltage Output Slew Rate Positive and negative 0.4 V/s Output Settling Time To 1/2 LSB, 50k and 50pF load (Note 6) 20 s Digital Feedthrough Code = 0, all digital inputs from 0 to VDD 2 nVs Digital-Analog Glitch Impulse Code 127 to 128 40 nVs Wake-Up Time From software shutdown 50 s Output Load Regulation Output Resistance LSB DYNAMIC PERFORMANCE 2 _______________________________________________________________________________________ Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 (VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k; CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Supply Voltage VDD Supply Current IDD MAX5380 2.7 3.6 MAX5381 4.5 5.5 MAX5382 2.7 5.5 No load, all digital inputs at 0 or VDD, code = 255 150 230 Shutdown mode 1 V A DIGITAL INPUTS (SCL, SDA) Input Low Voltage VIL Input High Voltage VIH Input Hysteresis 0.3 x VDD 0.7 x VDD VHYS Input Capacitance CIN Input Leakage Current IIN Pulse Width of Spike Suppressed tSP V 0.05 x VDD (Note 7) V V 10 0 pF 10 A 50 ns DIGITAL OUTPUT (SDA, open drain) Output Low Voltage VOL Output Fall Time tOF ISINK = 3mA 0.4 ISINK = 6mA 0.6 VIH(MIN) to VIL(MAX), bus capacitance = 10pF to 400pF ISINK = 3mA 250 ISINK = 6mA 250 V ns TIMING CHARACTERISTICS (Figure 3; VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k; CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) (Note 7) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz SCL Clock Frequency fSCL 0 Bus Free Time Between a STOP and a START Condition tBUF 1.3 s tHD:STA 0.6 s Low Period of the SCL Clock tLOW 1.3 s High Period of the SCL Clock tHIGH 0.6 s Setup Time for a Repeated START Condition tSU:STA 0.6 s Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 Hold Time Repeated for a START Condition 0.9 s ns _______________________________________________________________________________________ 3 MAX5380/MAX5381/MAX5382 ELECTRICAL CHARACTERISTICS (continued) TIMING CHARACTERISTICS (continued) (Figure 3; VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k; CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) (Note 7) PARAMETER Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals SYMBOL Setup Time for STOP Condition Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: CONDITIONS MIN MAX UNITS tr 300 ns tf 300 ns tSU:STO Capacitive Load for Each Bus Line TYP 0.6 s Cb 400 pF Guaranteed from code 5 to code 255. The offset value extrapolated from the range over which the INL is guaranteed. MAX5382 tested at VDD = +5V 10%. MAX5380 tested at VDD = +3V 10%, MAX5381 tested at VDD = 5V 10%. Actual output voltages at full scale are 255/256 x VREF. Output settling time is measured by taking the code from code 5 to 255, and from code 255 to 5. Guaranteed by design. Typical Operating Characteristics (VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k, TA = +25C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE 0.050 0 MAX5380/1/2-02 0 MAX5380/1/2-01 0.075 INTEGRAL NONLINEARITY vs. TEMPERATURE -0.05 INL (LSB) 0 -0.025 INL (LSB) -0.05 0.025 MAX5380/1/2-03 INTEGRAL NONLINEARITY vs. CODE INL (LSB) MAX5380/MAX5381/MAX5382 Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 -0.10 -0.10 -0.050 -0.15 -0.15 -0.075 -0.100 -0.20 -0.20 0 50 100 150 CODE 4 200 250 300 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 -40 -20 0 20 40 60 TEMPERATURE (C) _______________________________________________________________________________________ 80 100 Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE -0.02 -0.02 -0.04 -0.02 DNL (LSB) DNL (LSB) 0 0 MAX5380/1/2-05 0.02 DNL (LSB) 0 MAX5380/1/2-04 0.04 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE -0.06 MAX5380/1/2-06 DIFFERENTIAL NONLINEARITY vs. CODE -0.04 -0.06 -0.04 -0.08 -0.06 -0.08 -0.10 -0.08 50 100 150 200 250 -0.10 2.5 300 3.0 4.0 4.5 5.0 5.5 -40 -20 SUPPLY VOLTAGE (V) CODE TOTAL UNADJUSTED ERROR vs. CODE -0.5 0 -0.15 -0.30 40 60 80 0 100 -0.5 OFFSET ERROR (mV) VOS (mV) 0.15 20 OFFSET ERROR vs. TEMPERATURE OFFSET ERROR vs. SUPPLY VOLTAGE MAX5380/1/2-08 0.30 0 TEMPERATURE (C) 0 MAX5380/1/2-07 0.45 TUE (LSB) 3.5 MAX5380/1/2-09 0 -1.0 -1.5 -1.0 -1.5 -0.45 -2.0 100 150 200 250 -2.0 2.5 300 3.0 FULL-SCALE ERROR vs. SUPPLY VOLTAGE MAX5380/1/2-10 MAX5381 5.0 5.5 3 0.8 2 0.4 0 0 -0.4 -1 -2 FULL-SCALE ERROR (%) MAX5382 0 20 40 60 80 MAX5380/1/2-11 SUPPLY CURRENT vs. SUPPLY VOLTAGE 200 1.2 0.8 MAX5380 MAX5381 1 100 0.4 0 0 MAX5382 -1 -0.4 -0.8 -2 -0.8 -1.2 5.5 -3 -1.2 100 MAX5381 160 MAX5380 140 120 MAX5382 100 80 60 40 20 -3 3.0 -20 TEMPERATURE (C) NO LOAD 2.5 -40 180 MAX5380 1 4.5 FULL-SCALE ERROR vs. TEMPERATURE 1.2 FULL-SCALE ERROR (LSB) FULL-SCALE ERROR (LSB) 2 4.0 SUPPLY VOLTAGE (V) CODE 3 3.5 SUPPLY CURRENT (A) 50 FULL-SCALE ERROR (%) 0 MAX5380/1/2-12 -0.60 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 MAX5380/MAX5381/MAX5382 Typical Operating Characteristics (continued) (VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k, TA = +25C, unless otherwise noted.) SUPPLY CURRENT vs. CODE SUPPLY CURRENT vs. TEMPERATURE 155 MAX5381, VDD = +5.0V SUPPLY CURRENT (A) MAX5381 150 MAX5382 145 MAX5380 140 MAX5380/1/2-14 NO LOAD 155 SUPPLY CURRENT (A) 160 MAX5380/1/2-13 160 150 MAX5382, VDD = +5.0V 145 MAX5380, VDD = +5.0V MAX5380, VDD = +3.0V 140 135 135 NO LOAD 130 130 -40 -20 0 20 40 60 80 0 100 32 64 96 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX5380/1/2-16 1.0 MAX5380/1/2-15 0.8 SUPPLY CURRENT (A) 0.8 0.6 0.4 0.2 0.6 VDD = +5.0V 0.4 VDD = +3.0V 0.2 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 SUPPLY VOLTAGE (V) -20 0 20 40 60 80 100 TEMPERATURE (C) OUTPUT LOAD REGULATION OUTPUT VOLTAGE ON POWER-UP MAX5380/1/2-17 MAX5380/1/2-18 4.5 A 4.0 3.5 OUT 50mV/div 3.0 2.5 C 0.2 D E 0.1 0 0 1 2 3 4 5 6 7 8 9 VOUT ZERO CODE (V) B 2.0 1.5 10 VDD 2V/div 4s/div LOAD CURRENT (mA) A: MAX5361/MAX5362, VDD = 4.5V FULL-SCALE OR SOURCING B: MAX5360, FULL-SCALE, VDD = 2.7V SINKING, VDD = 5.0V SOURCING C: MAX5360, FULL-SCALE, VDD = 2.7V SOURCING D: ZERO CODE, VDD = 2.7V SINKING E: ZERO CODE, VDD = 5.5V SINKING 6 256 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 1.0 SUPPLY CURRENT (A) 128 160 192 224 CODE TEMPERATURE (C) VOUT FULL SCALE (V) MAX5380/MAX5381/MAX5382 Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 _______________________________________________________________________________________ Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 OUTPUT VOLTAGE EXITING SHUTDOWN OUTPUT SETTLING FROM 1/4 FS TO 3/4 FS MAX5380/1/2-21 MAX5380/1/2-20 MAX5380/1/2-19 OUTPUT VOLTAGE ENTERING SHUTDOWN OUT 500mV/div OUT 500mV/div OUT 0.5V/div SDA 3V/div SDA 3V/div SDA 3V/div 10s/div 1s/div 1s/div MAX5380, SHDN TO 0x80 MAX5380 MAX5380, 0x80 TO SHDN OUTPUT SETTLING 1LSB STEP UP OUTPUT SETTLING 1LSB STEP DOWN MAX5380/1/2-24 MAX5380/1/2-22 MAX5380/1/2-23 OUTPUT SETTLING FROM 3/4 FS TO 1/4 FS OUT 0.5V/div OUT 20mV/div AC-COUPLED OUT 20mV/div AC-COUPLED SDA 3V/div SDA 3V/div SDA 3V/div 1s/div 2s/div MAX5380, 0x7F TO 0x80 MAX5380 2s/div MAX5380, 0x80 TO 0x7F Pin Description PIN NAME 1 OUT DAC Voltage Output 2 GND Ground 3 VDD Power-Supply Input 4 SDA Serial Data Input 5 SCL Serial Clock Input FUNCTION _______________________________________________________________________________________ 7 MAX5380/MAX5381/MAX5382 Typical Operating Characteristics (continued) (VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k, TA = +25C, unless otherwise noted.) MAX5380/MAX5381/MAX5382 Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 VDD VREF REF CURRENTSTEERING DAC OUT SW1 SW2 SW255 255 SDA SCL CONTROL LOGIC DATA LATCH 8 SERIAL INPUT REGISTER MAX5380 MAX5381 MAX5382 10k OUT GND Figure 1. Functional Diagram Figure 2. Current-Steering Topology Table 1. Unipolar Code Output Voltage OUTPUT VOLTAGE DAC CODE MAX5380 MAX5381 MAX5382 1111 1111 2V x (255 / 256) 4V x (255 / 256) 0.9 x VDD x (255 / 256) 1000 0000 +1V +2V 0.9 x VDD / 2 0000 0001 7.8mV 15.6mV 0.9 x VDD / 256 0000 0000 0 0 0 Detailed Description The MAX5380/MAX5381/MAX5382 voltage-output, 8-bit digital-to-analog converters (DACs) offer full 8-bit performance with less than 1LSB integral nonlinearity error and less than 1LSB differential nonlinearity error, ensuring monotonic performance. The devices use a simple 2-wire, fast-mode I2C-compatible serial interface that operates at up to 400kHz. The MAX5380/MAX5381/ MAX5382 include an internal reference, an output buffer, and a low-current shutdown mode, which make these devices ideal for low-power, highly integrated applications (See Figure 1. Functional Diagram). Analog Section The MAX5380/MAX5381/MAX5382 employ a currentsteering DAC topology as shown in Figure 2. At the core of the DAC is a reference voltage-to-current converter (V/I) that generates a reference current. This current is mirrored to 255 equally weighted current sources. DAC switches control the outputs of these current mirrors so that only the desired fraction of the total current-mirror 8 currents is steered to the DAC output. The current is then converted to a voltage across a resistor, and this voltage is buffered by the output buffer amplifier. Output Voltage Table 1 shows the relationship between the DAC code and the analog output voltage. The 8-bit DAC code is binary unipolar with 1LSB = VREF / 256. The MAX5380/ MAX5381 have a full-scale output voltage of (+2V 1LSB) and (+4V - 1LSB), respectively, set by the internal references. The MAX5382 has a full-scale output voltage of (0.9 x VDD - 1LSB). Output Buffer The DAC voltage output is an internally buffered unitygain follower that typically slews at 0.4V/s. The output can swing from 0 to full scale. With a 1/4 FS to 3/4 FS output transition, the amplifier outputs typically settle to 1/2LSB in less than 5s when loaded with 10k in parallel with 50pF. The buffer amplifiers are stable with any combination of resistive loads >10k and capacitive loads <50pF. _______________________________________________________________________________________ Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 tSU: DAT tBUF tSU: STA tHD: STA tLOW tSU: STO tHD: DAT SCL tHIGH tHD: STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 3. 2-Wire Serial Interface Timing Diagram after a loss of power. The output glitch at startup is typically less than 50mV. VDD C SDA SCL SCL RS* VDD MAX5380M 2V REFERENCE SDA OUT OFFSET ADJUSTMENT Shutdown Mode The MAX5380/MAX5381/MAX5382 include a softwarecontrolled shutdown mode that reduces the supply current to <1A. All internal circuitry is disabled, and an internal 10k resistor is placed from OUT to GND to ensure 0V at OUT while in shutdown. The device enters shutdown in less than 5s and exits shutdown in less than 50s. VDD Digital Section MAX5381N 4V REFERENCE SDA OUT Serial Interface The MAX5380/MAX5381/MAX5382 use a simple 2-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocessor (P) port. Figure 3 shows the timing diagram for signals on the 2-wire bus. SCL SCL THRESHOLD ADJUSTMENT VDD MAX5382P VDD REFERENCE SDA OUT GAIN ADJUSTMENT *RS IS OPTIONAL. Figure 4. Typical Application Circuit Power-On Reset The MAX5380/MAX5381/MAX5382 have a power-on reset circuit to set the DAC's output to 0 when VDD is first applied or when VDD dips below 1.7V (typ). This ensures that unwanted DAC output voltages will not occur immediately following a system startup, such as The two bus lines (SDA and SCL) must be high when the bus is not in use. The MAX5380/MAX5381/ MAX5382 are receive-only devices (slaves) and must be controlled by a bus master device. Figure 4 shows a typical application where up to four devices can be connected to the bus, provided they have different address settings. External pull-up resistors are not necessary on these lines (when driven by push-pull drivers), though these DACs can be used in applications where pull-up resistors are required (such as in I2C systems) to maintain compatibility with existing circuitry. The serial interface operates at SCL rates up to 400kHz. The SDA state is allowed to change only while SCL is low, with the exception of START and STOP conditions as shown in Figure 5. Each transmission consists of a START condition sent by the bus master _______________________________________________________________________________________ 9 MAX5380/MAX5381/MAX5382 SDA MAX5380/MAX5381/MAX5382 Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 define a write or read protocol, sets the device's power mode (SHDN). The device is powered-down when SHDN is set to one. During a device search routine, the MAX5380/MAX5381/MAX5382 acknowledge both options (SHDN = 0 or SHDN = 1), but do not change their power state if a stop condition (or restart) is issued immediately. The second byte (DAC data) must be sent/received for the device to update both power mode and DAC output. SDA SCL STOP CONDITION START CONDITION Figure 5. START and STOP Conditions DAC Data The 8-bit DAC data is decoded as straight binary MSB first with 1LSB = VREF / 256 and converted into the corresponding analog voltage as shown in Table 1. After receiving the data byte, the devices acknowledge its receipt and expect a STOP condition, at which point the DAC output is updated. device, followed by the MAX5380/MAX5381/MAX5382s' preset slave address, a power-mode bit, the DAC data, and finally, a STOP condition (Figure 6). The bus is then free for another transmission. SDA's state is sampled and therefore must remain stable while SCL is high. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer each byte to the MAX5380/MAX5381/MAX5382. Release SDA during the 9th clock cycle since the selected device acknowledges receipt of the byte by pulling SDA low during this time. A series resistor on the SDA line may be needed if the master's output is forced high while the selected device acknowledges (Figure 4). The MAX5380/MAX5381/MAX5382 update the output and the power mode only if the second byte is clocked in (SHDN = 0) or out (SHDN = 1) of the device. When SHDN = 1, the master will read all ones when clocking out a data byte. The MAX5380/MAX5381/MAX5382 do not drive SDA except for the acknowledge bit. I2C Compatibility The MAX5380/MAX5381/MAX5382 are compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the 9th clock pulse. Figure 7 shows a typical I2C application. The communication protocol supports standard I2C 8-bit communications. The general call address is ignored, and CBUS formats are not supported. The devices' address is compatible with the 7-bit I2C addressing protocol only. No 10-bit formats Slave Address The MAX5380/MAX5381/MAX5382 are available with one of four preset slave addresses. Each address option is identified by the suffix L, M, N, or P added to the part number. The address is defined as the 7MSBs sent by the master after a START condition. The address options are 0x60, 0x62, 0x64, 0x66 (left justified with LSB set to 0). The 8th bit, typically used to SLAVE ADDRESS BYTE 0 SDA 1 1 0 0 MSB 1 DAC CODE A1 A2 SHDN ACK LSB 8 9 D7 D6 D5 D4 D3 D2 D1 LSB 10 17 START CONDITION * L A1 A2 0 0 M N 0 1 1 0 P 1 1 ACK 18 STOP CONDITION *SEE ORDERING INFORMATION. Figure 6. A Complete Serial Transmission 10 D0 MSB ______________________________________________________________________________________ Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 Digital Inputs and Interface Logic C SDA SCL SCL VDD MAX5380L 2V REFERENCE SDA OUT OFFSET ADJUSTMENT The serial 2-wire interface has logic levels defined as VIL = 0.3 x VDD and VIH = 0.7 x VDD. All inputs include Schmitt trigger buffers to accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX5380/MAX5381/MAX5382 without additional external logic. The digital inputs are compatible with CMOS logic levels and must not be driven with voltages higher than VDD. Power-Supply Bypassing and Layout SCL VDD MAX5381M 4V REFERENCE SDA OUT SCL THRESHOLD ADJUSTMENT VDD MAX5382N VDD REFERENCE SDA OUT GAIN ADJUSTMENT Careful printed circuit board layout is important for best system performance. To reduce crosstalk and noise injection, keep analog and digital signals separate. Ensure that the ground return from GND to the supply ground is short and low impedance; a ground plane is recommended. Bypass VDD with a 0.1F capacitor to ground as close as possible to the device. If the supply is excessively noisy, connect a 10 resistor in series with the supply and VDD and add additional capacitance. Chip Information TRANSISTOR COUNT: 2910 Figure 7. Typical I2C Application are supported. RESTART protocol is supported, but an immediate STOP condition is necessary to update the DAC. The 8th bit of the address byte, typically used to indicate a read or write protocol, is used in the MAX5380/ MAX5381/MAX5382 to enter or exit shutdown mode. When MAX5380/MAX5381/MAX5382 are addressed in I2C read mode, they enter shutdown mode. ______________________________________________________________________________________ 11 MAX5380/MAX5381/MAX5382 Applications Information VDD Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SOT-23 5L .EPS MAX5380/MAX5381/MAX5382 Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 PACKAGE OUTLINE, SOT-23, 5L 21-0057 E 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.