ADC128D818CIMT/NOPB - NATIONAL SEMICONDUCTOR

SDA

SCL

INT

IN7 (+)

I2C Interface and Control

Interrupt

Masking

and

Interrupt

Control

ADC128D818

12-bit

Delta-Sigma

ADC

Internal

VREF = +2.56V

Temperature

Sensor

Interrupt

Status

Registers

GND

VREF

V+

Single-Ended

Positive Voltage

LM94022

Shutdown DC-DC

10VIN VOUT

Margining

Voltage

IN0

IN1

IN2

IN3

Pseudo-Differential

Positive Voltage

IN4 (+)

IN5 (-)

IN6 (-)

RTRACE

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ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

ADC128D818 12-Bit, 8-Channel, ADC System Monitor With Temperature Sensor,

Internal – External Reference, and I

C Interface

1 Features – Temperature Accuracy (–25°C to 100°C) ±2°C

1• 12-Bit Resolution Delta-Sigma ADC 2 Applications

• Local Temperature Sensing • Communications Infrastructure

• Configurable Single-Ended and/or Pseudo-Diff. • Thermal and Hardware Server Monitors

Inputs • System Monitors

• 2.56-V Internal VREF or Variable External VREF • Industrial and Medical Systems

• WATCHDOG Window Comparators with Status • Electronic Test Equipment and Instrumentation

and Mask Registers of All Measured Values • Power Supply Monitoring and Supervision

• Independent Registers for Storing Measured

Values 3 Description

• INT Output Notifies Microprocessor of Error Event The ADC128D818 I2C system monitor is designed for

• I2C Serial Bus Interface Compatibility maximum flexibility. The system monitor can be

• 9 Selectable Addresses configured for single-ended and/or pseudo-differential

• TIME-OUT Reset Function to Prevent I2C Bus inputs. An onboard temperature sensor, combined

Lock-Up with WATCHDOG window comparators, and an

interrupt output pin, INT, allow easy monitoring and

• Individual Channel Shutdown to Limit Power out-of-range alarms for every channel. A high

Consumption performance internal reference is also available to

• Deep Shutdown Mode to Minimize Power provide for a complete solution in the most difficult

Consumption operating conditions.

• TSSOP 16-Lead Package The ADC128D818’s 12-bit delta-sigma ADC supports

• Key Specifications Standard Mode (Sm, 100 kbps) and Fast Mode (Fm,

400 kbps) I2C interfaces. The ADC128D818 includes

– ADC Resolution 12-Bit a sequencer to control channel conversions and

– Supply Voltage Range 3 V to 5.5 V stores all converted results in independent registers

– Total Unadjusted Error –0.45%/+0.2% for easy microprocessor retrieval. Unused channels

can be shut down independently to conserve power.

– Integral Non-Linearity ±1 LSb

– Differential Non-Linearity ±1 LSb Device Information(1)

– Operating Current 0.56 mA PART NUMBER PACKAGE BODY SIZE (NOM)

– Deep Shutdown Current 10 µA ADC128D818 TSSOP (16) 5.00 mm × 4.40 mm

– Temperature Resolution °C/LSb (1) For all available packages, see the orderable addendum at

– Temperature Accuracy (–40°C to 125°C) ±3°C the end of the data sheet.

Typical Application Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

www.ti.com

Table of Contents

8.4 Device Functional Modes........................................ 16

1 Features.................................................................. 18.5 Programming........................................................... 16

2 Applications ........................................................... 18.6 Register Maps......................................................... 19

3 Description............................................................. 19 Application and Implementation ........................ 28

4 Revision History..................................................... 29.1 Application Information............................................ 28

5 Description (continued)......................................... 39.2 Typical Application ................................................. 31

6 Pin Configuration and Functions......................... 49.3 System Examples ................................................... 35

7 Specifications......................................................... 510 Power Supply Recommendations ..................... 38

7.1 Absolute Maximum Ratings ...................................... 511 Layout................................................................... 39

7.2 ESD Ratings.............................................................. 511.1 Layout Guidelines ................................................. 39

7.3 Recommended Operating Conditions....................... 611.2 Layout Example .................................................... 39

7.4 Thermal Information.................................................. 612 Device and Documentation Support................. 40

7.5 DC Electrical Characteristics .................................... 612.1 Documentation Support ........................................ 40

7.6 AC Electrical Characteristics..................................... 912.2 Community Resources.......................................... 40

7.7 Typical Characteristics............................................ 10 12.3 Trademarks........................................................... 40

8 Detailed Description............................................ 14 12.4 Electrostatic Discharge Caution............................ 40

8.1 Overview................................................................. 14 12.5 Glossary................................................................ 40

8.2 Functional Block Diagram....................................... 14 13 Mechanical, Packaging, and Orderable

8.3 Feature Description................................................. 15 Information ........................................................... 40

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (March 2013) to Revision F Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Removed Product Highlights ................................................................................................................................................. 1

Changes from Revision D (January 2011) to Revision E Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 27

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5 Description (continued)

The ADC can use either an internal 2.56-V reference or a variable external reference. An analog filter is included

on the I2C digital control lines to provide improved noise immunity. The device also includes a TIME-OUT reset

function on SDA and SCL to prevent I2C bus lock-up.

The ADC128D818 operates from 3-V to 5.5-V power supply voltage range, –40°C to 125°C temperature range,

and the device is available in a 16-pin TSSOP package.

Product Folder Links: ADC128D818

ESD

Clamp

SDA

SCL

GND

A1 8

V+

ADC128D818

16-pin TSSOP

IN7

VREF

IN6

IN5

IN4

IN3

IN2

IN1

IN0

INT

ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

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6 Pin Configuration and Functions

PW Package

16-Pin TSSOP

Top View

Pin Functions

PIN TYPE DESCRIPTION

NO. NAME ESD STRUCTURE

ADC external reference.

ADC128D818 allows two choices for sourcing VREF:

internal or external. If the 2.56-V internal VREF is used,

leave this pin unconnected. If the external VREF is used,

1 VREF Analog Input source this pin with a voltage between 1.25 V and V+. At

Power-On-Reset (POR), the default setting is the internal

VREF.

Bypass with the parallel combination of 1-μF (electrolytic or

tantalum) and 0.1-μF (ceramic) capacitors.

Serial Bus Bidirectional Data. NMOS open-drain output.

2 SDA Digital I/O Requires external pullup resistor to function properly.

Serial Bus Clock. Requires external pullup resistor to

3 SCL Digital Input function properly.

4 GND GROUND Internally connected to all of the circuitry.

3.0-V to 5.5-V power. Bypass with the parallel combination

5 V+POWER of 1-μF (electrolytic or tantalum) and 0.1-μF (ceramic)

bypass capacitors.

Interrupt Request. Active Low, NMOS, open-drain.

6 INT Digital Output Requires external pullup resistor to function properly.

7 A0 Tri-Level Serial Address pins that allow 9 devices on a

Tri-Level Inputs single I2C bus.

8 A1

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SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

Pin Functions (continued)

PIN TYPE DESCRIPTION

NO. NAME ESD STRUCTURE

9 IN7

10 IN6

11 IN5 The full scale range will be controlled by the internal or

12 IN4 Analog Inputs external VREF. These inputs can be assigned as single-

13 IN3 ended and/or pseudo-differential inputs.

14 IN2

15 IN1

16 IN0

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)Æ(4)

MIN MAX UNIT

Supply Voltage (V+) 6.0 6 V

Voltage on SCL, SDA, A0, A1, INT –0.3 6 V

Voltage on IN0-IN7, VREF –0.3 (V++ 0.3) V

Input Current at Any Pin(5) ±5 mA

Package Input Current(5) ±30 mA

Maximum Junction Temperature (TJMAX)(6) 150 °C

Storage Temperature, Tstg –65 150 °C

(1) All voltages are measured with respect to GND, unless otherwise specified.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(4) For soldering specifications, SNOA549

(5) If the input voltage at any pin exceeds the power supply ( that is, VIN < GND or VIN > V +) but is less than the absolute maximum

ratings, then the current at that pin must be limited to 5 mA. The 30 mA maximum package input current rating limits the number of pins

that can safely exceed the power supply with an input current of 5 mA to six pins. Parasitic components and/or ESD protection circuitry

are shown in the Pin Descriptions table.

(6) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA and the ambient temperature,

TA. The maximum allowable power dissipation at any temperature is PD= (TJMAX −TA) / RθJA.

7.2 ESD Ratings VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000

Charged-device model (CDM), per JEDEC specification JESD22- ±1000

V(ESD) Electrostatic discharge V

C101(2)

Machine model ±300

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Product Folder Links: ADC128D818

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted(1)

MIN MAX UNIT

Supply Voltage (V+) 3 5.5 V

Voltage on SCL, SDA, A0, A1, INT –0.05 5.5 V

Voltage on IN0-IN7, VREF –0.05 (V++ 0.05) V

Temperature Range for Electrical Characteristics –40 125 °C

Operating Temperature –40 125 °C

(1) All voltages are measured with respect to GND, unless otherwise specified.

7.4 Thermal Information ADC128D818

THERMAL METRIC(1) PW (TSSOP) UNIT

16 PINS

RθJA Junction-to-ambient thermal resistance 130 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 DC Electrical Characteristics

The following specifications apply for 3 VDC ≤V+≤5.5 VDC , External VREF = 2.56 V, unless otherwise specified. All limits TA

= TJ= 25°C unless otherwise specified(1).

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

POWER SUPPLY CHARACTERISTICS

3.3 or 5 V

V+Supply Voltage TA= TJ= TMIN to TMAX 3 5.5

2.56 V

External Reference Voltage TA= TJ= TMIN to TMAX 1.25 V+

VREF 2.56 V

Internal Reference Voltage 23 ppm/°C

Interface Inactive, V+ = 5.5 TA= TJ= TMIN to TMAX 0.74 mA

V, Mode 2

Interface Inactive, V+ = 3.6 TA= TJ= TMIN to TMAX 0.56 mA

V, Mode 2

Supply Current (see Power

I+Shutdown Mode, V+ = 5.5

Management). TA= TJ= TMIN to TMAX 0.65 mA

Shutdown Mode, V+ = 3.6 TA= TJ= TMIN to TMAX 0.48 mA

Deep Shutdown Mode(4). TA= TJ= TMIN to TMAX 10 µA

TEMPERATURE-to-DIGITAL CONVERTER CHARACTERISTICS

–40°C ≤TA≤+125°C TA= TJ= TMIN to TMAX ±3 °C

Temperature Error –25°C ≤TA≤+100°C TA= TJ= TMIN to TMAX ±2 °C

Resolution 0.5 °C

ANALOG-to-DIGITAL CONVERTER CHARACTERISTICS

n Resolution 12-bit with full-scale at VREF = 2.56 V. 0.625 mV

(1) Each input and output is protected by an ESD structure to GND, as shown in the . Input voltage magnitude up to 0.3 V above V+or 0.3

V below GND will not damage the ADC128D818. There are diodes that exist between some inputs and the power supply rails. Errors in

the ADC conversion can occur if these diodes are forward biased by more than 50 mV. As an example, if V+is 4.5 VDC, INx (where 0 ≤

x≤7) must be ≤4.55 VDC to ensure accurate conversions.

(2) Limits are ensured to AOQL (Average Outgoing Quality Level).

(3) Typicals are at TJ= TA= 25°C and represent most likely parametric normal.

(4) Limit is specified by characterization.

Product Folder Links: ADC128D818

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SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

DC Electrical Characteristics (continued)

The following specifications apply for 3 VDC ≤V+≤5.5 VDC , External VREF = 2.56 V, unless otherwise specified. All limits TA

= TJ= 25°C unless otherwise specified(1).

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

External VREF = 1.25 V, 0.36

Pseudo-Differential, V+ = 3 LSb

TA= TJ= TMIN to TMAX –1 1

V to 3.3 V.(4)

External VREF = 2.56 V, 1.58

INL Integral Non-Linearity Pseudo-Differential LSb

External VREF = 5 V, TA= TJ= TMIN to TMAX –2 4

Pseudo-Differential, V+ = 5

V to 5.5 V. ±0.25

DNL Differential Non-Linearity See (5) LSb

TA= TJ= TMIN to TMAX –1 1

Internal VREF, Single-

Ended, V+ = 3 V to 3.6 V. TA= TJ= TMIN to TMAX –0.5 0.5 % of FS

Internal VREF, Single-

Ended, V+ = 4.5 V to 5.5

V(7).

Internal VREF, Pseudo-

Differential, V+ = 3 V to 3.6 TA= TJ= TMIN to TMAX –0.3 0.5 % of FS

V or V+ = 4.5 V to 5.5 V(7).

External VREF = 1.25 V,

Single-Ended, V+ = 3 V to TA= TJ= TMIN to TMAX

TUE Total Unadjusted Error(6) 3.6 V. –0.6 0.1 % of FS

External VREF = 2.56 V,

Single-Ended, V+ = 3 V to TA= TJ= TMIN to TMAX

5.5 V.

External VREF = 1.25 V,

Pseudo-Differential, V+ = 3 TA= TJ= TMIN to TMAX

V to 3.6 V. –0.45 0.2 % of FS

External VREF = 2.56 V,

Pseudo-Differential, V+ = 3 TA= TJ= TMIN to TMAX

V to 5.5 V.

Internal VREF, V+ = 3 V to

3.6 V. TA= TJ= TMIN to TMAX –0.25 0.45 % of FS

Internal VREF, V+ = 4.5 V

to 5.5 V(7)

GE Gain Error External VREF = 1.25 V or

2.56 V, V+ = 3 V to 3.6 V. TA= TJ= TMIN to TMAX –0.45 0.2 % of FS

External VREF = 2.56 V or

5 V, V+ = 4.5 V to 5.5 V.

Internal VREF, Pseudo-

Differential,V+ = 4.5 V to TA= TJ= TMIN to TMAX –0.15 0.2 % of FS

5.5 V(7).

External VREF = 1.25 V or

2.56 V, Single-Ended, V+ =

3 V to 3.6 V. TA= TJ= TMIN to TMAX –0.5 0.1 % of FS

External VREF = 2.56 V or

OE Offset Error 5 V, Single-Ended, V+ =

4.5 V to 5.5 V

External VREF = 1.25 V or

2.56 V, Pseudo-Differential,

V+ = 3 V to 3.6 V. TA= TJ= TMIN to TMAX –0.2 0.15 % of FS

External VREF = 2.56 V or

5 V, Pseudo-Differential,

V+ = 4.5 V to 5.5 V

(5) Limit is specified by design.

(6) TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.

(7) The range is up to 7/8 of full scale.

Product Folder Links: ADC128D818

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DC Electrical Characteristics (continued)

The following specifications apply for 3 VDC ≤V+≤5.5 VDC , External VREF = 2.56 V, unless otherwise specified. All limits TA

= TJ= 25°C unless otherwise specified(1).

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

Each Enabled Voltage Channel 12 ms

Continuous Conversion Mode Internal Temperature Sensor 3.6 ms

tCEnabled Voltage Channel(s) and Internal

Low Power Conversion Mode 728 ms

Temperature Sensor

MULTIPLEXER / ADC INPUT CHARACTERISTICS

RON ON-Resistance kΩ

TA= TJ= TMIN to TMAX 10

Input Current (On Channel

ION ±0.005 μA

Leakage Current)

IOFF Off Channel Leakage Current ±0.005 μA

DIGITAL OUTPUTS: INT

IOUT = 5.0 mA at V+= 4.5

VOUT(0) Logical 0 Output Voltage V, IOUT = +3 mA at V+= +3 TA= TJ= TMIN to TMAX 0.4 V

OPEN DRAIN SERIAL BUS OUTPUT: SDA

IOUT = 3.0 mA at V+= 4.5

VOUT(0) Logical 0 Output Voltage TA= TJ= TMIN to TMAX 0.4 V

V, 0.005

IOH High Level Output Current VOUT = V+μA

TA= TJ= TMIN to TMAX 1

DIGITAL INPUTS: A0 and A1

VIN(1) Logical 1 Input Voltage TA= TJ= TMIN to TMAX 0.9 × V+ 5.5 V

VIM Logical Middle Input Voltage TA= TJ= TMIN to TMAX 0.43 × 0.57 ×

V+ V+

VIN(0) Logical 0 Input Voltage TA= TJ= TMIN to TMAX GND – 0.1 × V+ V

0.05

SERIAL BUS INPUTS: SCL and SDA

VIN(1) Logical 1 Input Voltage TA= TJ= TMIN to TMAX 0.7 × V+5.5 v

GND –

VIN(0) Logical 0 Input Voltage TA= TJ= TMIN to TMAX 0.3 × V+V

0.05

V+= 3.3 V 0.67 V

VHYST Hysteresis Voltage V+= 5.5 V 1.45 V

ALL DIGITAL INPUTS: SCL, SDA, A0, A1

– 0.005

IIN(1) Logical 1 Input Current VIN = V+µA

TA= TJ= TMIN to TMAX −10.005

IIN(0) Logical 0 Input Current VIN = 0 VDC µA

TA= TJ= TMIN to TMAX 1

CIN Digital Input Capacitance 20 pF

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SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

7.6 AC Electrical Characteristics

The following specifications apply for +3.0 VDC ≤V+≤+5.5 VDC , unless otherwise specified. All limits TA= TJ= 25°C unless

otherwise specified.

PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT

SERIAL BUS TIMING CHARACTERISTICS

t1SCL (Clock) Period TA= TJ= TMIN to TMAX 2.5 100 µs

t2Data In Set-up Time to SCL High TA= TJ= TMIN to TMAX 100 ns

t3Data Out Stable After SCL Low TA= TJ= TMIN to TMAX 0 ns

t4SDA Low Set-up Time to SCL Low TA= TJ= TMIN to TMAX 100 ns

(start)

t5SDA High Hold Time After SCL High TA= TJ= TMIN to TMAX 100 ns

(stop)

SCL or SDA time low for I2C bus TA= TJ= TMIN to TMAX 25 35 ms

tTIME-OUT reset

(1) Limits are ensured to AOQL (Average Outgoing Quality Level).

(2) Typicals are at TJ= TA= 25°C and represent most likely parametric normal.

Figure 1. Serial Bus Timing Diagram

Product Folder Links: ADC128D818

500.0 1.2k 1.9k 2.7k 3.4k 4.1k

CODE

TUE (%)

-0.020

-0.060

-0.100

-0.140

-0.180

-0.220

500.0 1.2k 1.9k 2.7k 3.4k 4.1k

CODE

TUE (%)

-0.020

-0.064

-0.108

-0.152

-0.196

-0.240

500.0 1.2k 1.9k 2.7k 3.4k 4.1k

CODE

TUE (%)

0.023

0.014

0.004

-0.005

-0.015

-0.024

500.0 1.2k 1.9k 2.7k 3.4k 4.1k

CODE

TUE (%)

-0.010

-0.074

-0.138

-0.202

-0.266

-0.330

ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

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7.7 Typical Characteristics

The following typical performance plots apply for the internal VREF = 2.56 V, V+ = 3.3 V, Pseudo-Differential connection,

unless otherwise specified. All limits TA= TJ= 25°C unless otherwise specified.

Figure 2. TUE vs. Code Figure 3. TUE vs. Code (External VREF = 1.25 V)

Figure 4. TUE vs. Code (External VREF = 2.56 V) Figure 5. TUE vs. Code (External VREF = 5 V, V+ = 5 V)

Figure 6. INL vs. Code (External VREF = 1.25 V for 1 Unit) Figure 7. INL vs. Code (External VREF = 1.25 V for 28 Units)

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Typical Characteristics (continued)

The following typical performance plots apply for the internal VREF = 2.56 V, V+ = 3.3 V, Pseudo-Differential connection,

unless otherwise specified. All limits TA= TJ= 25°C unless otherwise specified.

Figure 8. INL vs. Code (External VREF = 2.56 V for 1 Unit) Figure 9. INL vs. Code (External VREF = 2.56 V for 28 Units)

Figure 10. INL vs. Code (External VREF = 5 V, V+ = 5 V for 1 Figure 11. INL vs. Code (External VREF = 5 V, V+ = 5 V for

Unit) 28 Units)

Figure 12. DNL vs. Code (External VREF = 2.56 V for 1 Unit) Figure 13. DNL vs. Code (External VREF = 2.56 V for 28

Units)

Product Folder Links: ADC128D818

-50.0 -14.0 22.0 58.0 94.0 130.0

TEMPERATURE (°C)

0.460

0.440

0.420

0.400

0.380

0.360

I+ (mA)

2.7 3.3 3.8 4.4 4.9

V+ (V)

0.490

0.470

0.450

0.430

0.410

0.390

I+ (mA)

3.0 3.5 4.0 4.5 5.0 5.5

V+ (V)

GAIN ERROR (%)

0.100

0.075

0.050

0.025

-6.939E-18

-0.025

-0.050

-0.075

-0.100

-50.0 -14.0 22.0 58.0 94.0 130.0

TEMPERATURE (°C)

GAIN ERROR (%)

0.230

0.188

0.146

0.104

0.062

0.020

3.2 3.7 4.1 4.6 5.0 5.5

V+ (V)

OFFSET ERROR (%)

0.040

0.030

0.020

0.010

0.000

-50.0 -14.0 22.0 58.0 94.0 130.0

TEMPERATURE (°C)

OFFSET ERROR (%)

0.025

0.024

0.023

0.022

0.021

0.020

0.019

0.018

0.017

0.016

0.015

ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

www.ti.com

Typical Characteristics (continued)

The following typical performance plots apply for the internal VREF = 2.56 V, V+ = 3.3 V, Pseudo-Differential connection,

unless otherwise specified. All limits TA= TJ= 25°C unless otherwise specified.

Figure 14. Offset Error vs. V+ Figure 15. Offset Error vs. Temperature

Figure 16. Gain Error vs. V+ Figure 17. Gain Error vs. Temperature

Figure 18. I+ vs. Temperature Figure 19. I+ vs. V+ Typical

A. Timing specifications are tested at the Serial Bus Input logic levels: V IN(0) = 0.3 × V + for a falling edge and V IN(1)

= 0.7 × V + for a rising edge if the SCL and SDA edge rates are similar

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2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

V+ (V)

I+ (mA)

0.440

0.420

0.400

0.380

0.360

0.340

0.320

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

V+ (V)

0.004

0.003

0.002

0.001

I+ (mA)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

V+ (V)

I+ (mA)

1.340

1.298

1.256

1.214

1.172

1.130

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

V+ (V)

1.70

1.60

1.50

1.40

1.30

I+ (mA)

ADC128D818

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SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

Typical Characteristics (continued)

The following typical performance plots apply for the internal VREF = 2.56 V, V+ = 3.3 V, Pseudo-Differential connection,

unless otherwise specified. All limits TA= TJ= 25°C unless otherwise specified.

Figure 21. I+ vs. V+ for Temperature Conversion

Figure 20. I+ vs. V+ for Voltage Conversion

Figure 22. I+ vs. V+ in Shutdown Mode Figure 23. I+ vs. V+ in Deep Shutdown Mode

Product Folder Links: ADC128D818

12-bit

Delta-

Sigma

ADC and

MUX

Interrupt

Masking

and

Interrupt

Control

Interface and Control

IN0

IN1

IN2

IN3

IN4

IN5

Upper Limit

Lower Limit

Upper Limit

Lower Limit

Upper Limit

Lower Limit

Upper Limit

Lower Limit

Upper Limit

Lower Limit

Upper Limit

Lower Limit

IN0

IN1

IN2

IN3

IN4

IN5

IN6

10 Interrupt

Status

Registers

Serial Bus Interface

SDA

SCL A0

Watchdog

327

IN6

IN7

Upper Limit

Lower Limit

Upper Limit

Lower Limit

IN7 9

V+

GND

VREF 1

INT

Internal

VREF =

2.56V

Tempe-

rature

Temperature Thot

Thot_hyst

ADC128D818

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8 Detailed Description

8.1 Overview

The ADC128D818 provides 8 analog inputs, a temperature sensor, a delta-sigma ADC, an external or internal

VREF option, and WATCHDOG registers on a single chip. An I2C Serial Bus interface is also provided. The

ADC128D818 can perform voltage and temperature monitoring for a variety of systems.

The ADC128D818 continuously converts the voltage input to 12-bit resolution with an internal VREF of 0.625-mV

LSb (Least Significant bit) weighting, yielding input range of 0 V to 2.56 V. There is also an external VREF option

that ranges from 1.25 V to V+. The analog inputs are intended to be connected to several power supplies

present in a variety of systems. Eight inputs can be configured for single-ended and/or pseudo-differential

channels. Temperature can be converted to a 9-bit two's complement word with resolutions of 0.5°C per LSb.

The ADC128D818 provides a number of internal registers. These registers are summarized in Table 19.

The ADC128D818 supports Standard Mode (Sm, 100 kbps) and Fast Mode (Fm, 400 kbps) I2C interface modes

of operation. ADC128D818 includes an analog filter on the I2C digital control lines that allows improved noise

immunity. The device also supports TIME-OUT reset function on SDA and SCL to prevent I2C bus lock-up. Two

tri-level address pins allow up to 9 devices on a single I2C bus.

At start-up, ADC128D818 cycles through each measurement in sequence and continuously loops through the

sequence based on the Conversion Rate Register (address 07h) setting. Each measured value is compared to

values stored in the Limit Registers (addresses 2Ah - 39h). When the measured value violates the programmed

limit, the ADC128D818 will set a corresponding interrupt bit in the Interrupt Status Registers (address 01h). An

interrupt output pin, INT, is also available and fully programmable.

8.2 Functional Block Diagram

Product Folder Links: ADC128D818

SRC

IN0

ADC128D818

IN1

IN2

IN3

IN6

IN7

IN4

IN5

GND

ADC128D818

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8.3 Feature Description

8.3.1 Supply Voltage (V+)

The ADC128D818 operates with a supply voltage, V+, that has a range between 3 V to 5.5 V. Take care to

bypass this pin with a parallel combination of 1-µF (electrolytic or tantalum) capacitor and 0.1-µF (ceramic)

bypass capacitor.

8.3.2 Voltage References (VREF)

The reference voltage (VREF) sets the analog input range. The ADC128D818 has two options for setting VREF.

The first option is to use the internal VREF, which is equal to 2.56 V. The second option is to source VREF

externally through pin 1 of ADC128D818. In this case, the external VREF will operate in the range of 1.25 V to

V+. The default VREF selection is the internal VREF. If the external VREF is preferred, use the Advanced

Configuration Register — Address 0Bh to change this setting.

VREF source must have a low output impedance and needs to be bypassed with a minimum capacitor value of

0.1 µF. A larger capacitor value of 1 µF placed in parallel with the 0.1 µF is preferred. VREF of the

ADC128D818, like all ADC converters, does not reject noise or voltage variations. Keep this in mind if VREF is

derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external

reference circuitry will appear in the digital results. The use of a reference source is recommended. The LM4040

and LM4050 shunt reference families as well as the LM4120 and LM4140 series reference families are excellent

choices for a reference source.

8.3.3 Analog Inputs (IN0 - IN7)

The ADC128D818 allows up to 8 single-ended inputs or 4 pseudo-differential inputs as selected by the modes of

operation. The input types are described in the next subsections.

8.3.3.1 Single-Ended Input

ADC128D818 allows a maximum of 8 single-ended inputs, where the source's voltage is connected to INx (0 ≤x

≤7). The source’s ground must be connected to ADC128D818’s GND pin. In theory, INx can be of any value

between 0V and (VREF-3LSb/2), where LSb = VREF/212.

To use the device single-endedly, refer to the Modes of Operation section and to bits [2:1] of the Advanced

Configuration Register — Address 0Bh.Figure 24 shows the appropriate configuration for a single-ended

connection.

Figure 24. Single-Ended Configuration

8.3.3.2 Pseudo-Differential Input

Pseudo-differential mode is defined as the positive input voltage applied differentially to the ADC128D818, as

shown in Figure 25. The input that is digitized is (ΔVIN = IN+ - IN–), where (IN+ - IN–) is (IN0-IN1), (IN3-IN2),

(IN4-IN5), or (IN7-IN6). Be aware of this input configuration because the order is swapped. In theory, ΔVIN can

be of any value between 0 V and (VREF – 3LSb/2), where LSb = VREF/212.

By using this pseudo-differential input, small signals common to both inputs are rejected. Thus, operation with a

pseudo-differential input signal will provide better performance than with a single-ended input. See Modes of

Operation for more information.

Product Folder Links: ADC128D818

SRC

IN0 (+)

ADC128D818

IN1 (-)

IN3 (+)

IN2 (-)

IN7 (+)

IN6 (-)

IN4 (+)

IN5 (-)

ADC128D818

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Feature Description (continued)

Figure 25. Pseudo-Differential Configuration

8.4 Device Functional Modes

8.4.1 Modes of Operation

ADC128D818 allows 4 modes of operation, as summarized in the following table. Set the desired mode of

operation using the Advanced Configuration Register — Address 0Bh, bits [2:1]).

Table 1. Modes of Operation

CH. MODE 0 MODE 1 MODE 2 MODE 3

IN0 (+) and

1 IN0 IN0 IN1 (-) IN0

IN3 (+) and

2 IN1 IN1 IN2 (-) IN1

IN4 (+) and

3 IN2 IN2 IN5 (-) IN2

IN7 (+) and

4 IN3 IN3 IN6 (-) IN3

IN4 (+) and

5 IN4 IN4 IN5 (-)

IN7 (+) and

6 IN5 IN5 IN6 (-)

7 IN6 IN6

8 nc(1) IN7

Local

Temp Yes No Yes Yes

(1) nc = No Connect

8.5 Programming

8.5.1 Interface

The Serial Bus control lines include the SDA (serial data), SCL (serial clock), and A0-A1 (Serial Bus Address)

pins. The ADC128D818 can only operate as a slave. The SCL line only controls the serial interface, and all of

other clock functions within ADC128D818 are done with a separate asynchronous internal clock.

When the Serial Bus Interface is used, a write will always consists of the ADC128D818 Serial Bus Address byte,

followed by the Register Address byte, then the Data byte. Figure 26 and Figure 27 are two examples showing

how to write to the ADC128D818.

There are two cases for a read:

1. If the Register Address is known to be at the desired address, simply read the ADC128D818 with the Serial

Bus Address byte, followed by the Data byte read from the ADC128D818. Examples of this type of read can

be seen in Figure 28 and Figure 29.

2. If the Register Address value is unknown, write to the ADC128D818 with the Serial Bus Address byte,

followed by the desired Register Address byte. Then restart the Serial Communication with a Read

consisting of the Serial Bus Address byte, followed by the Data byte read from the ADC128D818. See

Figure 30 and Figure 31 for examples of this type of read.

Product Folder Links: ADC128D818

D7 D6 D5 D4 D3 D2 D1 D0

1 9 1 9

Ack by

ADC128D818

Start by

Master

R/W

Frame 1

Serial Bus Address

Byte from Master

Frame 2

Byte from Master

A2 A0A1

A3A4A5A6

SCL

SDA Stop by

Master

Ack by

ADC128D818

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Programming (continued)

The Serial Bus Address can be found in the next section, and the Register Address can be found in Register

Maps. For more information on the I2C Interface, refer to NXP's "I2C-Bus Specification and User Manual", rev.

03.

8.5.1.1 Serial Bus Address

There are nine different configurations for the ADC128D818 Serial Bus Address, thus nine devices are allowed

on a single I2C bus. Examples to set each address bit low, high, or to midscale can be found in System

Examples. The Serial Bus Address can be set as follows:

Table 2. Serial Bus Address Table

SERIAL BUS ADDRESS

A1 A0 SERIAL BUS ADDRESS (HEX)

[A6][A5][A4]...[A0]

LOW LOW 001_1101b 1Dh

LOW MID 001_1110b 1Eh

LOW HIGH 001_1111b 1Fh

MID LOW 010_1101b 2Dh

MID MID 010_1110b 2Eh

MID HIGH 010_1111b 2Fh

HIGH LOW 011_0101b 35h

HIGH MID 011_0110b 36h

HIGH HIGH 011_0111b 37h

8.5.1.2 Time-out

The ADC128D818 I2C state machine resets to its idle state if either SCL or SDA is held low for longer than 35

ms. This feature also ensures that ADC128D818 will automatically release SDA after driving it low continuously

for 25 to 35 ms, hence preventing I2C bus lock-up. The TIME-OUT feature should not be used when the device

is operating in deep shutdown mode.

8.5.1.2.1 Example Writes and Reads

Figure 26. Serial Bus Interface Write Example 1 - Internal Address Register Set Only

Product Folder Links: ADC128D818

D7 D6 D5 D4 D3 D2 D1 D0

1 9 1 9

Ack by

ADC128D818

Start by

Master

R/W Ack by

ADC128D818

Frame 1

Serial Bus Address

Byte from Master

Frame 2

Byte from Master

D7 D6 D5 D4 D3 D2 D1 D0

1 9

Ack by

ADC128D818

No Ack

Master

Stop

Master

1 9

Frame 3

Serial Bus Address

Byte from Master

Frame 4

Data Byte

from ADC128D818

R/W

A2 A0A1

A3A4A5A6

Repeat

Start by

Master

A2 A0A1A3A4A5A6

SCL

SDA

SCL

(continued)

SDA

(continued)

D7 D6 D5 D4 D3 D2 D1 D0

1 9 1 9

Ack by

ADC128D818

Start by

Master No Ack

Master

SCL

SDA Stop

Master

1 9

D15 D14 D13 D12 D11 D10 D9 D8 Ack

Master

Frame 1

Serial Bus Address

Byte from Master

Frame 2

Data Byte

from ADC128D818

Frame 3

Data Byte

from ADC128D818

R/W

A2 A0A1

A3A4A5A6

D7 D6 D5 D4 D3 D2 D1 D0

1 9

Start by

Master No Ack

Master

SCL

SDA

Stop

Master

1 9

Frame 1

Serial Bus Address

Byte from Master

Frame 2

Data Byte

from ADC128D818

R/W

A2 A0A1

A3A4A5A6

Ack by

ADC128D818

D7 D6 D5 D4 D3 D2 D1 D0

1 9 1 9

Start by

Master

R/W

Frame 1

Serial Bus Address

Byte from Master

Frame 2

Byte from Master

1 9

Frame 3

Data Byte

D3 D1D2

D4D5D6D7

A2 A0A1A3A4A5A6

SCL

SDA

SCL

(continued)

SDA

(continued) Stop by

Master

Ack by

ADC128D818 Ack by

ADC128D818

Ack by

ADC128D818

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Figure 27. Serial Bus Interface Write Example 2 - Internal Address Register Set With Data Byte Write

Figure 28. Serial Bus Interface Read Example 1 - Single Byte Read With Preset Internal Address Register

Figure 29. Serial Bus Interface Read Example 2 - Double Byte Read With Preset Internal Address

Figure 30. Serial Bus Interface Read Example 3 - Single Byte Read With Internal Address Set Using a

Repeat Start

Product Folder Links: ADC128D818

D7 D6 D5 D4 D3 D2 D1 D0

1 9 1 9

Ack by

ADC128D818

Start by

Master

R/W

Ack by

ADC128D818

Frame 1

Serial Bus Address

Byte from Master

Frame 2

Byte from Master

D7 D6 D5 D4 D3 D2 D1 D0

1 9 1 9

Ack by

ADC128D818 No Ack by

Master

Stop

Master

1 9

D15 D14 D13 D12 D11 D10 D9 D8

Ack by

Master

Frame 3

Serial Bus Address

Byte from Master

Frame 4

Data Byte

from ADC128D818

Frame 5

Data Byte from

ADC128D818

R/W

A2 A0A1

A3A4A5A6

Repeat

Start by

Master

A2 A0A1A3A4A5A6

SCL

SDA

SCL

(continued)

SDA

(continued)

ADC128D818

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SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

Figure 31. Serial Bus Interface Read Example 4 - Double Byte Read With Internal Address Set Using a

Repeat Start

8.6 Register Maps

8.6.1 ADC128D818 Internal Registers

Table 3. ADC128D818 Internal Registers

READ/ DEFAULT REGISTER

WRITE VALUE [7:0] FORMAT

(HEX)

Configuration Register R/W 00h 0000_1000 Provides control and configuration 8-bit

Provides status of each WATCHDOG limit or

Interrupt Status Register R 01h 0000_0000 8-bit

interrupt event

Masks the interrupt status from propagating

Interrupt Mask Register R/W 03h 0000_0000 8-bit

to INT

Conversion Rate Register R/W 07h 0000_0000 Controls the conversion rate 8-bit

Disables conversion for each voltage or

Channel Disable Register R/W 08h 0000_0000 8-bit

temperature channel

Initiates a single conversion of all enabled

One-Shot Register W 09h 0000_0000 8-bit

channels

Deep Shutdown Register R/W 0Ah 0000_0000 Enables deep shutdown mode 8-bit

Selects internal or external VREF and modes

Advanced Configuration Register R/W 0Bh 0000_0000 8-bit

of operation

Reflects ADC128D818 'Busy' and 'Not Ready'

Busy Status Register R 0Ch 0000_0010 8-bit

statuses

Report the channels (voltage or temperature)

Channel Readings Registers R 20h - 27h - - - 16-bit

readings

Set the limits for the voltage and temperature

Limit Registers R/W 2Ah - 39h - - - 8-bit

channels

Manufacturer ID Register R 3Eh 0000_0001 Reports the manufacturer's ID 8-bit

Revision ID Register R 3Fh 0000_1001 Reports the revision's ID 8-bit

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8.6.2 Configuration Register — Address 00h

Default Value [7:0] = 0000_1000 binary

Table 4. Address 00h

BIT BIT NAME READ/WRITE BIT DESCRIPTION

ALL MODES

0: ADC128D818 in shutdown mode

0 Start Read/Write 1: Enable startup of monitoring operations

1 INT_Enable Read/Write 1: Enable the interrupt output pin, INT

2 Reserved Read Only 1: Clear the interrupt output pin, INT, without affecting the contents of Interrupt Status

3 INT_Clear Read/Write Registers. When this bit is set high, the device stops the round-robin monitoring loop.

4 Reserved Read Only

5 Reserved Read Only

6 Reserved Read Only 1: Restore default values to the following registers: Configuration, Interrupt Status, Interrupt

Mask, Conversion Rate, Channel Disable, One-Shot, Deep Shutdown, Advanced

7 Initialization Read/Write Configuration, Busy Status, Channel Readings, Limit, Manufacturer ID, Revision ID. This bit

clears itself

8.6.3 Interrupt Status Register — Address 01h

Default Value [7:0] = 0000_0000 binary

Table 5. Address 01h

BIT BIT NAME READ/WRITE BIT DESCRIPTION

MODE 0

0 IN0 Error Read Only 1: A High or Low limit has been exceeded

1 IN1 Error Read Only 1: A High or Low limit has been exceeded

2 IN2 Error Read Only 1: A High or Low limit has been exceeded

3 IN3 Error Read Only 1: A High or Low limit has been exceeded

4 IN4 Error Read Only 1: A High or Low limit has been exceeded

5 IN5 Error Read Only 1: A High or Low limit has been exceeded

6 IN6 Error Read Only 1: A High or Low limit has been exceeded

7 Hot Temperature Error Read Only 1: A High limit has been exceeded

MODE 1

0 IN0 Error Read Only 1: A High or Low limit has been exceeded

1 IN1 Error Read Only 1: A High or Low limit has been exceeded

2 IN2 Error Read Only 1: A High or Low limit has been exceeded

3 IN3 Error Read Only 1: A High or Low limit has been exceeded

4 IN4 Error Read Only 1: A High or Low limit has been exceeded

5 IN5 Error Read Only 1: A High or Low limit has been exceeded

6 IN6 Error Read Only 1: A High or Low limit has been exceeded

7 IN7 Error Read Only 1: A High or Low limit has been exceeded

MODE 2

0 IN0(+) and IN1(-) Error Read Only 1: A High or Low limit has been exceeded

1 IN3(+) and IN2(-) Error Read Only 1: A High or Low limit has been exceeded

2 IN4(+) and IN5(-) Error Read Only 1: A High or Low limit has been exceeded

3 IN7(+) and IN6(-) Error Read Only 1: A High or Low limit has been exceeded

4 Reserved Read Only

5 Reserved Read Only

6 Reserved Read Only

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Table 5. Address 01h (continued)

BIT BIT NAME READ/WRITE BIT DESCRIPTION

7 Hot Temperature Error Read Only 1: A High limit has been exceeded

MODE 3

0 IN0 Error Read Only 1: A High or Low limit has been exceeded

1 IN1 Error Read Only 1: A High or Low limit has been exceeded

2 IN2 Error Read Only 1: A High or Low limit has been exceeded

3 IN3 Error Read Only 1: A High or Low limit has been exceeded

4 IN4(+) and IN5(-) Error Read Only 1: A High or Low limit has been exceeded

5 IN7(+) and IN6(-) Error Read Only 1: A High or Low limit has been exceeded

6 Reserved Read Only

7 Hot Temperature Error Read Only 1: A High limit has been exceeded

8.6.4 Interrupt Mask Register — Address 03h

Default Value [7:0] = 0000_0000 binary

Table 6. Address 03h

BIT BIT NAME READ/WRITE BIT DESCRIPTION

MODE 0

1: Mask the corresponding interrupt status from propagating to the interrupt

0 IN0 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

1 IN1 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

2 IN2 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

3 IN3 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

4 IN4 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

5 IN5 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

6 IN6 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

7 Temperature Mask Read/Write output pin, INT

MODE 1

1: Mask the corresponding interrupt status from propagating to the interrupt

0 IN0 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

1 IN1 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

2 IN2 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

3 IN3 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

4 IN4 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

5 IN5 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

6 IN6 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

7 IN7 Mask Read/Write output pin, INT

MODE 2

1: Mask the corresponding interrupt status from propagating to the interrupt

0 IN0(+) and IN1(-) Mask Read/Write output pin, INT

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Table 6. Address 03h (continued)

BIT BIT NAME READ/WRITE BIT DESCRIPTION

1: Mask the corresponding interrupt status from propagating to the interrupt

1 IN3(+) and IN2(-) Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

2 IN4(+) and IN5(-) Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

3 IN7(+) and IN6(-) Mask Read/Write output pin, INT

4 Reserved Read Only

5 Reserved Read Only

6 Reserved Read Only 1: Mask the corresponding interrupt status from propagating to the interrupt

7 Temperature Mask Read/Write output pin, INT

MODE 3

1: Mask the corresponding interrupt status from propagating to the interrupt

0 IN0 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

1 IN1 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

2 IN2 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

3 IN3 Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

4 IN4(+) and IN5(-) Mask Read/Write output pin, INT

1: Mask the corresponding interrupt status from propagating to the interrupt

5 IN7(+) and IN6(-) Mask Read/Write output pin, INT

6 Reserved Read Only 1: Mask the corresponding interrupt status from propagating to the interrupt

7 Temperature Mask Read/Write output pin, INT

8.6.5 Conversion Rate Register — Address 07h

Default Value [7:0] = 0000_0000 binary

Table 7. Address 07h

BIT BIT NAME READ/WRITE BIT DESCRIPTION

Controls the conversion rate:

0: Low Power Conversion Mode

1: Continuous Conversion Mode

0 Conversion Rate Read/Write Note: This register must only be programmed when the device is in shutdown

mode, that is, when the 'START' bit of the 'Configuration Register' (address 00h)

= 0

1–7 Reserved Read Only

8.6.6 Channel Disable Register — Address 08h

Default Value [7:0] = 0000_0000 binary

• This register must only be programmed when the device is in shutdown mode, that is, when the ‘START’ bit

of the “Configuration Register’ (address 00h) = 0.

• Whenever this register is programmed, all of the values in the Channel Reading Registers and Interrupt

Status Registers will return to their default values.

Table 8. Address 08h

BIT BIT NAME READ/WRITE BIT DESCRIPTION

MODE 0

1: Conversions are skipped and disabled, value register reading will be 0, and

0 IN0 Disable Read/Write error events will be suppressed.

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Table 8. Address 08h (continued)

BIT BIT NAME READ/WRITE BIT DESCRIPTION

1: Conversions are skipped and disabled, value register reading will be 0, and

1 IN1 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

2 IN2 Disable Read/Write error events will be suppressed

1: Conversions are skipped and disabled, value register reading will be 0, and

3 IN3 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

4 IN4 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

5 IN5 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

6 IN6 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

7 Temperature Disable Read/Write error events will be suppressed.

MODE 1

1: Conversions are skipped and disabled, value register reading will be 0, and

0 IN0 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

1 IN1 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

2 IN2 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

3 IN3 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

4 IN4 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

5 IN5 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

6 IN6 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

7 IN7 Disable Read/Write error events will be suppressed.

MODE 2

1: Conversions are skipped and disabled, value register reading will be 0, and

0 IN0(+) and IN1(-) Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

1 IN3(+) and IN2(-) Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

2 IN4(+) and IN5(-) Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

3 IN7(+) and IN6(-) Disable Read/Write error events will be suppressed.

4 Reserved Read Only

5 Reserved Read Only

6 Reserved Read Only 1: Conversions are skipped and disabled, value register reading will be 0, and

7 Temperature Disable Read/Write error events will be suppressed.

MODE 3

1: Conversions are skipped and disabled, value register reading will be 0, and

0 IN0 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

1 IN1 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

2 IN2 Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

3 IN3 Disable Read/Write error events will be suppressed.

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Table 8. Address 08h (continued)

BIT BIT NAME READ/WRITE BIT DESCRIPTION

1: Conversions are skipped and disabled, value register reading will be 0, and

4 IN4(+) and IN5(-) Disable Read/Write error events will be suppressed.

1: Conversions are skipped and disabled, value register reading will be 0, and

5 IN7(+) and IN6(-) Disable Read/Write error events will be suppressed.

6 Reserved Read Only 1: Conversions are skipped and disabled, value register reading will be 0, and

7 Temperature Disable Read/Write error events will be suppressed.

8.6.7 One-Shot Register — Address 09h

Default Value [7:0] = 0000_0000 binary

Table 9. Address 09h

BIT BIT NAME READ/WRITE BIT DESCRIPTION

1: Initiate a single conversion and comparison cycle when the device is in

0 One-Shot Write Only shutdown mode or deep shutdown mode, after which the device returns to the

respective mode that it was in

1–7 Reserved Read Only

8.6.8 Deep Shutdown Register — Address 0Ah

Default Value [7:0] = 0000_0000 binary

Table 10. Address 0Ah

BIT BIT NAME READ/WRITE BIT DESCRIPTION

1: When 'START' = 0 (address 00h, bit 0), setting this bit high will place the

0 Deep Shutdown Enable Read/Write device in deep shutdown mode

1–7 Reserved Read Only

8.6.9 Advanced Configuration Register — Address 0Bh

Default Value [7:0] = 0000_0000 binary

Note: Whenever the Advanced Configuration Register is programmed, all of the values in the Channel Reading

Registers and Interrupt Status Registers will return to their default values.

Table 11. Address 0Bh

BIT BIT NAME READ/WRITE BIT DESCRIPTION

0: Selects the 2.56V internal VREF

0 External Reference Enable Read/Write 1: Selects the variable external VREF

Mode Select [1] Mode Select [0] Mode

0 0 Mode 0

1 Mode Select [0] Read/Write 0 1 Mode 1

1 0 Mode 2

2 Mode Select [1] 1 1 Mode 3

3–7 Reserved Read Only

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8.6.10 Busy Status Register — Address 0Ch

Default Value [7:0] = 0000_0010 binary

Table 12. Address 0Ch

BIT BIT NAME READ/WRITE BIT DESCRIPTION

0 Busy Read Only 1: ADC128D818 is converting

1 Not Ready Read Only 1: Waiting for the power-up sequence to end

2–7 Reserved Read Only

8.6.11 Channel Readings Registers — Addresses 20h – 27h

ADDRESS REGISTER NAME READ/WRITE REGISTER DESCRIPTION

MODE 0

20h IN0 Reading Read Only Reading for this perspective channel

21h IN1 Reading Read Only Reading for this perspective channel

22h IN2 Reading Read Only Reading for this perspective channel

23h IN3 Reading Read Only Reading for this perspective channel

24h IN4 Reading Read Only Reading for this perspective channel

25h IN5 Reading Read Only Reading for this perspective channel

26h IN6 Reading Read Only Reading for this perspective channel

27h Temperature Reading Read Only Reading for this perspective channel

MODE 1

20h IN0 Reading Read Only Reading for this perspective channel

21h IN1 Reading Read Only Reading for this perspective channel

22h IN2 Reading Read Only Reading for this perspective channel

23h IN3 Reading Read Only Reading for this perspective channel

24h IN4 Reading Read Only Reading for this perspective channel

25h IN5 Reading Read Only Reading for this perspective channel

26h IN6 Reading Read Only Reading for this perspective channel

27h IN7 Reading Read Only Reading for this perspective channel

MODE 2

20h IN0(+) and IN1(-) Reading Read Only Reading for this perspective channel

21h IN3(+) and IN2(-) Reading Read Only Reading for this perspective channel

22h IN4(+) and IN5(-) Reading Read Only Reading for this perspective channel

23h IN7(+) and IN6(-) Reading Read Only Reading for this perspective channel

24h Reserved Read Only

25h Reserved Read Only

26h Reserved Read Only

27h Temperature Reading Read Only Reading for this perspective channel

MODE 3

20h IN0 Reading Read Only Reading for this perspective channel

21h IN1 Reading Read Only Reading for this perspective channel

22h IN2 Reading Read Only Reading for this perspective channel

23h IN3 Reading Read Only Reading for this perspective channel

24h IN4(+) and IN5(-) Reading Read Only Reading for this perspective channel

25h IN7(+) and IN6(-) Reading Read Only Reading for this perspective channel

26h Reserved Read Only

27h Temperature Reading Read Only Reading for this perspective channel

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8.6.12 Limit Registers — Addresses 2Ah – 39h

Table 13. Addresses 2Ah – 39h

ADDRESS REGISTER NAME READ/WRITE REGISTER DESCRIPTION

MODE 0

2Ah IN0 High Limit Read/Write High Limit

2Bh IN0 Low Limit Read/Write Low Limit

2Ch IN1 High Limit Read/Write High Limit

2Dh IN1 Low Limit Read/Write Low Limit

2Eh IN2 High Limit Read/Write High Limit

2Fh IN2 Low Limit Read/Write Low Limit

30h IN3 High Limit Read/Write High Limit

31h IN3 Low Limit Read/Write Low Limit

32h IN4 High Limit Read/Write High Limit

33h IN4 Low Limit Read/Write Low Limit

34h IN5 High Limit Read/Write High Limit

35h IN5 Low Limit Read/Write Low Limit

36h IN6 High Limit Read/Write High Limit

37h IN6 Low Limit Read/Write Low Limit

38h Temperature High Limit Read/Write High Limit

39h Temperature Hysteresis Limit Read/Write Hysteresis Limit

MODE 1

2Ah IN0 High Limit Read/Write High Limit

2Bh IN0 Low Limit Read/Write Low Limit

2Ch IN1 High Limit Read/Write High Limit

2Dh IN1 Low Limit Read/Write Low Limit

2Eh IN2 High Limit Read/Write High Limit

2Fh IN2 Low Limit Read/Write Low Limit

30h IN3 High Limit Read/Write High Limit

31h IN3 Low Limit Read/Write Low Limit

32h IN4 High Limit Read/Write High Limit

33h IN4 Low Limit Read/Write Low Limit

34h IN5 High Limit Read/Write High Limit

35h IN5 Low Limit Read/Write Low Limit

36h IN6 High Limit Read/Write High Limit

37h IN6 Low Limit Read/Write Low Limit

38h IN7 High Limit Read/Write High Limit

39h IN7 Low Limit Read/Write Low Limit

MODE 2

2Ah IN0(+) and IN1(-) High Limit Read/Write High Limit

2Bh IN0(+) and IN1(-) Low Limit Read/Write Low Limit

2Ch IN3(+) and IN2(-) High Limit Read/Write High Limit

2Dh IN3(+) and IN2(-) Low Limit Read/Write Low Limit

2Eh IN4(+) and IN5(-) High Limit Read/Write High Limit

2Fh IN4(+) and IN5(-) Low Limit Read/Write Low Limit

30h IN7(+) and IN6(-) High Limit Read/Write High Limit

31h IN7(+) and IN6(-) Low Limit Read/Write Low Limit

32h Reserved Read Only

33h Reserved Read Only

34h Reserved Read Only

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Table 13. Addresses 2Ah – 39h (continued)

ADDRESS REGISTER NAME READ/WRITE REGISTER DESCRIPTION

35h Reserved Read Only

36h Reserved Read Only

37h Reserved Read Only

38h Temperature High Limit Read/Write High Limit

39h Temperature Hysteresis Limit Read/Write Hysteresis Limit

MODE 3

2Ah IN0 High Limit Read/Write High Limit

2Bh IN0 Low Limit Read/Write Low Limit

2Ch IN1 High Limit Read/Write High Limit

2Dh IN1 Low Limit Read/Write Low Limit

2Eh IN2 High Limit Read/Write High Limit

2Fh IN2 Low Limit Read/Write Low Limit

30h IN3 High Limit Read/Write High Limit

31h IN3 Low Limit Read/Write Low Limit

32h IN4(+) and IN5(-) High Limit Read/Write High Limit

33h IN4(+) and IN5(-) Low Limit Read/Write Low Limit

34h IN7(+) and IN6(-) High Limit Read/Write High Limit

35h IN7(+) and IN6(-) Low Limit Read/Write Low Limit

36h Reserved Read Only

37h Reserved Read Only

38h Temperature High Limit Read/Write High Limit

39h Temperature Hysteresis Limit Read/Write Hysteresis Limit

8.6.13 Manufacturer ID Register — Address 3Eh

Default Value [7:0] = 0000_0001 binary

Table 14. Address 3Eh

ADDRESS REGISTER NAME READ/WRITE REGISTER DESCRIPTION

3Eh Manufacturer ID Read Only Manufacturer's ID always defaults to 0000_0001.

8.6.14 Revision ID Register — Addresses 3Fh

Default Value [7:0] = 0000_1001 binary

Table 15. Addresses 3Fh

ADDRESS REGISTER NAME READ/WRITE REGISTER DESCRIPTION

3Fh Revision ID Read Only Revision's ID always defaults to 0000_1001.

Product Folder Links: ADC128D818

4095d

DOUT

'VIN

(VREF - 3VREF)

1V 2V

3200d

1600d

2(212)

ADC128D818

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Digital Output (DOUT)

The digital output code for a 12-bit ADC can be calculated as:

DOUT = [ΔVIN / VREF] × 212 (1)

For Equation 1,ΔVIN = INx – GND, where 0 ≤x≤7, for the single-ended configuration, and ΔVIN = (IN+ - IN–)

for the pseudo-differential configuration. In theory, ΔVIN can be of any value between 0 V and (VREF-3LSb/2).

Any ΔVIN value outside of this range will produce a digital output code of 0 or 4095. Figure 32 shows a

theoretical plot of DOUT vs. ΔVIN and some sample DOUT calculation using Equation 1.

Figure 32. DOUT vs ΔVIN for a 12-Bit ADC Assuming VREF = 2.56 V.

9.1.2 Temperature Measurement System

The ADC128D818 delta-VBE type temperature sensor and delta-sigma ADC perform 9-bit two's-complement

conversions of the temperature. This temperature reading can be obtained at the Temperature Reading Register

(address 27h). This register is 16-bit wide, and thus, all 9 bits of the temperature reading can be read using a

double byte read (Figure 29 or Figure 31). The following Figure 33 and Figure 33 show the theoretical output

code (DOUT) vs. temperature and some typical temperature-to-code conversions.

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Application Information (continued)

(Non-Linear Scale for Clarity)

Figure 33. 9-Bit Temperature-to-Digital Transfer Function

Table 16. Temperature Registers Sample Temperatures

DIGITAL OUTPUT (DOUT)

TEMP BINARY [MSb...LSb] DECIMAL HEX

+125°C 0 _1111_1010 250 0_FA

+25°C 0_0011_0010 50 0_32

+0.5°C 0_0000_0001 1 0_01

+0°C 0_0000_0000 0 0_00

−0.5°C 1_1111_1111 511 1_FF

−25°C 1_1100_1110 462 1_CE

−40°C 1_1011_0000 432 1_B0

In general, the easiest way to calculate the temperature (°C) is to use the following formulas:

If DOUT[MSb] = 0: + Temp(°C) = DOUT(dec) / 2 (2)

If DOUT[MSb] = 1: – Temp(°C) = [29– DOUT(dec)] / 2 (3)

9.1.2.1 Temperature Limits

One of the ADC128D818 features is monitoring the temperature reading. This monitoring is accomplished by

setting a temperature limit to the Temperature High Limit Register (Thot , address 38h) and Temperature

Hysteresis Limit Register (Thot_hyst, address 39h). When the temperature reading > Thot, an interrupt occurs. How

this interrupt occurs will be explained in Temperature Interrupt.

Each temperature limit is represented by an 8-bit, two's complement word with a least significant bit (LSb) equal

to 1°C. Table 17 shows some sample temperatures that can be programmed to the Temperature Limit Registers.

In general, use the following equations to calculate the digital code that represents the desired temperature limit:

If Temp Limit (°C) ≥0: Digital Code (dec) = Temp Limit(°C) (4)

If Temp Limit (°C) < 0: Digital Code (dec) = 28– |Temp Limit(°C)| (5)

Product Folder Links: ADC128D818

IN0 Watchdog

Interrupt

Status

Registers

Interrupt

Mask

Registers

IN1 Watchdog

IN2 Watchdog

IN3 Watchdog

IN4 Watchdog

IN5 Watchdog

IN6 Watchdog

IN7 Watchdog

TEMP Watchdog

INT_Clear

(00h[3])

INT

Enable

(00h[1])

INT

ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

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Table 17. Temperature Limit Registers Sample Temperatures

DIGITAL CODE

TEMP LIMIT BINARY [MSb...LSb] DECIMAL HEX

+125°C 0111_1101 125 7D

+25°C 0001_1001 25 19

+1.0°C 0000_0001 1 01

+0°C 0000_0000 0 00

−1.0°C 1111_1111 255 FF

−25°C 1110_1111 231 E7

−40°C 1101_1000 216 D8

9.1.3 Interrupt Structure

Figure 34. Interrupt Structure

Figure 34 shows the ADC128D818's Interrupt Structure.

NOTE

The number next to each bit name represents its register address and bit number. For

example, 'INT_Clear' (00h[3]) refers to bit 3 of register address 00h.

9.1.3.1 Interrupt Output (INT)

ADC128D818 generates an interrupt as a result of each of its internal WATCHDOG registers on the voltage and

temperature channels. In general, INT becomes active when all three scenarios, as depicted in Figure 34, occur:

1. 'INT_Clear' (00h[3]) = 0.

2. 'INT_Enable' (00h[1]) = 1 to enable interrupt output.

3. The voltage reading > the voltage high limit or ≤the voltage low limit, or the temperature reading > Thot.

9.1.3.2 Interrupt Clearing

Reading the Interrupt Status Register (addresses 01h) will output the contents of the register and clear the

updated by the round-robin monitoring loop.

Another method to clear the interrupt output pin, INT, is setting 'INT_Clear' bit (address 00h, bit 3) = 1. When this

bit is high, the ADC128D818 round-robin monitoring loop will stop.

Product Folder Links: ADC128D818

SDA

SCL

INT

IN7 (+)

I2C Interface and Control

Interrupt

Masking

and

Interrupt

Control

ADC128D818

12-bit

Delta-Sigma

ADC

Internal

VREF = +2.56V

Temperature

Sensor

Interrupt

Status

Registers

GND

VREF

V+

Single-Ended

Positive Voltage

LM94022

Shutdown DC-DC

10VIN VOUT

Margining

Voltage

IN0

IN1

IN2

IN3

Pseudo-Differential

Positive Voltage

IN4 (+)

IN5 (-)

IN6 (-)

RTRACE

ADC128D818

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SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

9.1.3.3 Temperature Interrupt

One of the ADC128D818 features is monitoring the temperature reading. This monitoring is accomplished by

setting a temperature limit to the Temperature High Limit Register (Thot , address 38h) and Temperature

Hysteresis Limit Register (Thot_hyst, address 39h). These limit registers have an interrupt mode, shown in

Figure 35, that operates in the following way: if the temperature reading > Thot, an interrupt will occur and will

remain active indefinitely until reset by reading the Interrupt Status Register (address 01h) or cleared by the

'INT_Clear' bit.

Once an interrupt event has occurred by crossing Thot, then reset, an interrupt will occur again once the next

temperature conversion has completed. The interrupts will continue to occur in this manner until the temperature

reading is ≤Thot_hyst and a read of the Interrupt Status Register has occurred.

Figure 35. Temperature Response Structure

(Assuming the Interrupt Output Pin, INT, is Reset Before the Next Temperature Reading)

9.2 Typical Application

Figure 36. Hardware Monitor Application

9.2.1 Design Requirements

In this typical hardware monitor application, several different sources are being monitored by the ADC128D818.

First, an external temperature sensor (LM94022) is being monitored. An external temperature sensor is

frequently used to monitor ambient temperature of the system.

Product Folder Links: ADC128D818

I+ = [(0.0168)(b)(I+_VOLTAGE)] + [(4.932)(10-3)(a)(I+_TEMP)]

+ [1 ± (4.932)(10-3)(a) ± 0.0168(b)](I+_SHUTDOWN)

ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

www.ti.com

Typical Application (continued)

9.2.2 Detailed Design Procedure

9.2.2.1 Power Management

To understand the average supply current (I+), the conversion rates must be introduced. ADC128D818 has three

types of conversion rates: Continuous Conversion Mode, Low Power Conversion Mode, and One Shot Mode. In

the Low Power Conversion Mode, the device converts all of the enabled channels then enters shutdown mode;

this process takes approximately 728 ms to complete. (More information on the conversion rate will be discussed

in the Conversion Rate Register — Address 07h and One-Shot Register — Address 09h sections).

Each type of conversion produces a different average supply current. The supply current for a voltage conversion

will be referred to as I+_VOLTAGE, a temperature conversion as I+_TEMP, and the shutdown mode as

I+_SHUTDOWN. These values can be obtained from Typical Performance Characteristics plots.

In general, I+ is the average supply current while ADC128D818 is operating in the Low Power Conversion Mode

with all of the available channels enabled. Its plot can be seen in Typical Characteristics and its equation,

Equation 6.

where

• a is the number of local temperature available.

• b is the number of ENABLED voltage channel. (6)

Each mode of operation has a different "a" and "b" values. The following table shows the value for "a" and the

maximum value for "b" for each mode.

Table 18. "A" and "B" Values

a b (MAX)

Mode 0 1 7

Mode 1 0 8

Mode 2 1 4

Mode 3 1 6

9.2.2.2 Using the ADC128D818

Table 19. ADC128D818 Internal Registers

READ/ DEFAULT REGISTER

WRITE VALUE [7:0] FORMAT

(HEX)

Configuration Register R/W 00h 0000_1000 Provides control and configuration 8-bit

Provides status of each WATCHDOG limit or interrupt

Interrupt Status Register R 01h 0000_0000 8-bit

event

Interrupt Mask Register R/W 03h 0000_0000 Masks the interrupt status from propagating to INT 8-bit

Conversion Rate Register R/W 07h 0000_0000 Controls the conversion rate 8-bit

Disables conversion for each voltage or temperature

Channel Disable Register R/W 08h 0000_0000 8-bit

channel

One-Shot Register W 09h 0000_0000 Initiates a single conversion of all enabled channels 8-bit

Deep Shutdown Register R/W 0Ah 0000_0000 Enables deep shutdown mode 8-bit

Advanced Configuration Selects internal or external VREF and modes of

R/W 0Bh 0000_0000 8-bit

Reflects the ADC128D818 'Busy' and 'Not Ready'

Busy Status Register R 0Ch 0000_0010 8-bit

statuses

Channel Readings R 20h - 27h - - - Report channels (voltage or temperature) readings 16-bit

Registers

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Table 19. ADC128D818 Internal Registers (continued)

READ/ DEFAULT REGISTER

WRITE VALUE [7:0] FORMAT

(HEX)

Set the limits for the voltage and temperature

Limit Registers R/W 2Ah - 39h - - - 8-bit

channels

Manufacturer ID Register R 3Eh 0000_0001 Reports the manufacturer's ID 8-bit

Revision ID Register R 3Fh 0000_1001 Reports the revision's ID 8-bit

9.2.2.2.1 Quick Start

1. Power on the device, then wait for at least 33ms.

2. Read the Busy Status Register (address 0Ch). If the 'Not Ready' bit = 1, then increase the wait time until 'Not

Ready' bit = 0 before proceeding to the next step.

3. Program the Advanced Configuration Register — Address 0Bh:

– a. Choose to use the internal or external VREF (bit 0).

– b. Choose the mode of operation (bits [2:1]).

4. Program the Conversion Rate Register (address 07h).

5. Choose to enable or disable the channels using the Channel Disable Register (address 08h).

6. Using the Interrupt Mask Register (address 03h), choose to mask or not to mask the interrupt status from

propagating to the interrupt output pin, INT.

7. Program the Limit Registers (addresses 2Ah – 39h).

8. Set the ‘START’ bit of the Configuration Register (address 00h, bit 0) to 1.

9. Set the 'INT_Clear' bit (address 00h, bit 3) to 0. If needed, program the 'INT_Enable' bit (address 00h, bit 1)

to 1 to enable the INT output.

The ADC128D818 then performs a round-robin monitoring of enabled voltage and temperature channels. The

sequence of items being monitored corresponds to locations in the Channel Readings Registers (except for the

temperature reading). Detailed descriptions of the register map can be found at the end of this data sheet.

9.2.2.2.2 Poweron Reset (POR)

When power is first applied, the ADC128D818 performs a power on reset (POR) on several of its registers, which

sets the registers to their default values. These default values are shown in Table 19 or in Register Maps.

Registers whose default values are not shown have power on conditions that are indeterminate.

9.2.2.2.3 Configuration Register (address 00h)

The Configuration Register (address 00h) provides all control to the ADC128D818. After POR, the 'START' bit

(bit 0) is set low and the 'INT_Clear' bit (bit 3) is set high.

The Configuration Register has the ability to start and stop the ADC128D818, enable and disable the INT output,

and set the registers to their default values.

• Bit 0, ‘START’, controls the monitoring loop of the ADC128D818. After POR, set this bit high to start

conversion. Setting this bit low stops the ADC128D818 monitoring loop and puts the ADC128D818 in

shutdown mode; thus, reducing power consumption. Even though this bit is set low, serial bus communication

is possible with any register in the ADC128D818.

– After an interrupt occurs, the INT pin will not be cleared if the user sets this bit low.

• Bit 1, 'INT_Enable', enables the interrupt output pin, INT, when this bit is set high.

• Bit 3, 'INT_Clear', clears the interrupt output pin, INT, when this bit is set high. When this bit is set high, the

ADC128D818 monitoring function will stop. The content of the Interrupt Status Register (address 01h) will not

be affected.

• Bit 7, ‘INITIALIZATION’, accomplishes the same function as POR, that is, it initializes some of the registers to

their default values. This bit automatically clears after being set high. Setting this bit high, however, does not

reset the Channel Readings Registers (addresses 20h - 27h) and the Limit Registers (addresses 2Ah - 39h).

These registers will be indeterminate immediately after power on. If the Channel Readings Registers contain

valid conversion results and/or the Limit Registers have been previously set, they will not be affected by this

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bit.

9.2.2.2.4 Interrupt Status Register (address 01h)

Each bit in this read-only register indicates whether the voltage reading > the voltage high limit or ≤the voltage

low limit, or the temperature reading > the temperature high limit. For example, if "IN0 High Limit" register

(address 2Ah) were set to 2 V and if IN0 reading (address 20h) were 2.56 V, then bit 'IN0 Error' would be 1,

indicating that the voltage high limit has been exceeded.

9.2.2.2.5 Interrupt Mask Register (address 03h)

This register masks the interrupt status from propagating to the interrupt output pin, INT. For example, if bit 'IN0

Mask' = 1, then the interrupt output pin, INT, would not be pulled low even if an error event occurs at IN0.

9.2.2.2.6 Conversion Rate Register (address 07h)

There are three options for controlling the conversion rate. The first option is called the Low Power Conversion

Mode, where the device converts all of the enabled channels then enters shutdown mode. This process takes

approximately 728 ms to complete.

The second option is the Continuous Conversion Mode, where the device continuously converts the enabled

channels, thus never entering shutdown mode. A voltage conversion takes 12.2 ms, and a temperature

conversion takes 3.6 ms. For example, if operating in mode 2 and three voltage channels were enabled, then

each round-robin monitor would take 40.2 ms (3 x 12.2ms + 3.6ms) to complete. Use the "Channel Disable

The third option is called the ON-Shot mode, which will be discussed in the next subsection.

9.2.2.2.7 One-Shot Register (address 09h)

The One-Shot register is used to initiate a single conversion and comparison cycle when the device is in

shutdown mode or deep shutdown mode, after which the device returns to the respective mode it was in. The

obvious advantage of using this mode is lower power consumption because the device is operating in shutdown

or deep shutdown mode.

This register is not a data register, and it is the write operation that causes the one-shot conversion. The data

written to this address is irrelevant and is not stored. A zero will always be read from this register.

9.2.2.2.8 Deep Shutdown Register (address 0Ah)

The ADC128D818 can be placed in deep shutdown mode, thus reducing more power consumption. The

procedures for deep shutdown entrance are:

1. Enter shutdown by setting the ‘START’ bit of the “Configuration Register’ (address 00h, bit 0) to 0.

2. Enter deep shutdown by setting the ‘DEEP SHUTDOWN’ bit (address 0Ah, bit 0) to 1.

3. A one-shot conversion can be triggered by writing any values to register address 09h.

Deep Shutdown Exit Procedure:

1. Set the ‘DEEP SHUTDOWN’ bit to 0.

9.2.2.2.9 Channel Readings Registers (addresses 20h - 27h)

The channel conversion readings are available in registers 20h to 27h. Each register is 16-bit wide to

accommodate the 12-bit voltage reading or 9-bit temperature reading. Conversions can be read at any time and

will provide the result of the last conversion. If a conversion is in progress while a communication is started, that

conversion will be completed, and the Channel Reading Registers will not be updated until the communication is

complete.

Product Folder Links: ADC128D818

SDA

SCL

IN0

ADC128D818

GND

V+

IN1

VREF

IN5-

LM4140 +

+0.1 PF

(optional)

Positive

Pseudo-

Differential

Input Voltage

Positive

Single-Ended

Input Voltage

VS1 INT

Microcontroller

GPO1

GPO2

GPO3

GPO4

RA_top

RA_bottom

R R

1 PF

0.1 PF

IN4+

VS2

VIN2 IN2

IN3

IN7+

IN6-

RTRACE

RA_top

RA_bottom

500.0 1.2k 1.9k 2.7k 3.4k 4.1k

CODE

TUE (%)

-0.020

-0.060

-0.100

-0.140

-0.180

-0.220

ADC128D818

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SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

9.2.3 Application Curve

Figure 37. Total Unadjusted Error

9.3 System Examples

9.3.1 General Voltage Monitoring

Figure 38. Typical Analog Input Application

A typical application for ADC128D818 is voltage monitoring. In this application, the inputs would most often be

connected to linear power supplies of 2.5-V, 3.3-V, ±5-V and ±12-V inputs. These inputs must be attenuated with

external resistors to any desired value within the input range. The attenuation is done with resistors R1 and R2

for the positive single-ended voltage, and R3 and R4 for the positive pseudo-differential voltage.

A typical single-ended application might select the input voltage divider to provide 1.9 V at the analog input of the

ADC128D818. This is sufficiently high for good resolution of the voltage, yet leaves headroom for upward

excursions from the supply of about 25%. To simplify the process of resistor selection, set the value of R2 first.

Select a value for R2 between 10 kΩand 100 kΩ. This is low enough to avoid errors due to input leakage

currents yet high enough to protect both the inputs under and overdrive conditions as well as minimize loading of

the source. Finally, calculate R1 to provide a 1.9-V input using simple voltage divider derived formula:

R1 = [(VS1 - VIN2) / VIN2 ] × R2 (7)

Product Folder Links: ADC128D818

Microcontroller

SDA

SCL

INT

IN0

ADC128D818

GND

V+

IN1

IN2

IN3

IN4+

VREF

IN5-

IN6

IN7

RB_top

LM4140 +

(optional)

+0.1 PF

SHUTDOWN DC-DC

10VIN

rgining Voltage V+

V+

RTRACE

RRR

RB_bottom

1 PF

1 PF0.1 PF

RB_top

RB_bottom

ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

www.ti.com

System Examples (continued)

Take care to bypass V+ with decoupling 0.1-µF ceramic capacitor and 1-µF tantalum capacitor. If using the

external reference option, VREF must be connected to a voltage reference, such as the LM4140, and must also

be decoupled to the ground plane by a 0.1-µF ceramic capacitor and a 1-µF tantalum capacitor. For both

supplies, the 0.1-µF capacitor must be located as close as possible to the ADC128D818.

Since SDA, SCL, and INT are open-drain pins, they must have external pullup resistors to ensure that the bus is

pulled high until a master device or slave device sinks enough current to pull the bus low. A typical pullup

resistor, R, ranges from 1.1 kΩto 10 kΩ. Refer to NXP's "I2C-Bus Specification and User Manual" for more

information on sizing R.

Because there are two tri-level address pins (A0 and A1), up to 9 devices can share the same I2C bus. A trick to

set these serial addresses uses four GPO (general purpose output) pins from the master device as shown in the

example diagram. Table 20 shows how to program these GPO pins.

Table 20. Setting Serial Bus Address Using GPO

A1 A0 GPO1 GPO2 GPO3 GPO4

LOW LOW Z LOW Z LOW

LOW MID Z LOW HIGH LOW

LOW HIGH Z LOW HIGH Z

MID LOW HIGH LOW Z LOW

MID MID HIGH LOW HIGH LOW

MID HIGH HIGH LOW HIGH Z

HIGH LOW HIGH Z Z LOW

HIGH MID HIGH Z HIGH LOW

HIGH HIGH HIGH Z HIGH Z

9.3.2 Voltage Monitoring for Power Supplies

Figure 39. Power Supply Application

Figure 39 shows a more complete systems application using a DC–DC converter. Such configuration can be

used in a power supply application. The point to make with this example diagram is the Serial Bus Address

connections. The previous example shows A0 and A1 connected to four GPOs, but this example shows a

simpler A0 and A1 connection using two resistor dividers. This connection accomplishes the same goal as the

GPO connection, that is, it can set A0 and A1 high, low, or to midscale.

Product Folder Links: ADC128D818

SDA

SCL

INT

IN0

ADC128D818

GND

V+

IN1

IN2

IN3

IN4

VREF

IN5

IN6

IN7

LM4140 +

(optional)

OUT

VDD

GND

LM94022

GS1

GS0

+0.1 PF

Microcontroller

RA_top GPO1

GPO2

GPO3

GPO4

RR R

RA_bottom

1 PF

1 PF0.1 PF

RA_top

RA_bottom

ADC128D818

www.ti.com

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

For example, to set A0 high, don't populate RB_bottom; to set A0 low, don't populate RB_top; and to set A0 to

midscale, leave RB_top and RB_bottom as is and set them equal to each other. A typical RB value ranges from

1 kOhm to 10 kOhm.

9.3.3 Temperature Sensors

Figure 40. Temperature Sensor Applications

An external temperature sensor can be connected to any of ADC128D818's eight single-ended input for

additional temperature sensing. One such temperature sensor can be TI's LM94022, a precision analog

temperature sensor with selectable gains. The application diagram shows LM94022's gains (GS1 and GS0) both

grounded indicating the lowest gain setting. Four possible gains can be set using these GS1 and GS0 pins.

According to the LM94022 data sheet (SNIS140), the voltage-to-temperature output plot can be determined using

the method of linear approximation as follows:

V – V1 = (V2 – V1) / (T2 – T1) × (T – T1)

where

• V is in mV

• T is in °C

• V1 and T1 are the coordinates of the lowest temperature

• and T2 and V2 are the coordinates of the highest temperature. (8)

For example, to determine the equation of a line over a temperature range of 20°C to 50°C, first find V1 and V2

relative to those temperatures, then use Equation 8 to find the transfer function.

V – 925 mV = (760 mV – 925 mV) / (50°C – 20°C) × (T – 20°C) (9)

V = (–5.50 mV /°C) × T + 1035 mV (10)

For more information and explanation of this example, refer to the LM94022 (SNIS140) data sheet.

Product Folder Links: ADC128D818

SDA

SCL

INT

IN0

ADC128D818

GND

V+

IN1

IN2

IN3

IN4

VREF

IN5

IN6

IN7

LM4140 +

+0.1 PF

Bridge Sensor

Instrumentation

Op-Amp

Microcontroller

V+

RB_top

RRR

RB_bottom

R2 R2

1 PF

0.1 PF

1 PF

RB_top

RB_bottom

ADC128D818

SNAS483F –FEBRUARY 2010–REVISED AUGUST 2015

www.ti.com

9.3.4 Bridge Sensors

Figure 41. Bridge Sensor Application

ADC128D818 is perfect for transducer applications such as pressure sensors. These sensors measure pressure

of gases or liquids and produce a pressure-equivalent voltage at their outputs. Figure 41 shows a typical

connection of a pressure sensor, represented by the bridge sensor.

Most pressure sensor has a low sensitivity characteristic, which means its output is typically in the millivolts

range. Because of that reason, an op-amp, such as an instrumentation amplifier, can be used for the gain stage.

The positive aspect of this configuration is its ratiometric connection. A ratiometric connection is when the ADC’s

VREF and GND are connected to the bridge sensor’s voltage references. With a ratiometric configuration,

external VREF accuracy can be ignored.

10 Power Supply Recommendations