Dual-Channel Isolators with Integrated DC-to-DC Converters ADuM5210/ADuM5211/ADuM5212 Data Sheet FUNCTIONAL BLOCK DIAGRAM isoPower integrated, isolated dc-to-dc converter Regulated 3.15 V to 5.25 V output Up to 150 mW output power Dual dc-to-100 Mbps (NRZ) signal isolation channels Soft start power supply 20-lead SSOP package with 5.3 mm creepage Supports SPI up to 15 MHz High temperature operation: 105C High common-mode transient immunity: >25 kV/s Safety and regulatory approvals UL recognition (pending) 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak VDD1 1 20 VDD2 GNDP 2 19 GNDISO 2-CHANNEL iCoupler CORE VIA/VOA 3 18 VOA/VIA ADuM5210/ADuM5211/ ADuM5212 VIB/VOB 4 17 VOB/VIB GNDP 5 16 GNDISO GNDP 6 15 GNDISO NC 7 14 NC PCS PDIS 8 13 VSEL VDDP 9 1.25V 12 VISO GNDP 10 OSC RECT REG 11 GNDISO 10980-001 FEATURES Figure 1. ADuM5210/ADuM5211/ADuM5212 APPLICATIONS RS-232 transceivers Power supply start-up bias and gate drives Isolated sensor interfaces Industrial PLCs GENERAL DESCRIPTION The ADuM5210/ADuM5211/ADuM52121 are dual-channel digital isolators with isoPower(R), an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler(R) technology, the dc-todc converter provides regulated, isolated power that is adjustable between 3.15 V and 5.25 V. Input supply voltages can range from slightly below the required output to significantly higher. Popular voltage combinations and their associated power levels are shown in Table 2. Table 1. Data I/O Port Assignments The ADuM5210/ADuM5211/ADuM5212 eliminate the need for a separate, isolated dc-to-dc converter in low power, isolated designs. The iCoupler chip-scale transformer technology is used for isolated logic signals and for the magnetic components of the dc-to-dc converter. The result is a small form factor, total isolation solution. Table 2. Power Levels Channel VIA/VOA VIB/VOB VOA/VIA VOB/VIB Pin 3 4 18 17 Input Voltage (V) 5 5 3.3 ADuM5210 VIA VIB VOA VOB ADuM5211 VOA VIB VIA VOB Output Voltage (V) 5 3.3 3.3 ADuM5212 VOA VOB VIA VIB Output Power (mW) 150 100 66 isoPower uses high frequency switching elements to transfer power through its transformer. Take special care during printed circuit board (PCB) layout to meet emissions standards. See the AN-0971 Application Note for board layout recommendations. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADuM5210/ADuM5211/ADuM5212 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .................................... 10 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 11 Functional Block Diagram .............................................................. 1 ESD Caution................................................................................ 11 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 12 Revision History ............................................................................... 2 Truth Table .................................................................................. 15 Specifications..................................................................................... 3 Typical Performance Characteristics ........................................... 16 Electrical Characteristics--5 V Primary Input Supply/ 5 V Secondary Isolated Supply ................................................... 3 Applications Information .............................................................. 19 Electrical Characteristics--3.3 V Primary Input Supply/ 3.3 V Secondary Isolated Supply ................................................ 5 Thermal Analysis ....................................................................... 20 Electrical Characteristics--5 V Primary Input Supply/ 3.3 V Secondary Isolated Supply ................................................ 7 EMI Considerations ................................................................... 20 Package Characteristics ............................................................... 9 Regulatory Approvals................................................................... 9 Insulation and Safety-Related Specifications ............................ 9 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 10 PCB Layout ................................................................................. 19 Propagation Delay Parameters ................................................. 20 DC Correctness and Magnetic Field Immunity........................... 20 Power Consumption .................................................................. 21 Insulation Lifetime ..................................................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 REVISION HISTORY 4/15--Rev. A to Rev. B Changes to Table 25 ........................................................................ 15 5/13--Rev. 0 to Rev. A Added Table 1, Renumbered Sequentially .................................... 1 Changes to Table 3 ............................................................................ 3 1/13--Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 SPECIFICATIONS ELECTRICAL CHARACTERISTICS--5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY All typical specifications are at TA = 25C, VDD1 = VDD2 = VDDP = 5 V, VSEL resistor network: R1 = 10 k, R2 = 30.9 k between VISO and GNDISO. Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V VDD1, VDD2, VDDP 5.5 V and -40C TA +105C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 3. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Setpoint Thermal Coefficient Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Pulse-Width Modulation Frequency Output Supply Efficiency at IISO (MAX) IDDP, No VISO Load IDDP, Full VISO Load Thermal Shutdown Shutdown Temperature Thermal Hysteresis Symbol Min VISO VISO (TC) VISO (LINE) VISO (LOAD) VISO (RIP) VISO (NOISE) fOSC fPWM IISO (MAX) Typ Max 5.0 -44 20 1.3 75 200 125 600 3 30 29 6.8 104 IDDP (Q) IDDP (MAX) 12 154 10 Unit Test Conditions/Comments V V/C mV/V % mV p-p mV p-p MHz kHz mA % mA mA IISO = 15 mA, R1 = 10 k, R2 = 30.9 k IISO = 15 mA, VDDP = 4.5 V to 5.5 V IISO = 3 mA to 27 mA 20 MHz bandwidth, CBO = 0.1 F||10 F, IISO = 27 mA CBO = 0.1 F||10 F, IISO = 27 mA 5.5 V > VISO > 4.5 V IISO = 27 mA C C Table 4. Data Channel Supply Current Parameter SUPPLY CURRENT ADuM5210 ADuM5211 ADuM5212 Symbol 1 Mbps--A, B, C Grades Min Typ Max IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 1.1 2.7 2.1 2.3 2.7 1.1 25 Mbps--B, C Grades Min Typ Max 1.6 4.5 2.7 2.9 4.5 1.6 6.2 4.8 4.9 4.7 4.8 6.2 100 Mbps--C Grade Min Typ Max Unit Test Conditions/ Comments 20 9.5 15 15.6 9.5 20 mA mA mA mA mA mA CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF 7.0 7.0 6.5 6.5 7.0 7.0 25 15 19 19 15 25 Table 5. Switching Specifications Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Pulse Width Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter Symbol tPHL, tPLH PWD PW tPSK Min A Grade Typ Max Min B Grade Typ Max 1 50 10 1000 25 35 3 40 tPSKCD tPSKOD 2 Min 13 C Grade Typ Max 18 100 24 2 10 38 12 9 5 10 3 6 2 5 2 Rev. B | Page 3 of 24 1 Unit Test Conditions/ Comments Mbps ns ns ns ns Within PWD limit 50% input to 50% output |tPLH - tPHL| Within PWD limit Between any two units ns ns ns ADuM5210/ADuM5211/ADuM5212 Data Sheet Table 6. Input and Output Characteristics Parameter DC SPECIFICATIONS Logic High Input Threshold Symbol Min VIH 0.7 VISO, 0.7 VDD1 Logic Low Input Threshold VIL Logic High Output Voltages VOH Logic Low Output Voltages Undervoltage Lockout Positive Going Threshold Negative Going Threshold Hysteresis Supply Current per Channel Quiescent Input Supply Current Quiescent Output Supply Current Dynamic Input Supply Current Dynamic Output Supply Current Input Currents per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Typ Max VOL V VDD1, VDD2 V IOx = -20 A, VIx = VIxH VDD1 - 0.2, VDD2 - 0.2 0.0 0.2 V IOx = -4 mA, VIx = VIxH V V IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL VDD1, VDD2 ,VDDP supply 0.1 0.4 VUV+ VUV- VUVH 2.6 2.4 0.2 IDDI(Q) IDDO(Q) IDDI(D) IDDO(D) II -10 0.54 1.6 0.09 0.04 +0.01 tR/tF |CM| 25 2.5 35 ns kV/s 1.6 s tr Test Conditions/Comments V 0.3 VISO, 0.3 VDD1 VDD1 - 0.1, VDD2 - 0.1 VDD1 - 0.4, VDD2 - 0.4 Unit V V V 0.8 2.0 +10 mA mA mA/Mbps mA/Mbps A 0 V VIx VDDx 10% to 90% VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 x VDD1 or 0.8 x VISO for a high input or VOx < 0.8 x VDD1 or 0.8 x VISO for a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 4 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 ELECTRICAL CHARACTERISTICS--3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY All typical specifications are at TA = 25C, VDD1 =VDD2 = VDDP = 3.3 V, VSEL resistor network: R1 = 10 k, R2 = 16.9 k between VISO and GNDISO. Minimum/maximum specifications apply over the entire recommended operation range, which is 3.0 V VDD1, VDD2, VDDP 3.6 V, and -40C TA +105C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. The digital isolator channels and the power section work independently, and under the operating voltages in this section, there may not be sufficient current from the VISO to run both data channels at the maximum data rate. Verify that the application is within the power capability of VISO if that supply is providing power to VDD2. Table 7. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Setpoint Thermal Coefficient Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Pulse-Width Modulation Frequency Output Supply Efficiency at IISO (MAX) IDDP, No VISO Load IDDP, Full VISO Load Thermal Shutdown Shutdown Temperature Thermal Hysteresis Symbol Min VISO VISO (TC) VISO (LINE) VISO (LOAD) VISO (RIP) VISO (NOISE) fOSC fPWM IISO (MAX) Typ 3.3 -26 20 1.3 50 130 125 600 Max 3 20 27 3.3 77 IDDP (Q) IDDP (MAX) 10.5 154 10 Unit Test Conditions/Comments V V/C mV/V % mV p-p mV p-p MHz kHz mA % mA mA IISO = 10 mA, R1 = 10 k, R2 = 16.9 k IISO = 20 mA IISO = 10 mA, VDDP = 3.0 V to 3.6 V IISO = 2 mA to 18 mA 20 MHz bandwidth, CBO = 0.1 F||10 F, IISO = 18 mA CBO = 0.1 F||10 F, IISO = 18 mA 3.6 V > VISO > 3 V IISO = 18 mA C C Table 8. Data Channel Supply Current Parameter SUPPLY CURRENT ADuM5210 ADuM5211 ADuM5212 Symbol 1 Mbps--A, B, C Grades Min Typ Max IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 0.75 2.0 1.6 1.7 2.0 0.75 25 Mbps--B, C Grades Min Typ Max 5.1 2.7 3.8 3.9 2.7 5.1 1.4 3.5 2.1 2.3 3.5 1.4 100 Mbps--C Grade Min Typ Max 9.0 4.6 5.0 6.2 4.6 9.0 17 4.8 11 11 4.8 17 23 9 15 15 9 23 Unit Test Conditions/ Comments mA mA mA mA mA mA CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF Table 9. Switching Specifications Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Pulse Width Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter Symbol tPHL, tPLH PWD PW tPSK A Grade B Grade Min Typ Max Min Typ Max 1 50 10 1000 25 35 3 40 tPSKCD tPSKOD 2 C Grade Min Typ Max 20 25 100 33 2.5 10 38 16 12 5 10 3 6 2.5 5 2 Rev. B | Page 5 of 24 1 Unit Test Conditions/Comments Mbps ns ns ns ns Within PWD limit 50% input to 50% output |tPLH - tPHL| Within PWD limit Between any two units ns ns ns ADuM5210/ADuM5211/ADuM5212 Data Sheet Table 10. Input and Output Characteristics Parameter DC SPECIFICATIONS Logic High Input Threshold Min VIH 0.7 VISO, 0.7 VDD1 Logic Low Input Threshold VIL Logic High Output Voltages VOH Logic Low Output Voltages Undervoltage Lockout Positive Going Threshold Negative Going Threshold Hysteresis Supply Current per Channel Quiescent Input Supply Current Quiescent Output Supply Current Dynamic Input Supply Current Dynamic Output Supply Current Input Currents per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Symbol Typ Max VOL V VDD1, VDD2 V IOx = -20 A, VIx = VIxH VDD1 - 0.2, VDD2 - 0.2 0.0 0.2 V IOx = -4 mA, VIx = VIxH V V IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL VDD1, VDD2 ,VDDP supply 0.1 0.4 VUV+ VUV- VUVH 2.6 2.4 0.2 IDDI(Q) IDDO(Q) IDDI(D) IDDO(D) II -10 0.4 1.2 0.08 0.015 +0.01 tR/tF |CM| 25 3 35 ns kV/s 1.6 s tr Test Conditions/Comments V 0.3 VISO, 0.3 VDD1 VDD1 - 0.1, VDD2 - 0.1 VDD1 - 0.4, VDD2 - 0.4 Unit V V V 0.6 1.7 +10 mA mA mA/Mbps mA/Mbps A 0 V VIx VDDx 10% to 90% VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 x VDD1 or 0.8 x VISO for a high input or VOx < 0.8 x VDD1 or 0.8 x VISO for a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 6 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 ELECTRICAL CHARACTERISTICS--5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY All typical specifications are at TA = 25C, VDD1 = VDDP = 5 V, VDD2 = 3.3 V, VSEL resistor network: R1 = 10 k, R2 = 16.9 k between VISO and GNDISO. Minimum/maximum specifications apply over the entire recommended operation range which is 4.5 V VDD1, VDDP 5.5 V, 3.0 V VDD2 3.6 V, and -40C TA +105C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 11. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Setpoint Thermal Coefficient Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Pulse Width Modulation Frequency Output Supply Efficiency at IISO (MAX) IDDP, No VISO Load IDDP, Full VISO Load Thermal Shutdown Shutdown Temperature Thermal Hysteresis Symbol Min VISO VISO (TC) VISO (LINE) VISO (LOAD) VISO (RIP) VISO (NOISE) fOSC fPWM IISO (MAX) Typ Max 3.3 -26 20 1.3 50 130 125 600 3 30 24 3.2 85 IDDP (Q) IDDP (MAX) 8 154 10 Unit Test Conditions/Comments V V/C mV/V % mV p-p mV p-p MHz kHz mA % mA mA IISO = 15 mA, R1 = 10 k, R2 = 16.9 k IISO = 15 mA, VDDP = 4.5 V to 5.5 V IISO = 3 mA to 27 mA 20 MHz bandwidth, CBO = 0.1 F||10 F, IISO = 27 mA CBO = 0.1 F||10 F, IISO = 27 mA 3.6 V > VISO > 3 V IISO = 27 mA C C Table 12. Data Channel Supply Current Parameter SUPPLY CURRENT ADuM5210 ADuM5211 ADuM5212 Symbol 1 Mbps--A, B, C Grades Min Typ Max IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 1.1 2.0 2.1 1.7 2.0 1.1 25 Mbps--B, C Grades Min Typ Max 6.2 2.7 4.9 3.9 2.7 6.2 1.6 3.5 2.7 2.3 3.5 1.6 100 Mbps--C Grade Min Typ Max 20 4.8 15 11 4.8 20 7.0 4.6 6.5 6.2 4.6 7.0 25 9.0 19 15 9.0 25 Unit Test Conditions/ Comments mA mA mA mA mA mA CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF Table 13. Switching Specifications 7 Codirectional channel matchi ng is the absol ute value of the difference in propa gation delays betwee n any two c hannels with i nputs on the same side of the isolati on barrier. Opposing-directional channel matching is the abs olute val ue of the differe nce in propagati on delays betwee n any two c hannels wit h inputs on opposi ng sides of the is olation barrier. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Pulse Width Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter Symbol tPHL, tPLH PWD PW tPSK Min A Grade Typ Max Min B Grade Typ Max 1 50 10 1000 25 35 3 40 tPSKCD tPSKOD 2 Min 13 C Grade Typ Max 20 100 26 2.5 10 38 16 12 5 10 3 6 2 5 2 Rev. B | Page 7 of 24 1 Unit Test Conditions/ Comments Mbps ns ns ns ns Within PWD limit 50% input to 50% output |tPLH - tPHL| Within PWD limit Between any two units ns ns ns ADuM5210/ADuM5211/ADuM5212 Data Sheet Table 14. Input and Output Characteristics Parameter DC SPECIFICATIONS Logic High Input Threshold Min VIH 0.7 VISO, 0.7 VDD1 Logic Low Input Threshold VIL Logic High Output Voltages VOH Logic Low Output Voltages Undervoltage Lockout Positive Going Threshold Negative Going Threshold Hysteresis Supply Current per Channel Quiescent Input Supply Current Quiescent Output Supply Current Dynamic Input Supply Current Dynamic Output Supply Current Input Currents per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Symbol Typ Max VDD1 - 0.1, VDD2 - 0.1 VDD1 - 0.4, VDD2 - 0.4 V VDD1, VDD2 V IOx = -20 A, VIx = VIxH VDD1 - 0.2, VDD2 - 0.2 0.0 0.2 V IOx = -4 mA, VIx = VIxH V V IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL VDD1, VDD2 ,VDDP supply 0.1 0.4 VUV+ VUV- VUVH 2.6 2.4 0.2 IDDI(Q) IDDO(Q) IDDI(D) IDDO(D) II -10 0.54 1.2 0.09 0.02 +0.01 tR/tF |CM| 25 2.5 35 ns kV/s 1.6 s tr Test Conditions/Comments V 0.3 VISO, 0.3 VDD1 VOL Unit V V V 0.75 2.0 +10 mA mA mA/Mbps mA/Mbps A 0 V VIx VDDx 10% to 90% VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 x VDD1 or 0.8 x VISO for a high input or VOx < 0.8 x VDD1 or 0.8 x VISO for a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 8 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 PACKAGE CHARACTERISTICS Table 15. Thermal and Isolation Characteristics Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 Input Capacitance2 IC Junction-to-Ambient Thermal Resistance Symbol RI-O CI-O CI JA Min Typ 1012 2.2 4.0 50 Max Unit pF pF C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces3 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together. Input capacitance is from any input data pin to ground. 3 See the Thermal Analysis section for thermal model definitions. 1 2 REGULATORY APPROVALS Table 16. UL (Pending)1 Recognized under 1577 Component Recognition Program1 Single Protection, 2500 V RMS Isolation Voltage File E214100 CSA (Pending) Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage File 205078 VDE (Pending)2 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, 560 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM5210/ADuM5211/ADuM5212 is proof tested by applying an insulation test voltage 3000 V rms for 1 second (current leakage detection limit = 10 A). 2 In accordance with DIN V VDE V 0884-10, each ADuM5210/ADuM5211/ADuM5212 is proof tested by applying an insulation test voltage 1590 V peak for 1 second (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. 1 INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 17. Critical Safety-Related Dimensions and Material Properties Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Value 2500 L(I01) 5.3 Unit Test Conditions/Comments V rms 1-minute duration mm Measured from input terminals to output terminals, shortest distance through air 5.3 mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Distance through insulation >400 V DIN IEC 112/VDE 0303, Part 1 II Material group (DIN VDE 0110, 1/89, Table 1) Minimum External Tracking (Creepage) L(I02) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Rev. B | Page 9 of 24 ADuM5210/ADuM5211/ADuM5212 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval. Table 18. VDE Characteristics Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 Test Conditions/Comments VIORM x 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 VIORM x 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM x 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values Case Temperature Safety Total Dissipated Power Insulation Resistance at TS VIOSM(TEST) = 10 kV, 1.2 s rise time, 50 s, 50% fall time Maximum value allowed in the event of a failure (see Figure 2) VIO = 500 V Symbol Characteristic Unit VIORM Vpd(m) I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak Vpd(m) 840 V peak Vpd(m) 672 V peak VIOTM VIOSM 3535 4000 V peak V peak TS IS1 RS 150 2.5 >109 C W 3.0 SAFE LIMITING POWER (W) 2.5 2.0 1.5 1.0 0 0 50 100 150 AMBIENT TEMPERATURE (C) 200 10980-002 0.5 Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-10 RECOMMENDED OPERATING CONDITIONS Table 19. Parameter Operating Temperature1 Supply Voltages2 VDDP at VISO = 3.0 V to 3.6 V VDDP at VISO = 4.5 V to 5.5 V VDD1, VDD2 1 2 Symbol TA Min -40 Max +105 Unit C VDDP 3.0 4.5 2.7 5.5 5.5 5.5 V V V VDD1, VDD2 Operation at 105C requires reduction of the maximum load current as specified in Table 20. Each voltage is relative to its respective ground. Rev. B | Page 10 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 20. Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VDDP, VDD1, VDD2, VISO)1 VISO Supply Current2 TA = -40C to +105C Input Voltage (VIA, VIB, PDIS, VSEL)1, 3 Output Voltage ( VOA, VOB )1, 3 Average Output Current Per Data Output Pin4 Common-Mode Transients5 Rating -55C to +150C -40C to +105C -0.5 V to +7.0 V Table 21. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1 30 mA -0.5 V to VDDI + 0.5 V -0.5 V to VDDO + 0.5 V -10 mA to +10 mA -100 kV/s to +100 kV/s All voltages are relative to their respective ground. The VISO provides current for dc and dynamic loads on the VISO I/O channels. This current must be included when determining the total VISO supply current. For ambient temperatures between 85C and 105C, maximum allowed current is reduced. 3 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PCB Layout section. 4 See Figure 2 for the maximum rated current values for various temperatures. 5 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. 1 2 Parameter AC Voltage Bipolar Waveform Max Unit 560 V peak Unipolar Waveform DC Voltage |DC Peak Voltage| 560 V peak 560 V peak 1 Applicable Certification All certifications, 50-year operation Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. ESD CAUTION Rev. B | Page 11 of 24 ADuM5210/ADuM5211/ADuM5212 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 20 VDD2 GNDP 2 19 GNDISO VIA 3 GNDP 5 GNDP 6 NC 7 18 VOA ADuM5210 TOP VIEW (Not to Scale) 17 VOB 16 GNDISO 15 GNDISO 14 NC PDIS 8 13 VSEL VDDP 9 12 GNDP 10 VISO 11 GNDISO NOTES 1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. 10980-003 VIB 4 Figure 3. ADuM5210 Pin Configuration Table 22. ADuM5210 Pin Function Descriptions Pin No. 1 Mnemonic Description VDD1 Power Supply for the Side 1 Logic Circuits of the Device. It is independent of VDDP and can operate between 3.0 V and 5.5 V. 2, 5, 6, 10 GNDP Ground Reference for Isolator Side 1. All of these pins are internally connected, and it is recommended that all GNDP pins be connected to a common ground. 3 VIA Logic Input A. 4 VIB Logic Input B. 7, 14 NC This pin is not connected internally (see Figure 3). 8 PDIS Power Disable. When this pin is tied to a logic low, the power converter is active; when tied to a logic high, the power supply enters a low power standby mode. 9 VDDP Primary isoPower Supply Voltage, 3.0 V to 5.5 V. 11, 15, 16, 19 GNDISO Ground Reference for Isolator Side 2. All of these pins are internally connected, and it is recommended that all GNDISO pins be connected to a common ground. 12 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High). 13 VSEL Output Voltage Select. Provide a thermally matched resistor network between VISO and GNDISO to divide the required output voltage to match the 1.25 V reference voltage. VISO voltage can be programmed up to 20% higher or 75% lower than VDDP but must be within the allowed output voltage range. 17 VOB Logic Output B. 18 VOA Logic Output A. 20 VDD2 Power Supply for the Side 2 Logic Circuits of the Device. It is independent of VISO and can operate between 3.0 V and 5.5 V. Rev. B | Page 12 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 VDD1 1 20 VDD2 GNDP 2 19 GNDISO VOA 3 18 VIA VIB 4 17 VOB 16 GNDISO GNDP 6 ADuM5211 TOP VIEW (Not to Scale) 15 GNDISO NC 7 14 NC PDIS 8 13 VSEL VDDP 9 12 GNDP 10 11 VISO GNDISO NOTES 1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. 10980-005 GNDP 5 Figure 4. ADuM5211 Pin Configuration Table 23. ADuM5211 Pin Function Descriptions Pin No. 1 Mnemonic Description VDD1 Power Supply for the Side 1 Logic Circuits of the Device. It is independent of VDDP and can operate between 3.0 V and 5.5 V. 2, 5, 6, 10 GNDP Ground Reference for Isolator Side 1. All of these pins are internally connected, and it is recommended that all GNDP pins be connected to a common ground. 3 VOA Logic Output A. 4 VIB Logic Input B. 7, 14 NC This pin is not connected internally (see Figure 4). 8 PDIS Power Disable. When this pin is tied to a logic low, the power converter is active; when tied to a logic high, the power supply enters a low power standby mode. 9 VDDP Primary isoPower Supply Voltage, 3.0 V to 5.5 V. 11, 15, 16,19 GNDISO Ground Reference for Isolator Side 2. All of these pins are internally connected, and it is recommended that all GNDISO pins be connected to a common ground. 12 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High). 13 VSEL Output Voltage Select. Provide a thermally matched resistor network between VISO and GNDISO to divide the required output voltage to match the 1.25 V reference voltage. VISO voltage can be programmed up to 20% higher or 75% lower than VDDP but must be within the allowed output voltage range. 17 VOB Logic Output B. 18 VIA Logic Input A. 20 VDD2 Power Supply for the Side 2 Logic Circuits of the Device. It is independent of VISO and can operate between 3.0 V and 5.5 V. Rev. B | Page 13 of 24 ADuM5210/ADuM5211/ADuM5212 Data Sheet VDD1 1 20 VDD2 GNDP 2 19 GNDISO VOA 3 GNDP 5 GNDP 6 NC 7 18 VIA ADuM5212 TOP VIEW (Not to Scale) 17 VIB 16 GNDISO 15 GNDISO 14 NC PDIS 8 13 VSEL VDDP 9 12 GNDP 10 VISO 11 GNDISO NOTES 1. PINS LABELED NC CAN BE ALLOWED TO FLOAT OR CAN BE CONNECTED TO THE GROUND. AVOID CONNECTING THEM TO HIGH SPEED SIGNALS TO MINIMIZE CAPACITIVE COUPLING OF NOISE. 10980-007 VOB 4 Figure 5. ADuM5212 Pin Configuration Table 24. ADuM5212 Pin Function Descriptions Pin No. 1 Mnemonic Description VDD1 Power Supply for the Side 1 Logic Circuits of the Device. It is independent of VDDP and can operate between 3.0 V and 5.5 V. 2, 5, 6, 10 GNDP Ground Reference for Isolator Side 1. All of these pins are internally connected, and it is recommended that all GNDP pins be connected to a common ground. 3 VOA Logic Output A. 4 VOB Logic Output B. 7, 14 NC This pin is not connected internally (see Figure 5). 8 PDIS Power Disable. When this pin is tied to a logic low, the power converter is active; when tied to a logic high, the power supply enters a low power standby mode. 9 VDDP Primary isoPower Supply Voltage, 3.0 V to 5.5 V. 11, 15, 16, 19 GNDISO Ground Reference for Isolator Side 2. All of these pins are internally connected, and it is recommended that all GNDISO pins be connected to a common ground. 12 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High). 13 VSEL Output Voltage Select. Provide a thermally matched resistor network between VISO and GNDISO to divide the required output voltage to match the 1.25 V reference voltage. VISO voltage can be programmed up to 20% higher or 75% lower than VDDP but must be within the allowed output voltage range. 17 VIB Logic Input B. 18 VIA Logic Input A. 20 VDD2 Power Supply for the Side 2 Logic Circuits of the Device. It is independent of VISO and can operate between 3.0 V and 5.5 V. Rev. B | Page 14 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 TRUTH TABLE Table 25. Power Section Truth Table (Positive Logic) VDDP (V) 5 5 3.3 3.3 5 5 3.3 3.3 VSEL Input R1 = 10 k, R2 = 30.9 k R1 = 10 k, R2 = 30.9 k R1 = 10 k, R2 = 16.9 k R1 = 10 k, R2 = 16.9 k R1 = 10 k, R2 = 16.9 k R1 = 10 k, R2 = 16.9 k R1 = 10 k, R2 = 30.9 k R1 = 10 k, R2 = 30.9 k PDIS Input Low High Low High Low High Low High VISO Output (V) 5 0 3.3 0 3.3 0 5 0 Notes Configuration not recommended Table 26. Data Section Truth Table (Positive Logic) VDDI State1 Powered Powered X2 Unpowered Unpowered VIx Input1 High Low X2 Low High VDDO State1 Powered Powered Unpowered Powered Powered VOx Output1 High Low Z3 Low Indeterminate Notes Normal operation, data is high Normal operation, data is low Output is off Output default low If a high level is applied to an input when no supply is present, then it can parasitically power the input side causing unpredictable operation The references to I and O in this table refer to the input side and output side of a given data path and the associated power supply. X = don't care. 3 Z = high impedance state. 1 2 Rev. B | Page 15 of 24 ADuM5210/ADuM5211/ADuM5212 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.8 0.25 0.20 0.15 0.10 0.45 0.40 1.6 0.35 1.4 0.30 1.0 0.25 0.8 0.20 0.6 0.15 0.4 0.05 VDD1 = VDDP = 5V/VDD2 = 5V VDD1 = VDDP = 5V/VDD2 = 3.3V VDD1 = VDDP = 3.3V/VDD2 = 3.3V 0 0.02 0.04 0.06 0.10 0.2 0.08 LOAD CURRENT (A) Figure 6. Typical Power Supply Efficiency at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V 0.05 0 3.0 10980-004 0 3.5 4.0 4.5 VDD1 (V) 5.0 5.5 0 6.0 Figure 9. Typical Short-Circuit Input Current and Power vs. VDD1 Supply Voltage VISO (100mV/DIV) 450 350 300 250 200 150 90% LOAD 100 VDD1 = VDDP = 5V/VDD2 = 5V VDD1 = VDDP = 5V/VDD2 = 3.3V VDD1 = VDDP = 3.3V/VDD2 = 3.3V 10% LOAD 0 10 20 30 10980-006 0 40 IISO (mA) Figure 7. Typical Total Power Dissipation vs. IISO (1ms/DIV) 10980-010 POWER DISSIPATION (mW) 400 50 Figure 10. Typical VISO Transient Load Response, 5 V Output, 10% to 90% Load Step 35 VISO (100mV/DIV) VDD1 = VDDP = 5V/VDD2 = 5V VDD1 = VDDP = 5V/VDD2 = 3.3V VDD1 = VDDP = 3.3V/VDD2 = 3.3V 30 IISO (mA) 25 20 15 90% LOAD 10 10% LOAD 25 50 IDDP (mA) 75 100 10980-008 0 (1ms/DIV) Figure 11. Typical Transient Load Response, 3 V Output, 10% to 90% Load Step Figure 8. Typical Isolated Output Supply Current, IISO, as a Function of External Load, at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V Rev. B | Page 16 of 24 10980-011 5 0 IDDP CURRENT (A) POWER DISSIPATION (W) EFFICIENCY (%) 0.30 0.50 IDDP POWER DISSIPATION 10980-009 0.35 Data Sheet ADuM5210/ADuM5211/ADuM5212 VISO (100mV/DIV) 5.0 4.0 3.5 3.0 30mA LOAD 20mA LOAD 10mA LOAD 10980-013 2.5 (1ms/DIV) 2.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT VOLTAGE (V) 10980-115 MINIMUM INPUT VOLTAGE (V) 4.5 Figure 15. Relationship Between Output Voltage and Required Input Voltage, Under Load, to Maintain >80% Duty Factor in the PWM Figure 12. Typical Transient Load Response, 5 V Input, 3.3 V Output, 10% to 90% Load Step 4.970 500 VDD1 = VDDP = 5V/VDD2 = 5V 450 VDD1 = VDDP = 5V/VDD2 = 3.3V POWER DISSIPATION (mW) 4.965 VISO (V) 4.960 4.955 4.950 400 350 300 250 200 4.945 0 1 2 3 4 TIME (s) 100 -40 10980-014 4.940 Figure 13. Typical VISO = 5 V Output Voltage Ripple at 90% Load -20 0 20 40 60 80 AMBIENT TEMPERATURE (C) 100 120 10980-116 150 Figure 16. Power Dissipation with a 30 mA Load vs. Temperature 3.280 500 450 POWER DISSIPATION (mW) 3.276 3.274 3.272 VDD1 = 5V/VDD2 = 5V VDD1 = 3.3V/VDD2 = 3.3V VDDP = 5V/VDD2 3.3V 400 350 300 250 200 0 1 2 3 4 TIME (s) 100 -40 -20 0 20 40 60 80 AMBIENT TEMPERATURE (C) 100 120 Figure 17. Power Dissipation with a 20 mA Load vs. Temperature Figure 14. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load Rev. B | Page 17 of 24 10980-117 150 3.270 10980-015 VISO (V) 2.278 ADuM5210/ADuM5211/ADuM5212 Data Sheet 10 20 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 8 6 5V 3.3V 4 15 5V 10 3V 5 0 10 20 30 40 50 60 70 80 90 100 DATA RATE (Mbps) 0 10980-016 0 Figure 18. Typical Supply Current per Input Channel vs. Data Rate for 5 V and 3.3 V Operation 0 10 20 30 40 50 60 70 80 90 100 DATA RATE (Mbps) 10980-019 2 Figure 21. Typical ADuM5210 VDD1 or ADuM5212 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 10 20 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 8 6 4 5V 15 10 5V 5 2 0 10 20 30 40 50 60 70 80 90 100 DATA RATE (Mbps) 0 10980-017 0 Figure 19. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3.3 V Operation (No Output Load) 0 10 20 40 30 50 60 70 80 90 100 DATA RATE (Mbps) 10980-020 3.3V 3.3V Figure 22. Typical ADuM5210 VDD2 or ADuM5212 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 20 10 SUPPLY CURRENT (mA) 6 5V 4 3.3V 15 10 5V 5 2 3.3V 0 10 20 30 40 50 60 70 80 90 100 DATA RATE (Mbps) Figure 20. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3.3 V Operation (15 pF Output Load) 0 10980-018 0 0 10 20 30 40 50 60 DATA RATE (Mbps) 70 80 90 100 10980-012 SUPPLY CURRENT (mA) 8 Figure 23. Typical ADuM5211 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation Rev. B | Page 18 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 APPLICATIONS INFORMATION PDIS VDDP 10F + 0.1F GNDP 8 9 10 Figure 24. VDDP Bias and Bypass Components 13 12 11 (1) VSEL R2 30k VISO GNDISO 0.1F R1 10k 10F + 10980-023 Figure 25. VISO Bias and Bypass Components where: R1 is a resistor between VSEL and GNDISO. R2 is a resistor between VSEL and VISO. Because the output voltage can be adjusted continuously there are an infinite number of operating conditions. This data sheet addresses three discrete operating conditions in the Specifications tables. Many other combinations of input and output voltage are possible; Figure 15 depicts the supported voltage combinations at room temperature. Figure 15 was generated by fixing the VISO load and decreasing the input voltage until the PWM was at 80% duty cycle. Each of the curves represents the minimum input voltage that is required for operation under this criterion. For example, if the application requires 30 mA of output current at 5 V, the minimum input voltage at VDDP is 4.25 V. Figure 15 also illustrates why the VDDP = 3.3 V input and VISO = 5 V configuration is not recommended. Even at 10 mA of output current, the PWM cannot maintain less than 80% duty factor, leaving no margin to support load or temperature variations. Typically, the ADuM5210/ADuM5211/ADuM5212 dissipate about 17% more power between room temperature and maximum temperature; therefore, the 20% PWM margin covers temperature variations. The ADuM5210/ADuM5211/ADuM5212 implement undervoltage lockout (UVLO) with hysteresis on the primary and secondary side I/O pins as well as the VDDP power input. This feature ensures that the converter does not go into oscillation due to noisy input power or slow power-on ramp rates. The power supply section of the ADuM5210/ADuM5211/ ADuM5212 uses a 125 MHz oscillator frequency to efficiently pass power through its chip-scale transformers. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value bulk capacitor. These capacitors are most conveniently connected between Pin 9 and Pin 10 for VDDP and between Pin 11 and Pin 12 for VISO. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0.1 F and 10 F for VDD1. The smaller capacitor must have a low ESR; for example, use of an NPO or X5R ceramic capacitor is advised. Ceramic capacitors are also recommended for the 10 F bulk capacitance. An additional 10 nF capacitor can be added in parallel if further EMI reduction is required. Note that the total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. VDD1 VDD2 GNDP GNDISO VOA/VIA VIA/VOA VIB/VOB GNDP ADuM5210/ ADuM5211/ ADuM5212 VOB/VIB GNDISO PDIS VSEL VDDP VISO GNDP GNDISO BYPASS < 2mm PCB LAYOUT Figure 26. Recommended PCB Layout The ADuM5210/ADuM5211/ADuM5212 digital isolators with 0.15 W isoPower integrated dc-to-dc converters require no external interface circuitry for the logic interfaces. Power supply bypassing with a low ESR capacitor is required, as close to the chip pads as possible. The isoPower inputs require several In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Rev. B | Page 19 of 24 10980-024 VISO (R1 R2) 1.25 V R1 passive components to bypass the power effectively as well as set the output voltage and bypass the core voltage regulator (see Figure 24 through Figure 26). 10980-022 The dc-to-dc converter section of the ADuM5210/ADuM5211/ ADuM5212 works on principles that are common to most modern power supplies. It has a split controller architecture with isolated pulse-width modulation (PWM) feedback. VDDP power is supplied to an oscillating circuit that switches current into a chipscale air core transformer. Power transferred to the secondary side is rectified and regulated to a value between 3.15 V and 5.25 V, depending on the setpoint supplied by an external voltage divider (see Equation 1). The secondary (VISO) side controller regulates the output by creating a PWM control signal that is sent to the primary (VDDP) side by a dedicated iCoupler data channel. The PWM modulates the oscillator circuit to control the power being sent to the secondary side. Feedback allows for significantly higher power and efficiency. ADuM5210/ADuM5211/ADuM5212 Data Sheet Failure to ensure this can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in Table 20, thereby leading to latch-up and/or permanent damage. THERMAL ANALYSIS The ADuM5210/ADuM5211/ADuM5212 consist of four internal die attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, the chip is treated as a thermal unit, with the highest junction temperature reflected in the JA from Table 15. The value of JA is based on measurements taken with the parts mounted on a JEDEC standard, 4-layer board with fine width traces and still air. Under normal operating conditions, the ADuM5210/ADuM5211/ADuM5212 can operate at full load across the full temperature range without derating the output current. PROPAGATION DELAY PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see Figure 27). The propagation delay to a logic low output may differ from the propagation delay to a logic high. 50% V = (-d/dt)rn2; n = 1, 2, ... , N 50% Figure 27. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM5210/ADuM5211/ADuM5212 component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM5210/ ADuM5211/ADuM5212 devices operating under the same conditions. EMI CONSIDERATIONS The dc-to-dc converter section of the ADuM5210/ADuM5211/ ADuM5212 components must, of necessity, operate at a very high frequency to allow efficient power transfer through the small transformers. This creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. Grounded enclosures are recommended for applications that use these devices. If grounded enclosures are not possible, follow good RF design practices in the layout of the PCB. See the AN-0971 Application Note for the most current PCB layout recommendations for the ADuM5210/ADuM5211/ADuM5212. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of where: is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM5210/ ADuM5211/ADuM5212 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 28. 100 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGauss) OUTPUT (VOx) The pulses at the transformer output have an amplitude of >1.5 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by tPHL 10980-025 tPLH The limitation on the ADuM5210/ADuM5211/ADuM5212 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3.3 V operating condition of the ADuM5210/ADuM5211/ADuM5212 is examined because it represents the most susceptible mode of operation. 10 1 0.1 0.01 0.001 1k 10k 100k 10M 1M MAGNETIC FIELD FREQUENCY (Hz) 100M 10980-026 INPUT (VIx) logic transitions at the input for more than 1.6 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 6.4 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit. This situation should occur in the ADuM5210/ ADuM5211/ADuM5212 only during power-up and power-down operations. Figure 28. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing threshold of the decoder. Rev. B | Page 20 of 24 Data Sheet ADuM5210/ADuM5211/ADuM5212 The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM5210/ ADuM5211/ADuM5212 transformers. Figure 29 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 29, the ADuM5210/ ADuM5211/ADuM5212 are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example, a 0.5 kA current, placed 5 mm away from the ADuM5210/ ADuM5211/ADuM5212, is required to affect component operation. The VDDP power supply input provides power only to the converter. Power for the data channels is provided through VDD1 and VDD2. These power supplies can be connected to VDDP and VISO, if desired, or the supplies can receive power from an independent source. The converter should be treated as a standalone supply to be utilized at the discretion of the designer. The VDD1 or VDD2 supply current at a given channel of the ADuM5210/ADuM5211/ADuM5212 isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. For each input channel, the supply current is given by DISTANCE = 1m 100 IDDI = IDDI(Q) f 0.5 fr IDDI = IDDI(D) x (2f - fr) + IDDI(Q) f > 0.5 fr For each output channel, the supply current is given by 10 DISTANCE = 100mm IDDO = IDDO(Q) 1 f 0.5 fr IDDO = (IDDO(D) + (0.5 x 10 ) x CL x VDDO) x (2f - fr) + IDDO Q) f > 0.5 fr -3 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 10980-027 MAXIMUM ALLOWABLE CURRENT (kA) 1k POWER CONSUMPTION Figure 29. Maximum Allowable Current for Various Current-to-ADuM521x Spacings Note that, in combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. Exercise care in the layout of such traces to avoid this possibility. where: IDDI(D), IDDO(D) are the input and output dynamic supply currents per channel (mA/Mbps). IDDI(Q), IDDO(Q) are the specified input and output quiescent supply currents (mA). f is the input logic signal frequency (MHz); it is half the input data rate, expressed in units of Mbps. fr is the input stage refresh rate (Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 18 and Figure 19 show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 20 shows the per-channel supply current as a function of data rate for a 15 pF output condition. Figure 21 through Figure 23 show the total VDD1 and VDD2 supply current as a function of data rate for ADuM5210/ADuM5211/ADuM5212 channel configurations. Rev. B | Page 21 of 24 ADuM5210/ADuM5211/ADuM5212 Data Sheet The insulation lifetime of the ADuM5210/ADuM5211/ ADuM5212 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30, Figure 31, and Figure 32 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. A 50-year operating lifetime under the bipolar ac condition determines the Analog Devices recommended maximum working voltage. RATED PEAK VOLTAGE 0V Figure 30. Bipolar AC Waveform RATED PEAK VOLTAGE 0V Figure 31. DC Waveform RATED PEAK VOLTAGE 0V NOTES 1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION PUPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE. THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE VOLTAGE CANNOT CROSS 0V. Figure 32. Unipolar AC Waveform Rev. B | Page 22 of 24 10980-030 Accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. The values shown in Table 21 summarize the peak voltages for 50 years of service life in several operating conditions. In many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. Operation at working voltages higher than the service life voltage listed leads to premature insulation failure. 10980-028 All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. Analog Devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM5210/ ADuM5211/ADuM5212. In the case of dc or unipolar ac voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 21 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the dc or unipolar ac voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 31 or Figure 32 must be treated as a bipolar ac waveform, and its peak voltage must be limited to the 50-year lifetime voltage value listed in Table 21. 10980-029 INSULATION LIFETIME Data Sheet ADuM5210/ADuM5211/ADuM5212 OUTLINE DIMENSIONS 7.50 7.20 6.90 11 20 5.60 5.30 5.00 1 8.20 7.80 7.40 10 0.65 BSC SEATING PLANE 8 4 0 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150-AE 060106-A 0.38 0.22 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 33. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 ADuM5210ARSZ ADuM5210ARSZ-RL7 ADuM5210BRSZ ADuM5210BRSZ-RL7 ADuM5210CRSZ ADuM5210CRSZ-RL7 ADuM5211ARSZ ADuM5211ARSZ-RL7 ADuM5211BRSZ ADuM5211BRSZ-RL7 ADuM5211CRSZ ADuM5211CRSZ-RL7 ADuM5212ARSZ ADuM5212ARSZ-RL7 ADuM5212BRSZ ADuM5212BRSZ-RL7 ADuM5212CRSZ ADuM5212CRSZ-RL7 1 2 Number of Inputs, VDDP Side 2 2 2 2 2 2 1 1 1 1 1 1 0 0 0 0 0 0 Number of Inputs, VISO Side 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 Maximum Data Rate (Mbps) 1 1 25 25 100 100 1 1 25 25 100 100 1 1 25 25 100 100 Maximum Propagation Delay, 5 V (ns) 75 75 40 40 15 15 75 75 40 40 15 15 75 75 40 40 15 15 The addition of an RL7 suffix designates a 7" tape and reel option. Z = RoHS Compliant Part. Rev. B | Page 23 of 24 Maximum Pulse Width Distortion (ns) 40 40 3 3 2 2 40 40 3 3 2 2 40 40 3 3 2 2 Temperature Range (C) -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 Package Description 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP Package Option RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 ADuM5210/ADuM5211/ADuM5212 Data Sheet NOTES (c)2013-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10980-0-4/15(B) Rev. B | Page 24 of 24 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: EVAL-ADUM5211EBZ ADUM5211ARSZ ADUM5212BRSZ ADUM5212CRSZ ADUM5210CRSZ-RL7 ADUM5212ARSZ ADUM5210BRSZ ADUM5211BRSZ-RL7 ADUM5210ARSZ-RL7 ADUM5211ARSZ-RL7 ADUM5211CRSZ-RL7 ADUM5211BRSZ ADUM5211CRSZ ADUM5212CRSZ-RL7 ADUM5212ARSZ-RL7 ADUM5210BRSZ-RL7 ADUM5210ARSZ ADUM5210CRSZ ADUM5212BRSZ-RL7