Dual-Channel Isolators with
Integrated DC-to-DC Converters
Data Sheet ADuM5210/ADuM5211/ADuM5212
Rev. B Document Feedback
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FEATURES
isoPower integrated, isolated dc-to-dc converter
Regulated 3.15 V to 5.25 V output
Up to 150 mW output power
Dual dc-to-100 Mbps (NRZ) signal isolation channels
Soft start power supply
20-lead SSOP package with 5.3 mm creepage
Supports SPI up to 15 MHz
High temperature operation: 105°C
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition (pending)
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
APPLICATIONS
RS-232 transceivers
Power supply start-up bias and gate drives
Isolated sensor interfaces
Industrial PLCs
FUNCTIONAL BLOCK DIAGRAM
GND
P
V
IB
/V
OB
V
IA
/V
OA
V
DD1
GND
P
GND
P
NC
PDIS
V
DDP
GND
P
V
DD2
GND
ISO
GND
ISO
GND
ISO
GND
ISO
V
OA
/V
IA
V
OB
/V
IB
NC
V
SEL
V
ISO
1.25V
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
19
20
18
17
11
OSC RECT REG
PCS
2-CHANNEL iCoupler CORE
ADuM5210/ADuM5211/
ADuM5212
10980-001
Figure 1. ADuM5210/ADuM5211/ADuM5212
GENERAL DESCRIPTION
The ADuM5210/ADuM5211/ADuM52121 are dual-channel digital
isolators with isoPower®, an integrated, isolated dc-to-dc converter.
Based on the Analog Devices, Inc., iCoupler® technology, the dc-to-
dc converter provides regulated, isolated power that is adjustable
between 3.15 V and 5.25 V. Input supply voltages can range from
slightly below the required output to significantly higher. Popular
voltage combinations and their associated power levels are shown
in Table 2.
The ADuM5210/ADuM5211/ADuM5212 eliminate the need for a
separate, isolated dc-to-dc converter in low power, isolated designs.
The iCoupler chip-scale transformer technology is used for isolated
logic signals and for the magnetic components of the dc-to-dc
converter. The result is a small form factor, total isolation
solution.
isoPower uses high frequency switching elements to transfer
power through its transformer. Take special care during printed
circuit board (PCB) layout to meet emissions standards. See the
AN-0971 Application Note for board layout recommendations.
Table 1. Data I/O Port Assignments
Channel Pin ADuM5210 ADuM5211 ADuM5212
VIA/VOA 3 VIA V
OA V
OA
VIB/VOB 4 VIB V
IB V
OB
VOA/VIA 18 VOA V
IA V
IA
VOB/VIB 17 VOB V
OB V
IB
Table 2. Power Levels
Input Voltage (V) Output Voltage (V) Output Power (mW)
5 5 150
5 3.3 100
3.3 3.3 66
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ADuM5210/ADuM5211/ADuM5212 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Primary Input Supply/
5 V Secondary Isolated Supply ................................................... 3
Electrical Characteristics—3.3 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 5
Electrical Characteristics—5 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 7
Package Characteristics ............................................................... 9
Regulatory Approvals ................................................................... 9
Insulation and Safety-Related Specifications ............................ 9
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 10
Recommended Operating Conditions .................................... 10
Absolute Maximum Ratings ......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Truth Table .................................................................................. 15
Typical Performance Characteristics ........................................... 16
Applications Information .............................................................. 19
PCB Layout ................................................................................. 19
Thermal Analysis ....................................................................... 20
Propagation Delay Parameters ................................................. 20
EMI Considerations ................................................................... 20
DC Correctness and Magnetic Field Immunity........................... 20
Power Consumption .................................................................. 21
Insulation Lifetime ..................................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
4/15—Rev. A to Rev. B
Changes to Table 25 ........................................................................ 15
5/13—Rev. 0 to Rev. A
Added Table 1, Renumbered Sequentially .................................... 1
Changes to Table 3 ............................................................................ 3
1/13—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = VDDP = 5 V, V SEL resistor network: R1 = 10 kΩ, R2 = 30.9 kΩ between VISO and
GNDISO. Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VDD1, VDD2, VDDP ≤ 5.5 V
and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless
otherwise noted.
Table 3. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 5.0 V IISO = 15 mA, R1 = 10 kΩ, R2 = 30.9 kΩ
Thermal Coefficient VISO (TC) −44 μV/°C
Line Regulation VISO (LINE) 20 mV/V IISO = 15 mA, VDDP = 4.5 V to 5.5 V
Load Regulation VISO (LOAD) 1.3 3 % IISO = 3 mA to 27 mA
Output Ripple VISO (RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 27 mA
Output Noise VISO (NOISE) 200 mV p-p CBO = 0.1 µF||10 µF, IISO = 27 mA
Switching Frequency fOSC 125 MHz
Pulse-Width Modulation Frequency fPWM 600 kHz
Output Supply IISO (MAX) 30 mA 5.5 V > VISO > 4.5 V
Efficiency at IISO (MAX) 29 % IISO = 27 mA
IDDP, No VISO Load IDDP (Q) 6.8 12 mA
I
DDP
, Full V
ISO
Load
I
DDP (MAX)
104
mA
Thermal Shutdown
Shutdown Temperature 154 °C
Thermal Hysteresis 10 °C
Table 4. Data Channel Supply Current
Parameter Symbol
1 Mbps—A, B, C Grades 25 Mbps—B, C Grades 100 Mbps—C Grade
Unit
Test Conditions/
Comments Min Typ Max Min Typ Max Min Typ Max
SUPPLY CURRENT
ADuM5210 IDD1 1.1 1.6 6.2 7.0 20 25 mA CL = 0 pF
IDD2 2.7 4.5 4.8 7.0 9.5 15 mA CL = 0 pF
ADuM5211 IDD1 2.1 2.7 4.9 6.5 15 19 mA CL = 0 pF
IDD2 2.3 2.9 4.7 6.5 15.6 19 mA CL = 0 pF
I
DD1
2.7
4.5
4.8
7.0
9.5
15
mA
C
L
= 0 pF
IDD2 1.1 1.6 6.2 7.0 20 25 mA CL = 0 pF
Table 5. Switching Specifications
Parameter Symbol
A Grade B Grade C Grade
Unit
Test Conditions/
Comments Min Typ Max Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 100 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 50 35 13 18 24 ns 50% input to 50% output
Pulse Width Distortion PWD 10 3 2 ns |tPLH − tPHL|
Pulse Width PW 1000 40 10 ns Within PWD limit
Propagation Delay Skew tPSK 38 12 9 ns Between any two units
Channel Matching
Codirectional tPSKCD 5 3 2 ns
Opposing Direction tPSKOD 10 6 5 ns
Jitter 2 2 1 ns
Rev. B | Page 3 of 24
ADuM5210/ADuM5211/ADuM5212 Data Sheet
Table 6. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 VISO,
0.7 VDD1
V
Logic Low Input Threshold VIL 0.3 VISO,
0.3 VDD1
V
Logic High Output Voltages VOH VDD1 − 0.1,
VDD2 − 0.1
VDD1, VDD2 V IOx = −20 µA, VIx = VIxH
VDD1 − 0.4,
VDD2 − 0.4
VDD1 − 0.2,
VDD2 − 0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.2
0.4
V
I
Ox
= 4 mA, V
Ix
= V
IxL
Undervoltage Lockout VDD1, VDD2 ,VDDP supply
Positive Going Threshold VUV+ 2.6 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.2 V
Supply Current per Channel
Quiescent Input Supply Current IDDI(Q) 0.54 0.8 mA
Quiescent Output Supply Current IDDO(Q) 1.6 2.0 mA
Dynamic Input Supply Current IDDI(D) 0.09 mA/Mbps
Dynamic Output Supply Current IDDO(D) 0.04 mA/Mbps
Input Currents per Channel
I
I
−10
+0.01
+10
µA
0 V ≤ V
Ix
≤ V
DDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity1 |CM| 25 35 kV/µs VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate tr 1.6 µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 × VDD1 or 0.8 × VISO for a high input or VOx < 0.8 × VDD1 or 0.8 × VISO for a
low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 4 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 =VDD2 = VDDP = 3.3 V, VSEL resistor network: R1 = 10 kΩ, R2 = 16.9 kΩ between VISO and
GNDISO. Minimum/maximum specifications apply over the entire recommended operation range, which is 3.0 V ≤ VDD1, VDD2, VDDP ≤
3.6 V, an d −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels,
unless otherwise noted.
The digital isolator channels and the power section work independently, and under the operating voltages in this section, there may not
be sufficient current from the VISO to run both data channels at the maximum data rate. Verify that the application is within the power
capability of VISO if that supply is providing power to VDD2.
Table 7. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 3.3 V IISO = 10 mA, R1 = 10 kΩ, R2 = 16.9 kΩ
Thermal Coefficient VISO (TC) −26 μV/°C IISO = 20 mA
Line Regulation VISO (LINE) 20 mV/V IISO = 10 mA, VDDP = 3.0 V to 3.6 V
Load Regulation VISO (LOAD) 1.3 3 % IISO = 2 mA to 18 mA
Output Ripple
V
ISO (RIP)
50
mV p-p
20 MHz bandwidth, C
BO
= 0.1 µF||10 µF, I
ISO
= 18 mA
Output Noise VISO (NOISE) 130 mV p-p CBO = 0.1 µF||10 µF, IISO = 18 mA
Switching Frequency fOSC 125 MHz
Pulse-Width Modulation Frequency fPWM 600 kHz
Output Supply IISO (MAX) 20 mA 3.6 V > VISO > 3 V
Efficiency at IISO (MAX) 27 % IISO = 18 mA
IDDP, No VISO Load IDDP (Q) 3.3 10.5 mA
IDDP, Full VISO Load IDDP (MAX) 77 mA
Thermal Shutdown
Shutdown Temperature 154 °C
Thermal Hysteresis 10 °C
Table 8. Data Channel Supply Current
Parameter Symbol
1 Mbps—A, B, C Grades
25 Mbps—B, C Grades
100 Mbps—C Grade
Unit
Test Conditions/
Comments Min Typ Max Min
Typ
Max Min Typ
Max
SUPPLY CURRENT
ADuM5210 IDD1 0.75 1.4 5.1 9.0 17 23 mA CL = 0 pF
IDD2 2.0 3.5 2.7 4.6 4.8 9 mA CL = 0 pF
ADuM5211 IDD1 1.6 2.1 3.8 5.0 11 15 mA CL = 0 pF
IDD2 1.7 2.3 3.9 6.2 11 15 mA CL = 0 pF
ADuM5212 IDD1 2.0 3.5 2.7 4.6 4.8 9 mA CL = 0 pF
IDD2 0.75 1.4 5.1 9.0 17 23 mA CL = 0 pF
Table 9. Switching Specifications
Parameter Symbol
A Grade B Grade C Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max Min
Typ
Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 100 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 50 35 20 25 33 ns 50% input to 50% output
Pulse Width Distortion PWD 10 3 2.5 ns |tPLH − tPHL|
Pulse Width
PW
1000
40
10
ns
Within PWD limit
Propagation Delay Skew tPSK 38 16 12 ns Between any two units
Channel Matching
Codirectional tPSKCD 5 3 2.5 ns
Opposing Direction tPSKOD 10 6 5 ns
Jitter 2 2 1 ns
Rev. B | Page 5 of 24
ADuM5210/ADuM5211/ADuM5212 Data Sheet
Table 10. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 VISO, 0.7
VDD1
V
Logic Low Input Threshold VIL 0.3 VISO,
0.3 VDD1
V
Logic High Output Voltages VOH VDD1 − 0.1,
VDD2 − 0.1
VDD1, VDD2 V IOx = −20 µA, VIx = VIxH
VDD1 − 0.4,
VDD2 − 0.4
VDD1 − 0.2,
VDD2 − 0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
V
OL
0.0
0.1
V
I
Ox
= 20 µA, V
Ix
= V
IxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout VDD1, VDD2 ,VDDP supply
Positive Going Threshold VUV+ 2.6 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.2 V
Supply Current per Channel
Quiescent Input Supply Current IDDI(Q) 0.4 0.6 mA
Quiescent Output Supply Current IDDO(Q) 1.2 1.7 mA
Dynamic Input Supply Current IDDI(D) 0.08 mA/Mbps
Dynamic Output Supply Current IDDO(D) 0.015 mA/Mbps
Input Currents per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 3 ns 10% to 90%
Common-Mode Transient Immunity
1
|CM|
25
35
kV/µs
V
Ix
= V
DD1
or V
ISO
, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate tr 1.6 µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 × VDD1 or 0.8 × VISO for a high input or VOx < 0.8 × VDD1 or 0.8 × VISO for a
low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 6 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VDDP = 5 V, VDD2 = 3.3 V, VSEL resistor network: R1 = 10 kΩ, R2 = 16.9 kΩ between VISO
and GNDISO. Minimum/maximum specifications apply over the entire recommended operation range which is 4.5 V ≤ VDD1, VDDP ≤ 5.5 V,
3.0 V ≤ VDD2 ≤ 3.6 V, a nd − 40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS
signal levels, unless otherwise noted.
Table 11. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 3.3 V IISO = 15 mA, R1 = 10 kΩ, R2 = 16.9 kΩ
Thermal Coefficient VISO (TC) −26 μV/°C
Line Regulation VISO (LINE) 20 mV/V IISO = 15 mA, VDDP = 4.5 V to 5.5 V
Load Regulation VISO (LOAD) 1.3 3 % IISO = 3 mA to 27 mA
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 27 mA
Output Noise VISO (NOISE) 130 mV p-p CBO = 0.1 µF||10 µF, IISO = 27 mA
Switching Frequency fOSC 125 MHz
Pulse Width Modulation Frequency fPWM 600 kHz
Output Supply IISO (MAX) 30 mA 3.6 V > VISO > 3 V
Efficiency at IISO (MAX) 24 % IISO = 27 mA
IDDP, No VISO Load IDDP (Q) 3.2 8 mA
IDDP, Full VISO Load IDDP (MAX) 85 mA
Thermal Shutdown
Shutdown Temperature
154
°C
Thermal Hysteresis 10 °C
Table 12. Data Channel Supply Current
Parameter Symbol
1 Mbps—A, B, C Grades 25 Mbps—B, C Grades 100 Mbps—C Grade
Unit
Test Conditions/
Comments Min Typ Max Min Typ Max Min Typ Max
SUPPLY CURRENT
ADuM5210 IDD1 1.1 1.6 6.2 7.0 20 25 mA CL = 0 pF
IDD2 2.0 3.5 2.7 4.6 4.8 9.0 mA CL = 0 pF
ADuM5211 IDD1 2.1 2.7 4.9 6.5 15 19 mA CL = 0 pF
IDD2 1.7 2.3 3.9 6.2 11 15 mA CL = 0 pF
ADuM5212 IDD1 2.0 3.5 2.7 4.6 4.8 9.0 mA CL = 0 pF
IDD2 1.1 1.6 6.2 7.0 20 25 mA CL = 0 pF
Table 13. Switching Specifications
7 Codi rec tiona l cha nnel mat chi ng is t he absol ut e val ue of the d iff erenc e in p rop aga tion d ela ys b etwe en a ny tw o c hanne ls wi th i nput s on t he sa me sid e of t he is olati on b arrier. Opposing-direc tio nal chan nel m atc hin g is the abs olut e val ue o f the diff ere nce in pr opaga ti on de lays bet wee n any two c han nels wit h inp uts on op posi ng sid es of the is olat io n bar rier .
Parameter Symbol
A Grade B Grade C Grade
Unit
Test Conditions/
Comments
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 100 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 50 35 13 20 26 ns 50% input to 50% output
Pulse Width Distortion PWD 10 3 2.5 ns |tPLH − tPHL|
Pulse Width PW 1000 40 10 ns Within PWD limit
Propagation Delay Skew tPSK 38 16 12 ns Between any two units
Channel Matching
Codirectional tPSKCD 5 3 2 ns
Opposing Direction tPSKOD 10 6 5 ns
Jitter 2 2 1 ns
Rev. B | Page 7 of 24
ADuM5210/ADuM5211/ADuM5212 Data Sheet
Table 14. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 VISO,
0.7 VDD1
V
Logic Low Input Threshold VIL 0.3 VISO,
0.3 VDD1
V
Logic High Output Voltages VOH VDD1 − 0.1,
VDD2 − 0.1
VDD1, VDD2 V IOx = −20 µA, VIx = VIxH
VDD1 − 0.4,
VDD2 − 0.4
VDD1 − 0.2,
VDD2 − 0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
V
OL
0.0
0.1
V
I
Ox
= 20 µA, V
Ix
= V
IxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout VDD1, VDD2 ,VDDP supply
Positive Going Threshold VUV+ 2.6 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.2 V
Supply Current per Channel
Quiescent Input Supply Current IDDI(Q) 0.54 0.75 mA
Quiescent Output Supply Current IDDO(Q) 1.2 2.0 mA
Dynamic Input Supply Current IDDI(D) 0.09 mA/Mbps
Dynamic Output Supply Current IDDO(D) 0.02 mA/Mbps
Input Currents per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity
1
|CM|
25
35
kV/µs
V
Ix
= V
DD1
or V
ISO
, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate tr 1.6 µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 × VDD1 or 0.8 × VISO for a high input or VOx < 0.8 × VDD1 or 0.8 × VISO for a
low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 8 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
PACKAGE CHARACTERISTICS
Table 15. Thermal and Isolation Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)
1
R
I-O
10
12
Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction-to-Ambient Thermal Resistance θJA 50 °C/W Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces3
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
3 See the Thermal Analysis section for thermal model definitions.
REGULATORY APPROVALS
Table 16.
UL (Pending)1 CSA (Pending) VDE (Pending)2
Recognized under 1577 Component
Recognition Program1
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Single Protection, 2500 V RMS
Isolation Voltage
Basic insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (565 V peak)
maximum working voltage
Reinforced insulation, 560 V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM5210/ADuM5211/ADuM5212 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage
detection limit = 10 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM5210/ADuM5211/ADuM5212 is proof tested by applying an insulation test voltage ≥1590 V peak for 1 second
(partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 17. Critical Safety-Related Dimensions and Material Properties
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 5.3 mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 5.3 mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303, Part 1
Isolation Group
II
Material group (DIN VDE 0110, 1/89, Table 1)
Rev. B | Page 9 of 24
ADuM5210/ADuM5211/ADuM5212 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
the protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 18. VDE Characteristics
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd(m) 1050 V peak
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Vpd(m) 840 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Vpd(m) 672 V peak
Highest Allowable Overvoltage VIOTM 3535 V peak
Surge Isolation Voltage VIOSM(TEST) = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 4000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 2)
Case Temperature TS 150 °C
Safety Total Dissipated Power IS1 2.5 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
0
0.5
1.0
1.5
2.0
2.5
3.0
050 100 150 200
AMBI ENT T E M P E RATURE ( °C)
SAFE LIMITING POWER (W)
10980-002
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 19.
Parameter Symbol Min Max Unit
Operating Temperature1 TA −40 +105 °C
Supply Voltages2
V
DDP
at V
ISO
= 3.0 V to 3.6 V
V
DDP
3.0
5.5
V
VDDP at VISO = 4.5 V to 5.5 V 4.5 5.5 V
VDD1, VDD2 VDD1, VDD2 2.7 5.5 V
1 Operation at 105°C requires reduction of the maximum load current as specified in Table 20.
2 Each voltage is relative to its respective ground.
Rev. B | Page 10 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 20.
Parameter Rating
Storage Temperature (TST) −55°C to +150°C
Ambient Operating Temperature (TA) −40°C to +105°C
Supply Voltages (VDDP, VDD1, VDD2, VISO)1 −0.5 V to +7.0 V
VISO Supply Current2
TA = −40°C to +105°C 30 mA
Input Voltage (VIA, VIB, PDIS, VSEL)1, 3 −0.5 V to VDDI + 0.5 V
Output Voltage ( V
OA
, V
OB
)
1, 3
−0.5 V to V
DDO
+ 0.5 V
Average Output Current Per Data
Output Pin4
−10 mA to +10 mA
Common-Mode Transients5 −100 kV/µs to +100 kV/µs
1 All voltages are relative to their respective ground.
2 The VISO provides current for dc and dynamic loads on the VISO I/O channels.
This current must be included when determining the total VISO supply
current. For ambient temperatures between 85°C and 105°C, maximum
allowed current is reduced.
3 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
4 See Figure 2 for the maximum rated current values for various temperatures.
5 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause latch-up
or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 21. Maximum Continuous Working Voltage
Supporting 50-Year Minimum Lifetime1
Parameter Max Unit
Applicable
Certification
AC Voltage
Bipolar Waveform 560 V peak All certifications,
50-year operation
Unipolar Waveform 560 V peak
DC Voltage
|DC Peak Voltage| 560 V peak
1 Refers to the continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more information.
ESD CAUTION
Rev. B | Page 11 of 24
ADuM5210/ADuM5211/ADuM5212 Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
20
19
18
17
516
615
714
8
9
10
13
12
11
ADuM5210
TOP VIEW
(No t t o Scal e)
GND
P
V
IB
V
IA
V
DD1
GND
P
GND
P
NC
PDIS
V
DDP
GND
P
V
DD2
NOTES
1. PINS LABELED NC CAN BE ALL OWE D
TO FLOAT, BUT IT IS BETTER TO
CONNECT T HE S E P INS T O G ROUND.
AVOID ROUTING HIGH SPEED SIGNALS
THROUGH THES E P I NS BE CAUS E NOI S E
COUPLI NG MAY RE SULT .
GND
ISO
GND
ISO
GND
ISO
GND
ISO
V
OA
V
OB
NC
V
SEL
V
ISO
10980-003
Figure 3. ADuM5210 Pin Configuration
Table 22. ADuM5210 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Power Supply for the Side 1 Logic Circuits of the Device. It is independent of VDDP and can operate between 3.0 V
and 5.5 V.
2, 5, 6, 10 GNDP Ground Reference for Isolator Side 1. All of these pins are internally connected, and it is recommended that all GNDP
pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
7, 14 NC This pin is not connected internally (see Figure 3).
8 PDIS Power Disable. When this pin is tied to a logic low, the power converter is active; when tied to a logic high, the
power supply enters a low power standby mode.
9 VDDP Primary
iso
Power Supply Voltage, 3.0 V to 5.5 V.
11, 15, 16, 19
GNDISO Ground Reference for Isolator Side 2. All of these pins are internally connected, and it is recommended that all GNDISO
pins be connected to a common ground.
12 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
13 VSEL Output Voltage Select. Provide a thermally matched resistor network between VISO and GNDISO to divide the
required output voltage to match the 1.25 V reference voltage. VISO voltage can be programmed up to 20%
higher or 75% lower than VDDP but must be within the allowed output voltage range.
17 VOB Logic Output B.
18 VOA Logic Output A.
20 VDD2 Power Supply for the Side 2 Logic Circuits of the Device. It is independent of VISO and can operate between 3.0 V
and 5.5 V.
Rev. B | Page 12 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
1
2
3
4
20
19
18
17
516
615
714
8
9
10
13
12
11
ADuM5211
TOP VIEW
(No t t o Scal e)
GND
P
V
IB
V
OA
V
DD1
GND
P
GND
P
NC
PDIS
V
DDP
GND
P
V
DD2
GND
ISO
GND
ISO
GND
ISO
GND
ISO
V
IA
V
OB
NC
V
SEL
V
ISO
10980-005
NOTES
1. PINS LABEL E D NC CAN BE ALL OW E D
TO FLOAT, BUT IT IS BETTER TO
CONNECT T HE S E P INS T O G ROUND.
AVOID ROUTING HIGH SPEED SIGNALS
THRO UGH T HE S E P INS BECAUS E
NOISE COUPLING MAY RESULT.
Figure 4. ADuM5211 Pin Configuration
Table 23. ADuM5211 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Power Supply for the Side 1 Logic Circuits of the Device. It is independent of VDDP and can operate between 3.0 V
and 5.5 V.
2, 5, 6, 10 GNDP Ground Reference for Isolator Side 1. All of these pins are internally connected, and it is recommended that all GNDP
pins be connected to a common ground.
3 VOA Logic Output A.
4 VIB Logic Input B.
7, 14
NC
This pin is not connected internally (see Figure 4).
8 PDIS Power Disable. When this pin is tied to a logic low, the power converter is active; when tied to a logic high, the
power supply enters a low power standby mode.
9 VDDP Primary
iso
Power Supply Voltage, 3.0 V to 5.5 V.
11, 15, 16,19 GNDISO Ground Reference for Isolator Side 2. All of these pins are internally connected, and it is recommended that all GNDISO
pins be connected to a common ground.
12 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
13 VSEL Output Voltage Select. Provide a thermally matched resistor network between VISO and GNDISO to divide the
required output voltage to match the 1.25 V reference voltage. VISO voltage can be programmed up to 20%
higher or 75% lower than VDDP but must be within the allowed output voltage range.
17 VOB Logic Output B.
18 VIA Logic Input A.
20 VDD2 Power Supply for the Side 2 Logic Circuits of the Device. It is independent of VISO and can operate between 3.0 V
and 5.5 V.
Rev. B | Page 13 of 24
ADuM5210/ADuM5211/ADuM5212 Data Sheet
1
2
3
4
20
19
18
17
516
615
714
8
9
10
13
12
11
ADuM5212
TOP VIEW
(No t t o Scal e)
GND
P
V
OB
V
OA
V
DD1
GND
P
GND
P
NC
PDIS
V
DDP
GND
P
V
DD2
GND
ISO
GND
ISO
GND
ISO
GND
ISO
V
IA
V
IB
NC
V
SEL
V
ISO
10980-007
NOTES
1. PINS LABELED NC CAN BE ALL OWE D
TO FLO AT OR CAN BE CONNECTED
TO THE GRO UND. AVO ID CO NNE CTING
THEM TO HIGH SPEED SIGNALS
TO MINIMIZE CAPACITIVE COUPLING
OF NOISE.
Figure 5. ADuM5212 Pin Configuration
Table 24. ADuM5212 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Power Supply for the Side 1 Logic Circuits of the Device. It is independent of VDDP and can operate between 3.0 V
and 5.5 V.
2, 5, 6, 10 GNDP Ground Reference for Isolator Side 1. All of these pins are internally connected, and it is recommended that all GNDP
pins be connected to a common ground.
3 VOA Logic Output A.
4 VOB Logic Output B.
7, 14 NC This pin is not connected internally (see Figure 5).
8
PDIS
Power Disable. When this pin is tied to a logic low, the power converter is active; when tied to a logic high, the
power supply enters a low power standby mode.
9 VDDP Primary
iso
Power Supply Voltage, 3.0 V to 5.5 V.
11, 15, 16, 19
GNDISO Ground Reference for Isolator Side 2. All of these pins are internally connected, and it is recommended that all GNDISO
pins be connected to a common ground.
12 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
13 VSEL Output Voltage Select. Provide a thermally matched resistor network between VISO and GNDISO to divide the
required output voltage to match the 1.25 V reference voltage. VISO voltage can be programmed up to 20%
higher or 75% lower than VDDP but must be within the allowed output voltage range.
17 VIB Logic Input B.
18 VIA Logic Input A.
20 VDD2 Power Supply for the Side 2 Logic Circuits of the Device. It is independent of VISO and can operate between 3.0 V
and 5.5 V.
Rev. B | Page 14 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
TRUTH TABLE
Table 25. Power Section Truth Table (Positive Logic)
VDDP (V) VSEL Input PDIS Input VISO Output (V) Notes
5
R1 = 10 kΩ, R2 = 30.9 kΩ
Low
5
5 R1 = 10 kΩ, R2 = 30.9 kΩ High 0
3.3 R1 = 10 kΩ, R2 = 16.9 kΩ Low 3.3
3.3 R1 = 10 kΩ, R2 = 16.9 kΩ High 0
5 R1 = 10 kΩ, R2 = 16.9 kΩ Low 3.3
5 R1 = 10 kΩ, R2 = 16.9 kΩ High 0
3.3 R1 = 10 kΩ, R2 = 30.9 kΩ Low 5 Configuration not recommended
3.3 R1 = 10 kΩ, R2 = 30.9 kΩ High 0
Table 26. Data Section Truth Table (Positive Logic)
VDDI State1 VIx Input1 VDDO State1 VOx Output1 Notes
Powered High Powered High Normal operation, data is high
Powered Low Powered Low Normal operation, data is low
X2 X2 Unpowered Z3 Output is off
Unpowered Low Powered Low Output default low
Unpowered High Powered Indeterminate If a high level is applied to an input when no supply is present, then it
can parasitically power the input side causing unpredictable operation
1 The references to I and O in this table refer to the input side and output side of a given data path and the associated power supply.
2 X = don’t care.
3 Z = high impedance state.
Rev. B | Page 15 of 24
ADuM5210/ADuM5211/ADuM5212 Data Sheet
Rev. B | Page 16 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0 0.02 0.04 0.06 0.08
LOAD CURRENT (A)
EF FI CIENCY (%)
10980-004
V
DD1
= V
DDP
=5V/V
DD2
= 5V
V
DD1
= V
DDP
=5V/V
DD2
= 3.3V
V
DD1
= V
DDP
= 3.3V/V
DD2
= 3.3V
Figure 6. Typical Power Supply Efficiency at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V
0
50
100
150
200
250
300
350
400
450
010203040
POWER DISSIP
A
TION (
m
W)
IISO (mA)
10980-006
V
DD1
= V
DDP
= 5V/V
DD2
= 3.3V
V
DD1
= V
DDP
= 3.3V/V
DD2
= 3.3V
V
DD1
= V
DDP
= 5V/V
DD2
= 5V
Figure 7. Typical Total Power Dissipation vs. IISO
10980-008
0
5
10
15
20
25
30
35
0255075100
I
ISO
(mA)
I
DDP
(mA)
VDD1 = VDDP = 5V/VDD2 = 3.3V
VDD1 = VDDP = 3. 3V/VDD2 = 3.3V
VDD1 = VDDP = 5V/VDD2 = 5V
Figure 8. Typical Isolated Output Supply Current, IISO, as a Function
of External Load, at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V
0
0.4
0.2
0.8
0.6
1.0
1.4
1.8
1.6
2.0
0
0.10
0.05
0.20
0.15
0.25
0.30
0.40
0.45
0.35
0.50
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD1 (V)
POWER DISSIPATIO N (W)
IDDP CURRENT (A)
10980-009
POWER DISSIPATIO N
IDDP
Figure 9. Typical Short-Circuit Input Current and Power vs. VDD1 Supply Voltage
(1ms/DIV)
VISO (100mV/DIV)
10% LOAD
90% LOAD
10980-010
Figure 10. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
(1ms/DIV)
V
ISO
(100mV/DIV)
10% LOAD
90% LOAD
10980-011
Figure 11. Typical Transient Load Response, 3 V Output,
10% to 90% Load Step
Data Sheet ADuM5210/ADuM5211/ADuM5212
Rev. B | Page 17 of 24
(1ms/DIV)
V
ISO
(100mV/DIV)
10980-013
Figure 12. Typical Transient Load Response, 5 V Input, 3.3 V Output,
10% to 90% Load Step
V
ISO
(V)
TIME (µs)
4.970
4.965
4.960
4.955
4.950
4.945
4.940
10 234
10980-014
Figure 13. Typical VISO = 5 V Output Voltage Ripple at 90% Load
V
ISO
(V)
TIME (µs)
3.280
2.278
3.276
3.274
3.272
3.270
10 234
10980-015
Figure 14. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load
2.0
2.5
3.0
3.5
4.0
4.5
5.0
3.03.54.04.55.05.56.0
MINIMUM INPUT VOL
T
AGE ( V )
OUTPUT VOLTAGE (V )
30mA LO AD
20mA LO AD
10mA LO AD
10980-115
Figure 15. Relationship Between Output Voltage and Required Input Voltage,
Under Load, to Maintain >80% Duty Factor in the PWM
500
450
400
350
300
250
200
150
100 –20 0 20 40
AMBIENT TEMPERATURE (°C)
POWER DISSIP
A
TION (mW)
60 80 100 120–40
V
DD1
= V
DDP
= 5V/V
DD2
= 5V
V
DD1
= V
DDP
= 5V/V
DD2
= 3.3V
10980-116
Figure 16. Power Dissipation with a 30 mA Load vs. Temperature
500
450
400
350
300
250
200
150
100 –20 0 20 40
AMBI E NT TEM P E RATURE (° C)
POWER DISSIP
A
TION (mW)
60 80 100 120–40
V
DDP
= 5V/V
DD2
3.3V
V
DD1
= 3.3V/V
DD2
= 3.3V
V
DD1
= 5V/V
DD2
= 5V
10980-117
Figure 17. Power Dissipation with a 20 mA Load vs. Temperature
ADuM5210/ADuM5211/ADuM5212 Data Sheet
10
0
2
4
6
8
0 20 40 60 8010010 3050 70 90
DATARATE (Mbps)
5V 3.3V
10980-016
SUPPLY CURRENT (mA)
Figure 18. Typical Supply Current per Input Channel vs. Data Rate
for 5 V and 3.3 V Operation
10
0
2
4
6
8
0 20 40 60 80 10010 30 50 70 90
DATA RATE (Mbps)
5V
3.3V
10980-017
SUPPLY CURRENT (mA)
Figure 19. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3.3 V Operation (No Output Load)
10
0
4
2
6
8
020 40 60 80 10010 30 50 70 90
DATA RATE (Mbps)
5V
3.3V
10980-018
SUPPLY CURRENT (mA)
Figure 20. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3.3 V Operation (15 pF Output Load)
20
0
5
10
15
0 2040 60 80100
10 30 50 70 90
DATARATE (Mbps)
5V
3V
10980-019
SUPPLY CURRENT (mA)
Figure 21. Typical ADuM5210 VDD1 or ADuM5212 VDD2 Supply Current vs.
Data Rate for 5 V and 3.3 V Operation
20
0
5
10
15
0 20 40 60 80 10010 30 50 70 90
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5V
3.3V
10980-020
Figure 22. Typical ADuM5210 VDD2 or ADuM5212 VDD2 Supply Current vs.
Data Rate for 5 V and 3.3 V Operation
20
0
5
10
15
020 40 60 80 10010 30 50 70 90
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5V
3.3V
10980-012
Figure 23. Typical ADuM5211 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V
and 3.3 V Operation
Rev. B | Page 18 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
Rev. B | Page 19 of 24
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM5210/ADuM5211/
ADuM5212 works on principles that are common to most
modern power supplies. It has a split controller architecture with
isolated pulse-width modulation (PWM) feedback. VDDP power is
supplied to an oscillating circuit that switches current into a chip-
scale air core transformer. Power transferred to the secondary
side is rectified and regulated to a value between 3.15 V and
5.25 V, depending on the setpoint supplied by an external
voltage divider (see Equation 1). The secondary (VISO) side
controller regulates the output by creating a PWM control signal
that is sent to the primary (VDDP) side by a dedicated iCoupler
data channel. The PWM modulates the oscillator circuit to control
the power being sent to the secondary side. Feedback allows for
significantly higher power and efficiency.
R1
R2R1
VISO
)(
V25.1
(1)
where:
R1 is a resistor between VSEL and GNDISO.
R2 is a resistor between VSEL and VISO.
Because the output voltage can be adjusted continuously
there are an infinite number of operating conditions. This
data sheet addresses three discrete operating conditions in the
Specifications tables. Many other combinations of input and
output voltage are possible; Figure 15 depicts the supported
voltage combinations at room temperature. Figure 15 was
generated by fixing the VISO load and decreasing the input
voltage until the PWM was at 80% duty cycle. Each of the
curves represents the minimum input voltage that is required
for operation under this criterion. For example, if the applica-
tion requires 30 mA of output current at 5 V, the minimum
input voltage at VDDP is 4.25 V. Figure 15 also illustrates why
the VDDP = 3.3 V input and VISO = 5 V configuration is not
recommended. Even at 10 mA of output current, the PWM
cannot maintain less than 80% duty factor, leaving no margin
to support load or temperature variations.
Typically, the ADuM5210/ADuM5211/ADuM5212 dissipate
about 17% more power between room temperature and maxi-
mum temperature; therefore, the 20% PWM margin covers
temperature variations.
The ADuM5210/ADuM5211/ADuM5212 implement
undervoltage lockout (UVLO) with hysteresis on the primary
and secondary side I/O pins as well as the VDDP power input.
This feature ensures that the converter does not go into
oscillation due to noisy input power or slow power-on ramp rates.
PCB LAYOUT
The ADuM5210/ADuM5211/ADuM5212 digital isolators with
0.15 W isoPower integrated dc-to-dc converters require no exter-
nal interface circuitry for the logic interfaces. Power supply
bypassing with a low ESR capacitor is required, as close to the
chip pads as possible. The isoPower inputs require several
passive components to bypass the power effectively as well as
set the output voltage and bypass the core voltage regulator (see
Figure 24 through Figure 26).
PDIS
V
DDP
GND
P
10µF 0.1µF
+
8
9
10
10980-022
Figure 24. VDDP Bias and Bypass Components
V
SEL
V
ISO
GND
ISO
10µF0.1µF +
R1
10kΩ
R2
30kΩ
13
12
11
10980-023
Figure 25. VISO Bias and Bypass Components
The power supply section of the ADuM5210/ADuM5211/
ADuM5212 uses a 125 MHz oscillator frequency to efficiently
pass power through its chip-scale transformers. Bypass capaci-
tors are required for several operating frequencies. Noise
suppression requires a low inductance, high frequency capacitor;
ripple suppression and proper regulation require a large value
bulk capacitor. These capacitors are most conveniently connected
between Pin 9 and Pin 10 for VDDP and between Pin 11 and Pin 12
for VISO. To suppress noise and reduce ripple, a parallel combination
of at least two capacitors is required. The recommended capacitor
values are 0.1 µF and 10 µF for VDD1. The smaller capacitor must
have a low ESR; for example, use of an NPO or X5R ceramic
capacitor is advised. Ceramic capacitors are also recommended for
the 10 F bulk capacitance. An additional 10 nF capacitor can be
added in parallel if further EMI reduction is required.
Note that the total lead length between the ends of the low ESR
capacitor and the input power supply pin must not exceed 2 mm.
GND
ISO
V
SEL
PDIS
V
DDP
V
ISO
GND
P
BYPASS < 2mm
GND
ISO
ADuM5210/
ADuM5211/
ADuM5212
10980-024
GND
P
V
IB
/V
OB
V
IA
/V
OA
V
OB
/V
IB
V
OA
/V
IA
V
DD1
V
DD2
GND
P
GND
ISO
Figure 26. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component side.
ADuM5210/ADuM5211/ADuM5212 Data Sheet
Rev. B | Page 20 of 24
Failure to ensure this can cause voltage differentials between pins,
exceeding the absolute maximum ratings specified in Table 20,
thereby leading to latch-up and/or permanent damage.
THERMAL ANALYSIS
The ADuM5210/ADuM5211/ADuM5212 consist of four internal
die attached to a split lead frame with two die attach paddles. For
the purposes of thermal analysis, the chip is treated as a thermal
unit, with the highest junction temperature reflected in the θJA from
Table 15. The value of θJA is based on measurements taken with the
parts mounted on a JEDEC standard, 4-layer board with fine
width traces and still air. Under normal operating conditions, the
ADuM5210/ADuM5211/ADuM5212 can operate at full load across
the full temperature range without derating the output current.
PROPAGATION DELAY PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component (see Figure 27).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
10980-025
Figure 27. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5210/ADuM5211/ADuM5212 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM5210/
ADuM5211/ADuM5212 devices operating under the same
conditions.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5210/ADuM5211/
ADuM5212 components must, of necessity, operate at a very high
frequency to allow efficient power transfer through the small
transformers. This creates high frequency currents that can
propagate in circuit board ground and power planes, causing
edge and dipole radiation. Grounded enclosures are recom-
mended for applications that use these devices. If grounded
enclosures are not possible, follow good RF design practices
in the layout of the PCB. See the AN-0971 Application Note
for the most current PCB layout recommendations for the
ADuM5210/ADuM5211/ADuM5212.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 1.6 μs, periodic sets
of refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than approximately 6.4 μs, the input side
is assumed to be unpowered or nonfunctional, in which case,
the isolator output is forced to a default low state by the watchdog
timer circuit. This situation should occur in the ADuM5210/
ADuM5211/ADuM5212 only during power-up and power-down
operations.
The limitation on the ADuM5210/ADuM5211/ADuM5212
magnetic field immunity is set by the condition in which induced
voltage in the transformer receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3.3 V operating
condition of the ADuM5210/ADuM5211/ADuM5212 is examined
because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude of >1.5 V.
The decoder has a sensing threshold of about 0.5 V, thus estab-
lishing a 0.5 V margin in which induced voltages can be tolerated.
The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑πrn2; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM5210/
ADuM5211/ADuM5212 and an imposed requirement that
the induced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 28.
MAGNETI C FI E LD F RE QUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kGauss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
10980-026
Figure 28. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and is of the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing
threshold of the decoder.
Data Sheet ADuM5210/ADuM5211/ADuM5212
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM5210/
ADuM5211/ADuM5212 transformers. Figure 29 expresses these
allowable current magnitudes as a function of frequency for
selected distances. As shown in Figure 29, the ADuM5210/
ADuM5211/ADuM5212 are extremely immune and can be
affected only by extremely large currents operated at high
frequency very close to the component. For the 1 MHz example,
a 0.5 kA current, placed 5 mm away from the ADuM5210/
ADuM5211/ADuM5212, is required to affect component
operation.
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOWABLE CURRENT (kA)
1k
100
10
1
0.1
0.011k 10k100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
10980-027
Figure 29. Maximum Allowable Current for Various Current-to-ADuM521x
Spacings
Note that, in combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
POWER CONSUMPTION
The VDDP power supply input provides power only to the converter.
Power for the data channels is provided through VDD1 and VDD2.
These power supplies can be connected to VDDP and VISO, if desired,
or the supplies can receive power from an independent source. The
converter should be treated as a standalone supply to be utilized at
the discretion of the designer.
The VDD1 or VDD2 supply current at a given channel of the
ADuM5210/ADuM5211/ADuM5212 isolator is a function of the
supply voltage, the data rate of the channel, and the output load
of the channel.
For each input channel, the supply current is given by
IDDI = IDDI(Q) f ≤ 0.5 fr
IDDI = IDDI(D) × (2f − fr) + IDDI(Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO(Q) f ≤ 0.5 fr
IDDO = (IDDO(D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO Q)
f > 0.5 fr
where:
IDDI(D), IDDO(D) are the input and output dynamic supply currents
per channel (mA/Mbps).
IDDI(Q), IDDO(Q) are the specified input and output quiescent
supply currents (mA).
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 18 and
Figure 19 show per-channel supply currents as a function of
data rate for an unloaded output condition. Figure 20 shows the
per-channel supply current as a function of data rate for a 15 pF
output condition. Figure 21 through Figure 23 show the total
VDD1 and VDD2 supply current as a function of data rate for
ADuM5210/ADuM5211/ADuM5212 channel configurations.
Rev. B | Page 21 of 24
ADuM5210/ADuM5211/ADuM5212 Data Sheet
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. Analog
Devices conducts an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM5210/
ADuM5211/ADuM5212.
Accelerated life testing is performed using voltage levels higher
than the rated continuous working voltage. Acceleration factors
for several operating conditions are determined, allowing
calculation of the time to failure at the working voltage of
interest. The values shown in Table 21 summarize the peak
voltages for 50 years of service life in several operating
conditions. In many cases, the working voltage approved by
agency testing is higher than the 50-year service life voltage.
Operation at working voltages higher than the service life
voltage listed leads to premature insulation failure.
The insulation lifetime of the ADuM5210/ADuM5211/
ADuM5212 depends on the voltage waveform type imposed
across the isolation barrier. The iCoupler insulation structure
degrades at different rates, depending on whether the wave-
form is bipolar ac, unipolar ac, or dc. Figure 30, Figure 31, and
Figure 32 illustrate these different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. A 50-year
operating lifetime under the bipolar ac condition determines
the Analog Devices recommended maximum working voltage.
In the case of dc or unipolar ac voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 21 can be applied while maintaining the
50-year minimum lifetime, provided the voltage conforms to either
the dc or unipolar ac voltage cases. Any cross-insulation voltage
waveform that does not conform to Figure 31 or Figure 32 must be
treated as a bipolar ac waveform, and its peak voltage must be
limited to the 50-year lifetime voltage value listed in Table 21.
0V
RATED P E AK V OL TAGE
10980-028
Figure 30. Bipolar AC Waveform
0V
RATED P E AK V OL TAGE
10980-029
Figure 31. DC Waveform
0V
RATED P E AK V OL TAGE
10980-030
NOTES
1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION
PUPOSES ONLY. IT I S MEANT TO REPRESENT ANY VOLTAGE
WAVEFORM VARYING BETWEEN 0V AND SOME LI MI T I NG VALUE.
THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE,
BUT THE VOL TAGE CANNOT CROSS 0V .
Figure 32. Unipolar AC Waveform
Rev. B | Page 22 of 24
Data Sheet ADuM5210/ADuM5211/ADuM5212
Rev. B | Page 23 of 24
OUTLINE DIMENSIONS
COMP LI ANT TO JEDE C S TANDARDS MO - 150-A E
060106-A
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 MIN
0.65 BS C
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 33. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Number
of Inputs,
VDDP Side
Number
of Inputs,
VISO Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Temperature
Range (°C)
Package
Description
Package
Option
ADuM5210ARSZ 2 0 1 75 40 −40 to +105 20-Lead SSOP RS-20
ADuM5210ARSZ-RL7 2 0 1 75 40 −40 to +105 20-Lead SSOP RS-20
ADuM5210BRSZ 2 0 25 40 3 −40 to +105 20-Lead SSOP RS-20
ADuM5210BRSZ-RL7 2 0 25 40 3 −40 to +105 20-Lead SSOP RS-20
ADuM5210CRSZ 2 0 100 15 2 −40 to +105 20-Lead SSOP RS-20
ADuM5210CRSZ-RL7 2 0 100 15 2 −40 to +105 20-Lead SSOP RS-20
ADuM5211ARSZ 1 1 1 75 40 −40 to +105 20-Lead SSOP RS-20
ADuM5211ARSZ-RL7 1 1 1 75 40 −40 to +105 20-Lead SSOP RS-20
ADuM5211BRSZ 1 1 25 40 3 −40 to +105 20-Lead SSOP RS-20
ADuM5211BRSZ-RL7 1 1 25 40 3 −40 to +105 20-Lead SSOP RS-20
ADuM5211CRSZ 1 1 100 15 2 −40 to +105 20-Lead SSOP RS-20
ADuM5211CRSZ-RL7 1 1 100 15 2 −40 to +105 20-Lead SSOP RS-20
ADuM5212ARSZ 0 2 1 75 40 −40 to +105 20-Lead SSOP RS-20
ADuM5212ARSZ-RL7 0 2 1 75 40 −40 to +105 20-Lead SSOP RS-20
ADuM5212BRSZ 0 2 25 40 3 −40 to +105 20-Lead SSOP RS-20
ADuM5212BRSZ-RL7 0 2 25 40 3 −40 to +105 20-Lead SSOP RS-20
ADuM5212CRSZ 0 2 100 15 2 −40 to +105 20-Lead SSOP RS-20
ADuM5212CRSZ-RL7 0 2 100 15 2 −40 to +105 20-Lead SSOP RS-20
1 The addition of an RL7 suffix designates a 7” tape and reel option.
2 Z = RoHS Compliant Part.
ADuM5210/ADuM5211/ADuM5212 Data Sheet
NOTES
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10980-0-4/15(B)
Rev. B | Page 24 of 24
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