DATA SH EET
Product specification
Supersedes data of 2002 Nov 15 2003 Jan 24
INTEGRATED CIRCUITS
74ALVC74
Dual D-type flip-flop with set and
reset; positive-edge trigger
2003 Jan 24 2
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
FEATURES
•Wide supply voltage range from 1.65 to 3.6 V
•Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V)
•3.6 V tolerant inputs/outputs
•CMOS low power consumption
•Direct interface with TTL levels (2.7 to 3.6 V)
•Power-down mode
•Latch-up performance exceeds 250 mA
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC74 is a dual positive-edge triggered, D-type
flip-flop with individual data (D), clock (CP), set (SD) and
reset (RD) inputs and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay nCP to nQ, nQV
CC = 1.8 V; CL= 30 pF; RL=1kΩ3.7 ns
VCC = 2.5 V; CL= 30 pF; RL= 500 Ω2.6 ns
VCC = 2.7 V; CL= 50 pF; RL= 500 Ω2.8 ns
VCC = 3.3 V; CL= 50 pF; RL= 500 Ω2.7 ns
tPHL/tPLH propagation delay nSD,nR
Dto nQ, nQV
CC = 1.8 V; CL= 30 pF; RL=1kΩ3.5 ns
VCC = 2.5 V; CL= 30 pF; RL= 500 Ω2.5 ns
VCC = 2.7 V; CL= 50 pF; RL= 500 Ω3.1 ns
VCC = 3.3 V; CL= 50 pF; RL= 500 Ω2.3 ns
fmax maximum clock frequency 425 MHz
CIinput capacitance 3.5 pF
CPD power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 35 pF
2003 Jan 24 3
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
ORDERING INFORMATION
FUNCTION TABLES
Table 1 See note 1
Table 2 See note 1
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑= LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH transition of CP.
TYPE NUMBER PACKAGE
PINS PACKAGE MATERIAL CODE
74ALVC74D 14 SO14 plastic SOT108-1
74ALVC74PW 14 TSSOP14 plastic SOT402-1
INPUT OUTPUT
nSDnRDnCP nD nQ nQ
LHXXHL
HLXXLH
LLXXHH
INPUT OUTPUT
nSDnRDnCP nD nQn+1 nQn+1
HH↑LLH
HH↑HHL
2003 Jan 24 4
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
PINNING
PIN SYMBOL DESCRIPTION
11
R
Dasynchronous reset-direct input (active LOW)
2 1D data input
3 1CP clock input (LOW-to-HIGH, edge-triggered)
41
S
Dasynchronous set-direct input (active LOW)
5 1Q true flip-flop output
61
Q complement flip-flop output
7 GND ground (0 V)
82
Q complement flip-flop output
9 2Q true flip-flop output
10 2SDasynchronous set-direct input (active LOW)
11 2CP clock input (LOW-to-HIGH, edge-triggered)
12 2D data input
13 2RDasynchronous reset-direct input (active LOW)
14 VCC supply voltage
Fig.1 Pin configuration.
handbook, halfpage
MNA417
74
1
2
3
4
5
6
78
14
13
12
11
10
9
1RD
1D
1CP
1SD
1Q
1Q
GND 2Q
2Q
2SD
2CP
2D
2RD
VCC
Fig.2 Logic diagram.
MNA418
handbook, halfpage
RD
FF
SD
410
Q1Q
2Q
1Q
2Q
5
9
2
12
3
11 6
8
Q
1SD
CP
2CP
1CP
2D
1D D
2SD
113
1RD2RD
2003 Jan 24 5
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
Fig.3 IEC logic symbol.
handbook, halfpage
MNA419
6
3
2C1
4S
1D
1R
5
8
11
12 C1
10 S
1D
13 R
9
Fig.4 Functional diagram.
handbook, halfpage
RD
FF
SD
4
Q1Q
1Q
5
2
3
6
Q
1SD
CP
1CP
1D D
11RD
MNA420
RD
FF
SD
10
Q2Q
2Q
9
12
11
8
Q
2SD
CP
2CP
2D D
13 2RD
Fig.5 Logic diagram (one flip-flop).
handbook, full pagewidth
MNA421
SD
CP
RD
D
C
C
Q
C
C
C
C
C
C
Q
C
C
2003 Jan 24 6
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage 1.65 3.6 V
VIinput voltage 0 3.6 V
VOoutput voltage VCC = 1.65 to 3.6 V 0 VCC V
VCC = 0 V; Power-down mode 0 3.6 V
Tamb operating ambient temperature −40 +85 °C
tr,t
finput rise and fall times VCC = 1.65 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +4.6 V
IIK input diode current VI<0 −−50 mA
VIinput voltage −0.5 +4.6 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage notes 1 and 2 −0.5 VCC + 0.5 V
Power-down mode; note 2 −0.5 +4.6 V
IOoutput source or sink current VO=0toV
CC −±50 mA
ICC, IGND VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation per package
SO package above 70 °C derate linearly with
8 mW/K −500 mW
TSSOP package above 60 °C derate linearly with
5.5 mW/K −500 mW
2003 Jan 24 7
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Note
1. All typical values are measured at Tamb =25°C.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb =−40 to +85 °C
VIH HIGH-level input
voltage 1.65 to 1.95 0.65 ×VCC −− V
2.3 to 2.7 1.7 −− V
2.7 to 3.6 2 −− V
V
IL LOW-level input
voltage 1.65 to 1.95 −−0.35 ×VCC V
2.3 to 2.7 −−0.7 V
2.7 to 3.6 −−0.8 V
VOL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 1.65 to 3.6 −−0.2 V
IO= 6 mA 1.65 −0.11 0.3 V
IO=12mA 2.3 −0.17 0.4 V
IO=18mA 2.3 −0.25 0.6 V
IO=12mA 2.7 −0.16 0.4 V
IO=18mA 3.0 −0.23 0.4 V
IO=24mA 3.0 −0.30 0.55 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 1.65 to 3.6 VCC −0.2 −− V
I
O
=−6 mA 1.65 1.25 1.51 −V
IO=−12 mA 2.3 1.8 2.10 −V
IO=−18 mA 2.3 1.7 2.01 −V
IO=−12 mA 2.7 2.2 2.53 −V
IO=−18 mA 3.0 2.4 2.76 −V
IO=−24 mA 3.0 2.2 2.68 −V
ILI input leakage
current VI= 3.6 Vor GND 3.6 −±0.1 ±5µA
Ioff powerOFFleakage
current VIor VO= 3.6 V 0.0 −±0.1 ±10 µA
ICC quiescent supply
current VI=V
CC or GND; IO= 0 3.6 −0.2 10 µA
∆ICC additional
quiescent supply
current per input
pin
VI=V
CC −0.6 V; IO= 0 3.0 to 3.6 −5 750 µA
2003 Jan 24 8
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
AC CHARACTERISTICS
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb =−40 to +85 °C
tPHL/tPLH propagation delay
nCP to nQ, nQ see Figs 5 and 7 1.65 to 1.95 1.0 3.7 6.2 ns
2.3 to 2.7 1.0 2.6 4.2 ns
2.7 1.0 2.8 4.2 ns
3.0 to 3.6 1.0 2.7 3.8 ns
tPHL/tPLH propagation delay
nSDto nQ, nQ see Figs 6 and 7 1.65 to 1.95 1.0 3.4 5.4 ns
2.3 to 2.7 1.0 2.4 3.8 ns
2.7 1.0 3.2 4.2 ns
3.0 to 3.6 1.0 2.3 3.5 ns
tPHL/tPLH propagation delay
nRDto nQ, nQ see Figs 6 and 7 1.65 to 1.95 1.0 3.5 5.4 ns
2.3 to 2.7 1.0 2.5 3.8 ns
2.7 1.0 3.1 4.3 ns
3.0 to 3.6 1.0 2.3 3.5 ns
tWclock pulse width
HIGH or LOW see Figs 5 and 7 1.65 to 1.95 2.5 0.9 −ns
2.3 to 2.7 2.5 0.6 −ns
2.7 2.5 1.3 −ns
3.0 to 3.6 2.5 1.3 −ns
tWset or reset pulse width LOW see Figs 6 and 7 1.65 to 1.95 2.5 0.9 −ns
2.3 to 2.7 2.5 0.9 −ns
2.7 2.5 1.0 −ns
3.0 to 3.6 2.5 0.7 −ns
trem removal time set or reset see Figs 6 and 7 1.65 to 1.95 0.7 −0.2 −ns
2.3 to 2.7 0.7 −0.1 −ns
2.7 0.7 −0.1 −ns
3.0 to 3.6 0.7 −0.1 −ns
tsu set-up time nD to nCP see Figs 5 and 7 1.65 to 1.95 1.2 0.6 −ns
2.3 to 2.7 1.2 0.8 −ns
2.7 0.9 0.5 −ns
3.0 to 3.6 0.8 0.4 −ns
thhold time nD to nCP see Figs 5 and 7 1.65 to 1.95 0.6 −0.4 −ns
2.3 to 2.7 0.6 −0.3 −ns
2.7 0.7 −0.4 −ns
3.0 to 3.6 0.8 −0.1 −ns
2003 Jan 24 9
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
Note
1. All typical values are measured at Tamb =25°C.
AC WAVEFORMS
fmax maximum clock pulse
frequency see Figs 5 and 7 1.65 to 1.95 150 275 −MHz
2.3 to 2.7 200 325 −MHz
2.7 250 375 −MHz
3.0 to 3.6 300 425 −MHz
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
handbook, full pagewidth
MNA422
th
tsu
th
tPHL
tPHL
tW
tPLH
tPLH
tsu
1/fmax
VM
VM
VM
VM
VI
GND
VI
GND
nCP input
nD input
VOH
VOL
nQ output
VOH
VOL
nQ output
Fig.5 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the
nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
VCC VMINPUT
VItr=t
f
1.65 to 1.95 V 0.5 ×VCC VCC ≤2.0 ns
2.3 to 2.7 V 0.5 ×VCC VCC ≤2.0 ns
2.7 V 1.5 V 2.7 V ≤2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns
2003 Jan 24 10
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
handbook, full pagewidth
MNA423
trem
tPHL
tPHL
tW
tPLH
tPLH
VM
VM
VM
tW
VM
VM
VI
GND
VI
GND
nSD input
VI
GND
nRD input
nCP input
VOH
VOL
nQ output
VOH
VOL
nQ output
Fig.6 The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths
and the nRDto nCP removal time.
VCC VMINPUT
VItr=t
f
1.65 to 1.95 V 0.5 ×VCC VCC ≤2.0 ns
2.3 to 2.7 V 0.5 ×VCC VCC ≤2.0 ns
2.7 V 1.5 V 2.7 V ≤2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns
2003 Jan 24 11
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
handbook, full pagewidth
VEXT
VCC
VIVO
MNA616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
Fig.7 Load circuitry for switching times.
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
VCC VICLRLVEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
1.65 to 1.95 V VCC 30 pF 1 kΩopen GND 2 ×VCC
2.3 to 2.7 V VCC 30 pF 500 Ωopen GND 2 ×VCC
2.7 V 2.7 V 50 pF 500 Ωopen GND 6 V
3.0 to 3.6 V 2.7 V 50 pF 500 Ωopen GND 6 V
2003 Jan 24 12
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
PACKAGE OUTLINES
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.050
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
97-05-22
99-12-27
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
2003 Jan 24 13
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21.0
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 95-04-04
99-12-27
w
M
b
p
D
Z
e
0.25
17
14 8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.10
pin 1 index
2003 Jan 24 14
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butitis not suitable forfinepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit board by screenprinting,stencillingor
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleadsonfoursides, the footprint must
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2003 Jan 24 15
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formoredetailedinformation on the BGA packagesrefertothe
“(LF)BGAApplicationNote
”(AN01026);ordera copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
2003 Jan 24 16
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratanyotherconditionsabovethosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarranty thatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingor sellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2003 Jan 24 17
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
NOTES
2003 Jan 24 18
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
NOTES
2003 Jan 24 19
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
NOTES
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands 613508/02/pp20 Date of release: 2003 Jan 24 Document order number: 9397 750 10973
