NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Based on DDR2-667/800 128Mx8 (1GB/2GB) and 256MX4 (2GB/4GB) SDRAM D-Die Features * 1GB/2GB: 128Mx72/256Mx72 Registered DDR2 DIMM based on 128Mx8 DDR2 SDRAM. (NT5TU128M8DE) * 2GB/4GB: 256Mx72/512MX72 Registered DDR2 DIMM based on 256Mx4 DDR2 SDRAM. (NT5TU256M4DE) * 240-Pin Registered Dual In-Line Memory Module (RDIMM) * Error Check Correction (ECC) Support * Phase-lock loop (PLL) clock driver to reduce loading * Performance: Speed Sort DIMM Latency fck - Clock Freqency tck - Clock Cycle fDQ - DQ Burst Freqency * Differential clock inputs * Off-Chip Driver (OCD) Impedance Adjustment * On Die Termination * Data is read or written on both clock edges * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble * Programmable Operation: - Device Latency: 3,4,5,6 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 14/11/2 (row/column/rank) Addressing for 4GB 14/11/1 (row/column/rank) Addressing for 2GB 14/10/1 (row/column/rank) Addressing for 1GB/2GB * Serial Presence Detect * Gold contacts * SDRAMs in 60-ball BGA Package * RoHS Complianc PC2-5300 PC2-6400 Unit -3C -AD 5 6 333 400 3 2.5 ns 667 800 Mbps MHz * Intended for 333MHz & 400MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = 1.8Volt 0.1Volt, VDDQ = 1.8Volt 0.1Volt * SDRAMs have 8 internal banks for concurrent operation * One clock cycle added for registered DIMMs to account for input register Description NT1GT72U89D0BV, NT2GT72U4PD0BV, NT2GT72U8PD0BV and NT4GT72U4ND0BV are Registered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one rank 128Mx72, 256Mx72 high-speed memory array and two ranks 512MX72 high-speed memory array. The module uses nine 128Mx8 (NT1GT72U89D0BV), eighteen 128Mx8 (NT2GT72U8PD0BV), eighteen 256Mx4 (NT2GT72U4PD0BV) and thirty-six 256Mx4 (NT4GT72U4ND0BV) DDR2 SDRAMs in BGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 333 MHz (or 400 MHz) clock speeds and achieves high-speed data transfer rates of up to 667Mbps (or 800Mbps ). Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.1 01/2009 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Ordering Information Part Number Speed Organization NT1GT72U89D0BV-3C NT2GT72U4PD0BV-3C 333MHz (3ns @ CL = 5) NT2GT72U8PD0BV-3C DDR2-667 PC2-5300 Gold 1.8V 256Mx72 512Mx72 NT1GT72U89D0BV-AD 128Mx72 NT2GT72U8PD0BV-AD Power 256Mx72 NT4GT72U4ND0BV-3C NT2GT72U4PD0BV-AD Leads 128Mx72 400MHz (2.5ns @ CL = 6) DDR2-800 PC2-6400 NT4GT72U4ND0BV-AD 256Mx72 256Mx72 512Mx72 Pin Description Pin Name CK0 CKE[1:0] Pin Name Description Clock Input, positive line Description ODT[1:0] On Die Termination Inputs Clock input, negative line DQ[63:0] Data input/output Clock Enables CB[7:0] Row Address Strobe DQS[8:0] Column Address Strobe [8:0] Write Enable [1:0] A[9:0], A[13:11] [17:9] Address Inputs Address Input/Autoprecharge BA[2:0] Data strobes Data strobes / negative line DM[8:0] / DQS[17:9] Data Masks / Data strobes Chip Selects A10/AP Data Check Bit Input/Output RFU NC Data strobes / negative line Reserved for Future use No Connect SDRAM Bank Addresses TEST Memory bus test tool SCL Serial Presence Detect (SPD) Clock Input VDDSPD Serial EEPROM positive power supply SDA SPD Data Input/Output VSS Ground SA[2:0] SPD Address Inputs VDD Core Power Par_In Parity bit for the Address and Control bus VDDQ I/O Power Parity error found on the Address and Control bus VREF Input/Output Reference Register and PLL control pin REV 1.1 01/2009 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin Front Back Pin Back Pin Back 1 VREF 2 VSS 121 VSS 162 CB5 202 DM4/DQS13 122 DQ4 163 VSS 203 3 DQ0 44 DQS4 123 DQ5 164 DM8/DQS17 204 4 DQ1 45 VSS 85 VSS 124 VSS 165 205 DQ38 5 VSS 46 47 DQS8 86 DQ34 125 DM0 / DQS9 166 VSS 206 DQ39 VSS 87 DQ35 126 167 CB6 207 DQS0 VSS 48 CB2 88 VSS 127 VSS 168 CB7 208 DQ44 8 9 VSS 49 CB3 89 DQ40 128 DQ6 169 VSS 209 DQ45 DQ2 50 VSS 90 DQ41 129 DQ7 170 VDDQ 210 VSS 10 DQ3 11 VSS 51 VDDQ 91 VSS 130 VSS 171 NC,CKE1 211 DM5/DQS14 52 CKE0 92 131 DQ12 172 VDD 212 12 DQ8 53 VDD 93 DQS5 132 DQ13 173 NC 213 VSS 13 DQ9 54 BA2 94 VSS 133 VSS 174 NC 214 DQ46 14 VSS 55 DM1/DQS10 175 VDDQ 215 DQ47 176 A12 216 VSS 217 DQ52 6 7 15 Pin Front Pin Front Pin 42 CB0 82 VSS 43 CB1 83 VSS 84 NC, NC, 95 DQ42 134 56 VDDQ 96 DQ43 135 A11 97 VSS 136 VSS 177 A9 NC, NC, NC, 16 DQS1 57 17 VSS 58 A7 98 DQ48 137 RFU 178 VDD 218 DQ53 59 VDD 99 DQ49 138 RFU 179 A8 219 VSS 18 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 RFU 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 RFU 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS 142 VSS 183 A1 223 DM6/DQS15 23 VSS 64 VDD 104 143 DQ20 184 VDD 224 24 DQ16 25 DQ17 65 26 VSS 27 KEY 105 DQS6 144 DQ21 VSS 106 VSS 145 VSS 185 66 VSS 107 DQ50 146 DM2/DQS11 186 67 VDD 108 DQ51 147 NC, KEY 187 CK0 NC, 225 VSS 226 DQ54 227 DQ55 VDD 228 VSS 28 DQS2 68 Par_In 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS 151 VSS 191 VDDQ 232 DM7/DQS16 32 VSS 72 VDDQ 113 152 DQ28 192 233 33 DQ24 73 114 DQS7 153 DQ29 193 234 VSS 34 DQ25 74 115 VSS 154 VSS 194 VDDQ 235 DQ62 35 Vss 75 VDDQ 116 DQ58 155 DM3/DQS12 195 ODT0 236 DQ63 76 NC, 117 DQ59 156 196 A13 237 VSS 36 NC, NC, 37 DQS3 77 NC, ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 Vss 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 Vss 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 Vss 81 DQ33 161 CB4 201 VSS Note: NC = No Connect; RFU = Reserved Future Use ODT1, CKE1, = for4GB module uses only DQS9~DQS17 & ~ = for 2GB/4GB modules use only REV 1.1 01/2009 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Input/Output Functional Description Symbol Type CK0 IN Positive Positive line of the differential pair of system clock inputs that drives input to the Edge on-DIMM PLL. 0 IN Negative Negative line of the differential pair of system clock inputs that drives the input to the Edge on-DIMM PLL. CKE[1:0] IN Polarity Function Active High CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) [1:0] IN Active Low Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations continue. These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both [0:1] are high, all register outputs (except CKE, ODT and Chip select) remain in the previous state. For modules supporting 4 ranks, [2:3] operate similarly to [0:1] for a second set of register outputs. , IN Active Low When sampled at the positive rising edge of the clock, operation to be executed by the SDRAM. , , , define the VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR2 SDRAM output buffers to provide improved noise immunity ODT[1:0] IN Active High BA[2:0] IN - Selects which SDRAM bank is to be active. On-Die Termination control signals A[13:11,10/AP,9:0] IN - During a Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1,BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to precharge. DQ[63:0] CB[7:0] I/O - Data and Check Bit Input/Output pins. VDD, VSS Supply - Power and ground for the DDR2 SDRAM input buffers and core logic DQS[17:0] I/O Positive Data strobe for input and output data Edge [17:0] I/O Negative Data strobe for input and output data Edge I/O Active High Masks write data when high, issued concurrently with input data. IN Active Low The pin is connected to the pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be nset to low level (the PLL will remain synchronized with the input clock) SA[2:0] IN - These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA I/O - This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up. SCL IN - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. V DDSPD Supply - Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt and 3.3 Volt) operation. DM[8:0] Par_In REV 1.1 01/2009 IN - Parity bit for the Address and Control bus. (1 for Odd, 0 for Even) OUT - Parity error found in the Address and Control bus. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Functional Block Diagram: Raw Card Version F [1GB, 1Rank, 128Mx8 DDR2 SDRAMs] REV 1.1 01/2009 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Functional Block Diagram: Raw Card Version G [2GB, 2Rank, 128Mx8 DDR2 SDRAMs] REV 1.1 01/2009 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Functional Block Diagram: Raw Card Version H [2GB, 1Rank, 256Mx4 DDR2 SDRAMs] $ $ $ $ ! ! ! ! $ $ $ $ ! ! ! ! ! ! ! ! $ $ $ $ ! ! ! ! $ $ $ $ ! ! ! ! $ $ $ $ ! ! ! ! $ $ $ $ ! ! ! ! $ $ $ $ ! ! ! ! $ $ $ $ ! ! ! ! $ $ $ $ ! ! ! ! 3 $ $ $ $ 5 6 3 5 6 3 5 6 5 5 5 6 3 5 5 5 6 6 5 5 5 5 $ $ $ $ ! ! ! ! 55 56 53 5 6 $ $ $ $ ! ! ! ! $ $ $ $ ! ! ! ! 5 5 6 6 & , 5 & , " $ $ $ $ ! ! ! ! 6 6 65 66 3 63 6 6 6 $ $ $ $ 3 3 3 3 ! ! ! ! /)'' /, ,) % )( $ $ $ $ ! ! ! ! %% 3 %%% $ $ $ $ 11 # $ " ! " 11111 11111 1111 ! " %% $ $ $ $ '* )( '* )( & , /)'' /, ,)9),2 /)'' /, ,))' )(,8) & , 2 ; ,2 )>, )' >. *)8' )2+ @4 82/2 & , /)'' /, ,) '), '*/ , * 2 & , 7 7 7 7 ,) 7 ! ! ! ! 11 &' / 111 111 111 &' & , '* () ** '* )++ '* ,- .'/, )' & , 1$0 )2+ ! " 1$0 & , ! 1$0 ! !., " %% REV 1.1 01/2009 5 6 3 ! ! ! ! )( & , '* "4 !,2 ? " %% ! 7 ,) $ ! 8 '& + -9 /2 '& * 8 ,2' '99 7 7 :' ),2 8 '), *4 ,) ; . !2+ <6= 6 3 3 %%% %%% 4 4 6 6 3 3 % 34 34 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Functional Block Diagram: Raw Card Version AF [4GB, 2Ranks, 256Mx4 DDR2 SDRAMs] REV 1.1 01/2009 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Serial Presence Detect (Part 1 of 2) Byte [NT1GT72U89D0BV, 1GB - 1 Rank, 128Mx8 DDR2 SDRAMs] Description 0 1 2 3 4 5 6 7 8 9 10 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Ranks Data Width of Assembly Reserved Voltage Interface Level of this Assembly DDR2 SDRAM Device Cycle Time at CL=X DDR2 SDRAM Device Access Time from Clock at CL=X 11 DIMM Configuration Type 12 13 14 15 16 17 18 19 20 Refresh Rate/Type Primary DDR2 SDRAM Width Error Checking DDR2 SDRAM Device Width Reserved DDR2 SDRAM Device Attributes: Burst Length Supported DDR2 SDRAM Device Attributes: Number of Device Banks DDR2 SDRAM Device Attributes: CAS Latencies Supported DIMM Mechanical Characteristics DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Minimum Clock Cycle at CL=X-1 Maximum Data Access Time from Clock at CL=X-1 Minimum Clock Cycle Time at CL=X-2 Maximum Data Access Time from Clock at CL=X-2 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock (tIS) Address and Command Hold Time After Clock (tIH) Data Input Setup Time Before Clock (tDS) Data Input Hold Time After Clock (tDH) Write Recovery Time (tWR) Internal Write to Read Command delay (tWTR) Internal Read to Precharge delay (tRTP) Reserved 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 42 43 44 45 Minimum Core Cycle Time (tRC) Min. Auto Refresh Command Cycle Time (tRFC) Maximum Clock Cycle Time (tCK) Max. DQS-DQ Skew Factor (tDQS) Read Data Hold Skew Factor (tQHS) 46 PLL Relock Time 47 Tcasemax, DT4R4W Delta Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) DRAM Case Temperature Rise from Ambient due to ActivatePrecharge/Mode Bits (DT0/Mode Bits) DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) DRAM Case Temperature Rise from Ambient due to Active PowerDown with Fast PDN Exit (DT3P fast) 48 49 50 51 52 53 REV 1.1 01/2009 SPD Entry Value Serial PD Data Entry (Hex.) -3C -AD 128 128 256 256 DDR2 SDRAM DDR2 SDRAM 14 14 10 10 Module Height = 30.0mm, 1 rank Module Height = 30.0mm, 1 rank X72 X72 Undefined Undefined SSTL 1.8V SSTL 1.8V 3ns 2.5ns 0.45ns 0.4ns Address/Command Parity, Address/Command Parity, Data ECC, Data ECC, Non Data Parity, Non Data Parity, 7.8 As 7.8 As X8 X8 X8 X8 Undefined Undefined 4,8 4,8 8 8 3,4,5 4,5,6 x B 4.10 (mm) x B 4.10 (mm) RDIMM (133.35mm) RDIMM (133.35mm) Analysis probe installed : No, Analysis probe installed : No, FET Switch External Enable : No, FET Switch External Enable : No, Number of PLLs : 1, Number of PLLs : 1, Number of Active Registers : 1, Number of Active Registers : 1, Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 3.75ns 0.5ns 5ns 0.6ns 15ns 7.5ns 15ns 45ns 1GB 0.2ns 0.27ns 0.1ns 0.17ns 15ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 60ns 127.5ns 8ns 0.24ns 0.34ns Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 3ns 0.45ns 3.75ns 0.5ns 15ns 7.5ns 15ns 45ns 1GB 0.17ns 0.25ns 0.05ns 0.12ns 15ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 60ns 127.5ns 8ns 0.2ns 0.3ns -3C 80 08 08 0E 0A 60 48 00 05 30 45 -AD 80 08 08 0E 0A 60 48 00 05 25 40 06 06 82 08 08 00 0C 08 38 01 01 82 08 08 00 0C 08 70 01 01 04 04 07 07 3D 50 50 60 3C 1E 3C 2D 01 20 27 10 17 3C 1E 1E 00 30 45 3D 50 3C 1E 3C 2D 01 17 25 05 12 3C 1E 1E 00 06 06 3C 7F 80 18 22 3C 7F 80 14 1E 0F 15As 15As 0F Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Serial Presence Detect (Part 1 of 2) Byte [NT1GT72U89D0BV, 1GB - 1 Rank, 128Mx8 DDR2 SDRAMs] Description 0 1 2 3 4 5 6 7 8 9 10 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Ranks Data Width of Assembly Reserved Voltage Interface Level of this Assembly DDR2 SDRAM Device Cycle Time at CL=X DDR2 SDRAM Device Access Time from Clock at CL=X 11 DIMM Configuration Type 12 13 14 Refresh Rate/Type Primary DDR2 SDRAM Width Error Checking DDR2 SDRAM Device Width REV 1.1 01/2009 SPD Entry Value Serial PD Data Entry (Hex.) -3C -AD 128 128 256 256 DDR2 SDRAM DDR2 SDRAM 14 14 10 10 Module Height = 30.0mm, 1 rank Module Height = 30.0mm, 1 rank X72 X72 Undefined Undefined SSTL 1.8V SSTL 1.8V 3ns 2.5ns 0.45ns 0.4ns Address/Command Parity, Address/Command Parity, Data ECC, Data ECC, Non Data Parity, Non Data Parity, 7.8 As 7.8 As X8 X8 X8 X8 -3C 80 08 08 0E 0A 60 48 00 05 30 45 -AD 80 08 08 0E 0A 60 48 00 05 25 40 06 06 82 08 08 82 08 08 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Serial Presence Detect (Part 1 of 2) Byte [NT2GT72U4PD0BV, 2GB - 1 Rank, 256Mx4 DDR2 SDRAMs] Description 0 1 2 3 4 5 6 7 8 9 10 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Ranks Data Width of Assembly Reserved Voltage Interface Level of this Assembly DDR2 SDRAM Device Cycle Time at CL=X DDR2 SDRAM Device Access Time from Clock at CL=X 11 DIMM Configuration Type 12 13 14 15 16 17 18 19 20 Refresh Rate/Type Primary DDR2 SDRAM Width Error Checking DDR2 SDRAM Device Width Reserved DDR2 SDRAM Device Attributes: Burst Length Supported DDR2 SDRAM Device Attributes: Number of Device Banks DDR2 SDRAM Device Attributes: CAS Latencies Supported DIMM Mechanical Characteristics DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Minimum Clock Cycle at CL=X-1 Maximum Data Access Time from Clock at CL=X-1 Minimum Clock Cycle Time at CL=X-2 Maximum Data Access Time from Clock at CL=X-2 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock (tIS) Address and Command Hold Time After Clock (tIH) Data Input Setup Time Before Clock (tDS) Data Input Hold Time After Clock (tDH) Write Recovery Time (tWR) Internal Write to Read Command delay (tWTR) Internal Read to Precharge delay (tRTP) Reserved 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 42 43 44 45 Minimum Core Cycle Time (tRC) Min. Auto Refresh Command Cycle Time (tRFC) Maximum Clock Cycle Time (tCK) Max. DQS-DQ Skew Factor (tDQS) Read Data Hold Skew Factor (tQHS) 46 PLL Relock Time 47 Tcasemax, DT4R4W Delta Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) DRAM Case Temperature Rise from Ambient due to ActivatePrecharge/Mode Bits (DT0/Mode Bits) DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) DRAM Case Temperature Rise from Ambient due to Active PowerDown with Fast PDN Exit (DT3P fast) 48 49 50 51 52 53 REV 1.1 01/2009 SPD Entry Value Serial PD Data Entry (Hex.) -3C -AD 128 128 256 256 DDR2 SDRAM DDR2 SDRAM 14 14 11 11 Module Height = 30.0mm, 1 rank Module Height = 30.0mm, 1 rank X72 X72 Undefined Undefined SSTL 1.8V SSTL 1.8V 3ns 2.5ns 0.45ns 0.4ns Address/Command Parity, Address/Command Parity, Data ECC, Data ECC, Non Data Parity, Non Data Parity, 7.8 As 7.8 As X4 X4 X4 X4 Undefined Undefined 4,8 4,8 8 8 3,4,5 4,5,6 x B 4.10 (mm) x B 4.10 (mm) RDIMM (133.35mm) RDIMM (133.35mm) Analysis probe installed : No, Analysis probe installed : No, FET Switch External Enable : No, FET Switch External Enable : No, Number of PLLs : 1, Number of PLLs : 1, Number of Active Registers : 2, Number of Active Registers : 2, Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 3.75ns 0.5ns 5ns 0.6ns 15ns 7.5ns 15ns 45ns 2GB 0.2ns 0.27ns 0.1ns 0.17ns 15ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 60ns 127.5ns 8ns 0.24ns 0.34ns Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 3ns 0.45ns 3.75ns 0.5ns 15ns 7.5ns 15ns 45ns 2GB 0.17ns 0.25ns 0.05ns 0.12ns 15ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 60ns 127.5ns 8ns 0.2ns 0.3ns -3C 80 08 08 0E 0B 60 48 00 05 30 45 -AD 80 08 08 0E 0B 60 48 00 05 25 40 06 06 82 04 04 00 0C 08 38 01 01 82 04 04 00 0C 08 70 01 01 05 05 07 07 3D 50 50 60 3C 1E 3C 2D 02 20 27 10 17 3C 1E 1E 00 30 45 3D 50 3C 1E 3C 2D 02 17 25 05 12 3C 1E 1E 00 06 06 3C 7F 80 18 22 3C 7F 80 14 1E 15As 15As 0F 0F Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Serial Presence Detect (Part 1 of 2) Byte 54 55 56 57 58 59 60 61 62 63 64-71 72 73-91 [NT2GT72U4PD0BV, 2GB - 1 Rank, 256Mx4 DDR2 SDRAMs] SPD Entry Value Description -AD -3C -AD Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 1.3 1.3 13 13 Checksum Data Checksum Data 3A 04 Nanya Nanya DRAM Case Temperature Rise from Ambient due to Active PowerDown with Slow PDN Exit (DT3P slow) DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) SPD Revision Checksum for Byte 0-62 Manufacturer's JEDEC ID Code Module Manufacturing Location Module Part Number 01/2009 7F7F7F0B00000000 Manufacturing code Manufacturing code -- -- Module Part Number in ASCII Module Part Number in ASCII -- -- Undefined Undefined -- -- 92-255 Reserved Note1: NT2GT72U4PD0BV-3C -> 4E543247543732553450443042562D33432020 NT2GT72U4PD0BV-AD -> 4E543247543732553450443042562D41442020 REV 1.1 Serial PD Data Entry (Hex.) -3C 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Serial Presence Detect (Part 1 of 2) Byte [NT2GT72U8PD0BV, 2GB - 2 Ranks, 128Mx8 DDR2 SDRAMs] Description 0 1 2 3 4 5 6 7 8 9 10 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Ranks Data Width of Assembly Reserved Voltage Interface Level of this Assembly DDR2 SDRAM Device Cycle Time at CL=X DDR2 SDRAM Device Access Time from Clock at CL=X 11 DIMM Configuration Type 12 13 14 15 16 17 18 19 20 Refresh Rate/Type Primary DDR2 SDRAM Width Error Checking DDR2 SDRAM Device Width Reserved DDR2 SDRAM Device Attributes: Burst Length Supported DDR2 SDRAM Device Attributes: Number of Device Banks DDR2 SDRAM Device Attributes: CAS Latencies Supported DIMM Mechanical Characteristics DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Minimum Clock Cycle at CL=X-1 Maximum Data Access Time from Clock at CL=X-1 Minimum Clock Cycle Time at CL=X-2 Maximum Data Access Time from Clock at CL=X-2 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock (tIS) Address and Command Hold Time After Clock (tIH) Data Input Setup Time Before Clock (tDS) Data Input Hold Time After Clock (tDH) Write Recovery Time (tWR) Internal Write to Read Command delay (tWTR) Internal Read to Precharge delay (tRTP) Reserved 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 42 43 44 45 Minimum Core Cycle Time (tRC) Min. Auto Refresh Command Cycle Time (tRFC) Maximum Clock Cycle Time (tCK) Max. DQS-DQ Skew Factor (tDQS) Read Data Hold Skew Factor (tQHS) 46 PLL Relock Time 47 Tcasemax, DT4R4W Delta Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) DRAM Case Temperature Rise from Ambient due to ActivatePrecharge/Mode Bits (DT0/Mode Bits) DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) DRAM Case Temperature Rise from Ambient due to Active PowerDown with Fast PDN Exit (DT3P fast) 48 49 50 51 52 53 REV 1.1 01/2009 SPD Entry Value Serial PD Data Entry (Hex.) -3C -AD 128 128 256 256 DDR2 SDRAM DDR2 SDRAM 14 14 10 10 Module Height = 30.0mm, 2 Module Height = 30.0mm, 2 ranks ranks X72 X72 Undefined Undefined SSTL 1.8V SSTL 1.8V 3ns 2.5ns 0.45ns 0.4ns Address/Command Parity, Address/Command Parity, Data ECC, Data ECC, Non Data Parity, Non Data Parity, 7.8 As 7.8 As X8 X8 X8 X8 Undefined Undefined 4,8 4,8 8 8 3,4,5 4,5,6 x B 4.10 (mm) x B 4.10 (mm) RDIMM (133.35mm) RDIMM (133.35mm) Analysis probe installed : No, Analysis probe installed : No, FET Switch External Enable : No, FET Switch External Enable : No, Number of PLLs : 1, Number of PLLs : 1, Number of Active Registers : 2, Number of Active Registers : 2, Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 3.75ns 0.5ns 5ns 0.6ns 15ns 7.5ns 15ns 45ns 1GB 0.2ns 0.27ns 0.1ns 0.17ns 15ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 60ns 127.5ns 8ns 0.24ns 0.34ns Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 3ns 0.45ns 3.75ns 0.5ns 15ns 7.5ns 15ns 45ns 1GB 0.17ns 0.25ns 0.05ns 0.12ns 15ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 60ns 127.5ns 8ns 0.2ns 0.3ns -3C 80 08 08 0E 0A 61 48 00 05 30 45 -AD 80 08 08 0E 0A 61 48 00 05 25 40 06 06 82 08 08 00 0C 08 38 01 01 82 08 08 00 0C 08 70 01 01 05 05 07 07 3D 50 50 60 3C 1E 3C 2D 01 20 27 10 17 3C 1E 1E 00 30 45 3D 50 3C 1E 3C 2D 01 17 25 05 12 3C 1E 1E 00 06 06 3C 7F 80 18 22 3C 7F 80 14 1E 15As 15As 0F 0F Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Serial Presence Detect (Part 1 of 2) Byte 54 55 56 57 58 59 60 61 [NT2GT72U8PD0BV, 2GB - 2 Ranks, 128Mx8 DDR2 SDRAMs] SPD Entry Value Description -AD -3C -AD Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 1.3 1.3 13 13 Checksum Data Checksum Data 41 0B DRAM Case Temperature Rise from Ambient due to Active PowerDown with Slow PDN Exit (DT3P slow) DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 62 SPD Revision 63 Checksum for Byte 0-62 Serial PD Data Entry (Hex.) -3C 7F7F7F0B00000000 64-71 Manufacturer's JEDEC ID Code Nanya Nanya 72 Module Manufacturing Location Manufacturing code Manufacturing code -- -- Module Part Number in ASCII Module Part Number in ASCII -- -- Undefined Undefined -- -- 73-91 Module Part Number 92-255 Reserved Note1: NT2GT72U8PD0BV-3C -> 4E543247543732553850443042562D33432020 NT2GT72U8PD0BV-AD -> 4E543247543732553850443042562D41442020 REV 1.1 01/2009 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Serial Presence Detect (Part 1 of 2) Byte [NT4GT72U4ND0BV, 4GB - 2 Ranks, 256Mx4 DDR2 SDRAMs] Description 0 1 2 3 4 5 6 7 8 9 10 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Ranks Data Width of Assembly Reserved Voltage Interface Level of this Assembly DDR2 SDRAM Device Cycle Time at CL=X DDR2 SDRAM Device Access Time from Clock at CL=X 11 DIMM Configuration Type 12 13 14 15 16 17 18 19 20 Refresh Rate/Type Primary DDR2 SDRAM Width Error Checking DDR2 SDRAM Device Width Reserved DDR2 SDRAM Device Attributes: Burst Length Supported DDR2 SDRAM Device Attributes: Number of Device Banks DDR2 SDRAM Device Attributes: CAS Latencies Supported DIMM Mechanical Characteristics DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Minimum Clock Cycle at CL=X-1 Maximum Data Access Time from Clock at CL=X-1 Minimum Clock Cycle Time at CL=X-2 Maximum Data Access Time from Clock at CL=X-2 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock (tIS) Address and Command Hold Time After Clock (tIH) Data Input Setup Time Before Clock (tDS) Data Input Hold Time After Clock (tDH) Write Recovery Time (tWR) Internal Write to Read Command delay (tWTR) Internal Read to Precharge delay (tRTP) Reserved 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 42 43 44 45 Minimum Core Cycle Time (tRC) Min. Auto Refresh Command Cycle Time (tRFC) Maximum Clock Cycle Time (tCK) Max. DQS-DQ Skew Factor (tDQS) Read Data Hold Skew Factor (tQHS) 46 PLL Relock Time 47 Tcasemax, DT4R4W Delta Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) DRAM Case Temperature Rise from Ambient due to ActivatePrecharge/Mode Bits (DT0/Mode Bits) DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) DRAM Case Temperature Rise from Ambient due to Active PowerDown with Fast PDN Exit (DT3P fast) 48 49 50 51 52 53 REV 1.1 01/2009 SPD Entry Value -3C 128 256 DDR2 SDRAM 14 11 Module Height = 30.0mm, 2 ranks X72 Undefined SSTL 1.8V 3ns 0.45ns Address/Command Parity, Data ECC, Non Data Parity, 7.8 As X4 X4 Undefined 4,8 8 3,4,5 x B 4.10 (mm) RDIMM (133.35mm) Serial PD Data Entry (Hex.) -AD 128 256 DDR2 SDRAM 14 11 Module Height = 30.0mm, 2 ranks X72 Undefined SSTL 1.8V 2.5ns 0.4ns Address/Command Parity, Data ECC, Non Data Parity, 7.8 As X4 X4 Undefined 4,8 8 4,5,6 x B 4.10 (mm) RDIMM (133.35mm) Analysis probe installed : No, Analysis probe installed : No, FET Switch External Enable : No, FET Switch External Enable : No, Number of PLLs : 1, Number of PLLs : 1, Number of Active Registers : 4, Number of Active Registers : 4, Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 3.75ns 0.5ns 5ns 0.6ns 15ns 7.5ns 15ns 45ns 2GB 0.2ns 0.27ns 0.1ns 0.17ns 15ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 60ns 127.5ns 8ns 0.24ns 0.34ns Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 3ns 0.45ns 3.75ns 0.5ns 15ns 7.5ns 15ns 45ns 2GB 0.17ns 0.25ns 0.05ns 0.12ns 15ns 7.5ns 7.5ns Undefined The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 60ns 127.5ns 8ns 0.2ns 0.3ns -3C 80 08 08 0E 0B 61 48 00 05 30 45 -AD 80 08 08 0E 0B 61 48 00 05 25 40 06 06 82 04 04 00 0C 08 38 01 01 82 04 04 00 0C 08 70 01 01 07 07 07 07 3D 50 50 60 3C 1E 3C 2D 02 20 27 10 17 3C 1E 1E 00 30 45 3D 50 3C 1E 3C 2D 02 17 25 05 12 3C 1E 1E 00 06 06 3C 7F 80 18 22 3C 7F 80 14 1E 0F 15As 15As 0F Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Serial Presence Detect (Part 1 of 2) Byte 54 55 56 57 58 59 60 61 SPD Entry Value SPD Revision 63 Checksum for Byte 0-62 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location Module Part Number -AD -3C -AD Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 Undefined Undefined 00 00 1.3 1.3 13 13 Checksum Data Checksum Data 3D 07 Nanya Nanya 01/2009 7F7F7F0B00000000 Manufacturing code Manufacturing code -- Module Part Number in ASCII Module Part Number in ASCII -- -- Undefined Undefined -- -- 92-255 Reserved Note1: NT4GT72U4ND0BV-3C -> 4E54344754373255344E443042562D33432020 NT4GT72U4ND0BV-AD -> 4E54344754373255344E443042562D41442020 REV 1.1 Serial PD Data Entry (Hex.) -3C DRAM Case Temperature Rise from Ambient due to Active PowerDown with Slow PDN Exit (DT3P slow) DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 62 73-91 [NT4GT72U4ND0BV, 4GB - 2 Ranks, 256Mx4 DDR2 SDRAMs] Description -- 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol Rating Units Voltage on I/O pins relative to VSS -0.5 to 2.3 V Voltage on VDD supply relative to VSS -1.0 to 2.3 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to 2.3 V VDDL Voltage on VDDL supply relative to VSS -0.5 to 2.3 V VIN, VOUT VDD Parameter Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Environmental Parameters Symbol Parameter Rating Units Note TOPR Operating temperature (ambient) See Note HOPR Operating Humidity (relative) 10 to 90 % 1 TOPR Storage temperature -50 to 100 C 1 HOPR Storage humidity (without condensation) PBAR Short Circuit Output Current 3 5 to 95 % 1 105 to 69 K Pascal 1,2 Note: 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. The designer must meet the case temperature specifications for individual module components. DC Electrical Characteristics and Operating Conditions (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol Min. Typ. Max. Units Notes Supply Voltage 1.7 1.8 1.9 V 1 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 5 VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 1, 5 VREF Input Reference Voltage 0.49VDDQ 0.5 VDDQ 0.51VDDQ V 2, 3 VREF - 0.04 VREF VDDQ + 0.04 V 4 VDD VTT Parameter Termination Voltage Note: 1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ must be less than or equal to VDD. 2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 4. VTT of transmitting device must track VREF of receiving device. 5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together REV 1.1 01/2009 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) [1GB, 1Rank, 128Mx8 DDR2 SDRAMs] Symbol Parameter/Condition PC2-5300 (-3C) PC2-6400 Unit (-AD) I DD0 Operating Current: One bank Active - Precharge; tCK = tCK (MIN), tRC = tRC (MIN), tRAS = tRAS (MIN), CKE is HIGH, is HIGH between valid commands. Address and control inputs are switching; Data bus inputs are switching. 1243 1392 mA I DD1 Operating Current: One bank; active/read/precharge; BL = 4; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; tRAS = tRAS (MIN). CKE is HIGH, is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. 1144 1293 mA I DD2P Precharge Power-Down Current: Other control and address inputs are stable, Data bus inputs are floating. 332 332 mA I DD2N Precharge Standby Current: All banks idle; is HIGH; CKE is HIGH. tCK = tCK (MIN). Other control and address inputs are switching, data bus inputs are switching. 897 997 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 748 798 mA Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and I DD3PF address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 530 550 mA Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and I DD3PS address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 362 362 mA I DD3N Active Standby Current: All banks open; Continuous burst reads; BL=4; AL=0; CL=CLMIN; tRAS = tRAS (MAX); tRP = tRP (MIN); tCK = tCK (MIN); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching; I OUT = 0mA 847 946 mA I DD4R Operating Current: Burst read: All banks open; Continuous burst reads; BL = 4; AL = 0; CL = CL MIN; tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MIN); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching. 1441 1590 mA I DD4W Operating Current: Burst write: All banks open; Continuous burst writes; BL = 4; AL = 0; CL = CL MIN; tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MAX); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching. 1293 1441 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN), Refresh command every tRFC = tRFC (MIN) interval, CKE is HIGH, CS is HIGH between valid commands, other control and address inputs are switching, Data bus inputs are switching. 1837 1986 mA I DD6 Self-Refresh Current: CKE 0.2V; external clock off, CK and at 0V; Other control and address inputs are floating, Data bus inputs are floating. RESET is LOW. IDD6 current values are guaranteed up to TCASE of 85 C max 342 342 mA I DD7 All Bank Interleave Read Current: All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are stable during deselects. IOUT = 0mA 2085 2283 mA Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.1 01/2009 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) [2GB, 1Rank, 256Mx4 DDR2 SDRAMs] Symbol Parameter/Condition PC2-5300 (-3C) PC2-6400 Unit (-AD) I DD0 Operating Current: One bank Active - Precharge; tCK = tCK (MIN), tRC = tRC (MIN), tRAS = tRAS (MIN), CKE is HIGH, is HIGH between valid commands. Address and control inputs are switching; Data bus inputs are switching. 2321 2618 mA I DD1 Operating Current: One bank; active/read/precharge; BL = 4; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; tRAS = tRAS (MIN). CKE is HIGH, is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. 2123 2420 mA I DD2P Precharge Power-Down Current: Other control and address inputs are stable, Data bus inputs are floating. 499 499 mA I DD2N Precharge Standby Current: All banks idle; is HIGH; CKE is HIGH. tCK = tCK (MIN). Other control and address inputs are switching, data bus inputs are switching. 1628 1829 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 1331 1430 mA Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and I DD3PF address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 895 935 mA Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and I DD3PS address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 559 559 mA I DD3N Active Standby Current: All banks open; Continuous burst reads; BL=4; AL=0; CL=CLMIN; tRAS = tRAS (MAX); tRP = tRP (MIN); tCK = tCK (MIN); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching; I OUT = 0mA 1529 1727 mA I DD4R Operating Current: Burst read: All banks open; Continuous burst reads; BL = 4; AL = 0; CL = CL MIN; tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MIN); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching. 2717 3014 mA I DD4W Operating Current: Burst write: All banks open; Continuous burst writes; BL = 4; AL = 0; CL = CL MIN; tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MAX); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching. 2420 2717 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN), Refresh command every tRFC = tRFC (MIN) interval, CKE is HIGH, CS is HIGH between valid commands, other control and address inputs are switching, Data bus inputs are switching. 3509 3806 mA I DD6 Self-Refresh Current: CKE 0.2V; external clock off, CK and at 0V; Other control and address inputs are floating, Data bus inputs are floating. RESET is LOW. IDD6 current values are guaranteed up to TCASE of 85 C max 519 519 mA I DD7 All Bank Interleave Read Current: All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are stable during deselects. IOUT = 0mA 4004 4400 mA Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.1 01/2009 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) [2GB, 2Rank, 128Mx8 DDR2 SDRAMs] Symbol Parameter/Condition PC2-5300 (-3C) PC2-6400 Unit (-AD) I DD0 Operating Current: One bank Active - Precharge; tCK = tCK (MIN), tRC = tRC (MIN), tRAS = tRAS (MIN), CKE is HIGH, is HIGH between valid commands. Address and control inputs are switching; Data bus inputs are switching. 1925 2173 mA I DD1 Operating Current: One bank; active/read/precharge; BL = 4; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; tRAS = tRAS (MIN). CKE is HIGH, is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. 1826 2074 mA I DD2P Precharge Power-Down Current: Other control and address inputs are stable, Data bus inputs are floating. 499 499 mA I DD2N Precharge Standby Current: All banks idle; is HIGH; CKE is HIGH. tCK = tCK (MIN). Other control and address inputs are switching, data bus inputs are switching. 1628 1829 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 1331 1430 mA Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and I DD3PF address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 895 935 mA Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and I DD3PS address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 559 559 mA I DD3N Active Standby Current: All banks open; Continuous burst reads; BL=4; AL=0; CL=CLMIN; tRAS = tRAS (MAX); tRP = tRP (MIN); tCK = tCK (MIN); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching; I OUT = 0mA 1529 1727 mA I DD4R Operating Current: Burst read: All banks open; Continuous burst reads; BL = 4; AL = 0; CL = CL MIN; tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MIN); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching. 2123 2371 mA I DD4W Operating Current: Burst write: All banks open; Continuous burst writes; BL = 4; AL = 0; CL = CL MIN; tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MAX); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching. 1975 2222 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN), Refresh command every tRFC = tRFC (MIN) interval, CKE is HIGH, CS is HIGH between valid commands, other control and address inputs are switching, Data bus inputs are switching. 2519 2767 mA I DD6 Self-Refresh Current: CKE 0.2V; external clock off, CK and at 0V; Other control and address inputs are floating, Data bus inputs are floating. RESET is LOW. IDD6 current values are guaranteed up to TCASE of 85 C max 519 519 mA I DD7 All Bank Interleave Read Current: All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are stable during deselects. IOUT = 0mA 2767 3064 mA Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.1 01/2009 20 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) [4GB, 2Ranks, 256Mx4 DDR2 SDRAMs] Symbol Parameter/Condition PC2-5300 (-3C) PC2-6400 Unit (-AD) I DD0 Operating Current: One bank Active - Precharge; tCK = tCK (MIN), tRC = tRC (MIN), tRAS = tRAS (MIN), CKE is HIGH, is HIGH between valid commands. Address and control inputs are switching; Data bus inputs are switching. 3509 4004 mA I DD1 Operating Current: One bank; active/read/precharge; BL = 4; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; tRAS = tRAS (MIN). CKE is HIGH, is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. 3311 3806 mA I DD2P Precharge Power-Down Current: Other control and address inputs are stable, Data bus inputs are floating. 658 658 mA I DD2N Precharge Standby Current: All banks idle; is HIGH; CKE is HIGH. tCK = tCK (MIN). Other control and address inputs are switching, data bus inputs are switching. 2915 3317 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 2321 2519 mA Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and I DD3PF address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 1450 1529 mA Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and I DD3PS address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 777 777 mA I DD3N Active Standby Current: All banks open; Continuous burst reads; BL=4; AL=0; CL=CLMIN; tRAS = tRAS (MAX); tRP = tRP (MIN); tCK = tCK (MIN); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching; I OUT = 0mA 2717 3113 mA I DD4R Operating Current: Burst read: All banks open; Continuous burst reads; BL = 4; AL = 0; CL = CL MIN; tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MIN); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching. 3905 4400 mA I DD4W Operating Current: Burst write: All banks open; Continuous burst writes; BL = 4; AL = 0; CL = CL MIN; tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MAX); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data bus inputs are switching. 3608 4103 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN), Refresh command every tRFC = tRFC (MIN) interval, CKE is HIGH, CS is HIGH between valid commands, other control and address inputs are switching, Data bus inputs are switching. 4697 5192 mA I DD6 Self-Refresh Current: CKE 0.2V; external clock off, CK and at 0V; Other control and address inputs are floating, Data bus inputs are floating. RESET is LOW. IDD6 current values are guaranteed up to TCASE of 85 C max 697 697 mA I DD7 All Bank Interleave Read Current: All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are stable during deselects. IOUT = 0mA 5192 5786 mA Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.1 01/2009 21 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol PC2-5300 -3C Parameter PC2-6400 -AD Min. Max. Min. Max. Unit tCK Average clock period 3000 8000 2500 8000 ps tCH Average clock high-level width 0.48 0.52 0.48 0.52 tCK tCL Average clock low-level width 0.48 0.52 0.48 0.52 tCK WL Write command to DQS associated clock edge tDQSS DQS latching rising transitions to associated clock edges RL-1 RL-1 nCK -0.25 0.25 -0.25 +0.25 tCK tDSS DQS falling edge to CK setup time 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK 0.2 - 0.2 - tCK tCK tDQSL,(H) DQS input low (high) pulse width 0.35 - 0.35 - tWPRE Write preamble 0.35 - 0.35 - tCK tWPST Write postamble 0.4 0.6 0.40 0.60 tCK tIS Address and control input setup time 200 - 175 - ps tIH Address and control input hold time 275 - 250 - ps tIPW Control & Address Input pulse width for each input 0.6 - 0.6 - tCK tDS DQ and DM input setup time 100 - 50 - ps tDH DQ and DM input hold time 175 - 125 - ps DQ and DM input pulse width for each input 0.35 - 0.35 - tCK tDIPW tAC tDQSCK tHZ DQ output access time from CK/ -450 450 -400 400 ps DQS output access time from CK/ -400 400 -350 350 ps - tAC max - tACmax ps tAC max tACmin tACmax ps Data-out high-impedance time from CK/ tLZ(DQS) DQS low-impedance time from CK/ tAC min tLZ(DQ) DQ low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max tDQSQ DQS-DQ skew (DQS & associated DQ signals) tHP tQHS tQH CK half pulse width Min(tCH( abs), - - tCL(abs)) Data hold Skew Factor DQ/DQS output hold time from DQS 240 - ps 200 ps abs), - ps Min(tCH( tCL(abs)) 340 - 300 ps tHP tQHS - tHP tQHS - ps tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.40 0.60 tCK tRRD Active to Active command period 7.5 - 7.5 - ns tFAW Four Activate Window 37.5 - 35 - tCCD to command delay tWR Write recovery time 2 15 2 - 15 ns nCK - ns tDAL Auto precharge write recovery + precharge time WR+tRP - WR+tRP - nCK tWTR Internal write to read command delay 7.5 - 7.5 - ns tRTP Internal read to precharge command delay 7.5 7.5 ns tCKE CKE minimum pulse width 3 3 nCK tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command tXP REV 1.1 01/2009 tRFC+10 - tRFC+10 ns 200 - 200 nCK 2 - 2 Exit precharge power down to any command - nCK 22 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol PC2-5300 -3C Parameter tXARD Exit active power down to read command tXARDS Exit active power down to read command (slow exit, lower power) tAOND ODT turn-on delay tAON PC2-6400 -AD Min. Max. Min. Max. 2 - 2 - 7-AL 8-AL 2 2 2 2 ODT turn-on tAC (min) tAC (max) tAC (min) tAC (max) ODT turn-on (Power down mode) tAC (min) +2 +0.7 +0.7 tAC (min) +2 2.5 2.5 ODT turn-off tAC(min) tAC(max) +0.6 tAOFPD ODT turn-off (Power down mode) tAC (min)+2 tANPD ODT to power down entry latency 3 tAXPD ODT power down exit latency 8 tMRD Mode register set command cycle time 2 - tMOD MRS command to ODT update delay 0 tOIT OCD drive mode output delay 0 tAOFD tAOF tDelay tREFI ODT turn-off delay Minimum time clocks remains ON after CKE asynchronously drops Low nCK nCK 2tCK + tAC(max) +1 tAONPD Unit nCK ns 2tCK + tAC(max) +1 ns 2.5 2.5 nCK tAC(min) tAC(max) +0.6 ns 2.5tCK + tAC(max) +1 tAC (min)+2 2.5tCK + tAC(max) +1 ns - 3 - nCK 2 - nCK 12 0 12 ns 12 0 12 ns - tIS + tCK + tIH - ns 8 tIS + tCK + tIH nCK Average Periodic Refresh Interval (85C < TCASE B 95C) 3.9 3.9 As Average Periodic Refresh Interval (0C B TCASE B 85C) 7.8 7.8 As Speed Grade Definition Symbol Parameter PC2-5300 -3C PC2-6400 -AD Min Max Min Max Unit tRAS Row Active Time 45 70,000 45 70,000 ns tRC Row Cycle Time 60 - 60 - ns tRCD RAS to CAS delay 15 - 15 - ns Row Precharge Time 15 - 15 - ns tRP REV 1.1 01/2009 23 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Package Dimensions (1GB, 1Rank, 128MX8 DDR2 SDRAMs) !0" 7 6 67 6 7 6 67 7 6 7 7 , 7 7 , 7 7 7 5 7 & , ? C@ 57 7 6 67 76 7 $ 7 7 7 D 7 7 6 D 7 76 57 7 6 , 7 7 6 , 0), *+ ' )' :', + , REV 1.1 01/2009 5 7 D 76 7 D 7 7 67 7 76 D 7 7 6 D 7 + E 3+ E 7 7 ,/2 5 ,->/ 8 ,2,) '/ )(D 7 6? 7 3 @ .' ),2 8 , , 7* ?$'/2 @ 24 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Package Dimensions (2GB, 1Rank, 256MX4 DDR2 SDRAMs) REV 1.1 01/2009 7 7 57 7 6 7 7 6 & , 7 7 7 7 7 5 7 & , ? C@ 57 7 6 (2GB, 2Rank, 128MX8 DDR2 SDRAMs) 25 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Package Dimensions (4GB, 2Ranks, 256MX4 DDR2 SDRAMs) !0" 7 6 67 6 7 6 67 7 6 7 , 7 7 , 7 & , 7 7 5 7 7 ? E@ 57 7 6 67 76 7 $ 57 + E 7 6 + E & , 7 D 7 7 6 D 7 57 7 6 76 7 D 76 7 D 7 7 67 7 76 D 7 6 D 0), *+ ' )' :', + , REV 1.1 01/2009 5 , 7 7 6 , 7 7 7 7 ,/2 5 ,->/ 8 ,2,) '/ )(D 7 6? 7 3 @ .' ),2 8 , ,7 * ?$'/2 @ 26 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV NT2GT72U8PD0BV 1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 PC2-5300 / PC3-6400 Registered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 02/2008 Preliminary Release 1.0 04/2008 Official Release 1.1 01/2009 Add NT2GT72U8PD0BV-3C/AD REV 1.1 01/2009 Modification 27 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.