Product Flyer
December 96
MB86687A Version 2.05
Adaptation Layer Controller (ALC) FML/NPD/ALC/FL/1205
Copyright © 1996 Fujitsu Microelectronics Limited Page 1 of 6
The Fujitsu MB86687A is an ATM protocol controller which
autonomously terminates ATM Adaptation Layer standards
Type 3/4 and Type 5. Simultaneous segmentation and
reassembly can be achieved at up to 155Mbps.
Communication with the host system is through a high speed
bus interface.
VBR and CBR ATM traffic classes are implemented in this
device. Traffic management to ATM Forum TM 3.1 is
supported on up to 1024 virtual circuits (VCs) without local
SRAM. Flexible bus configuration allows optimised system
design.
The device is ideally suited to many customer premises
equipment applications including ATM s witches , access units
and adaptor cards and multi-protocol hubs, bridges and
routers.
FEATURES
• Supports Broadband ISDN Adaptation Layer standards Type 3/4 and Type 5
• Supports simultaneous segmentation and reassembly on up to 1024 VCs with on-chip cache
• Supports up to 12 peak segmentation rates with leaky bucket averaging on a per VC basis with
optional bucket fill before segmentation continue.
• Programmable peak and average rates and leaky bucket averaging on total ALC cell stream output.
• Support for scatter / gather mode
• Transparent ATM cell and cell payload modes including support for OAM and Resource Management
cells
• UTOPIA Level 1 v2.01 functionally compatible cell stream interface with optional HEC checking on
receive
• Flexible routing tag append/remove mode for direct ATM Switch connection
• Supports buffer chaining, streaming and ageing time-out
• Separate 32 bit data and 16 bit control ports with optimized DMA interface
• JTAG pins compliant to IEEE1149.1 are provided
• Fabricated in 0.8 micron CMOS technology with CMOS/TTL compatible I/O and single +5V power
supply
PLASTIC PACKAGE
SQFP-208
December 96 Version 2.05
FML/NPD/ALC/FL/1205
MB86687A Adaptation Layer Controller (ALC)
Copyright © 1996 Fujitsu Microelectronics Limited Page 2 of 6
General The ALC simultaneously supports autonomous segmentation and reassembly
of user data packets on up to 1024 virtual circuits (VCs). User data packets are
transferred to and from shared data structure memory using a high speed
intelligent DMA controller with a 32 bit data bus. Shared data structures are
stored in SAR (Segmentation and Reassembly) memory which can be either
dual port memory or a partition of system memory.
Adaptation Support The ALC autonomously terminates the protocols involved in segmenting and
reassembling data streams conforming to Adaptation Layer Types 3/4 and 5.
AAL 3/4 and AAL 5 traffic can be handled simultaneously. Streaming and
Message Modes as defined for AAL 3/4 and AAL5 are supported.
Transmit
Buffer
(3 Cells)
Segmentation &
Convergence
Sub-layer
ATM
Cell
Transmitter
ATM
Cell
Receiver
Reassembly and
Convergence
Sub-layer
Receive
Buffer
(2 Cells)
Fig. 1 - ALC Block Diagram
SAR
Memory
Interface
High
Speed
DMA
Traffic Management
Controller
ALC Internal Registers Cell
Stream Interface
Processor Interface
VCI Status/
Descriptor
Table
Cell
Stream
Interface
JTAG Interface
JTAG
December 96 Version 2.05
FML/NPD/ALC/FL/1205
MB86687A Adaptation Layer Controller (ALC)
Copyright © 1996 Fujitsu Microelectronics Limited Page 3 of 6
Traffic Shaping The Traffic Manager initiates periodic packet segmentation from one of 12 Peak
Rate Queues at programmable intervals. The queues are grouped into three
priority classes: high, medium and low, with 4 queues in each priority class. It
also manages total ALC peak transmission rate. If the total peak transmission
rate exceeds a specified threshold, the traffic management controller will service
the queues according to their priority until the total peak rate falls below the
threshold. This mechanism ensures that the ALC will not e xceed the negotiated
quality of service for the overall link connection. The average rate shaping of
transmit traffic on a per virtual circuit basis uses the leaky bucket algorithm. The
leaky bucket algorithm also controls the total ALC transmission.
Cell Stream The Cell Stream Interface transmits and receives an asynchronous stream of
ATM cells in 8-bit parallel form with separate synchronisation signals used to
identify the start of a cell. The ALC Cell Stream Interface operates in one of two
environments; either in a Switch Device or a Termination Device.
DMA Interface The ALC has a 32-bit data and a 24-bit address DMA interface that may be
programmed for either big or little endian formats. It supports standard and
extended Intel/Motorola bus cycles. Intel and Motorola bus negotiations are also
supported.
Microprocessor A 16-bit control/status port is used to configure the device. This includes the
setting up of receive circuits. The maintenance of the queue structures and
monitoring of cell and packet loss are also achieved using this interface. An
interrupt mechanism is implemented to indicate queue updates and exception
conditions.
Transmit Operation Transmit operation is implemented using a simple queue structure. A buffer
containing part or all of a packet’s data is scheduled by placing a Transmit
Descriptor identifier on a Pending Queue. The ALC links queued descriptors for
the same VC into a list. Data is then assembled under the control of the traffic
scheduler into packets. A data pointer is contained in the transmit descriptor as
is a pointer to a table containing circuit traffic parameters. When a buffer is
exhausted, it is returned to the host by putting the transmit descriptor identifier
on a Release Queue.
Receive Operation Receive operation is implemented using a simple queue structure. At the start
of reassembly for each new packet the ALC finds a new Receive Descriptor
(RD) by reading a Buffer Free Queue. Each RD contains a pointer to a receive
buffer. The RD also contains fields to support receive buffer chaining and the
received VCI or MID fields as well as receive buffer ageing timeout. After
reception is complete, the ALC passes the receive descriptor to the host using
a Buffer Ready Queue. Each entry in the queue contains a pointer to the
appropriate RD and the status of the associated buffer.
JTAG The ALC provides boundary scan test circuitry fully compliant with IEEE 1149.1.
The ALC’s JTAG circuitry permits easier board level testing to be carried out by
allowing the signal pins on the device to forma serial scan chain around the
device. JTAG test modes are controlled by accessing an internal test access
December 96 Version 2.05
FML/NPD/ALC/FL/1205
MB86687A Adaptation Layer Controller (ALC)
Copyright © 1996 Fujitsu Microelectronics Limited Page 4 of 6
Host
CPU
Host
CPU
SAR
Memory
(Data and
Control)
System
Memory
(Data and
Control)
PHY
or
Switch
Host
CPU
System
Memory
(Data)
SAR
Memory
(Control)
System
Memory
Dual Port Memory -SAR data and control parameters stored in shared
dual port memory
Shared Memory - SAR data and control parameters stored in
system memory
Hybrid - SAR data stored in system memory and SAR control
parameters stored in shared pual port memory
ALC PHY
or
Switch
PHY
or
Switch
ALC
ALC
Fig. 2- ALC Possible Configurations
December 96 Version 2.05
FML/NPD/ALC/FL/1205
MB86687A Adaptation Layer Controller (ALC)
Copyright © 1996 Fujitsu Microelectronics Limited Page 5 of 6
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to
this high impedance circuit.
SRD0-SRD31
SRA2-SRA23
MB86687A
D0-D15
TXD0-TXD7
TXSOC
TXCLK
RXD0-RXD7
RXSOC
RXCLK
DCCK
TIN
TOUT
IRQ RD WR
BGACK
DTACK / READ Y /BERR
HOLD / BR
HLD A / BG
MRD / AS / ADS / TS
MWR / R/W / R/W
DS / BLAST / TIP
Fig. 3 - MB86687A I/O Block Diagram
CSA1-A6
SAR
Memory
Interface
Cell
Stream
Interface
Microprocessor
TDI TCKTDO TMS
JTAG Test Port
TOCS
TDCS
ROCS
RDCS
SADRV
BE0 / A0
BE1 / A1
BE2 / SIZ0
BE3 / SIZ1
PRTY0-PRTY3
TXEN
TXFULL
TXDRV
RXEN
RXEMPTY
RESET
ALC
December 96 Version 2.05
FML/NPD/ALC/FL/1205
MB86687A Adaptation Layer Controller (ALC)
Copyright © 1996 Fujitsu Microelectronics Limited Page 6 of 6
FML/NPD/ALC/FL/1205 - 2.05
This document is proprietary to Fujitsu. No part of this document may be copied or reproduced in any form or by any
means, or disclosed or transferred to any third party without written prior consent of Fujitsu.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu
assumes no responsibility for inaccuracies.
The information contained in this document does not convey any title or licence under the copyright, patent rights or trade
marks claimed and owned by Fujitsu or its licensors.
Fujitsu reserves the right to change specifications without notice.
Worldwide Headquarters
Japan Fujitsu Limited Asia Fujitsu Microelectronics Asia
PTE Limited
Tel:
Fax: +81 44 754 3753
+81 44 754 3332
1015 Kamiodanaka
Nakaharaku
Kawasaki 211
Japan
Tel:
Fax: +65 336 1600
+65 336 1609
No. 51 Bras Basah Road
Plaza by the Park
#06-04/07
Singapore 0718
http://www.fujitsu.co.jp/ http://www.fsl.com.sg/
USA Europe
Tel:
Fax: +1 408 922 9000
+1 408 922 9179
Fujitsu Microelectronics Inc
3545 North First Street
San Jose CA 95134-1804
USA
Tel:
Fax: +49 6103 6900
+49 6103 690122
Fujitsu Mikroelektronik GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel:
Fax: +1 800 866 8608
+1 408 922 9179
Customer Response Center
Mon-Fri: 7am-5pm (PST)
http://www.fujitsu-ede.com/
http://www.fujitsumicro.com/
