UBA2033TS/N2,118 - NXP Semiconductors

DATA SH EET

Product specification 2002 Oct 08

INTEGRATED CIRCUITS

UBA2033

HF full bridge driver IC

2002 Oct 08 2

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

FEATURES

•Full bridge driver circuit

•Integrated bootstrap diodes

•Integrated high voltage level shift function

•High voltage input fo r the internal supply voltage

•550 V maximum voltage

•Bridge disable function

•Input for start-up delay

•Adjustable oscillator frequency

•Predefined bridge p osition during start- up.

APPLICATIONS

•The UBA2033 can drive (via the MOSFETs) any kind of

load in a full bridge configuration

•The circuit is especia lly de sig ned as a commutator for

High Intensity Dischar ge (HID) lamps.

GENERAL DESCRIPTION

The UBA2033 is a high voltage monolithic integrated

circuit made in the EZ-HV SOI process. The circuit is

designed for driving th e MOSFETs in a full bridge

configuratio n. In addition, i t features a disable functi on, an

internal adjustable oscillator and an external drive function

with a low-voltage level shifter for drivin g the bridge.

To guarantee an accurate 50% duty factor, the oscillator

signal can be passed through a divider before being fed to

the output driver.

ORDERING INFORMATION

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

UBA2033TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

2002 Oct 08 3

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

BLOCK DIAGRAM

handbook, full pagewidth

MBL457

LOW VOLTAGE

LEVEL SHIFTER

OSCILLATOR

STABILIZER

UVLO

SGND

VDD

HIGH VOLTAGE

LEVEL SHIFTER

HIGHER LEFT

DRIVER

LOWER RIGHT

DRIVER

LOWER LEFT

DRIVER

HIGHER RIGHT

DRIVER

LOGIC SIGNAL

GENERATOR

LOGIC

1.29 V

213

EXTDR +LVS−LVS

4, 5, 7, 8, 18,

19, 22, 24, 25

n.c.

20 GLL

PGND

23 GLR

26 SHR

28 GHR

15 GHL

27 FSR

17 SHL

16 FSL

UBA2033TS

bridge disable

Fig.1 Block diagram.

2002 Oct 08 4

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

PINNING

SYMBOL PIN DESCRIPTION

−LVS 1 negative supply voltage (for logic

input)

EXTDR 2 oscillator signal input

+LVS 3 positive supply voltage (for logic

input)

n.c. 4 not connec te d

n.c. 5 not connec te d

HV 6 high voltage supply input

n.c. 7 not connec te d

n.c. 8 not connec te d

VDD 9 internal low voltage supply

SU 10 input signal for start-up delay

DD 11 divi der disable input

BD 12 bridge disable contro l inpu t

RC 13 RC input for internal oscillator

SGND 14 signal grou nd

GHL 15 gate of higher left output MOSFET

FSL 16 floating supply voltage left

SHL 17 source of higher left MOSFET

n.c. 18 not connected

n.c. 19 not connected

GLL 20 gate of lower left output MOSFET

PGND 21 powe r ground

n.c. 22 not connected

GLR 23 gate of lower right output MOSFET

n.c. 24 not connected

n.c. 25 not connected

SHR 26 source of higher right MOSFET

FSR 27 floating supply voltage right

GHR 28 gate of higher right ou tput MOSFET

handbook, halfpage

UBA2033TS

MBL458

EXTDR

n.c.

VDD

SGND

GHR

FSR

SHR

n.c.

GLR

n.c.

PGND

GLL

n.c.

SHL

FSL

GHL

+LVS

−LVS

Fig.2 Pin configuration.

2002 Oct 08 5

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

FUNCTIONAL DESCRIPTION

Supply voltage

The UBA2033 is powered by a supply voltage applied to

pin HV, for instance the supply voltage of the full bridge.

The IC generates its own low supply voltage for the

internal circuitry. Therefore an additional low voltage

supply is not required. A capacitor has to be connected to

pin VDD to obtain a ripple-free inte rn al su pply voltage.

The circuit can also b e powered by a low voltage supply

directly applied to pin VDD. In this case pin HV should be

connected to pin VDD or SGND.

Start-up

With an increasing supply voltage the IC enters the

start-up state; the higher power transistors are kept off and

the lower power transistors are switched on. During the

start-up state the bootstrap capacitors are charged and the

bridge output current is zero. The start-up state is defined

until VDD =V

DD(UVLO), where UVLO stands for Under

Voltage Lock-out. The stat e of the outputs during the

start-up phase is overruled by the bridge disable function.

Release of the power drive

At the moment the supply voltage on pin VDD or HV

exceeds the le vel of release power dr ive, the output

voltage of the bridge depends on the control signal on

pin EXTDR (see Table 1). The bridge position after

start-up, disable, or delayed start-up (via pin SU) depends

on the status of the pins DD and EXTDR. If pin DD = LOW

(divider enabled) the bridge will start in the pre-defined

position: pin GLR and pin GHL = HIGH and pin GLL and

pin GHR = LOW. If pin DD = HIGH (divider disabled) the

bridge position will depend on the status of pin EXTDR.

If the supply voltage on pin VDD or HV decreases and

drops below the reset level of power drive the IC enters the

start-up state again.

Oscillation

At the point where the supply voltage on pin HV crosses

the level of release pow er drive, the bridge begins

commutating between the follo wing two defined states:

•Higher left and lower right MOSFETs on,

higher right and lower left MOSFETs o ff

•Higher left and lower right MOSFETs off,

higher right and lower left MOSFETs o n.

The oscillation can take place in three different modes:

•Internal oscillator mode.

In this mode the bridge commutating frequency is

determined by the value s of an external resistor (Rosc)

and capacitor (C osc). In this mode pin EXTDR must be

connected to pin +L VS. To realize an accurate 50% duty

factor, the internal divider s hould be used. The internal

divider is enabled by co nnecting pin DD to SGND. Due

to the presence of the divider the bridge frequency

is half the oscillator frequency. The commutation of the

bridge will take place at the falling edge of the signal on

pin RC. To minimize the cur ren t consumption

pins +LVS, −LVS and EXTDR can be connected

together to either pin SGND or VDD. In this way the

current source in the logic voltage supply circuit is shut

off.

•External oscillator mode without the internal divider.

In the external oscilla tor mode the extern al sou rce is

connected to pin EXTDR and pin RC is short-circuited to

pin SGND to disable the internal oscillator. If the internal

divider is disabled (pin DD = VDD) the duty factor of the

bridge output signal is determined by the external

oscillator signal and the bridge frequency equals the

external oscillator frequency.

•External oscillator mode with the internal divider.

The external oscillator mode can also be used with the

internal divider function ena bled (pin RC and

pin DD = SGND). Due to the presence of the divider the

bridge frequency is half the external oscillator

frequency. The commutation of the bridge is triggered by

the falling edge of the EXTDR signal with respect to

V−LVS.

The design eq uation for the bridge oscill ator fr equency i s:

Non-overlap time

The non-over lap time is the time between turning off the

conducting pair of MOSFETs and turning on the next pair.

The non-overlap time is internally fixed to a very small

value, which allows an HID system to operate with a very

small phase difference between load current and full

bridge voltage (pin s SHL an d SHR). Especially when

igniting an HID lamp via a LC resonance circuit, a small

‘dead time’ is essential. The high maximum oper ating

frequency, together with a small ‘dead time’, also gives the

opportunity to ig ni te the HID lamp at the third harmonic of

the full bridge voltage, thereby reducing costs in the

magnetic power compo ne nts .

fbridge 1

kosc Rosc

×Cosc

×()

--------------------------------------------------

2002 Oct 08 6

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

’Dead time’ can be increased by adding a resistor (for

slowly turning on the full bridge power FETs) and a diode

(for quickly turning off the full br idge power FETs) in

parallel, both in s eries with the gate driver s (see Fig.3).

Divider function

If pin DD = SGND, then the div i der function is

enabled/present. If the divider function is pres ent there is

no direct relation between the position of the bridge output

and the status of pin EXTDR.

Start-up delay

Normally, the circuit starts oscillating as soon as pin VDD or

HV reaches the level of relea se power drive. At this

moment the gate drive voltage is equal to the voltage on

pin VDD for the low side transistors and VDD −0.6 V for the

high side transistors. If this voltage is too low for sufficient

drive of the MOSFETs the release of the power drive can

be delayed via pin SU.

A simple RC filter (R between pins VDD and SU;

C between pins SU and SGND) ca n be used to make a

delay, or a control s ig nal from a processor can be used.

Bridge disable

The bridge disable function can be used to switch off all the

MOSFETs as soon as the voltage on pin BD exceeds the

bridge disable voltage (1.2 9 V). The bridg e dis ab l e

function overrules all the ot her states.

Table 1 Logic table; note 1

Note

1. X = don’t care

a) BD, SU and DD logi c lev els are with respect to SGND

b) EXTDR logic levels are with respect to V−LVS

c) GHL logic levels are with respect to SHL

d) GHR logic levels are with respect to SHR

e) GLL and GLR logic levels are with respect to PG ND

f) If pin DD = LOW the bridge enters the state (oscillation state and pin BD = LOW and pin SU = HIGH) in the

pre-defined pos i tion pin GHL and pin GLR = HIGH and pin GLL and pin GHR = LOW.

DEVICE

STATUS INPUTS OUTPUTS

BD SU DD EXTDR GHL GHR GLL GLR

Start-up state HIGH X X X LOW LOW LOW LOW

LOW X X X LOW LOW HIGH HIGH

Oscillation state HIGH X X X LOW LOW LOW LOW

LOW LOW X X LOW LOW HIGH HIGH

LOW HIGH HIGH HIGH LOW HIGH HIGH LOW

LOW HIGH LOW LOW HIGH

LOW HIGH LOW LOW HIGH LOW LOW HIGH

LOW-to-HIGH

HIGH

HIGH-to-LOW LOW HIGH HIGH LOW

2002 Oct 08 7

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are measured with respe ct to

SGND; positive currents flow into th e IC.

Note

1. In accordance with the Human Body Model (HBM): equivalent to discharging a 100 pF capacitor through a 1.5 kΩ

series resisto r.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage (low voltage) DC v alue 0 14 V

transient at t < 0.1 μs017V

VHV supply voltage (high voltage) 0 550 V

VFSL floating supply voltage left VSHL =V

SHR = 550 V 0 564 V

VSHL =V

SHR =0V 0 14 V

VFSR floating supply voltage right VSHL =V

SHR = 550 V 0 564 V

VSHL =V

SHR =0V 0 14 V

VSHL source voltage for higher left

MOSFETs with respect to PGND and SGND −3+550V

with respect to SGND; t < 1 μs−14 −V

VSHR source voltage for higher right

MOSFETs with respect to PGND and SGND −3+550V

with respect to SGND; t < 1 μs−14 −V

VPGND power ground voltage with respect to SGND 0 5 V

V−LVS negative supply voltage for logic

input −0.9 +17 V

I−LVS negative supply current for logic input pin EXTDR = HIGH −1−mA

V+LVS positive supply voltage for logic input VHV =0V; DCvalue 0 14 V

transient at t < 0.1 μs017V

Vi(EXTDR) input voltage from external oscillator

on pin EXTDR with respect to V−LVS 0V

+LVS V

Vi(RC) input voltage on pin RC DC v alue 0 VDD V

transient at t < 0.1 μs017V

Vi(SU) input voltage on pin SU DC v alue 0 VDD V

transient at t < 0.1 μs017V

Vi(BD) input voltage on pin BD DC v alue 0 VDD V

transient at t < 0.1 μs017V

Vi(DD) input voltage on pin DD DC v alue 0 VDD V

transient at t < 0.1 μs017V

SR slew rate at output pins repetitive 0 4 V/ns

Tjjunction temperature −40 +150 °C

Tamb ambient temperature −40 +150 °C

Tstg storage temperature −55 +150 °C

Vesd electrostatic dischar ge voltage on

pins HV, +LVS, −LVS, EXTDR, FSL,

GHL, SHL, SHR, GHR and FSR

note 1 −900 V

2002 Oct 08 8

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

THERMAL CHARACTE RISTICS

QUALITY SPECIFICATION

In accordance with “SNW-FQ-611D”.

CHARACTERISTICS

Tj=25°C; all voltages are measured with respect to SGND; positive currents flow into the IC; unless otherwise

specified.

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 100 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

High voltage

IHV high voltage supply current t < 0.5 s and VHV =550V 0 −30 μA

IFSL, IFSR high voltage floating supply

current t < 0.5 s a nd VFSL =V

FSR =564V 0 −30 μA

Start-up; powered via pin HV

Ii(HV) HV input current VHV =11V; note1 −0.5 1.0 mA

VHV(rel) level of release power drive

voltage 11 12.5 14 V

VHV(UVLO) reset level of power drive voltage 8.5 10 11.5 V

VHV(hys) HV hysteresis voltage 2.0 2.5 3.0 V

VDD internal supply voltage VHV = 20 V 10.5 11.5 13.5 V

Start-up; powered via pin VDD

Ii(DD) VDD input current VDD = 8.25 V; note 2 −0.5 1.0 mA

VDD(rel) level of release power drive

voltage 8.25 9.0 9.75 V

VDD(UVLO) reset level of power drive voltage 5.75 6.5 7.25 V

VDD(hys) hysteresis voltage 2.0 2.5 3.0 V

Output stage

Ron(H) higher MOSFETs on resistance VFSR =V

FSL = 12 V (with respect

to SHR and SHL); Isource =50mA 15 21 26 Ω

Roff(H) higher MOSFETs off resistance VFSR =V

FSL = 12 V (with respect

to SHR and SHL); Isink =50mA 91418Ω

Ron(L) lower MOSFETs on resistance VDD =12V; I

source =50mA 15 21 26 Ω

Roff(L) lower MOSFETs off resist ance VDD =12V; I

sink = 50 mA 9 14 18 Ω

Io(source) output source current VDD =V

FSL =V

FSR =12V;

VGHR =V

GHL =V

GLR =V

GLL =0V 130 180 −mA

Io(sink) output sink current VDD =V

FSL =V

FSR =12V;

VGHR =V

GHL =V

GLR =V

GLL =12V 150 200 −mA

Vdiode bootstrap diode voltage drop Idiode = 20 mA 1.7 2.1 2.5 V

tno non-overlap time −−250 ns

VFSL HS lockout voltage left 3.0 4.0 5.0 V

2002 Oct 08 9

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

Notes

1. The current is specified without commutation of the bridge. The current into pin HV is limited by a thermal protection

circuit. The current is limited to 11 mA at Tj=150°C.

2. The current is specified wi th ou t commutation of the bridge an d pin HV is connecte d to V DD.

3. The minimum frequency is mainly determined by the value of the bootstrap capacitors.

VFSR HS lockou t voltage right 3.0 4.0 5.0 V

IFSL FS su pply current left VFSL =12V 246μA

IFSR FS su pply current right VFSR =12V 246μA

DD input

VIH HIGH-level input voltage VDD =12V 6 −−V

VIL LOW-level input voltage −−3V

Ii(DD) input current into pin DD −−1μA

SU input

VIH HIGH-level input voltage VDD =12V 4 −−V

VIL LOW-level input voltage −−2V

Ii(SU) input current into pin SU −−1μA

External drive input

VIH HIGH-level input voltage with respect to V−LVS 4.0 −−V

VIL LOW-level input voltage with respect to V−LVS −−1.0 V

Ii(EXTDR) input current into pin EXTDR −−1μA

fbridge bridge frequency note 3 −−250 kHz

Low voltage logic supply

I+LVS low voltage supply current V+LVS =V

EXTDR =5.75to14V with

respect to V−LVS

−250 500 μA

V+LVS low voltage supply voltage with respect to V−LVS 5.75 −14 V

Bridge disable input

Vref(dis) disable reference voltage 1.23 1.29 1.35 V

Ii(BD) disable input curre nt −−1μA

Internal oscillator

fbridge bridge oscillating frequency note 3 −−100 kHz

Δfosc(T) oscillator frequency variation

with temperature fbridge = 250 Hz and

Tamb =−40 to +150 °C−10 0 +10 %

Δfosc(VDD) oscillator frequency variation

with VDD

fbridge = 250 Hz and

VDD =7.25to14V −10 0 +10 %

kHhigh level trip point VRC(high) =k

H×VDD 0.38 0.4 0.42

kLlow level trip point VRC(low) =k

L×VDD −0.01 −

kosc oscillator constant fbridge = 250 Hz 0.94 1.02 1.10

Rext external resistor to VDD 100 −−kΩ

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2002 Oct 08 10

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

APPLICATION INFORMATION

Basic application

A basic full bridge configuration with an HID lamp is shown

in Fig.3. The bridge disable, the start-up delay and the

external drive functio ns are not used in this application.

The pins −LVS, +LVS, EXTDR and BD are short-circuited

to SGND. The internal oscillator is used and to realize a

50% duty cycle the internal divider function has to be used

by connecting pin DD to SGND. The IC is powered by the

high voltage supply. Because the internal oscillator is

used, the brid ge commutating freque ncy is determi ned by

the values of Rosc and Cosc. The bridge starts oscillating

when the HV supply voltage exceeds the level of release

power drive (typically 12.5 V on pin HV). If the supply

voltage on pin HV drops below the reset level of power

drive (typically 10 V on pin HV), the UBA2033 enters the

start-up state.

handbook, full pagewidth

UBA2033TS

VDD

EXTDR

SGND

GHR

FSR

SHR

GLR R>100 Ω

R>100 Ω

GLL

SHL

FSL

GHL

PGND

IGNITOR

Rosc

Cosc

high voltage

550 V (max)

GND

MBL459

+LVS

−LVS

Fig.3 Basic configuratio n.

2002 Oct 08 11

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

Application with external control

Figure 4 shows an application con taining a system

ground-refe renced control circui t. Pin +LVS can be

connected to the same supply as the extern al oscillator

control unit and pin −L VS is connected to SGND. Pin RC is

short-circuited to SGND. The bridge co mmutation

frequency is determined by the external oscillator. The

bridge disable input (pin BD) can be used to immediately

turn off all four MOSFETs in the full bridge.

handbook, full pagewidth

UBA2033TS

VDD

EXTDR

SGND

GHR

FSR

SHR

GLR R>100 Ω

R>100 Ω

GLL

SHL

FSL

GHL

PGND

IGNITOR

high voltage

550 V (max)

GND MBL460

EXTERNAL

OSCILLATOR

CONTROL

CIRCUIT

low voltage

+LVS

−LVS

Fig.4 External control configu ra tio n.

2002 Oct 08 12

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

Additional application information

GATE RESISTORS

At ignition of an HID lamp, a large EMC spark occurs. This

can result in a large voltage transient or oscillation at the

gates of the full bridge MOSFETs (LL, LR, HR and HL).

When these gates are directly coupled to the gate drivers

(pins GHR, GLR, GHL and GLL), voltage overstress of the

driver outputs may oc cur. Therefore it is advised to add a

resistor with a minimum value of 100 Ω in series with each

gate driver to isolate the gate driver outputs from the actual

power MOSFETs gate.

’Dead time’ can also be adjusted via the combination gate

resistor and g ate-source capacitance.

GATE CHARGE AND SUPPLY CURRENT AT HIGH FREQUENCY

USE

The total gate curre nt needed to charge the gate s of the

power MOSFETs equals:

Where:

Igate = gate curr ent

fbridge =bridge frequency

Qgate = gate charge.

This current is supplied via the internal low voltage supply

(VDD). Since this current is limited to 11 mA (see

“Characteristics” table note 1), at higher frequencies and

with MOSFETs having a relative hig h ga te charge, this

maximum VDD supply current may not be sufficient

anymore. As a result the internal low voltage supply (VDD)

and the gate drive voltage will drop resulting in an increase

of the higher resistance (Ron) of the full bridge MOSFETs.

In this case an auxiliary low voltage supply is necessary.

Igate 4f

bridge Qgate

××=

2002 Oct 08 13

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.38

0.25 0.20

0.09 10.4

10.0 5.4

5.2 0.65 1.25

7.9

7.6 0.9

0.7 1.1

0.7 8

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

1.03

0.63

SOT341-1 MO-150 99-12-27

03-02-19

detail X

vMA

(A )

114

28 15

0.25

pin 1 index

0 2.5 5 mm

scale

SOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341

-1

max.

2002 Oct 08 14

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.

A more in-depth acco un t of sold er ing ICs can be found in

our “Data Handbook IC26; Integrate d Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method tha t is idea l for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

Reflow soldering

Reflow soldering requires solder pas te (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-s yringe dispensin g before package place ment.

Several methods exist for reflowing; for example,

convection or convection/infrared h eating in a conveyor

type oven. Through put times (preheating, soldering and

cooling) vary between 100 a nd 200 seconds depending

on heating method.

Typical reflow peak temperatur es range from

215to250°C. The top-surface temperature of the

packages sh ould preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

Wave soldering

Conventional single wave soldering is not re commended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wa ve soldering meth od comprising a

turbulent wave with high up ward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axi s is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footp rint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board .

The footprint must incorporate solder thieves at the

downstream end.

•For packages with leads on four sides, the footprint must

be plac ed at a 45° angle to the transp ort direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the s id e c orners.

During placement and before soldering, the package must

be fixed with a droplet of adh esive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 secon ds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one ope ration within 2 to 5 seconds be tween

270 and 320 °C.

2002 Oct 08 15

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with res pect to time) and body size of the package, there is a risk that inter nal or external packag e

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circu it Packages; Section: Packing Methods” .

2. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot pene trat e bet ween the p rinte d-cir cui t boar d and the h eats ink . On ve rsio ns with the h eats ink on th e top sid e,

the solder might be deposited on the heatsin k s urface.

3. If wave soldering is con sid ered, then the package must be p lace d a t a 4 5° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller tha n 0.5 mm.

PACKAGE SOLDERING METHOD

WAVE REFLOW(1)

BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable

2002 Oct 08 16

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

DATA SHEET STATUS

Notes

1. Please consult the most recently issued docu ment before initiating or completing a design.

2. The prod uct status of device(s) described in this document may have changed since this document was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DOCUMENT

STATUS(1) PRODUCT

STATUS(2) DEFINITION

Objective data sheet Development This document contains data from the objective specification for product

development.

Preliminary data sheet Qualification This document contains data from the preliminary specification.

Product data sheet Production This document contains the product specification.

DISCLAIMERS

Limited warranty and liability ⎯ Information in this

document is believed to be accurate and reliab le.

However, NXP Semiconduc tors does not give any

representations or warranties, expressed or implied, as to

the accuracy or completeness of such information and

shall have no liability for the consequences of use of such

information.

In no event shall NXP Semiconductors be liable for any

indirect, incidental, punitive, special or conseq uential

damages (including - without limitation - lost profits, lost

savings, busin es s interru ption, costs related to the

removal or replacement of any products or rework

charges) whether or not such damages are based on tort

(including negligence), warranty, breach of contract or any

other legal theory.

Notwithstanding any damages that customer might incur

for any reason whatsoever, NXP Semiconductors’

aggregate and cu mulative liability towards customer for

the products described herein shall be limited in

accordance with the Terms and conditions of commercial

sale of NXP Semiconductors.

Right to make changes ⎯ NXP Semiconductors

reserves the right to make changes to information

published in this doc ument, including without limitation

specifications and product descriptions, at any time and

without notice. This document supersedes and replaces all

information supplied prior to the publication hereof.

Suitability for use ⎯ NXP Semiconduct ors pr oduc ts are

not designed, au thorized or warranted to be suitable for

use in life support, life-critical or safety-critical systems or

equipment, nor in applications where failure or malfunction

of an NXP Semiconductors product can reason ably be

expected to result in pe rs onal injury, death or severe

property or environmental damage. NXP Semiconductors

accepts no liability for inclusion and/or use of NXP

Semiconductor s pr oducts in such equipment or

application s and therefore such inclusion and /or use is at

the customer’s own risk.

Applications ⎯ Applications that are described herein for

any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or

warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of

their applications and products using NXP

Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or

customer product design. It is customer’s sole

responsibility to determine whether the NXP

Semiconductors pro du ct is su itable and fit for the

customer’s applications and products planned, as well as

for the planned a pplication and use of customer’s third

party customer(s). Customers should provide appropriate

design and opera t ing saf eg ua rd s to minimize the risks

associated with their applications and pr oducts.

NXP Semiconduc tors does n ot a ccept any liabil ity rela ted

to any default, damage, costs or problem which is based

on any weakne ss or default in t he customer’s applic ations

or products, or the application or use by customer’s third

party customer( s) . C us to m er is responsible for doing all

necessary testing for the customer’s applications and

products using NXP Semiconductors products in order to

avoid a default of the applic ations and the products or of

the application or use by customer’s third p arty

customer(s). NXP does not accept any liability in this

respect.

2002 Oct 08 17

NXP Semiconductors Product specification

HF full bridge driver IC UBA2033

Limiting values ⎯ Stress above one or more limiting

values (as defined in the Absolute Maximum Ratings

System of IEC 60134) will cause permanent damage to

the device. Limiting values are stress ratings only and

(proper) operation of the device at these or any other

conditions abo ve those given in the Recommended

operating conditions section (if present) or the

Characteristics sections of this document is not warranted.

Constant or repeated exposure to limiting values will

permanently and irreversibly affect the qua l ity and

reliability of the device.

Terms and conditions of commercial sale ⎯ NXP

Semiconductors products are sold subje ct to the general

terms and conditio ns of commercial sale, as published at

http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written ind i vidual agreemen t. I n cas e an

individual agreeme nt is co nc luded only the terms and

conditions of the resp ective agreement shall apply. NXP

Semiconductors hereby expressly objects to apply ing the

customer’s general terms and conditions with regard to the

purchase of NXP Semicon ductors produc ts by customer.

No offer to sell or license ⎯ Nothing in this document

may be interpreted or construed as an offer to sell products

that is open for acceptance or the grant, conveyance or

implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control ⎯ This document as well as the item(s)

described he re in may be subject to export con t ro l

regulations. Export might require a prior authorization from

national auth or itie s.

Quick refer ence data ⎯ The Quick reference data is an

extract of th e product data given in the Limiting values and

Characteristics sections of this document, an d as such is

not complete, exhaus tive or legally binding.

Non-automotive qualified products ⎯ Unless this data

sheet expressly states that this specific NXP

Semiconductors product is au tomotive qualified, the

product is not suitable for automotive use. It is neither

qualified nor te sted in accordanc e with automot ive testing

or application requirements. NXP Semiconductors accepts

no liability for inclusion and/or use of non-automotive

qualified prod ucts in automotive equipment or

applications.

In the event that customer uses the product for design-in

and use in automotive applications to automotive

specifications and standards, customer (a) shall use the

product without NXP Semiconductors’ warranty of the

product for such au t omo tive application s, us e and

specifications, and (b) whenever customer uses the

product for automotive applications be yond NXP

Semiconductors’ specifications such use sha ll be solely at

customer’s own ris k, and (c) customer fully inde m nif i es

NXP Semiconductors for any liability, damages or failed

product clai ms r esult ing fr om custo mer desi gn an d us e o f

the product for automotive ap plic ations beyond NXP

Semiconductors ’ st andard warranty and NXP

Semiconductors’ product specifications.

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product

solutions that leverage its leading RF, Analog, Power Management,

Interface, Security and Digital Processing expertise

Contact information

For additional information p lease visit: http://www.nxp.com

For sales offices addresses send e- mail to: salesaddresses@nxp.com

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information pr e sent ed in this documen t d oes not form part of an y quotation or cont ra ct, is believed to be accur ate a nd re li a ble and may be change d

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other indus trial or intellectual property rights.

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal

definitions and disclaimer s. No changes were made to the tech nical content, except for package outline

drawings which were updated to the latest version.

Printed in The Netherlands 613502/01/pp18 Date of release: 2002 Oct 08 Document order number: 9397 750 09574