1
MX23L12854
128M-BIT Low Voltage, Serial
MASK ROM
with 50MHz SPI Bus Interface
KEY FEATURES
• Operating voltage ranges from 3.0V to 3.6V
• Serial Peripferal Interface compatible-mode 0 and 3
• High performance : "fast read" mode at 50MHz and "normal read" at 20MHz
• Low power consumption : 8mA for fast read mode or 4mA for normal read mode
• Low standby current : 15uA
GENERAL DESCRIPTION
The MX23L12854 is a 128Mbit (16M Bytes) Serial Mask ROM accessed by a high speed Serial peripheral interface.
PIN CONFIGURATIONS
SYMBOL DESCRIPTION
SCLK Serial Clock
SI Serial Data Input
SO Serial Data Output
CS# Chip Select
HOLD# Hold to pause the device without
deselecting the device
VCC Power Supply
VSS Ground
PIN DESCRIPTION
16-PIN SOP (300 mil)
Note:
1. NC=No Connection
2. See page 15 for package dimensions, and how to
identify pin-1.
P/N: PM1141 REV. 1.7, NOV. 09, 2007
1
2
3
4
5
6
7
8
HOLD#
VCC
NC
NC
NC
NC
CS#
SO
16
15
14
13
12
11
10
9
SCLK
SI
NC
NC
NC
NC
VSS
NC
ORDER INFORMATION
Part No. Speed Package Remark
MX23L12854MC-20G 20ns 16-SOP Pb-free
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
MEMORY ORGANIZATION
The memory is organized as:
- 16M bytes
BLOCK DIAGRAM
Address
Generator
Memory Array
Y-Decoder
X-Decoder
Data
Register
SI
SCLK Clock Generator
State
Machine
Mode
Logic
Sense
Amplifier Output
Buffer
SO
CS#
HOLD#
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MX23L12854
Figure 1. SPI Modes Supported
SCLK
MSB
CPHA shift in shift out
SI
0
1
CPOL
0(SPI mode 0)
(SPI mode 3) 1
SO
SCLK
MSB
Note:
CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is
supported.
DEVICE OPERATION
Stand-by Mode
When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps in standby mode until next
CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
Active Mode
When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS#
rising edge.
SPI Feature
Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference
of SPI mode 0 and mode 3 is shown as Figure 1.
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MX23L12854
HOLD#
CS#
SCLK
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is a high impedance, that both Serial Data Input (SI) and Serial Clock (SCLK) are "don't care"
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the
device. To re-start the communication with chip, the HOLD# must be kept as high and CS# must be kept as low.
Figure 2. Hold Condition Operation
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device.
The operation of HOLD requires Chip Select(CS#) to stay low and starts on falling edge of HOLD# pin signal while Serial
Clock (SCLK) signal keeps to be low (if Serial Clock signal does not keep to be low, HOLD operation will not start until Serial
Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal
keeps to be low( if Serial Clock signal does not keep to be low, HOLD operation will not end until Serial Clock being low),
Please refer to Figure 2.
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
Table 1. COMMAND DEFINITION
Notes:
1. n bytes are read out until CS# goes high.
2. It is not recommended to adopt any code not in the above command definition table.
Command 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte
Set Code
RDID 9Fh Manufacturer Memory type Memory
(read ID) ID ID density ID
READ 03h AD1 AD2 AD3 Data out Note 1
(read data) (A23-A16) (A15-A8) (A7-A0) (D7-D0)
Fast Read 0Bh AD1 AD2 AD3 Dummy Data out
(fast read data) (A23-A16) (A15-A8) (A7-A0) Cycle (D7-D0)
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MX23L12854
COMMAND DESCRIPTION
(1) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and is followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2h, the memory type ID is 05h as the first-byte device ID, and the individual device ID of second-byte
ID is:18h.
The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data is sent out
on SO -> to end RDID operation which can use CS# to be high at any time during data out. (see Figure 3) When CS#
goes high, the device is at standby stage.
Table of ID Definitions:
RDID manufacturer ID memory type memory density
9Fh C2h 05h 18h
(2) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling
edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
READ instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address is sent
on SI -> data out on SO-> to end READ operation which can use CS# to be high at any time during data out. (see Figure
4)
(3) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of
each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory
can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has
been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low-> send FAST_READ instruction code-> 3-byte address
is sent on SI-> 1-dummy byte address is sent on SI->data out on SO-> to end FAST_READ operation which can use CS#
to be high at any time during data out. (see Figure 5)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
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MX23L12854
Figure 3. Read Identification (RDID) Sequence (Command 9F)
21 3456789101112131415
Command
0
Manufacturer Identification
High-Z
MSB
15 1413 3210
Device Identification
MSB
765 3210
16 17 18 28 29 30 31
SCLK
SI
CS#
SO
9F
Figure 4. Read Data Bytes (READ) Sequence (Command 03)
SCLK
SI
CS#
SO
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
Data Out 1
24-Bit Address
0
MSB
MSB
2
39
Data Out 2
03
High-Z
command
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
Figure 5. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
23
21 345678910 28293031
2221 3210
High-Z
24 BIT ADDRESS
0
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
SCLK
SI
CS#
SO
SCLK
SI
CS#
SO
0B
Command
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
NOTICE:
1. Stress greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage
of the device. This is stress rating only and functional
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions in
long period of time may affect reliability.
2. Specifications contained within the following Table 2
and 3 are subjects to change.
3. During voltage transitions, all pins may overshoot Vss
to -2.0V and Vcc to +2.0V for periods up to 20ns, see
Figure 3,4.
RATING VALUE
Ambient Operating Temperature 0°C to 70°C
Storage Temperature -65°C to 150°C
Applied Input Voltage -0.6V to 4.0V
Applied Output Voltage -0.6V to 4.0V
VCC to Ground Potential -0.6V to 4.0V
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS
CAPACITANCE TA = 25°°
°°
°C, f = 20 MHz
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
CIN Input Capacitance 6 pF VIN = 0V
COUT Output Capacitance 8 p F VOUT = 0V
Figure 6.Maximum Negative Overshoot Waveform Figure 7. Maximum Positive Overshoot Waveform
Vss
Vss - 2.0V
20ns 20ns
20ns
Vcc + 2.0V
Vcc
20ns 20ns
20ns
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
Figure 8. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Figure 9. OUTPUT LOADING
AC
Measurement
Level
Input timing referance level Output timing referance level
0.8VCC 0.7VCC
0.3VCC 0.5VCC
0.2VCC
Note: The rise and fall time of input pulse < 5ns
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm +3.3V
The condition "CL=30pF" includes jig capacitance
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
SYMBOL PARAMETER NOTES MIN. TYP MAX. UNITS TEST CONDITIONS
ISB1 VCC Standby 1 1 5 uA VIN = VCC or GND
Current CS# = VCC
ICC1 VCC Read 1 8 mA f=50MHz
SCLK=0.1VCC/0.9VCC, SO=Open
4 mA f=20MHz
SCLK=0.1VCC/0.9VCC, SO=Open
ILI Input Load 1 ± 2 uA VCC = VCC Max
Current VIN = VCC or GND
ILO Output Leakage 1 ± 2 uA VCC = VCC Max
Current VIN = VCC or GND
VIL Input Low Voltage -0.5 0.3VCC V
VOL Output Low Voltage 0.4 V IOL = 1.6mA
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOH Output High Voltage VCC-0.2 V IOH = -100uA
Table 2. DC CHARACTERISTICS (Temperature = 0 °°
°°
°C to 70°°
°°
°C, VCC = 3.0V ~ 3.6V)
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
Table 3. AC CHARACTERISTICS (Temperature = 0 °°
°°
°C to 70°°
°°
°C, VCC = 3.0V ~ 3.6V)
Symbol Alt. Parameter Min. Typ. Max. Unit
fSCLK fC Clock Frequency for FAST_READ, RDID D.C. 50 MHz
Commands (Condition:30pF)
fRSCLK fR Clock Frequency for READ Commands D.C. 20 MHz
tCH(1) tCLH Clock High Time 9 ns
tCL(1) tCLL Clock Low Time 9 ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 5 ns
tC H SL CS# Not Active Hold Time (relative to SCLK) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCH DX t DH Data In Hold Time 5 ns
t CH S H CS# Active Hold Time (relative to SCLK) 5 ns
tSHCH CS# Not Active Setup Time (relative to SCLK) 5 ns
tSHSL tCSH CS# Deselect Time 1 00 ns
tSHQZ(2) tDIS Output Disable Time 8 ns
tC LQ V tV Clock Low to Output Valid 8 ns
tCLQX tHO Output Hold Time 0 ns
tCLCH(2) Clock Rise Time (3) (peak to peak) 0. 1 V/ns
tCHCL(2) Clock Fall Time (3) (peak to peak) 0. 1 V/ns
tHHQX(2) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(2) tHZ HOLD# to Output High-Z 8 ns
tHLCH HOLD# Setup Time (relative to SCLK) 5 ns
tCHHH HOLD# Hold Time (relative to SCLK) 5 ns
tHHCH HOLD Setup Time (relative to SCLK) 5 ns
tCHHL HOLD Hold Time (relative to SCLK) 5 ns
Notes:
(1). tCH + tCL must be greater than or equal to 1/ fC
(2). The values in the table are guaranteed by characterization, not 100% tested in production.
(3). Indicated as a slew rate.
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MX23L12854
Figure 10. Input Timing
SCLK
SI
CS#
MSB
SO
tDVCH
High-Z
LSB
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
Figure 11. Output Timing
LSB
ADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
SCLK
SO
CS#
SI
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MX23L12854
Figure 12. Hold Timing
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
SCLK
SO
CS#
HOLD#
* SI is "don't care" during HOLD operation.
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
PACKAGE INFORMATION
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P/N: PM1141 REV. 1.7, NOV. 09, 2007
MX23L12854
REVISION HISTORY
Revision Description Page Date
1.0 1. Added "Order Information" P1 APR/06/2005
1. 1 1. Changed VCC from "2.7V to 3.6V" to "3.0V to 3.6V" P1 , 11 MAY/04/2005
1.2 1. Added "Read Identification (RDID)" information P7 SEP/23/2005
1.3 1. Modified Table 2. Read Identification (RDID) Data-Out Sequence P7 SEP/27/2005
1. 4 1. Modified memory type & memory capacity P7 OCT/21/2005
1. 5 1. Modified Table 9. AC Characteristics P 14 NOV/03/2005
1. 6 1. Added statement P19 NOV/07/2006
1. 7 1. Tightened maximum standby current from 50uA to 15uA P 1,11 NOV/09/2007
2. Changed format arrangement All
MX23L12854
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