SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
2−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
•Fully Synchronous Operation for Counting
and Programming
•Internal Carry Look-Ahead Circuitry for
Fast Counting
•Carry Output for n-Bit Cascading
•Fully Independent Clock Circuit
•Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These synchronous 4-bit up/down binary
presettable counters feature an internal carry
look-ahead circuitry for cascading in high-speed
counting applications. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change
coincident with each other when so instructed by
the count-enable (ENP, ENT) inputs and internal
gating. This mode of operation eliminates the
output counting spikes normally associated with
asynchronous (ripple-clock) counters. A buffered
clock (CLK) input triggers the four flip-flops on the
rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is,
they may be preset to either level. The load-input
circuitry allows loading with the carry-enable
output of cascaded counters. Because loading is
synchronous, setting up a low level at the load
(LOAD) input disables the counter and causes the
outputs to agree with the data inputs after the next
clock pulse.
The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without
additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in accomplishing this
function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the
up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward
to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting
down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enable successive
cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs
are diode clamped to minimize transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, or U/D)
that modify the operating mode have no ef fect on the contents of the counter until clocking occurs. The function
of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range
of −55°C to 125°C. The SN74ALS169B and SN74AS169A are characterized for operation from 0°C to 70°C.
SN54ALS169B, SN54AS169A...J PACKAGE
SN74ALS169B, SN74AS169A...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
QA
QB
NC
QC
QD
A
B
NC
C
D
SN54ALS169B, SN54AS169A...FK PACKAGE
(TOP VIEW)
CLK
U/D
NC
LOAD
ENT RCO
ENP
GND
NC
NC − No internal connection
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U/D
CLK
A
B
C
D
ENP
GND
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
!"#$ % &'!!($ #% )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
2−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
logic symbol†
CTRDIV16
LOAD
1, 7D
3
A4
B5
C6
D
M2 [COUNT]
M1 [LOAD]
9
2,3,5,6+/C7
G5
10 15
3,5CT=15
14
13
12
11
QA
QB
QC
QD
G6
7
2
CLK
1
2
4
8
U/D M4 [DOWN]
M3 [UP]
1
2,4,5,6 −
ENT
ENP
RCO
4,5CT=0
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
2−3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
logic diagram (positive logic)
C1
1D 142
3
7
10
1
9
15
C1
1D 13
4
C1
1D 12
5
C1
1D 11
6
LOAD
U/D
ENT
ENP
CLK
A
B
C
D
QA
QB
QC
QD
RCO
Pin numbers shown are for the D, J, and N packages.
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
2−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
typical load, count, and inhibit sequences
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
Data
Inputs
Data
Outputs
LOAD
A
B
C
D
CLK
U/D
ENP and ENT
RCO
QA
QB
QC
QD
Load
Count Up Inhibit
13 14 15 0 012
Count Down
221 1315 14
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54ALS169B −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS169B 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
2−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions
SN54ALS169B SN74ALS169B
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 4 8 mA
fclock Clock frequency 0 22 0 40 MHz
twPulse duration, CLK high or low 14 12.5 ns
A, B, C, or D 20 15
tsu
Setup time before CLK↑
ENP or ENT 25 15
ns
tsu Setup time before CLK↑LOAD 20 15 ns
U/D 28 15
thHold time, data after CLK↑0 0 ns
TAOperating free-air temperature −55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS169B SN74ALS169B
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = −18 mA −1.5 −1.5 V
VOH VCC = 4.5 V to 5.5 V, IOH = −0.4 mA VCC −2 VCC −2 V
VOL
VCC = 4.5 V
IOL = 4 mA 0.25 0.4 0.25 0.4
V
VOL VCC = 4.5 V IOL = 8 mA 0.35 0.5 V
IIVCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL VCC = 5.5 V, VI = 0.4 V −0.2 −0.2 mA
IO‡VCC = 5.5 V, VO = 2.25 V −20 −112 −30 −112 mA
ICC VCC = 5.5 V 15 25 15 25 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
2−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†UNIT
PARAMETER
(INPUT)
(OUTPUT)
SN54ALS169B SN74ALS169B
UNIT
MIN MAX MIN MAX
fmax 22 40 MHz
tPLH
CLK
RCO
3 20 3 20
ns
tPHL CLK RCO 6 25 6 20 ns
tPLH
CLK
Any Q
2 20 2 15
ns
tPHL CLK Any Q 5 23 5 20 ns
tPLH
ENT
RCO
2 16 2 13
ns
tPHL ENT RCO 3 24 3 16 ns
tPLH
U/D
RCO
4 22 5 19
ns
tPHL
U/D
RCO
5 26 5 19
ns
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54AS169A −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74AS169A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS169A SN74AS169A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −2 −2 mA
IOL Low-level output current 20 20 mA
fclock*Clock frequency 0 60 0 75 MHz
tw*Pulse duration, CLK high or low 7.7 6.7 ns
A, B, C, or D 10 8
tsu*
Setup time before CLK↑
ENP or ENT 10 8
ns
tsu*Setup time before CLK↑LOAD 10 8 ns
U/D 14 11
th*Hold time, data after CLK↑2 0 ns
TAOperating free-air temperature −55 125 0 70 °C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
2−7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54AS169A SN74AS169A
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V
VOH VCC = 4.5 V to 5.5 V, IOH = −2 mA VCC −2 VCC −2 V
VOL VCC = 4.5 V, IOL = 20 mA 0.25 0.5 0.25 0.5 V
II
LOAD, ENT, U/D
VCC = 5.5 V,
VI = 7 V
0.2 0.2
mA
IIAll others VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH
LOAD, ENT, U/D
VCC = 5.5 V,
VI = 2.7 V
40 40
A
IIH All others VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL
LOAD, ENT, U/D
VCC = 5.5 V,
VI = 0.4 V
−1 −1
mA
IIL All others VCC = 5.5 V, VI = 0.4 V −0.5 −0.5 mA
IO‡VCC = 5.5 V, VO = 2.25 V −30 −112 −30 −112 mA
ICC VCC = 5.5 V 41 63 41 63 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX§UNIT
PARAMETER
(INPUT)
(OUTPUT)
SN54AS169A SN74AS169A
UNIT
MIN MAX MIN MAX
fmax* 60 75 MHz
tPLH
CLK
RCO
3 17.5 3 16.5
ns
tPHL CLK
RCO
(LOAD high or low) 2 14 2 13 ns
tPLH
CLK
Any Q
1 7.5 1 7
ns
tPHL CLK Any Q 2 14 2 13 ns
tPLH
ENT
RCO
1.5 10 1.5 9
ns
tPHL ENT RCO 1.5 10 1.5 9 ns
tPLH
U/D
RCO
2 14 2 12
ns
tPHL
U/D
RCO
2 14.5 2 13
ns
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994
2−8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL tPLH
0.3 V
tPZL
tPZH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B) [0 V
VOH
VOL
[3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test Test
Point
CL
(see Note A) RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
83025012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
8302501EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
8302501FA OBSOLETE CFP W 16 TBD Call TI Call TI
JM38510/38003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
JM38510/38003BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
M38510/38003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
M38510/38003BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN54ALS169BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN54AS169AJ OBSOLETE CDIP J 16 TBD Call TI Call TI
SN74ALS169BD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS169BDE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS169BDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS169BDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS169BDRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS169BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS169BN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS169BNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS169BNSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS169BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS169BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS169AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AS169ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ54ALS169BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SNJ54ALS169BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54AS169AFK OBSOLETE LCCC FK 20 TBD Call TI Call TI
SNJ54AS169AJ OBSOLETE CDIP J 16 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A :
•Catalog: SN74ALS169B, SN74AS169A
•Military: SN54ALS169B, SN54AS169A
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 3
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALS169BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74ALS169BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS169BDR SOIC D 16 2500 333.2 345.9 28.6
SN74ALS169BNSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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