M1N51264DSH8B1G-6K - Nanya Technology Corporation

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 1

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

200 pin Unbuffered DDR SO-DIMM

Based on DDR333 512Mb bit B Die device

Features

• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)

• Unbuffered DDR SO-DIMM based on 110nm 512M bit die B

device, organized 32Mx16 DDR SDRAM

• Performance:

PC2700

Speed Sort 6K

DIMM  Latency 2.5

Unit

fCK

Clock Frequency 166 MHz

tCK

Clock Cycle 6 ns

fDQ

DQ Burst Frequency

333 MHz

• Intended for 166 MHz applications

• Inputs and outputs are SSTL-2 compatible

• VDD = VDDQ = 2.5V ± 0.2V

• SDRAMs have 4 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• DRAM DLL aligns DQ and DQS transitions with clock transitions.

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- DIMM  Latency: 2.5

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 7.8 µs Max. Average Periodic Refresh Interval

• Serial Presence Detect EEPROM

• Gold contacts on module PCB

• RoHS Compliance:

M1N51264DSH8B1G

M1N25664DSH4B1G

Description

M1N51264DSH8B1G, M1N25664DSH4B1G, M1S51264DSH8B1G and M1S25664DSH4B1G are un-buffered 200-Pin Double Data Rate

(DDR) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM). All devices on these modules are based on Nanya’s

110nm die B generation of 512M bit devices.

The M1N51264DSH8B1G and M1S51264DSH8B1G are organized as two ranks of 64Mx64 high-speed memory array and use eight

32Mx16 DDR SDRAMs TSOP packages. The M1N25664DSH4B1G and M1S25664DSH4B1G are also organized a single rank of 32Mx64

high-speed memory array but by using four 32Mx16 DDR SDRAMs TSOP packages.

The DIMM is intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to

333 MHz. Prior to any access operation, the device  latency and burst type/ length/operation type must be programmed into the DIMM

by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.

The SO-DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) data

can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 2

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Ordering Information

Green

Part Number Size Speed Power Leads

M1N51264DSH8B1G-6K 62Mx64

M1N25664DSH4B1G -6K 32Mx64

DDR333

Devices

PC2700

2.5-3-3

166MHz (6ns @ CL = 2.5) 2.5V

Gold

(lead and

halogen free)

Part Number Size Speed Power Leads

M1S51264DSH8B1G-6K 64Mx64

M1S25664DSH4B1G-6K 32Mx64

DDR333

Devices

PC2700

2.5-3-3

166MHz (6ns @ CL = 2.5) 2.5V Gold

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 3

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Pin Description

CK0, CK1, CK2,

, ,  Differential Clock Inputs. DQ0-DQ63 Data input/output

CKE0, CKE1 Clock Enable DQS0-DQS7 Bidirectional data strobes

 Row Address Strobe DM0-DM7 Input Data Mask

 Column Address Strobe VDD Power

  Write Enable VDDQ Supply voltage for DQs

,  Chip Selects VSS Ground

A0-A9, A11, A12

Address Inputs NC No Connect

A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input

BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output

VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs

VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply

Pinout

Front Pin

Back Pin

Front Pin

Back Pin

Front Pin

Back Pin

Front Pin

Back

1 VREF 2

VREF 51

VSS 52

VSS 101

A9 102

A8 151

DQ42 152

DQ46

3 VSS 4

VSS 53

DQ19 54

DQ23 103

VSS 104

VSS 153

DQ43 154

DQ47

5 DQ0 6

DQ4 55

DQ24 56

DQ28 105

A7 106

A6 155

VDD 156

VDD

7 DQ1 8

DQ5 57

VDD 58

VDD 107

A5 108

A4 157

VDD 158



9 VDD 10

VDD 59

DQ25 60

DQ29 109

A3 110

A2 159

VSS 160

CK1

11 DQS0 12

DM0 61

DQS3 62

DM3 111

A1 112

A0 161

VSS 162

VSS

13 DQ2 14

DQ6 63

VSS 64

VSS 113

VDD 114

VDD 163

DQ48 164

DQ52

15 VSS 16

VSS 65

DQ26 66

DQ30 115

A10/AP

116

BA1 165

DQ49 166

DQ53

17 DQ3 18

DQ7 67

DQ27 68

DQ31 117

BA0 118

 167

VDD 168

VDD

19 DQ8 20

DQ12 69

VDD 70

VDD 119

  120

 169

DQS6 170

DM6

21 VDD 22

VDD 71

NC 72

NC 121

 122

 171

DQ50 172

DQ54

23 DQ9 24

DQ13 73

NC 74

NC 123

DU 124

DU 173

VSS 174

VSS

25 DQS1 26

DM1 75

VSS 76

VSS 125

VSS 126

VSS 175

DQ51 176

DQ55

27 VSS 28

VSS 77

DQS8 78

NC 127

DQ32 128

DQ36 177

DQ56 178

DQ60

29 DQ10 30

DQ14 79

NC 80

NC 129

DQ33 130

DQ37 179

VDD 180

VDD

31 DQ11 32

DQ15 81

VDD 82

VDD 131

VDD 132

VDD 181

DQ57 182

DQ61

33 VDD 34

VDD 83

NC 84

NC 133

DQS4 134

DM4 183

DQS7 184

DM7

35 CK0 36

VDD 85

DU 86

DU 135

DQ34 136

DQ38 185

VSS 186

VSS

37  38

VSS 87

VSS 88

VSS 137

VSS 138

VSS 187

DQ58 188

DQ62

39 VSS 40

VSS 89

CK2 90

VSS 139

DQ35 140

DQ39 189

DQ59 190

DQ63

41 DQ16 42

DQ20 91

 92

VDD 141

DQ40 142

DQ44 191

VDD 192

VDD

43 DQ17 44

DQ21 93

VDD 94

VDD 143

VDD 144

VDD 193

SDA 194

SA0

45 VDD 46

VDD 95

CKE1 96

CKE0 145

DQ41 146

DQ45 195

SCL 196

SA1

47 DQS2 48

DM2 97

DU 98

DU 147

DQS5 148

DM5 197

VDDSPD 198

SA2

49 DQ18 50

DQ22 99

A12 100

A11 149

VSS 150

VSS 199

VDDID 200

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 4

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Input/Output Functional Description

Symbol Type

Polarity

Function

CK0, CK1, CK2,

, ,  (SSTL)

Cross

point

The system clock inputs. All address and command lines are sampled on the cross point of

the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven

from the clock inputs and output timing for read operations is synchronized to the input

clock.

CKE0, CKE1 (SSTL)

Active

High

Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.

By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

,  (SSTL)

Active

Low

Enables the associated DDR SDRAM command decoder when low and disables the

command

decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is

selected by S1.

, ,   (SSTL)

Active

Low When sampled at the positive rising edge of the clock, , ,  

define the operation to

be executed by the SDRAM.

VREF Supply

Reference voltage for SSTL-2 inputs

VDDQ Supply

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

BA0, BA1 (SSTL)

- Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11 - A13 (SSTL)

During a Bank Activate command cycle, these lines define the row address when sampled

at the rising clock edge.

During a Read or Write command cycle, these lines defines the column address when

sampled at the rising clock edge. In addition to the column address, AP is used to invoke

auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,

auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,

auto-precharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63 (SSTL)

- Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

DQS0 – DQS8 (SSTL)

Active

High

Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data. DQS8 is used for ECC modules

(CB0-CB7) and is not used on x64 modules.

CB0 – CB7 (SSTL)

- Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.

DM0 – DM8 Input

Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a byte

mask by allowing input data to

be written if it is low but blocks the write operation if it is high.

In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-

CB7, and is

not used on x64 modules.

VDD, VSS Supply

Power and ground for the DDR SDRAM input buffers and core logic

SA0 – SA2 - Address inputs. Connected to either VDD or VSS

on the system board to configure the Serial

Presence Detect EEPROM address.

SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to VDD to act as a pull-up.

SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to VDD to act as a pull-up.

VDDSPD Supply

Serial EEPROM positive power supply.

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 5

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

2 Ranks, 8 devices, 32Mx16 DDR SDRAMs



DM0

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

DQS0

DM4

DQS4

DM1

DQS1

DM2

DQS2

DM3

DQS3

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

DQS5

DM5

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQS6

DM6

DQS7

DM7



Serial PD

A0 A2A1

SCL

WP SDA

SA0 SA2SA1

DDSPD

SPD

D0-D7

DDQ

REF

DDID

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

Notes :

1. DQ wiring may differ from that described in this drawing.

2. DQ/DQS/DM/CKE/S relationships are maintained as shown.

3. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms.

4. V

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

A0-A12



BA0-BA1 BA0-BA1 : SDRAMs D0-D7

A0-A12 : SDRAMs D0-D7

 : SDRAMs D0-D7

CKE0

 

  : SDRAMs D0-D7

CKE : SDRAMs D0-D3

CKE : SDRAMs D4-D7

  : SDRAMs D0-D7

CKE1

Clock Wiring

Clock Input SDRAMs

CK0/

CK1/

CK2/

4 SDRAMs

* Clock Net Wiring D0/D4

D1/D5

D2/D6

D3/D7

Card

Edge

CK0/CK1

/

R=120 Ohms

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 6

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

1 Rank, 4 devices, 32Mx16 DDR SDRAMs



DM0

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

DQS0

DM4

DQS4

DM1

DQS1

DM2

DQS2

DM3

DQS3

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

DQS5

DM5

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQS6

DM6

DQS7

DM7

Serial PD

A0 A2A1

SCL

WP SDA

SA0 SA2SA1

DDSPD

SPD

D0-D3

DDQ

REF

DDID

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

LDM



I/O 8

I/O 9

I/O 14

I/O 13

I/O 12

I/O 11

I/O 10

I/O 15

UDM

UDQS

LDQS

Notes :

1. DQ wiring may differ from that described in this drawing.

2. DQ/DQS/DM/CKE/S relationships are maintained as shown.

3. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms.

4. V

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

2 loads

CK0



CK1



CK2



2 loads

0 loads

BA0-BA1

A0-A12



BA0-BA1 : SDRAMs D0-D3

A0-A12 : SDRAMs D0-D3

 : SDRAMs D0-D3

CKE0

 

  : SDRAMs D0-D3

CKE : SDRAMs D0-D3

N.C.

  : SDRAMs D0-D3

CKE1

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 7

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Serial Presence Detect

Byte Description Byte Description

0 Number of Serial PD Bytes Written during Production 27 Minimum Row Precharge Time (tRP)

1 Total Number of Bytes in Serial PD device 28 Minimum Row Active to Row Active delay (tRRD)

2 Fundamental Memory Type 29 Minimum RAS to CAS delay (tRCD)

3 Number of Row Addresses on Assembly 30 Minimum RAS Pulse Width (tRAS)

4 Number of Column Addresses on Assembly 31 Module Bank Density

5 Number of DIMM Rank 32 Address and Command Setup Time Before Clock

6 Data Width of Assembly 33 Address and Command Hold Time After Clock

7 Data Width of Assembly (cont’) 34 Data Input Setup Time Before Clock

8 Voltage Interface Level of this Assembly 35 Data Input Hold Time After Clock

9 DDR SDRAM Device Cycle Time

CL=2.5 36-40 Reserved

10 DDR SDRAM Device Access Time from Clock

CL=2.5 41 Minimum Active/Auto-refresh Time (tRC)

11 DIMM Configuration Type 42 Auto-refresh to Active/Auto-refresh Command Period

(tRFC)

12 Refresh Rate/Type 43 Max Cycle Time (tCK max)

13 Primary DDR SDRAM Width 44 Maximum DQS-DQ Skew Time (tDQSQ)

14 Error Checking DDR SDRAM Device Width 45 Maximum Read Data Hold Skew Factor (tQHS)

15 DDR SDRAM Device Attr: Min CLK Delay, Random Col

Access 46 Reserved

16 DDR SDRAM Device Attributes: Burst Length

Supported 47 Dimm Height

17 DDR SDRAM Device Attributes: Number of Device

Banks 48-61 Reserved

18 DDR SDRAM Device Attributes:

CAS Latencies Supported 62 SPD Revision

19 DDR SDRAM Device Attributes: CS Latency 63 Checksum Data

20 DDR SDRAM Device Attributes: WE Latency 64-71 Manufacturer’s JEDEC ID Code

21 DDR SDRAM Device Attributes: 72 Module Manufacturing Location

22 DDR SDRAM Device Attributes: General 73-90 Module Part number

23 Minimum Clock Cycle

CL=2.5 91-92 Module Revision Code

24 Maximum Data Access Time from Clock at

CL=2 93-94

Module Manufacturing Data

yy= Binary coded decimal year code, 0-99(Decimal),

00-63(Hex)

ww= Binary coded decimal year code, 01-52(Decimal),

01-34(Hex)

25 Minimum Clock Cycle Time at CL=1 95-98 Module Serial Number

26 Maximum Data Access Time from Clock at CL=1 99-127

Reserved

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 8

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

SPD Values for M1N51264DSH8B1G / M1S51264DSH8B1G

SPD Entry Value Serial PD Data Entry (Hexadecimal)

Note

Byte Description DDR333

-6K

DDR333

-6K

0 Number of Serial PD Bytes Written during Production 128 80

1 Total Number of Bytes in Serial PD device 256 08

2 Fundamental Memory Type DDR SDRAM 07

3 Number of Row Addresses on Assembly 13 0D

4 Number of Column Addresses on Assembly 10 0A

5 Number of DIMM Bank 2 02

6. Data Width of Assembly X64 40

7 Data Width of Assembly (cont’) X64 00

8 Voltage Interface Level of this Assembly SSTL 2.5V 04

9 DDR SDRAM Device Cycle Time at CL=2.5 6ns 60

10 DDR SDRAM Device Access Time from Clock at CL=2.5 0.7ns 70

11 DIMM Configuration Type Non-Parity 00

12 Refresh Rate/Type SR/1x(7.8us), Self Refresh Flag 82

13 Primary DDR SDRAM Width X16 10

14 Error Checking DDR SDRAM Device Width N/A 00

15 DDR SDRAM Device Attr: Min Clk Delay, Random Col Access 1 Clock 01

16 DDR SDRAM Device Attributes: Burst Length Supported 2,4,8 0E

17 DDR SDRAM Device Attributes: Number of Device Banks 4 04

18 DDR SDRAM Device Attributes: CAS Latencies Supported 2/2.5 0C

19 DDR SDRAM Device Attributes: CS Latency 0 01

20 DDR SDRAM Device Attributes: WE Latency 1 02

21 DDR SDRAM Device Attributes: Differential Clock 20

22 DDR SDRAM Device Attributes: General +/-0.2V Voltage Tolerance C0

23 Minimum Clock Cycle at CL=2.5/2/2 7.5ns 75

24 Maximum Data Access Time (tAC) from Clock at CL=2.5/2/.2 0.75ns 75

25 Minimum Clock Cycle Time at CL=2/1/1.5 N/A 00

26 Maximum Data Access Time (tAC) from Clock at CL=2/1/1.5 N/A 00

27 Minimum Row Precharge Time (tRP) 18ns 48

28 Minimum Row Active to Row Active delay (tRRD) 12ns 30

29 Minimum RAS to CAS delay (tRCD) 18ns 48

30 Minimum RAS Pulse Width (tRAS) 42ns 2A

31 Module Bank Density 256MB 40

32 Address and Command Setup Time Before Clock 0.75ns 75

33 Address and Command Hold Time After Clock 0.75ns 75

34 Data Input Setup Time Before Clock 0.45ns 45

35 Data Input Hold Time After Clock 0.45ns 45

36-40 Reserved Undefined 00

41 Minimum Active/Auto-Refresh Time (tRC) 60ns 3C

42 SDRAM Device Minimum Auto-Refresh to Active/Auto Refresh

Command Period (tRFC)

72ns 48

43 SDRAM Device Maximum Cycle Time (tCK max) 12 30

44 SDRAM Device Maximum DQS-DQ Skew Time (tDQSQ) 0.45 2D

45 SDRAM Device Maximum Read Data Hold Skew Factor (tQHS) 0.55 55

46 Superset Information (may be used in future) Undefined 00

47 SDRAM device Attributes – DDR SDRAM DIMM Height 31.75mm 01

48-61 Superset Information (may be used in future) Undefined 00

62 SPD Revision 1.0 10

63 Checksum Data 1F

64-71 Manufacturer’s JEDED ID Code 0B Hex bank 3 7F7F7F0B00000000

72 Module Manufacturing Location

Note 1 1

73-255

Reserved Undefined Note 2 2

1. please refer to BNDCJ-0082

2. byte 93-255 please refer to NDCJ-0969

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 9

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

SPD Values for M1N25664DSH4B1G / M1S25664DSH4B1G

SPD Entry Value Serial PD Data Entry (Hexadecimal)

Note

Byte Description DDR333

-6K

DDR333

-6K

0 Number of Serial PD Bytes Written during Production 128 80

1 Total Number of Bytes in Serial PD device 256 08

2 Fundamental Memory Type DDR SDRAM 07

3 Number of Row Addresses on Assembly 13 0D

4 Number of Column Addresses on Assembly 10 0A

5 Number of DIMM Bank 1 01

6. Data Width of Assembly X64 40

7 Data Width of Assembly (cont’) X64 00

8 Voltage Interface Level of this Assembly SSTL 2.5V 04

9 DDR SDRAM Device Cycle Time at CL=2.5 6ns 60

10 DDR SDRAM Device Access Time from Clock at CL=2.5 0.7ns 70

11 DIMM Configuration Type Non-Parity 00

12 Refresh Rate/Type SR/1x(7.8us), Self Refresh Flag 82

13 Primary DDR SDRAM Width X16 10

14 Error Checking DDR SDRAM Device Width N/A 00

15 DDR SDRAM Device Attr: Min Clk Delay, Random Col Access 1 Clock 01

16 DDR SDRAM Device Attributes: Burst Length Supported 2,4,8 0E

17 DDR SDRAM Device Attributes: Number of Device Banks 4 04

18 DDR SDRAM Device Attributes: CAS Latencies Supported 2/2.5 0C

19 DDR SDRAM Device Attributes: CS Latency 0 01

20 DDR SDRAM Device Attributes: WE Latency 1 02

21 DDR SDRAM Device Attributes: Differential Clock 20

22 DDR SDRAM Device Attributes: General +/-0.2V Voltage Tolerance C0

23 Minimum Clock Cycle at CL=2.5/2/2 7.5ns 75

24 Maximum Data Access Time (tAC) from Clock at CL=2.5/2/2 0.75ns 75

25 Minimum Clock Cycle Time at CL=2/1/1.5 N/A 00

26 Maximum Data Access Time (tAC) from Clock at CL=2/1/1.5 N/A 00

27 Minimum Row Precharge Time (tRP) 18ns 48

28 Minimum Row Active to Row Active delay (tRRD) 12ns 30

29 Minimum RAS to CAS delay (tRCD) 18ns 48

30 Minimum RAS Pulse Width (tRAS) 42ns 2A

31 Module Bank Density 256MB 40

32 Address and Command Setup Time Before Clock 0.75ns 75

33 Address and Command Hold Time After Clock 0.75ns 75

34 Data Input Setup Time Before Clock 0.45ns 45

35 Data Input Hold Time After Clock 0.45ns 45

36-40 Reserved Undefined 00

41 Minimum Active/Auto-Refresh Time (tRC) 60ns 3C

42 SDRAM Device Minimum Auto-Refresh to Active/Auto Refresh

Command Period (tRFC)

72ns 48

43 SDRAM Device Maximum Cycle Time (tCK max) 12 30

44 SDRAM Device Maximum DQS-DQ Skew Time (tDQSQ) 0.45 2D

45 SDRAM Device Maximum Read Data Hold Skew Factor (tQHS) 0.55 55

46 Superset Information (may be used in future) Undefined 00

47 SDRAM device Attributes – DDR SDRAM DIMM Height 31.75mm 01

48-61 Superset Information (may be used in future) Undefined 00

62 SPD Revision 1.0 10

63 Checksum Data 1E

64-71 Manufacturer’s JEDED ID Code 0B Hex bank 3 7F7F7F0B00000000

72 Module Manufacturing Location Note1 1

73-255

Reserved Undefined Note 2 2

1. please refer to BNDCJ-0082

2. byte 93-255 please refer to NDCJ-0969

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 10

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, VOUT Voltage on I/O pins relative to VSS -0.5V to VDDQ +0.5V V

VIN Voltage on Input relative to VSS -1 to +3.6 V

VDD Voltage on VDD supply relative to VSS -1 to +3.6 V

VDDQ Voltage on VDDQ supply relative to VSS -1 to +3.6 V

TA Operating Temperature (Ambient) 0 to +70 °C

TSTG Storage Temperature (Plastic) -55 to +150 °C

PD Power Dissipation (per device component) 1 W

IOUT Short Circuit Output Current 50 mA

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress

rating only, and functional operation of the device at these or any other conditions above those indicated in the operational secti

ons of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC Electrical Characteristics and Operating Conditions

TA = 0 °C ~ 70 °C; VDDQ = VDD = 2.5V ± 0.2V

Symbol Parameter Min Max Units

Notes

VDD Supply Voltage 2.3 2.7 V 1

VDDQ I/O Supply Voltage 2.3 2.7 V 1

VSS, VSSQ Supply Voltage, I/O Supply Voltage 0 0 V

VREF I/O Reference Voltage 0.49 x VDDQ

0.51 x VDDQ

V 1, 2

VTT I/O Termination Voltage (System) VREF – 0.04

VREF + 0.04

V 1, 3

VIH (DC) Input High (Logic1) Voltage VREF + 0.15

VDDQ + 0.3

V 1

VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15

V 1

VIN (DC) Input Voltage Level, CK and  Inputs -0.3 VDDQ + 0.3

V 1

VID (DC) Input Differential Voltage, CK and  Inputs 0.36 VDDQ + 0.6

V 1, 4

II Input Leakage Current

Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) -2 2 µA 1

IOZ Output Leakage Current

(DQs are disabled; 0V ≤ Vout ≤ VDDQ -5 5 µA 1

IOH Output High Current

(VOUT = VDDQ -0.373V, min VREF, min VTT) -16.2 - mA 1

IOL Output Low Current

(VOUT = 0.373, max VREF, max VTT) 16.2 - mA 1

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed 2% of the DC value.

3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,

and must track variations in the DC level of VREF.

4. VID is the magnitude of the difference between the input level on CK and the input level on .

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 11

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

AC Characteristics

Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the

related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to

the crossing point for CK, ), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions.

The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the

signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW

(HIGH) level.

AC Output Load Circuits

Timing Reference Point

50 ohms

30 pF

Output

OUT

AC Operating Conditions

TA = 0 °C ~ 70 °C; VDDQ = VDD = 2.5V ± 0.2V

Symbol

Parameter/Condition Min Max Unit Notes

VIH (AC)

Input High (Logic 1) Voltage. VREF + 0.31 V 1, 2

VIL (AC)

Input Low (Logic 0) Voltage. VREF - 0.31 V 1, 2

VID (AC)

Input Differential Voltage, CK and  Inputs 0.7 VDDQ + 0.6 V 1, 2, 3

VIX (AC)

Input Differential Pair Cross Point Voltage, CK and  Inputs (0.5* VDDQ) - 0.2

(0.5* VDDQ) + 0.2

V 1, 2, 4

1. Input slew rate = 1V/ ns.

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on .

4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 12

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Operating, Standby, and Refresh Currents

TA = 0 °C ~ 70 °C; VDDQ = VDD = 2.5V ± 0.2V

Symbol

Parameter/Condition Notes

IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing once per clock cycle 1,2

IDD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT

= 0mA; address and

control inputs changing once per clock cycle 1,2

IDD2P

Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) 1,2

IDD2N

Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK = tCK (MIN); address and control inputs changing once

per clock cycle 1,2

IDD3P

Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) 1,2

IDD3N

Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥ VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

, and

DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1,2

IDD4R

Operating Current: one bank; Burst = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1,2

IDD4W

Operating Current: one bank; Burst = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1,2

IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 1,2,3

IDD6 Self-Refresh Current: CKE ≤ 0.2V 1,2

IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of

data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1,2

1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s.

All IDD current values are calculated from device level.

M1N51264DSH8B1G

M1S51264DSH8B1G

M1N25664DSH4B1G

M1S25664DSH4B1G

Symbol PC2700

(6K)

PC2700

(6K)

Unit

IDD0 810 382 mA

IDD1 839 397 mA

IDD2P 30 13 mA

IDD2N 222 99 mA

IDD3P 103 46 mA

IDD3N 406 180 mA

IDD4R 875 415 mA

IDD4W 977 466 mA

IDD5 1585 770 mA

IDD6 20 9 mA

IDD7 2503 1229 mA

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 13

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Package Dimensions

Non-ECC, 8 TSOP devices, M1N51264DSH8B1G / M1S51264DSH8B1G

67.60

63.60

4.00+/-0.10

1.00+/- 0.1

FRONT

SIDE

1.00+/- 0.10

Detail A

2.55

0.60

Detail B

0.45

0.25 MAX

1991 39 41

Detail A Detail B

4.00

20.00

31.75

6.00

2.15 11.40

4.20

1.80

47.40

3.80 MAX

(2X)Θ

1.80

2.45

2 40 42 200

BACK

Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated.

Units: Millimeters (Inches)

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 14

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Package Dimensions

Non-ECC, 4 TSOP devices, M1N25664DSH4B1G / M1S25664DSH4B1G

67.60

63.60

4.00+/-0.10

1.00+/- 0.1

FRONT

SIDE

1.00+/- 0.10

Detail A

2.55

0.60

Detail B

0.45

0.25 MAX

1991 39 41

Detail A Detail B

4.00

20.00

31.75

6.00

2.15 11.40

4.20

1.80

47.40

3.00 MAX

(2X)Θ

1.80

2.45

2 40 42 200

BACK

Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated.

Units: Millimeters (Inches)

M1N51264DSH8B1G / M1N25664DSH4B1G

M1S51264DSH8B1G / M1S25664DSH4B1G

512MB and 256MB

PC2700

REV 1.0 15

September 13, 2006

NANYA reserves the right to change products and specifications without notice.

Revision Log

Rev Date Modification

1.0 September 13, 2006 Official Release