LTC2321-16
1
Rev. D
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual, 16-Bit, 2Msps
Differential Input ADC with Wide
Input Common Mode Range
The LTC
®
2321-16 is a low noise, high speed dual 16-bit
successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operating from a single 3.3V or 5V supply, the LTC2321-
16 has an 8VP-P differential input range, making it ideal
for applications which require a wide dynamic range with
high common mode rejection. The LTC2321-16 achieves
±4LSB INL typical, no missing codes at 16 bits and 81dB
SNR.
The LTC2321-16 has an onboard low drift (20ppm/°C
max) 2.048V or 4.096V temperature-compensated
reference. The LTC2321-16 also has a high speed SPI-
compatible serial interface that supports CMOS or LVDS.
The fast 2Msps per channel throughput with no cycle
latency makes the LTC2321-16 ideally suited for a wide
variety of high speed applications. The LTC2321-16
dissipates only 31mW per channel and offers nap and
sleep modes to reduce the power consumption to 5μW
for further power savings during inactive periods.
32k Point FFT fS = 2Msps, fIN = 500kHz
APPLICATIONS
n 2Msps Throughput Rate
n ±4LSB INL (Typ)
n Guaranteed 16-Bit, No Missing Codes
n 8VP-P Differential Inputs with Wide Input Common
Mode Range
n 81dB SNR (Typ) at fIN = 500kHz
n –90dB THD (Typ) at fIN = 500kHz
n No Cycle Latency
n Guaranteed Operation to 125°C
n Single 3.3V or 5V Supply
n Low Drift (20ppm/°C Max) 2.048V or 4.096V Internal
Reference
n 1.8V to 2.5V I/O Voltages
n CMOS or LVDS SPI-Compatible Serial I/O
n Power Dissipation 31mW/Ch (Typ)
n Small 28-Lead (4mm × 5mm) QFN Package
n High Speed Data Acquisition Systems
n Communications
n Remote Data Acquisition
n Imaging
n Optical Networking
n Automotive
n Multiphase Motor Control
All registered trademarks and trademarks are the property of their respective owners.
BIPOLAR
25Ω
25Ω
220pF
UNIPOLAR
INSTRUMENTATION
DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
IN+, IN–
DIFFERENTIAL
OVDD
VDD
LTC2321-16
VDD
OGNDGND 1.8V TO 2.5V
232116 TA01a
10µF
3.3V OR 5V
SDO1
0V 0V
0V 0V
REFOUT2
VBYP1
REFOUT1
VBYP2
SDO2
CLKOUT
AIN1–
AIN2–
AIN2+
AIN1+
SCK
CNVREFINT
CMOS/LVDS
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
1µF
1µF
10µF
10µF
232116 TA01b
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0 10.8
0.40.2 0.6
0
–20
–40
–60
–80
–100
–120
–140
SNR = 81.0dB
THD = –94.6dB
SINAD = 80.8dB
SFDR = 100.9dB
LTC2321-16
2
Rev. D
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ..................................................6V
Supply Voltage (OVDD) ................................................3V
Supply Bypass Voltage (VBYP1, VBYP2) .......................3V
Analog Input Voltage
AIN+, AIN– (Note 3) ................... –0.3V to (VDD + 0.3V)
REFOUT1,2 ............................. .–0.3V to (VDD + 0.3V)
CNV (Note 15) .......................... –0.3V to (VDD + 0.3V)
Digital Input Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation ...............................................200mW
Operating Temperature Range
LTC2321C ................................................ 0°C to 70°C
LTC2321I..............................................–40°C to 85°C
LTC2321H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
9 10
TOP VIEW
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
29
GND
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
VDD
AIN2+
A
IN2–
GND
GND
A
IN1–
AIN1+
VDD
SCK–
SCK+
SDO2–
SDO2+
CLKOUT
–
CLKOUT+
SDO1–
SDO1+
REFINT
REFRTN2
REFOUT2
CMOS/LVDS
VBYP2
OGND
CNV
GND
REFRTN1
REFOUT1
VBYP1
OVDD
7
17
18
19
20
21
22
16
815
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2321CUFD-16#PBF LTC2321CUFD-16#TRPBF 23216 28-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C
LTC2321IUFD-16#PBF LTC2321IUFD-16#TRPBF 23216 28-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C
LTC2321HUFD-16#PBF LTC2321HUFD-16#TRPBF 23216 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+Absolute Input Range (AIN1+, AIN2+) (Note 5) l0 VDD V
VIN–Absolute Input Range (AIN1–, AIN2–) (Note 5) l0 VDD V
VIN+ – VIN–Input Differential Voltage Range VIN = VIN+ – VIN– l–REFOUT1,2 REFOUT1,2 V
VCM Common Mode Input Range VIN = (VIN+ – VIN–)/2 l0 VDD V
IIN Analog Input DC Leakage Current l–1 1 µA
CIN Analog Input Capacitance 10 pF
CMRR Input Common Mode Rejection Ratio fIN = 500kHz 85 dB
IREFOUT External Reference Current REFINT = 0V, REFOUT = 4.096V 310 µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
LTC2321-16
3
Rev. D
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DYNAMIC ACCURACY
CONVERTER CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l16 Bits
No Missing Codes l16 Bits
Transition Noise 1.5 LSBRMS
INL Integral Linearity Error (Note 6) l–12 ±4 12 LSB
DNL Differential Linearity Error l–0.99 ±0.4 0.99 LSB
BZE Bipolar Zero-Scale Error (Note 7) l–12 0 12 LSB
Bipolar Zero-Scale Error Drift 0.01 LSB/°C
FSE Bipolar Full-Scale Error VREFOUT1,2 = 4.096V (REFINT Grounded) (Note 7) l–90 ±10 90 LSB
Bipolar Full-Scale Error Drift VREFOUT1,2 = 4.096V (REFINT Grounded) 15 ppm/°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 500kHz, VREFOUT1,2 = 4.096V, Internal Reference l74 80 dB
fIN = 500kHz, VREFOUT1,2 = 5V, External Reference 80 dB
SNR Signal-to-Noise Ratio fIN = 500kHz, VREFOUT1,2 = 4.096V, Internal Reference l74 81 dB
fIN = 500kHz, VREFOUT1,2 = 5V, External Reference 81.7 dB
THD Total Harmonic Distortion fIN = 500kHz, VREFOUT1,2 = 4.096V, Internal Reference l–85 –80 dB
fIN = 500kHz, VREFOUT1,2 = 5V, External Reference –84 dB
SFDR Spurious Free Dynamic Range fIN = 500kHz, VREFOUT1,2 = 4.096V, Internal Reference l81 88 dB
fIN = 500kHz, VREFOUT1,2 = 5V, External Reference 88 dB
–3dB Input Linear Bandwidth 10 MHz
Aperture Delay 500 ps
Aperture Delay Matching 500 ps
Aperture Jitter 1 psRMS
Transient Response Full-Scale Step 3 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
The
l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS (Notes 4, 8).
INTERNAL REFERENCE CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFOUT1,2 Internal Reference Output Voltage 4.75V < VDD < 5.25V
3.13V < VDD < 3.47V
l
l
4.088
2.044
4.096
2.048
4.106
2.053
V
V
VREFOUT1,2 Temperature Coefficient (Note 14) l3 20 ppm/°C
REFOUT1,2 Output Impedance 0.25 Ω
VREFOUT1,2 Line Regulation VDD = 4.75V to 5.25V 0.3 mV/V
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
LTC2321-16
4
Rev. D
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DIGITAL INPUTS AND DIGITAL OUTPUTS
POWER REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l0.8 • OVDD V
VIL Low Level Input Voltage l0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l–10 10 μA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IO = -500µA lOVDD – 0.2 V
VOL Low Level Output Voltage IO = 500µA l0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 µA
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = OVDD 10 mA
VID LVDS Differential Input Voltage 100Ω Differential Termination OVDD = 2.5V l240 600 mV
VIS LVDS Common Mode Input Voltage 100Ω Differential Termination OVDD = 2.5V l1 1.45 V
VOD LVDS Differential Output Voltage 100Ω Differential Load, LVDS Mode
OVDD = 2.5V
l100 150 300 mV
VOS LVDS Common Mode Output Voltage 100Ω Differential Load, LVDS Mode
OVDD = 2.5V
l0.85 1.2 1.4 V
VOD_LP Low Power LVDS Differential Output
Voltage
100Ω Differential Load, LVDS Mode
OVDD = 2.5V
l75 100 250 mV
VOS_LP Low Power LVDS Common Mode
Output Voltage
100Ω Differential Load, LVDS Mode
OVDD = 2.5V
l0.9 1.2 1.4 V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 5V Operation
3.3V Operation
l
l
4.75
3.13
5.25
3.47
V
V
OVDD Supply Voltage l1.71 2.63 V
IVDD Supply Current 2Msps Sample Rate (IN+ = IN– = 0V) l11.8 15 mA
IOVDD Supply Current 2Msps Sample Rate (CL = 5pF) CMOS Mode
2Msps Sample Rate (RL = 100Ω) LVDS Mode
l
l
1.8
7.1
2
11
mA
mA
INAP Nap Mode Current Conversion Done (IVDD)l2.55 5 mA
ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD) CMOS Mode
Sleep Mode (IVDD + IOVDD) LVDS Mode
l
l
1
1
5
5
μA
μA
PD_3.3V Power Dissipation VDD = 3.3V 2Msps Sample Rate (IN+ = IN– = 0V) CMOS Mode
VDD = 3.3V 2Msps Sample Rate (IN+ = IN– = 0V) LVDS Mode
l
l
37
52
58
86
mW
mW
Nap Mode VDD = 3.3V Conversion Done (IVDD + IOVDD) CMOS Mode
VDD = 3.3V Conversion Done (IVDD + IOVDD) LVDS Mode
l
l
7.8
26
13
41
mW
mW
Sleep Mode VDD = 3.3V Sleep Mode (IVDD + IOVDD) CMOS Mode
VDD = 3.3V Sleep Mode (IVDD + IOVDD) LVDS Mode
l
l
5
5
16.5
16.5
μW
μW
PD_5V Power Dissipation VDD = 5V 2Msps Sample Rate (IN+ = IN– = 0V) CMOS Mode
VDD = 5V 2Msps Sample Rate (IN+ = IN– = 0V) LVDS Mode
l
l
62
77
80
102.5
mW
mW
Nap Mode VDD = 5V Conversion Done (IVDD + IOVDD) CMOS Mode
VDD = 5V Conversion Done (IVDD + IOVDD) LVDS Mode
l
l
13
31
25
40
mW
mW
Sleep Mode VDD = 5V Sleep Mode (IVDD + IOVDD) CMOS Mode
VDD = 5V Sleep Mode (IVDD + IOVDD) LVDS Mode
l
l
5
5
25
25
μW
μW
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
LTC2321-16
5
Rev. D
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground, or above VDD
or OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground, or above VDD or OVDD, without
latch-up.
Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2 = 4.096V, fSMPL = 2MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or
+FS un-trimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with REFIN = 4.096V.
Note 9: When REFOUT1,2 is overdriven, the internal reference buffer must
be turned off by setting REFINT = 0V.
Note 10: fSMPL = 2MHz, IREFBUF varies proportionally with sample rate.
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V and
OVDD = 2.5V.
Note 13: tSCK of 15.6ns maximum allows a shift clock frequency up to
64MHz for rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OVDD
logic levels. This input pin has a TTL style input that will draw a small
amount of current.
Figure1. Voltage Levels for Timing Specifications
0.8 • OVDD
0.2 • OVDD
50% 50%
232116 F01
0.2 • OVDD
0.8 • OVDD
0.2 • OVDD
0.8 • OVDD
tDELAY
tWIDTH
tDELAY
ADC TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l2 Msps
tCYC Time Between Conversions (Note 11) tCYC = tCNVH + tCONV + tREADOUT l500 1000000 ns
tCONV Conversion Time l220 ns
tCNVH CNV High Time l25 ns
tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns
tSCK SCK Period (Notes 12, 13) l15.6 ns
tSCKH SCK High Time l7 ns
tSCKL SCK Low Time l7 ns
tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l2.8 10 ns
tDCLKOUTSDOV SDO Data Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l2 ns
tHSDO SDO Data Remains Valid Delay from
CLKOUT↓
CL = 5pF (Note 11) l2 ns
tDCNVSDOV SDO Data Valid Delay from CNV↓CL = 5pF (Note 11) l2.5 3 ns
tDCNVSDOZ Bus Relinquish Time After CNV↑(Note 11) l3 ns
tWAKE REFOUT1,2 Wakeup Time CREFOUT1,2 = 10μF 10 ms
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
LTC2321-16
6
Rev. D
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TYPICAL PERFORMANCE CHARACTERISTICS
THD, Harmonics vs Input
Common Mode (1.2MHz)
SNR, SINAD vs Reference Voltage,
fIN = 500kHz
32k Point FFT, IMD, fS = 2Msps,
VIN+ = 100kHz, VIN– = 500kHz
32k Point FFT, fS = 2Msps,
fIN = 500kHz SNR, SINAD vs Input Frequency
THD, Harmonics
vs Input Frequency
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code DC Histogram
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2 =
4.096V, fSMPL = 2Msps, unless otherwise noted.
OUTPUT CODE
0
–8
–4
–6
INL ERROR (LSB)
–2
2
0
4
6
8
–24576 –8192
16384 32768–32768 –16384
8192 24576
232116 G01 OUTPUT CODE
0
–1.0
DNL ERROR (LSB)
0
–0.5
0.5
1.0
–24576 –8192
16384 32768–32768 –16384
8192 24576
232116 G02
CODE
COUNTS
8000
18000
20000
–4 –2 0
4000
14000
6000
16000
2000
0
12000
10000
–5 –3 26
–1 14 53
232116 G03
232116 G04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0 10.8
0.40.2 0.6
0
–20
–40
–60
–80
–100
–120
–140
SNR = 81.0dB
THD = –94.6dB
SINAD = 80.8dB
SFDR = 100.9dB
FREQUENCY (MHz)
0
80.0
80.5
SNR, SINAD (dBFS)
81.5
81.0
82.0
82.5
83.0
10.5 1.5 22.5
232116 G05
SINAD
SNR
FREQUENCY (MHz)
–110
–105
THD, HARMONICS (dBFS)
–100
–95
–90
–85
232116 G06
0 10.5 1.5 22.5
H2
H3
THD
INPUT COMMON MODE (V)
1.7
THD, HARMONICS LEVEL (dBFS)
–90
–85
–80
3.1
–95
–100
2.1 2.5
1.9 2.3 2.7 2.9 3.3
–105
–110
–75
232116 G07
H2
H3
THD
VREF (V)
0.5
SNR, SINAD (dBFS)
78
80
4
76
74
1.5 2.5
12 3 4.5
3.5 5
68
72
82
70
232116 G08
SINAD
SNR
232116 G09
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0 10.8
0.40.2 0.6
0
–20
–40
–60
–80
–100
–120
–140
F1 = 100kHz
F2 = 500kHz
IMD = 97dBc
LTC2321-16
7
Rev. D
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TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs Temperature Gain Error vs Temperature REFOUT1,2 Output vs Temperature
Reference Current vs Temperature,
VREF = 4.096V
Supply Current
vs Sample Rate
OVDD Current vs SCK Frequency,
CLOAD = 10pF
Crosstalk vs Input Frequency CMRR vs Input Frequency
Output Match with Simultaneous
Input Steps at CH1, CH2
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2 =
4.096V, fSMPL = 2Msps, unless otherwise noted.
FREQUENCY (MHz)
–104
–95
–98
–101
CMRR (dB)
–92
–89
–83
–86
–80
232116 G11
0 10.5 1.5 22.5
FREQUENCY (MHz)
–136
–134
CROSSTALK (dBc)
–132
–130
–128
–126
232116 G10
0 10.5 1.5 22.5
232116 G12
TIME (ns)
OUTPUT CODE (CH1, CH2)
0500400200
100 300
35000
30000
25000
20000
15000
10000
5000
0
–5000
CH1
CH2
TEMPERATURE (°C)
–50
LSB
0.50
1.00
1.50
125
0
–0.50
0 50
–25 25 75 100 150
–2.00
–2.50
–1.00
2.00
–1.50
232116 G13
CH1
CH2
TEMPERATURE (°C)
–40
GAIN ERROR (16-BIT LSB)
0.5
1.0
0
–0.5
0 50
–25 25 75 100 125
–1.0
–1.5
1.5
232116 G14
232116 G15
TEMPERATURE (°C)
REFOUT (ppm)
–50 150
500100
200
100
0
–100
–200
–300
–400
–500
2.048V
4.096V
TEMPERATURE (°C)
–40
REFERENCE CURRENT (mA)
0.345
100
0 40
–20 20 60 80 120
0.335
0.340
0.350
232116 G16
SAMPLE RATE (Msps)
8.0
SUPPLY CURRENT (mA)
11.5
12.0
10.5
11.0
9.5
10.0
8.5
9.0
232116 G17
0 10.5 1.5 2
SCK FREQUENCY (MHz)
0
2
OVDD CURRENT (mA)
4
6
8
232116 G18
0 20 40 6010 30 8050 70 100 11090
LTC2321-16
8
Rev. D
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PIN FUNCTIONS
VDD (Pins 1, 8): Power Supply. Bypass VDD to GND with
a 10µF ceramic and a 0.1µF ceramic close to the part. The
VDD pins should be shorted together and driven from the
same supply.
AIN2+, AIN2– (Pins 2, 3): Analog Differential Input Pins.
Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage.
These pins can be driven from VDD to GND.
GND (Pins 4, 5, 10, 29): Ground. These pins and exposed
pad (Pin 29) must be tied directly to a solid ground plane.
AIN1–, AIN1+ (Pins 6, 7): Analog Differential Input Pins.
Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage.
These pins can be driven from VDD to GND.
CNV (Pin 9): Conversion Start Input. A falling edge on
CNV puts the internal sample-and-hold into the hold mode
and starts a conversion cycle. CNV must be driven by a
low jitter clock as shown in the Typical Application circuit
on the back page. The CNV pin is unaffected by the CMOS/
LVDS pin.
REFRTN1 (Pin 11): Reference Buffer 1 Output Return.
Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1
pin to the ground plane.
REFOUT1 (Pin 12): Reference Buffer 1 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to REFRTN1 and should be decoupled closely to
the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor
and a 10μF (X5R, 0805 size) ceramic capacitor in paral-
lel. The internal buffer driving this pin may be disabled
by grounding the REFINT pin. If the buffer is disabled,
an external reference may drive this pin in the range of
1.25V to 5V.
VBYP1 (Pin 13): Bypass this internally supplied pin to
ground with a 1µF ceramic capacitor. The nominal output
voltage on this pin is 1.6V.
OVDD (Pin 14): I/O Interface Digital Power. The range of
OVDD is 1.71V to 2.5V. This supply is nominally set to
the same supply as the host interface (CMOS: 1.8V or
2.5V, LVDS: 2.5V). Bypass OVDD to OGND with a 0.1μF
capacitor.
SDO1+, SDO1– (Pins 15, 16): Channel 1 Serial Data
Output. The conversion result is shifted MSB first on each
falling edge of SCK. In CMOS mode, the result is output
on SDO1+. The logic level is determined by OVDD. Do
not connect SDO1–. In LVDS mode, the result is output
differentially on SDO1+ and SDO1–. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (FPGA).
CLKOUT+, CLKOUT– (Pins 17, 18): Serial Data Clock
Output. CLKOUT provides a skew-matched clock to latch
the SDO output at the receiver. In CMOS mode, the skew-
matched clock is output on CLKOUT+. The logic level is
determined by OVDD. Do not connect CLKOUT–. For low
throughput applications using SCK to latch the SDO out-
put, CLKOUT+ can be disabled by tying CLKOUT– to OVDD.
In LVDS mode, the skew-matched clock is output differ-
entially on CLKOUT+ and CLKOUT–. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (FPGA).
SDO2+, SDO2– (Pins 19, 20): Channel 2 Serial Data
Output. The conversion result is shifted MSB first on each
falling edge of SCK. In CMOS mode, the result is output
on SDO2+. The logic level is determined by OVDD. Do
not connect SDO2–. In LVDS mode, the result is output
differentially on SDO2+ and SDO2–. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (FPGA).
SCK+, SCK– (Pins 21, 22): Serial Data Clock Input. The
falling edge of this clock shifts the conversion result MSB
first onto the SDO pins. In CMOS mode, drive SCK+ with
a single-ended clock. The logic level is determined by
OVDD. Do not connect SCK–. In LVDS mode, drive SCK+
and SCK– with a differential clock. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (ADC).
OGND (Pin 23): I/O Ground. This ground must be tied to
the ground plane at a single point. OVDD is bypassed to
this pin.
LTC2321-16
9
Rev. D
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PIN FUNCTIONS
VBYP2 (Pin 24): Bypass this internally supplied pin to
ground with a 1µF ceramic capacitor. The nominal output
voltage on this pin is 1.6V
CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin
to enable CMOS mode, tie to OVDD to enable LVDS mode.
Float this pin to enable low power LVDS mode.
REFOUT2 (Pin 26): Reference Buffer 2 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to REFRTN2 and should be decoupled closely to
the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor
and a 10μF (X5R, 0805 size) ceramic capacitor in paral-
lel. The internal buffer driving this pin may be disabled
by grounding the REFINT pin. If the buffer is disabled,
an external reference may drive this pin in the range of
1.25V to VDD.
REFRTN2 (Pin 27): Reference Buffer 2 Output Return.
Bypass REFRTN2 to REFOUT2. Do not tie the REFRTN2
pin to the ground plane.
REFINT (Pin 28): Reference Buffer Output Enable. Tie to
VDD when using the internal reference. Tie to ground to
disable the internal REFOUT1 and REFOUT2 buffers for
use with external voltage references. This pin has a 500k
internal pull-up to VDD.
Exposed Pad (Pin 29): Ground. Solder this pad to ground.
LTC2321-16
10
Rev. D
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FUNCTIONAL BLOCK DIAGRAM
TIMING DIAGRAM
B15 B14 B12 B11 B3 B2 B1 B0B13
1 2 4 5 6 13 14 15 163
CNV
SCK
CLKOUT
SDO
ACQUISITION CONVERSION READOUT
SERIAL DATA BITS B[15:0] CORRESPOND TO CURRENT CONVERSION
HI-ZHI-Z
232116 TD
1 2 4 5 6 13 14 15 163
15
13
16
16-BIT
SAR ADC
LVDS/CMOS
TRI-STATE
SERIAL OUTPUT
OUTPUT
CLOCK DRIVER
LVDS/CMOS
RECEIVERS
SDO1+
SDO1–
14
GND
4, 5, 10, 29
OVDD
7
6
AIN1+
12 REFOUT1
28 REFINT
26 REFOUT2
AIN1–
17
18
CLKOUT+
CLKOUT–
21
22
SCK+
SCK–
TIMING CONTROL
LOGIC
232116 BD
–
+
S/H
LDO
LDO
19
20
16-BIT
SAR ADC
LVDS/CMOS
TRI-STATE
SERIAL OUTPUT
SDO2+
SDO2–
24
VBYP2
2
3
AIN2+
9CNV
AIN2–
VDD
1,8
VDD
1,8 VBYP1
–
+
S/H
G
G
1.2V REF
LTC2321-16
11
Rev. D
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APPLICATIONS INFORMATION
OVERVIEW
The LTC2321-16 is a low noise, high speed 16-bit succes-
sive approximation register (SAR) ADC with differential
inputs and a wide input common mode range. Operating
from a single 3.3V or 5V supply, the LTC2321-16 has an
8VP-P differential input range, making it ideal for applica-
tions which require a wide dynamic range. The LTC2321-
16 achieves ±4LSB INL typical, no missing codes at 16
bits and 81dB SNR.
The LTC2321-16 has an onboard reference buffer and low
drift (20ppm/°C max) 4.096V temperature-compensated
reference. The LTC2321-16 also has a high speed SPI-
compatible serial interface that supports CMOS or LVDS.
The fast 2Msps per channel throughput with no cycle
latency makes the LTC2321-16 ideally suited for a wide
variety of high speed applications. The LTC2321-16 dis-
sipates only 31mW per channel. Nap and sleep modes
are also provided to reduce the power consumption of
the LTC2321-16 during inactive periods for further power
savings.
CONVERTER OPERATION
The LTC2321-16 operates in two phases. During the
acquisition phase, the sample capacitor is connected to
the analog input pins AIN+ and AIN– to sample the dif-
ferential analog input voltage, as shown in Figure 3. A
falling edge on the CNV pin initiates a conversion. During
the conversion phase, the 16-bit CDAC is sequenced
through a successive approximation algorithm, effectively
comparing the sampled input with binary-weighted frac-
tions of the reference voltage (e.g., VREFOUT/2, VREFOUT/4
… VREFOUT/32768) using the differential comparator. At
the end of conversion, a CDAC output approximates the
sampled analog input. The ADC control logic then pre-
pares the 16-bit digital output code for serial transfer .
The data is clocked out on each falling edge of the SCK+
input clock.
TRANSFER FUNCTION
The LTC2321-16 digitizes the full-scale voltage of 2 ×
REFOUT into 216 levels, resulting in an LSB size of
125µV with REFBUF = 4.096V. The ideal transfer function
is shown in Figure2. The output data is in 2’s comple-
ment format.
Analog Input
The differential inputs of the LTC2321-16 provide great
flexibility to convert a wide variety of analog signals with
no configuration required. The LTC2321-16 digitizes the
difference voltage between the AIN+ and AIN– pins while
supporting a wide common mode input range. The analog
input signals can have an arbitrary relationship to each
other, provided that they remain between VDD and GND.
The LTC2321-16 can also digitize more limited classes
of analog input signals such as pseudo-differential uni-
polar/bipolar and fully differential with no configuration
required.
Figure2. LTC2321-16 Transfer Function
Figure3. The Equivalent Circuit for the Differential
Analog Input of the LTC2321-16
RON
15Ω
RON
15Ω
BIAS
VOLTAGE
232116 F03
CIN
10pF
VDD
CIN
10pF
VDD
AIN1–
AIN1+
INPUT VOLTAGE (V)
–FSR/2
OUTPUT CODE (TWO’S COMPLEMENT)
232116 F02
011...111
011...110
111...111
100...000
100...001
000...000
000...001
–1
LSB
FSR = +FS – –FS
1LSB = FSR/65535
0 1
LSB
+FSR/2
–1
LTC2321-16
12
Rev. D
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APPLICATIONS INFORMATION
The analog inputs of the LTC2321-16 can be modeled
by the equivalent circuit shown in Figure3. The back-
to-back diodes at the inputs form clamps that provide
ESD protection. In the acquisition phase, 10pF (C
IN
) from
the sampling capacitor in series with approximately 15Ω
(RON) from the on-resistance of the sampling switch is
connected to the input. Any unwanted signal that is com-
mon to both inputs will be reduced by the common mode
rejection of the ADC sampler. The inputs of the ADC core
draw a small current spike while charging the CIN capaci-
tors during acquisition.
Single-Ended Signals
Single-ended signals can be directly digitized by the
LTC2321-16. These signals should be sensed pseudo-
differentially for improved common mode rejection. By
connecting the reference signal (e.g., ground sense) of
the main analog signal to the other AIN pin, any noise or
disturbance common to the two signals will be rejected
by the high CMRR of the ADC. The LTC2321-16 flexibility
handles both pseudo-differential unipolar and bipolar sig-
nals, with no configuration required. The wide common
mode input range relaxes the accuracy requirements of
any signal conditioning circuits prior to the analog inputs.
Pseudo-Differential Bipolar Input Range
The pseudo-differential bipolar configuration represents
driving one of the analog inputs at a fixed voltage, typi-
cally VREF/2, and applying a signal to the other AIN pin. In
this case the analog input swings symmetrically around
the fixed input yielding bipolar two’s complement output
codes with an ADC span of half of full-scale. This con-
figuration is illustrated in Figure4, and the corresponding
transfer function in Figure5. The fixed analog input pin
Figure4. Pseudo-Differential Bipolar Application Circuit
Figure5. Pseudo-Differential Bipolar Transfer Function
25Ω
25Ω
220pF
VREF
0V
VREF
0V
VREF /2
VREF /2
VREF
10k
10k
ONLY CHANNEL 1 SHOWN FOR CLARITY
+
–
+
–
LTC2321-16LT1819
232116 F04
SDO1
VBYP1
REFOUT1
CLKOUT
AIN1–
AIN1+
SCK
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
1µF
10µF
1µF
232116 F05
–VREF
–16384
16383
–32768
32767
VREF
DOTTED REGIONS AVAILABLE
BUT UNUSED
AIN
(AIN+ – AIN–)
ADC CODE
(2’s COMPLEMENT)
–VREF/2 VREF /20
LTC2321-16
13
Rev. D
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APPLICATIONS INFORMATION
need not be set at VREF/2, but at some point within the
VDD rails allowing the alternate input to swing symmetri-
cally around this voltage. If the input signal (AIN+ – AIN–)
swings beyond ±REFOUT/2, valid codes will be generated
by the ADC and must be clamped by the user, if necessary.
Pseudo-Differential Unipolar Input Range
The pseudo-differential unipolar configuration represents
driving one of the analog inputs at ground and applying a
signal to the other AIN pin. In this case, the analog input
swings between ground and VREF yielding unipolar two’s
complement output codes with an ADC span of half of full-
scale. This configuration is illustrated in Figure6, and the
corresponding transfer function in Figure7. If the input
signal (AIN+ – AIN–) swings negative, valid codes will be
generated by the ADC and must be clamped by the user,
if necessary.
Figure6. Pseudo-Differential Unipolar Application Circuit
Figure7. Pseudo-Differential Unipolar Transfer Function
232116 F07
–VREF
–16384
16383
–32768
32767
VREF
DOTTED REGIONS AVAILABLE
BUT UNUSED
AIN
(AIN+ – AIN–)
ADC CODE
(2’s COMPLEMENT)
–VREF/2 VREF /20
25Ω
25Ω
220pF
VREF
0V
VREF
0V
+
–
LTC2321-16
LT1818
232116 F06
SDO1
VBYP1
REFOUT1
CLKOUT
AIN1–
AIN1+
SCK
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
1µF
10µF
LTC2321-16
14
Rev. D
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APPLICATIONS INFORMATION
Single-Ended-to-Differential Conversion
While single-ended signals can be directly digitized as
previously discussed, single-ended to differential conver-
sion circuits may also be used when higher dynamic range
is desired. By producing a differential signal at the inputs
of the LTC2321-16, the signal swing presented to the ADC
is maximized, thus increasing the achievable SNR.
The LT
®
1819 high speed dual operational amplifier is
recommended for performing single-ended-to-differen-
tial conversions, as shown in Figure8. In this case, the
first amplifier is configured as a unity-gain buffer and the
single-ended input signal directly drives the high imped-
ance input of this amplifier.
Fully-Differential Inputs
To achieve the full distortion performance of the LTC2321-16,
a low distortion fully-differential signal source driven
through the LT1819 configured as two unity-gain buf-
fers, as shown in Figure9, can be used. This circuit
achieves the full data sheet THD specification of –85dB
at input frequencies of 500kHz and less. Data sheet typical
performance curves taken at higher frequencies used a
harmonic rejection filter between the ADC and the signal
source to eliminate the op amp as the dominant source
of distortion.
The fully-differential configuration yields an analog input
span (AIN+ – AIN–) of ±REFOUT. In this configuration, the
input signal is driven on each AIN pin, typically at equal
spans but opposite polarity. This yields a high common
mode rejection on the input signals. The common mode
voltage of the analog input can be anywhere within the
VDD input range, but will be limited by the peak swing of
the full-range input signal. For example, if the internal ref-
erence is used with VDD = 5VDC, the full-range input span
will be ±4.096V. Half of the input span is typically driven
on each AIN pin, yielding a signal span for each AIN pin of
4.096VP-P. This leaves ~0.9V of common mode variation
tolerance. When using external references, it is possible
to increase common mode tolerance by compressing the
ADC full-range codes into a tighter range. For example,
using an external 2.048V reference with VDD = 5V the
total span would be ±2.048V and each AIN span would
be limited to 2.048VP-P allowing a common mode range
of ~3V. Compressing the input span would incur a SNR
penalty of approximately 2.5dB. Input span compression
Figure8. Single-Ended to Differential Driver Figure9. LT1819 Buffering a Fully-Differential Signal Source
VREF
0V
VREF
0V
VREF
0V
VREF /2
+
–
+
–
200Ω
200Ω
LT1819
232116 F08
VREF
0V
VREF
0V
VREF
0V
VREF
0V
+
–
+
–
LT1819
232116 F09
LTC2321-16
15
Rev. D
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APPLICATIONS INFORMATION
may be useful if single-supply analog input drivers are
used which cannot swing rail-to-rail. The fully-differential
configuration is illustrated in Figure10, with the corre-
sponding transfer function illustrated in Figure11.
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high imped-
ance inputs of the LTC2321-16 without gain error. A high
impedance source should be buffered to minimize set-
tling time during acquisition and to optimize the distortion
performance of the ADC. Minimizing settling time is
important even for DC inputs, because the ADC inputs
draw a current spike when during acquisition.
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2321-16. The amplifier
provides low output impedance to minimize gain error
and allow for fast settling of the analog signal during the
acquisition phase. It also provides isolation between the
signal source and the ADC inputs, which draw a small
current spike during acquisition.
25Ω
25Ω
220pF
VREF
0V
VREF
0V
VREF
0V
VREF
0V
ONLY CHANNEL 1 SHOWN FOR CLARITY
+
–
+
–
LTC2321-16LT1819
232116 F10
SDO1
VBYP1
REFOUT1
CLKOUT
AIN1–
AIN1+
SCK
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
1µF
10µF
232116 F11
–VREF
–16384
16383
–32768
32767
VREF
AIN
(AINn+ – AINn–)
ADC CODE
(2’s COMPLEMENT)
–VREF/2 VREF /20
Figure10. Fully-Differential Application Circuit
Figure11. Fully-Differential Transfer Function
LTC2321-16
16
Rev. D
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APPLICATIONS INFORMATION
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC
noise and distortion. Noisy input signals should be filtered
prior to the buffer amplifier input with a low bandwidth
filter to minimize noise. The simple 1-pole RC lowpass fil-
ter shown in Figure12 is sufficient for many applications.
The input resistor divider network, sampling switch on-
resistance (RON) and the sample capacitor (CIN) form a
second lowpass filter that limits the input bandwidth to
the ADC core to 110MHz. A buffer amplifier with a low
noise density must be selected to minimize the degrada-
tion of the SNR over this bandwidth.
High quality capacitors and resistors should be used in
the RC filters since these components can add distor-
tion. NPO and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
ADC REFERENCE
Internal Reference
The LTC2321-16 has an on-chip, low noise, low drift
(20ppm/°C max), temperature compensated bandgap
reference. It is internally buffered and is available at
REFOUT1,2 (Pins 12, 26). The reference buffer gains
the internal reference voltage to 4.096V for supply volt-
ages VDD = 5V and to 2.048V for VDD = 3.3V. Bypass
REFOUT1,2 to REFRTN1,2 with the parallel combination
of a 0.1µF (X7R, 0402 size) capacitor and a 10μF (X5R,
0805 size) ceramic capacitor to compensate the reference
buffer and minimize noise. The 0.1µF capacitor should
be as close as possible to the LTC2321-16 package to
minimize wiring inductance. Tie the REFINT pin to VDD to
enable the internal reference buffer.
Table 1. REFOUT1,2 Sources and Ranges vs VDD
VDD
REFINT
PIN REFOUT1,2 PIN
DIFFERENTIAL
SPAN
5V 5V Internal 4.096V ±4.096V
5V 0V External (1.25V to 5V) ±1.25V to ±5V
3.3V 3.3V Internal 2.048V ±2.048V
3.3V 0V External (1.25V to 3.3V) ±1.25V to ±3.3V
50Ω
SINGLE-ENDED
INPUT SIGNAL
232116 F12
BW = 1MHz
3.3nF SINGLE-ENDED
TO DIFFERENTIAL
DRIVER
IN+
IN–
LTC2321
Figure12. Input Signal Chain
LTC2321-16
17
Rev. D
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APPLICATIONS INFORMATION
External Reference
The internal reference buffer can also be overdriven from
1.25V to 5V with an external reference at REFOUT1,2
as shown in Figure13 (b and c). To do so, REFINT must
be grounded to disable the reference buffer. A 55k inter-
nal resistance loads the REFOUT1,2 pins when the ref-
erence buffer is disabled. To maximize the input signal
swing and corresponding SNR, the LTC6655-5 is recom-
mended when overdriving REFOUT1,2. The LTC6655-5
offers the same small size, accuracy, drift and extended
temperature range as the LTC6655-4.096. By using a 5V
reference, a higher SNR can be achieved. We recommend
bypassing the LTC6655-5 with a parallel combination of
a 0.1µF (X7R, 0402 size) ceramic capacitor and a 10μF
ceramic capacitor (X5R, 0805 size) close to each of the
REFOUT1,2 and REFRTN1,2 pins.
Internal Reference Buffer Transient Response
The REFOUT1,2 pins of the LTC2321-16 draw charge
(QCONV) from the external bypass capacitors during each
conversion cycle. If the internal reference buffer is over-
driven, the external reference must provide all of this charge
with a DC current equivalent to IREF = QCONV/tCYC.
Thus, the DC current draw of REFOUT1,2 depends
on the sampling rate and output code. In applications
where a burst of samples is taken after idling for long
VDD
LTC2321-16
GND
232116 F13a
3.3V TO 5V
REFOUT2
REFOUT1
REFRTN1
REFRTN2
REFINT
0.1µF
10µF
0.1µF
10µF
VIN
SHDN
VOUT_F
VOUT_S
LTC6655-4.096
LTC2321-16
GND
232116 F13b
5V TO 13.2V
REFOUT2
REFOUT1
REFRTN1
REFRTN2
REFINT
0.1µF
0.1µF
10µF
0.1µF
10µF
VIN
SHDN
VOUT_F
VOUT_S
LTC6655-4.096
VIN
SHDN
VOUT_F
VOUT_S
LTC6655-2.048
LTC2321-16
GND
232116 F13c
5V TO 13.2V
REFOUT2
REFOUT1
REFRTN1
REFRTN2
REFINT
0.1µF
0.1µF
0.1µF
10µF
0.1µF
10µF
(13a) LTC2321-16 Internal Reference Circuit (13b) LTC2321-16 with a Shared External Reference Circuit
(13c) LTC2321-16 with Different External Reference Voltages
Figure13.
LTC2321-16
18
Rev. D
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APPLICATIONS INFORMATION
periods, as shown in Figure14, IREFBUF quickly goes
from approximately ~75µA to a maximum of 500µA for
REFOUT1,2 = 5V at 2Msps. This step in DC current draw
triggers a transient response in the external reference that
must be considered since any deviation in the voltage at
REFOUT1,2 will affect the accuracy of the output code. If
an external reference is used to overdrive REFOUT1,2 the
fast settling LTC6655 reference is recommended.
DYNAMIC PERFORMANCE
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2321-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is bandlimited
to frequencies from above DC and below half the sampling
frequency. Figure16 shows that the LTC2321-16 achieves
a typical SINAD of 80dB at a 2MHz sampling rate with a
500kHz input.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure16 shows
that the LTC2321-16 achieves a typical SNR of 81dB at a
2MHz sampling rate with a 500kHz input.
CNV
232116 F14
IDLE
PERIOD
Figure14. CNV Waveform Showing Burst Sampling
Figure15. Transient Response of the LTC2321-16
Figure16. 32k Point FFT of the LTC2321-16
232116 F15
TIME (ns)
OUTPUT CODE (CH1, CH2)
0
500
400200
100 300
35000
30000
25000
20000
15000
10000
5000
0
–5000
CH1
CH2
232116 F16
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0 10.8
0.40.2 0.6
0
–20
–40
–60
–80
–100
–120
–140
SNR = 81.0dB
THD = –94.6dB
SINAD = 80.8dB
SFDR = 100.9dB
LTC2321-16
19
Rev. D
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APPLICATIONS INFORMATION
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the
RMS sum of all harmonics of the input signal to the
fundamental itself. The out-of-band harmonics alias into
the frequency band between DC and half the sampling
frequency (fSMPL/2). THD is expressed as:
THD=20log V22+V32+V42+… + VN
2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2321-16 requires two power supplies: the 5V
power supply (V
DD
), and the digital input/output interface
power supply (OVDD). The flexible OVDD supply allows
the LTC2321-16 to communicate with any digital logic
operating between 1.8V and 2.5V. When using LVDS I/O,
the OVDD supply must be set to 2.5V.
Power Supply Sequencing
The LTC2321-16 does not have any specific power sup-
ply sequencing requirements. Care should be taken to
adhere to the maximum voltage relationships described
in the Absolute Maximum Ratings section. The LTC2321-
16 has a power-on-reset (POR) circuit that will reset the
LTC2321-16 at initial power-up or whenever the power
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 10ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
Figure17. Power Supply Current of the LTC2321-16 Versus Sampling Rate
SAMPLE RATE (Msps)
8.0
SUPPLY CURRENT (mA)
11.5
12.0
10.5
11.0
9.5
10.0
8.5
9.0
232116 F17
0 10.5 1.5
2
LTC2321-16
20
Rev. D
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APPLICATIONS INFORMATION
TIMING AND CONTROL
CNV Timing
A rising edge on CNV initiates the acquisition phase and
puts the internal sample-and-hold into the sample mode.
A falling edge on CNV puts the internal sample-and-hold
into the hold mode and starts a conversion cycle. The
CNV pulse must be at least 25ns wide for proper opera-
tion. CNV must be driven by a fast low jitter signal with a
fall time from OVDD to below 100mV of less than 1ns. To
achieve this fast falling edge, the distance from the CNV
source to the CNV pin should be minimized. The trace
for this pulse should be kept as narrow as possible and
routed away from adjacent traces or planes to minimize
capacitance. The drive strength of the gate driving the
CNV line must be sufficient to yield a fast falling edge at
the ADC pin to below 100mV. We recommend the Typical
Application circuit on the back page, which uses a high
speed flip-flop to generate the CNV pulse to the ADC,
eliminating the effect of jitter from the FPGA. If jitter from
the FPGA is not a concern, the flip-flop can be eliminated
and replaced with an inverter such as the NC7SZ04P5X.
SCK Serial Data Clock Input
The falling edge of this clock shifts the conversion result
MSB first onto the SDO pins. A 64MHz external clock must
be applied at the SCK pin to achieve 2Msps throughput.
CLKOUT Serial Data Clock Output
The CLKOUT output provides a skew-matched clock to
latch the SDO output at the receiver. The timing skew
of the CLKOUT and SDO outputs are matched. For high
throughput applications, using CLKOUT instead of SCK
to capture the SDO output eases timing requirements at
the receiver. For low throughput applications, CLKOUT+
can be disabled by tying CLKOUT– to OVDD.
Nap/Sleep Modes
Nap mode is a method to save power without sacrificing
power-up delays for subsequent conversions. Sleep mode
has substantial power savings, but a power-up delay is
incurred to allow the reference and power systems to
become valid. To enter nap mode on the LTC2321-16,
the SCK signal must be held high or low and a series
of two CNV pulses must be applied. This is the case for
both CMOS and LVDS modes. The second rising edge of
CNV initiates the nap state. The nap state will persist until
either a single rising edge of SCK is applied, or further
CNV pulses are applied. The SCK rising edge will put the
LTC2321-16 back into the operational (full-power) state.
When in nap mode, two additional pulses will put the
LTC2321-16 in sleep mode. When configured for CMOS
I/O operation, a single rising edge of SCK can return the
LTC2321-16 into operational mode. A 10ms delay is nec-
essary after exiting sleep mode to allow the reference buf-
fer to recharge the external filter capacitor. In LVDS mode,
exit sleep mode by supplying a fifth CNV pulse. The fifth
pulse will return the LTC2321-16 to operational mode,
and further SCK pulses will keep the part from re-entering
nap and sleep modes. The fifth SCK pulse also works in
CMOS mode as a method to exit sleep. In the absence of
SCK pulses, repetitive CNV pulses will cycle the LTC2321-
16 between operational, nap and sleep modes indefinitely.
Refer to the timing diagrams in Figure18, Figure19,
Figure20and Figure21 for more detailed timing infor-
mation about sleep and nap modes.
FULL POWER MODE
1 2CNV
SCK HOLD STATIC HIGH OR LOW
NAP MODE
SDO1
SDO2
WAKE ON 1ST SCK EDGE
Z Z 232116 F18
Figure18. CMOS and LVDS Mode NAP and WAKE Using SCK
LTC2321-16
21
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
FULL POWER MODE
1234
4.096V4.096V
REFOUT
RECOVERY
REFOUT1
REFOUT2
CNV
SCK HOLD STATIC HIGH OR LOW
NAP MODE SLEEP MODE
SDO1
SDO2
WAKE ON 1ST SCK EDGE
ZZZZ 232116 F19
tWAKE
Figure19. CMOS Mode SLEEP and WAKE Using SCK
1234 5
4.096V4.096V
REFOUT
RECOVERY
REFOUT1
REFOUT2
CNV
SCK HOLD STATIC HIGH OR LOW
NAP MODE SLEEP MODE FULL POWER MODE
SDO1
SDO2
WAKE ON 5TH
CSB EDGE
ZZZZ Z 232116 F20
tWAKE
tREADOUT
tCONV
tCNVH
tDSCKHCNVH
tSCK
tSCKL tSCKH
B15 B14 B12 B11 B3 B2 B1 B0B13
1 2 4 5 6 13 14 15 163
CNV
SCK
CLKOUT
SDO
HI-ZHI-Z
232116 TD
1 2 4 5 6 13 14 15 163
tDCLKOUTSDOV
SERIAL DATA BITS B[15:0] CORRESPOND TO CURRENT CONVERSION
tDSCKCLKOUT IS THE DELAY FROM SCK↓ TO CLKOUT↓
tCYC
tDCNVSDOV
tDCNVSDOZ
tHSDO
Figure20. LVDS and CMOS Mode SLEEP and WAKE Using CNV
Figure21. LTC2321-16 Timing Diagram
LTC2321-16
22
Rev. D
For more information www.analog.com
2.5V
2.5V
OVDD
LTC2321-16 FPGA OR DSP
232116 F22
SDO2+
SDO2–
SCK+
SCK–
CLKOUT+
CLKOUT–
SDO1+
SDO1–
CNV
CMOS/LVDS
+
–
100Ω
+
–
100Ω
+
–
100Ω
+
–
100Ω
APPLICATIONS INFORMATION
Figure22. LTC2321 Using the LVDS Interface
DIGITAL INTERFACE
The LTC2321-16 features a serial digital interface that
is simple and straight forward to use. The flexible OVDD
supply allows the LTC2321-16 to communicate with any
digital logic operating between 1.8V and 2.5V. A 64MHz
external clock must be applied at the SCK pin to achieve
2Msps throughput.
In addition to a standard CMOS SPI interface, the
LTC2321-16 provides an optional LVDS SPI interface to
support low noise digital design. The CMOS/LVDS pin is
used to select the digital interface mode.
The falling edge of SCK outputs the conversion result MSB
first on the SDO pins. CLKOUT provides a skew-matched
clock to latch the SDO output at the receiver. The timing
skew of the CLKOUT and SDO outputs are matched. For
high throughput applications, using CLKOUT instead of
SCK to capture the SDO output eases timing requirements
at the receiver.
In CMOS mode, use the SDO1
+
, SDO2
+
and CLKOUT
+
pins as outputs. Use the SCK+ pin as an input. Do not
connect the SDO1–, SDO2–, SCK– and CLKOUT– pins,
as they each have internal pull-down circuitry to OGND.
In LVDS mode, use the SDO1
+
/SDO1
–
, SDO2
+
/SDO2
–
and
CLKOUT
+
/CLKOUT
–
pins as differential outputs. These
pins must be differentially terminated by an external 100Ω
resistor at the receiver (FPGA). The SCK+/SCK– pins are
differential inputs and must be terminated differentially by
an external 100Ω resistor at the receiver (ADC).
BOARD LAYOUT
To obtain the best performance from the LTC2321-16,
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals adjacent to analog signals or underneath
the ADC.
Recommended Layout
The following is an example of a recommended PCB lay-
out. A single solid ground plane is used. Bypass capaci-
tors to the supplies are placed as close as possible to the
supply pins. Low impedance common returns for these
bypass capacitors are essential to the low noise opera-
tion of the ADC. The analog input traces are screened by
ground. For more details and information, refer to the
DC1996, the evaluation kit for the LTC2321-16.
LTC2321-16
24
Rev. D
For more information www.analog.com
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
4.00 ±0.10
(2 SIDES)
2.50 REF
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0816 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
3.65 ±0.10
3.65 ±0.05
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
LTC2321-16
25
Rev. D
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/14 Updated Timing Characteristics and Figure 21 5, 21
B 05/17 Changed the CNV pin description in the Pin Functions section, and the CNV Timing section in the Applications
Information section.
Changed Fairchild components on the Typical Application.
8, 20
26
C 09/17 Changed CNV minimum pulse width to 25ns. 20
D 1/19 Added maximum 10ns to tDSCKCLKOUT 5
LTC2321-16
26
Rev. D
For more information www.analog.com
ANALOG DEVICES, INC. 2014–2019
1/19
www.analog.com
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–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply
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LT1806 325MHz, Single, Rail-to-Rail Input and Output, Low
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–80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,
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NC7SZ04P5X (× 3)
50Ω
NC7SZ04P5X
CONV ENABLE
MASTER_CLOCK
CONV
1k
1k
LTC2321-16
232116 TA02
SDO1
SCK
GND
CLR
NL17SZ74USG CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
PRE
CLKOUT
CNV
CMOS/LVDS
VCC
VCC
Q
D
SDO2
0.1µF
10Ω
10Ω
10Ω
