PCI 9080 Data Book
Version 1.06
January 2000
Website: http://www.plxtech.com
Email: apps@plxtech.com
Phone: 408 774-9060
800 759-3735
Fax: 408 774-216 9
© 2000 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have
minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and names are
property of their respective owners.
Order Number: 9080-SIL-DB-P1-1.06
Printed in the USA, January 2000
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved v
CONTENTS
FIGURES XI
TABLES XIII
TIMING DIAGRAMS ..........................................................................................................................................................XVII
PREFACE XXI
REVISION HISTOR Y ........................................................................................................................................................XXIII
FEATURES 1
1. GENERAL DESCRIPTION..............................................................................................................................................3
1.1 COMPANY AND PRODUCT BACKGROUND ......................................................................................................................3
1.2 PCI 9080 APPLICATIONS ............................................................................................................................................3
1.2.1 PCI Adapter Cards.............................................................................................................................................3
1.2.2 Emb edd ed Sy stems ...........................................................................................................................................3
1.3 MAJOR FEATURES.......................................................................................................................................................3
1.4 COMPATIBILITY WITH PCI 9060, PCI 9060ES, AND PCI 9060SD.................................................................................4
1.4.1 Pin Compatibility.................................................................................................................................................4
1.4.2 Register Compatibility ........................................................................................................................................4
1.5 COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080.....................................................................5
2. BUS OPERATION ...........................................................................................................................................................7
2.1 PCI BUS CYCLES........................................................................................................................................................7
2.1.1 PCI Target Command Codes.............................................................................................................................7
2.1.2 PCI Master Command Codes ............................................................................................................................7
2.1.2.1 DMA Master Command Codes.......................................................................................................................................7
2.1.2.2 Direct Local-to-PCI Comm and Codes.............................................................................................................................7
2.1.3 PCI Arbitration....................................................................................................................................................7
2.2 LOCAL BUS CYCLES....................................................................................................................................................8
2.2.1 Loc al Bus Arbitration..........................................................................................................................................8
2.2.2 Local Bus Direct Master.....................................................................................................................................8
2.2.3 Local Bus Direct Slave.......................................................................................................................................8
2.2.3.1 Ready/Wait State Control................................................................................................................................................8
2.2.3.1.1 Wait State—Local Bus..............................................................................................................................................9
2.2.3.1.2 Wait State—PCI Bus.................................................................................................................................................9
2.2.3.2 Burst Mode and Continuous Burst Mode (Bterm “Burst Terminate” Mode).....................................................................9
2.2.3.2.1 Burst Mode................................................................................................................................................................9
2.2.3.2.2 Continuous Burst Mode (Bterm “Burst Terminate” Mode).......................................................................................10
2.2.3.2.3 Partial Lword Accesses...........................................................................................................................................10
Contents
PCI 9080 Data Book v1.06
vi PLX T e c hn ology, Inc. All r ights r e s e rved
2.2.3.3 Recovery States............................................................................................................................................................10
2.2.3.4 Local Bus Read Accesses ............................................................................................................................................10
2.2.3.5 Local Bus Write Accesses.............................................................................................................................................10
2.2.3.6 Direct Slave Write Accesses—8- and 16-Bit Buses......................................................................................................10
2.2.3.7 Local Bus Data Parity....................................................................................................................................................10
2.2.3.8 Local Bus Big/Little Endian ...........................................................................................................................................11
2.2.3.8.1 32
-
Bit
Local Bus—Big Endian Mode.......................................................................................................................11
2.2.3.8.2 16-Bit Local Bus—Big Endian Mode.......................................................................................................................11
2.2.3.8.3 8-Bit Local Bus—Big Endian Mode.........................................................................................................................12
3. FUNCTIONAL DESCRIPTION ......................................................................................................................................13
3.1 RESET......................................................................................................................................................................13
3.1.1 PCI Bus Input RST#.........................................................................................................................................13
3.1.2 Software Reset LRESETo#..............................................................................................................................13
3.1.3 Local Bus Input LRESETi#...............................................................................................................................13
3.1.4 Loc al Bus Output LRESETo#...........................................................................................................................13
3.1.5 Software Reset.................................................................................................................................................13
3.2 PCI 9080 INITIALIZATION...........................................................................................................................................13
3.2.1 Ser ial EE PRO M Initial izati on............................................................................................................................14
3.2.2 Loc al Ini tia liz a tio n...................................................................................................... .......................................14
3.3 SERIAL EEPROM.....................................................................................................................................................14
3.3.1 Short Serial EEPROM Load.............................................................................................................................15
3.3.2 Long Serial EEPROM Load..............................................................................................................................15
3.3.3 Ex tra Long Ser ial E EPROM Load....................................................................................................................17
3.3.4 R ecomm end ed Ser i al EEPRO Ms ....................................................................................................................17
3.3.5 Pr ogra mmi ng the Seri al E EPROM...................................................................................................................17
3.4 INTERNAL REGISTER ACCESS ....................................................................................................................................17
3.4.1 PCI Bus Access to Internal Registers ..............................................................................................................18
3.4.2 Loc al Bus Acc es s to Internal Reg ister s............................................................................................................18
3.5 RESPONSE TO FULL AND EMPTY FIFOS.....................................................................................................................19
3.6 DIRECT DATA TRANSFER MODES...............................................................................................................................19
3.6.1 Direct Master Operation (Local Master to PCI Target) ....................................................................................20
3.6.1.1 Decode..........................................................................................................................................................................20
3.6.1.2 FIFOs............................................................................................................................................................................20
3.6.1.3 Memory Access ............................................................................................................................................................21
3.6.1.4 IO/CFG Access.............................................................................................................................................................21
3.6.1.5 I/O.................................................................................................................................................................................21
Contents
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved vii
3.6.1.6 CFG (PCI Configuration Type 0 or Type 1 Cycles).......................................................................................................21
3.6.1.7 Direct Bus Master Lock.................................................................................................................................................22
3.6.1.8 Master/Target Abort......................................................................................................................................................22
3.6.1.9 Write and Invalidate......................................................................................................................................................22
3.6.1.9.1 DMA Write and Invalidate .......................................................................................................................................23
3.6.1.9.2 Direct Master Write and Invalidate..........................................................................................................................23
3.6.2 Direct Slave Operation (PCI Master to Local Bus Access)..............................................................................25
3.6.2.1 PCI 2.1 Mode................................................................................................................................................................25
3.6.2.2 PCI-to-Local Address Mapping.....................................................................................................................................27
3.6.2.2.1 Byte Enables...........................................................................................................................................................27
3.6.2.2.2 Local Bus Initialization Software.............................................................................................................................27
3.6.2.2.3 PCI Initialization Software.......................................................................................................................................27
3.6.2.3 Deadlock and BREQo...................................................................................................................................................29
3.6.2.3.1 Backoff....................................................................................................................................................................30
3.6.2.3.2 Software/Hardware Solution for Systems without Backoff Capability......................................................................30
3.6.2.3.3 Software Solutions to Deadlock..............................................................................................................................30
3.6.2.4 Direct Slave Lock..........................................................................................................................................................30
3.6.3 Direct Slave Priority..........................................................................................................................................31
3.7 DMA OPERATION .....................................................................................................................................................31
3.7.1 Non-Chaining Mode DMA ................................................................................................................................31
3.7.2 Chaining Mode DMA........................................................................................................................................33
3.7.3 D MA Data Transfers.........................................................................................................................................34
3.7.3.1 Local-to-PCI Bus DMA Transfer....................................................................................................................................35
3.7.3.2 PCI-to-Local Bus DMA Transfer....................................................................................................................................35
3.7.3.3 Unaligned Transfers......................................................................................................................................................36
3.7.4 D ema nd Mod e DMA.........................................................................................................................................36
3.7.5 D MA Pri ority .....................................................................................................................................................36
3.7.6 D MA Arb itrati on................................................................................................................................................36
3.7.6.1 End of Transfer (EOT0# or EOT1#) Input.....................................................................................................................36
3.7.6.2 DMA Abort ....................................................................................................................................................................37
3.7.6.3 Local Latency and Pause Timers..................................................................................................................................37
3.8 VENDOR AND DEVICE ID REGISTERS..........................................................................................................................37
3.9 DOORBELL REGISTERS..............................................................................................................................................37
3.10 MAILBOX REGISTERS.................................................................................................................................................37
3.11 USER INPUT AND OUTPUT..........................................................................................................................................37
3.12 INTERRUPTS .............................................................................................................................................................38
3.12.1 PCI Interrupts (INTA#)......................................................................................................................................38
Contents
PCI 9080 Data Book v1.06
viii PLX Tec hn ology, Inc. All rights r e s e rved
3.12.1.1 Local Interrupt Input..................................................................................................................................................38
3.12.1.2 Master/Target Abort Interrupt....................................................................................................................................38
3.12.2 Local interr upts (LINTo#)..................................................................................................................................39
3.12.2.1 Local-to-PCI Doorbell Interrupt .................................................................................................................................39
3.12.2.2 PCI-to-Local Doorbell Interrupt .................................................................................................................................39
3.12.2.3 Built-In Self Test Interrupt (BIST)..............................................................................................................................39
3.12.2.4 DMA Channel 0/1 Interrupts......................................................................................................................................40
3.12.3 PCI SERR# (PCI NMI) .....................................................................................................................................40
3.12.4 Local LSERR# (Local NMI)..............................................................................................................................40
3.13 I2O COMPATIBLE MESSAGE UNIT ...............................................................................................................................40
3.13.1 Inbound Mess ages...........................................................................................................................................41
3.13.2 Outbound Mess ages ........................................................................................................................................41
3.13.3 I
2
O Pointer Management..................................................................................................................................41
3.13.4 Inbound Free List FIFO....................................................................................................................................42
3.13.5 Inbound Post Lis t FIFO ....................................................................................................................................44
3.13.6 Outbound Post List FIFO..................................................................................................................................44
3.13.7 Outbound Post Queue......................................................................................................................................44
3.13.8 Inbound Free Queue........................................................................................................................................44
3.13.9 Outbound Free List FIFO .................................................................................................................................44
3.13.10 I
2
O Enable Sequence.......................................................................................................................................45
4. REGISTERS...................................................................................................................................................................47
4.1 NEW REGISTER DEFINITIONS SUMMARY.....................................................................................................................47
4.1.1 Register Differences between PCI 9080 and PCI 9060, PCI 9060ES, and PCI 9060SD................................48
4.2 REGISTER ADDRESS MAPPING...................................................................................................................................54
4.3 PCI CONFIGURATION REGISTERS ..............................................................................................................................59
4.4 LOCAL CONFIGURATION REGISTERS...........................................................................................................................66
4.5 RUNTIME REGISTERS ................................................................................................................................................75
4.6 DMA REGISTERS......................................................................................................................................................80
4.7 MESSAGING QUEUE REGISTERS ................................................................................................................................85
5. PIN DESCRIPTION........................................................................................................................................................89
5.1 PIN SUMMARY...........................................................................................................................................................89
5.2 PIN OUT COMMON TO ALL BUS MODES......................................................................................................................90
5.3 C BUS MODE PIN OUT ..............................................................................................................................................94
5.4 J BUS MODE PIN OUT ...............................................................................................................................................96
5.5 S BUS MODE PIN OUT...............................................................................................................................................98
6. ELECTRICAL SPECIF ICAT IO NS ...............................................................................................................................101
Contents
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved ix
6.1 GENERAL SPECIFICATIONS ......................................................................................................................................101
6.2 LOCAL INPUTS.........................................................................................................................................................103
6.3 LOCAL OUTPUTS.....................................................................................................................................................104
7. PACKAGE, SIGNAL, AND PIN OUT SPECS.............................................................................................................107
7.1 PACKAGE MECHANICAL DIMENSIONS........................................................................................................................107
7.2 TYPICAL PCI BUS MASTER ADAPTER.......................................................................................................................108
7.3 PCI 9080 PIN OUT .................................................................................................................................................109
8. TIMING DIAGRAMS....................................................................................................................................................111
8.1 INITIALIZATION.........................................................................................................................................................111
8.2 C MODE .................................................................................................................................................................115
8.2.1 C Mode Direct Slave ......................................................................................................................................115
8.2.2 C Mode Direct Master ....................................................................................................................................137
8.2.3 C Mode DMA..................................................................................................................................................159
8.3 J MODE..................................................................................................................................................................170
8.3.1 J Mode Direct Sl ave .......................................................................................................................................170
8.3.2 J Mode Direct Mas ter .....................................................................................................................................177
8.3.3 J Mode DMA...................................................................................................................................................180
8.4 S MODE..................................................................................................................................................................184
PCI 9080 Data Book v1.06
xPLX T e c hn ology, Inc. All r ights r e s e rved
This page intentionally left blank.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved xi
FIGURES
Typical Adapter Bl ock Diagram...............................................................................................................................................1
PCI 9080 Internal Block Diagram............................................................................................................................................2
Figure 2-1. Wait Stat es............................................................................................................................................................8
Figure 2-2. Big/L itt le End ian—3 2- Bi t Local Bus................................................................................. ...................................11
Figure 2-3. Big/L itt le End ian—1 6- Bi t Local Bus................................................................................. ...................................12
Figure 2-4. Big/L itt le End ian—8- B it Loca l Bus.................................................................................. ....................................12
Figure 3-1. Reset and Ini tia liza tio n Pr oces s..........................................................................................................................13
Figure 3-2. PCI 9080 Internal Register Access.....................................................................................................................17
Figure 3-3. Dual Address Decode Mode...............................................................................................................................18
Figure 3-4. Direct Master, Direct Slave, and DMA................................................................................................................19
Figure 3-5. Mailb ox /Doorbell Mess age Pas sin g................................................................................... .................................19
Figure 3-6. Direct Mas ter Wr ite .............................................................................................................................................20
Figure 3-7. Direct Mas ter Read.............................................................................................................................................20
Figure 3-8. Loca l Master Direct Master Acc es s of PCI Bus..................................................................................................24
Figure 3-9. PCI Specification v2.1 Delayed Reads...............................................................................................................25
Figure 3-10. PCI 9080 Read Ahead Mode............................................................................................................................26
Figure 3-11. Direct S lave Wr ite .............................................................................................................................................26
Figure 3-12. Direct S lave Read.............................................................................................................................................26
Figure 3-13. Direct Slave Access of Local Bus.....................................................................................................................28
Figure 3-14. Non-Chaining DMA Initialization.......................................................................................................................31
Figure 3-15. DMA, PCI- to-Local............................................................................................................................................32
Figure 3-16. DMA, Loc al-t o- PCI............................................................................................................................................32
Figure 3-17. Chaining DMA Initialization...............................................................................................................................33
Figure 3-18. Chaining Mode DMA from PCI-to-Local ...........................................................................................................34
Figure 3-19. Local-to-PCI Bus DMA Data Transfer Operation..............................................................................................35
Figure 3-20. PCI-to-Local Bus DMA Data Transfer Operation..............................................................................................35
Figure 3-21. Inter rupt and Er ror Sources ..............................................................................................................................38
Figure 3-22. I2O Sys tem Arc hitect ur e....................................................................................................................................40
Figure 3-23. I2O Softw are Arc hitec t ure..................................................................................................................................41
Figure 3-24. Circular FIFO Operation....................................................................................................................................43
Figure 6-1. PCI 9080 Local Input Setup and Hold Waveform.............................................................................................103
Figure 6-2. PCI 9080 Local Output Delay ...........................................................................................................................104
Figure 6-3. ALE Op erati on ...................................................................................................... .............................................105
Figures
PCI 9080 Data Book v1.06
xii PLX Technology, Inc . All ri ghts rese rved
Figure 7-1. Pack age Mec han ic al Dim ensi ons.....................................................................................................................107
Figure 7-2. Typical PCI Bus Master Adapter.......................................................................................................................108
Figure 7-3. PCI 9080 Pin Out (All Modes)...........................................................................................................................109
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved xiii
TABLES
Table 1-1. Programmable Local Bus Modes...........................................................................................................................4
Table 1-2. Pin Compatibility.....................................................................................................................................................4
Table 1-3. Comparison of the PCI 9060, PCI 9060ES, PCI 9060SD, and PCI 9080..............................................................5
Table 2-1. PCI Target Command Codes.................................................................................................................................7
Table 2-2. DMA Master Command Codes ..............................................................................................................................7
Table 2-3. Local-to-PCI Memory Access.................................................................................................................................7
Table 2-4. Local-to-PCI I/O Access.........................................................................................................................................7
Table 2-5. Local-to-PCI Configuration Access........................................................................................................................7
Table 2-6. Local Processor Bus Types ...................................................................................................................................8
Table 2-7. Burst and Bterm on the Local Bus .........................................................................................................................9
Table 2-8. Burst Mode ............................................................................................................................................................9
Table 2-9. Partial Lword Accesses........................................................................................................................................10
Table 2-10. Big/Little Endian Program Mode ........................................................................................................................11
Table 2-11. Upper Lword Lane Transfer...............................................................................................................................11
Table 2-12. Upper Word Lane Transfer ................................................................................................................................11
Table 2-13. Lower Word Lane Transfer ................................................................................................................................11
Table 2-14. Upper Byte Lane Transfer..................................................................................................................................12
Table 2-15. Lower Byte Lane Transfer..................................................................................................................................12
Table 3-1. NB# and Serial EEPROM Guidelines ..................................................................................................................14
Table 3-2. Short Seria l EEPRO M Loa d Regis ters .................................................................................................................15
Table 3-3. Long Serial EEPROM Load Registers.................................................................................................................16
Table 3-4. Extra Long Serial EEPROM Load Registers........................................................................................................17
Table 3-5. Recommended Serial EEPROM Loads...............................................................................................................17
Table 3-6. Response to Full and Empty FIFOs.....................................................................................................................19
Table 3-7. Queue Starting Address.......................................................................................................................................41
Table 3-8. Circular FIFO Summary .......................................................................................................................................45
Table 4-1. New Registers Definitions Summary....................................................................................................................47
Table 4-2. Register Differences between PCI 9080 and PCI 9060.......................................................................................48
Table 4-3. Register Differences between PCI 9080 and PCI 9060ES..................................................................................50
Table 4-4. Register Differences between PCI 9080 and PCI 9060SD..................................................................................52
Table 4-5. PCI Configuration Registers.................................................................................................................................54
Table 4-6. Local Configuration Registers..............................................................................................................................55
Table 4-7. Runtime Registers................................................................................................................................................56
Table 4-8. DMA Registers.....................................................................................................................................................57
Tables
PCI 9080 Data Book v1.06
xiv PLX Technology, Inc . All ri ghts rese rved
Table 4-9. Messaging Queue Registers................................................................................................................................58
Table 4-10. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register ............................................................................59
Table 4-11. (PCICR; PCI:04h, LOC:04h) PCI Command Register.......................................................................................59
Table 4-12. (PCISR; PCI:06h, LOC:06h) PCI Status Register..............................................................................................60
Table 4-13. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register...................................................................................60
Table 4-14. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register.......................................................................60
Table 4-15. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register........................................................................61
Table 4-16. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register..............................................................................61
Table 4-17. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register................................................................................61
Table 4-18. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register............................................................61
Table 4-19. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses
to Local, Runtime, and DMA Registers.............................................................................................62
Table 4-20. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesse s
to Local, Runtime, and DMA Registers.............................................................................................62
Table 4-21. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses
to Local Address Space 0.................................................................................................................63
Table 4-22. (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses
to Local Address Space 1.................................................................................................................63
Table 4-23. (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register.............................................................................64
Table 4-24. (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register.............................................................................64
Table 4-25. (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer Register......................................................................64
Table 4-26. (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID Register................................................................64
Table 4-27. (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID Register ...............................................................................64
Table 4-28. (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Register.............................................................64
Table 4-29. (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Register.................................................................................64
Table 4-30. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register..................................................................................65
Table 4-31. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register......................................................................................65
Table 4-32. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register.......................................................................................65
Table 4-33. (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI-to-Local Bus .........................66
Table 4-34. (LAS 0B A; PCI:04 h, LO C:8 4h) Loc al Ad dr ess Space 0 Local Base Ad dr es s (Remap) Reg ister.......................66
Table 4-35. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register........................................................67
Table 4-36. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register...............................................................68
Table 4-37. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register....................................................................69
Table 4-38. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register
and BREQo Control ..........................................................................................................................69
Table 4-39. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Register ........70
Table 4-40. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master to PCI...................................................71
Tables
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved xv
Table 4-41. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master to PCI Memory..............71
Table 4-42. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master to PCI IO/CFG........................71
Table 4-43. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to PCI Memory........72
Table 4-44. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master to PCI IO/CFG .........73
Table 4-45. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI-to-Local Bus.......................73
Table 4-46. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Register ....................74
Table 4-47. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register..................................74
Table 4-48. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0..................................................................................75
Table 4-49. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1 .................................................................................75
Table 4-50. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2.............................................................................................75
Table 4-51. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3............................................................................................75
Table 4-52. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4.............................................................................................75
Table 4-53. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5.............................................................................................75
Table 4-54. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6.............................................................................................75
Table 4-55. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7............................................................................................75
Table 4-56. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell Register.....................................................................76
Table 4-57. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell Register.....................................................................76
Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register.......................................................................77
Table 4-59. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control,
Init Control Register ..........................................................................................................................79
Table 4-60. (PCIHIDR; PCI:70h, LOC:F0h) PCI Permanent Configuration ID Register.......................................................79
Table 4-61. (PCIHREV; PCI:74h, LOC:F4h) PCI Permanent Revision ID Register .............................................................79
Table 4-62. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register ...............................................................80
Table 4-63. (DMAPADR0; PCI:84h, LOC:104h) DMA Channel 0 PCI Address Register.....................................................81
Table 4-64. (DMALADR0; PCI:88h, LOC:108h) DMA Channel 0 Local Address Register...................................................81
Table 4-65. (DMASIZ0; PCI:8Ch, LOC:10Ch) DMA Channel 0 Transfer Size (Bytes) Register ..........................................81
Table 4-66. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer Register...............................................81
Table 4-67. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Register ...............................................................82
Table 4-68. (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register.....................................................83
Table 4-69. (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register .................................................83
Table 4-70. (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register ...........................................83
Table 4-71. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register ..............................................83
Table 4-72. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register ...............................................83
Table 4-73. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register ...............................................84
Table 4-74. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register .............................................................................84
Table 4-75. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register...............................................................................84
Tables
PCI 9080 Data Book v1.06
xvi PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-76. (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register.............................................85
Table 4-77. (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register..............................................85
Table 4-78. (IQP; PCI:40h) Inbound Queue Port Register....................................................................................................85
Table 4-79. (OQP; PCI:44h) Outbound Queue Port Register...............................................................................................85
Table 4-80. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register ........................................................86
Table 4-81. (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register...........................................................................86
Table 4-82. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register.................................................................86
Table 4-83. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register...................................................................86
Table 4-84. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register.................................................................87
Table 4-85. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register....................................................................87
Table 4-86. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register............................................................87
Table 4-87. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register..............................................................87
Table 4-88. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register ............................................................87
Table 4-89. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register................................................................88
Table 4-90. (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register.............................................................................88
Table 5-1. Pin Type Abbreviations ........................................................................................................................................89
Table 5-2. Power and Ground Pin Description......................................................................................................................90
Table 5-3. Serial EEPROM Interface Pin Description...........................................................................................................90
Table 5-4. PCI System Bus Interface Pin Description...........................................................................................................91
Table 5-5. Local Bus Mode and Processor Independent Interface Pin Description..............................................................92
Table 5-6. C Bus Mode Interface Pin Description.................................................................................................................94
Table 5-7. J Bus Mode Interface Pin Description..................................................................................................................96
Table 5-8. S Bus Mode Interface Pin Description .................................................................................................................98
Table 6-1. Absolute Maximum Ratings ...............................................................................................................................101
Table 6-2. Operating Ranges..............................................................................................................................................101
Table 6-3. Capacitance (sample tested only)......................................................................................................................101
Table 6-4. Electrical Characteristics Estimated over Operating Range..............................................................................102
Table 6-5. AC Electrical Characteristics (Local Inputs) Estimated over Operating Range.................................................103
Table 6-6. AC Electrical Characteristics (Local Outputs) Estimated over Operating Range ..............................................104
Table 6-7. ALE Operation....................................................................................................................................................105
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved xvii
TIMING DIAGRAMS
Timing Diagram 8-1. (C, J Modes) PCI RST# Asserting Local Output LRESETo#............................................................111
Timing Diagram 8-2. (S Mode) Two Phase Clock Synchronization Using LRESETo#.......................................................111
Timing Diagram 8-3. PCI 9080 Local Bus Arbitration..........................................................................................................112
Timing Diagram 8-4. PCI 9080 1K Serial EEPROM PCI Initialization.................................................................................113
Timing Diagram 8-5. Local Interrupt (LINTi#) Input Asserting PCI Output INTA# ..............................................................114
Timing Diagram 8-6. (C Mode) PCI Configuration Write to PCI 9080 PCI Configuration Register.....................................115
Timing Diagram 8-7. (C Mode) PCI Configuration Read to PCI 9080 PCI Configuration Register ....................................115
Timing Diagram 8-8. (C Mode) PCI Memory Write to PCI 9080 Local Configuration Register ..........................................116
Timing Diagram 8-9. (C Mode) PCI Memory Read to PCI 9080 Local Configuration Register ..........................................116
Timing Diagram 8- 10. (C Mode) Direct S lave Si ngl e Cycle Rea d (32-Bit Loc al Bus)................................................ .........117
Timing Diagram 8- 11. (C Mode) Direct S lave Si ngl e Cycle Writ e.......................................................................................118
Timing Diagram 8-12. (C Mode) PCI 9080 DMA or Direct Slave Burst Read from Local Bus,
No Wait States, Bterm Enabled ......................................................................................................119
Timing Diagram 8-13. (C Mode) DMA or Direct Slave PCI 9080 Burst Write to Local Bus, Bterm Enabled......................120
Timing Diagram 8- 14. (C Mode) Direct S lave PCI- t o-Loc al Burs t Read, Bterm Dis ab led ..................................................121
Timing Diagram 8-15. (C Mode) PCI 9080 DMA or Direct Slave Burst Write, Bterm Disabled ..........................................122
Timing Diagram 8-16. (C Mode) Direct Slave Read with Prefetch Counter Set to 5 ..........................................................123
Timing Diagram 8-17. (C Mode) Direct Slave or DMA Burst Write to 32-Bit Local Bus Suspended by BREQ Input.........124
Timing Diagram 8-18. (C Mode) Direct Slave Burst Read of Five Lwords with One Wait State.........................................125
Timing Diagram 8-19. (C Mode) Direct Slave Burst Write of Five Lwords with One Wait State.........................................126
Timing Diagram 8-20. (C Mode) Direct Slave Read 2.1 Spec ............................................................................................127
Timing Diagram 8-21. (C Mode) Direct Slave Read No Flush Mode (Read Ahead Mode).................................................128
Timing Diagram 8-22. (C Mode) Direct Slave Read of Two Lwords from 8-Bit Bus...........................................................129
Timing Diagram 8-23. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 8-Bit Local Bus,
No Wait States, Bterm Enabled ......................................................................................................130
Timing Diagram 8-24. (C Mode) Direct Slave Read of Two Lwords from 16-Bit Bus.........................................................131
Timing Diagram 8-25. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16-Bit Local Bus,
No Wait States, Bterm Enabled ......................................................................................................132
Timing Diagram 8-26. (C Mode) Direct Slave Read of Two Lwords from 8-Bit I/O Local Bus, Burst Disabled..................133
Timing Diagram 8-27. (C Mode) Direct Slave Write of Two Lwords to 8-Bit I/O Local Bus, Burst Disabled.......................134
Timing Diagram 8-28. (C Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting ....135
Timing Diagram 8-29. (C Mode) Locked Direct Slave Read Followed by Write and Release (LLOCKo#).........................136
Timing Diagram 8-30. (C Mode) Local Bus Read from PCI 9080 CFG Registers..............................................................137
Timing Diagram 8- 31. (C Mode) Loca l Bus Write to PCI 908 0 CFG Regis ters ........................................................ ..........138
Timing Diagram 8-32. (C Mode) Local Bus Direct Master Single Memory Read................................................................139
Timing DIagrams
PCI 9080 Data Book v1.06
xviii PLX Techn o logy, In c . All ri ghts rese r v e d
Timing Diagram 8-33. (C Mode) Local Bus Direct Master Single Memory Write Cycle......................................................140
Timing Diagram 8-34. (C Mode) PCI 9080 Direct Master Memory Read, 12 Lword Burst.................................................141
Timing Diagram 8-35. (C Mode) PCI 9080 Direct Master Memory Write of 12 Lwords......................................................142
Timing Diagram 8-36. (C Mode) PCI 9080 Direct Master Memory Read with WAITI#.......................................................143
Timing Diagram 8-37. (C Mode) PCI 9080 Direct Master Memory Write with WAITI#.......................................................144
Timing Diagram 8-38. (C Mode) PCI 9080 Direct Master Configuration Read—Type 1 or Type 0....................................145
Timing Diagram 8-39. (C Mode) PCI 9080 Direct Master Configuration Write—Type 1 or Type 0 ....................................146
Timing Diagram 8-40. (C Mode) Local Bus Direct Master Read from PCI I/O....................................................................147
Timing Diagram 8-41. (C Mode) Direct Master Write to PCI I/O.........................................................................................148
Timing Diagram 8-42. (C Mode) PCI 9080 Direct Master Memory Read—Keep Bus........................................................149
Timing Diagram 8-43. (C Mode) PCI 9080 Direct Master Memory Read—Drop Bus.........................................................150
Timing Diagram 8-44. (C Mode) PCI Bus Request (REQ#) Delay During Direct Master Write (8 PCI Clock Delay).........151
Timing Diagram 8- 45. (C Mode) Direct Mas ter Me mor y Read, Pr efetch of 16...................................................................152
Timing Diagram 8-46. (C Mode) Direct Master Memory Write and Invalidate (MWI)—Cache Line Size of 8 ....................153
Timing Diagram 8- 47. (C Mod e) Direct Mas ter in BIGEND Local Bus w ith BIG END# Inp ut or Interrupt............................154
Timing Diagram 8-48. (C Mode) Direct Master Burst, Memory Read Cycles (Changing LBE[3:0]#) .................................155
Timing Diagram 8-49. (C Mode) Direct Master Five Lword Burst Write (Changing LBE[3:0]#)..........................................156
Timing Diagram 8-50. (C Mode) Direct Master Locked Read Followed by Write and Release (LLOCK# and LOCK#).....157
Timing Diagram 8-51. (C Mode) BREQo and Deadlock .....................................................................................................158
Timing Diagram 8-52. (C Mode) DMA Aligned PCI Address to Aligned Local Address, Bterm Disabled...........................159
Timing Diagram 8-53. (C Mode) DMA Aligned Local Address to Aligned PCI Address, Burst Enabled, Bterm Enabled...160
Timing Diagram 8-54. (C Mode) DMA Aligned PCI Address to Aligned Local Address
(External Generation of Wait States)..............................................................................................161
Timing Diagram 8-55. (C Mode) Read of DMA Chaining Parameters from PCI and Local Buses.....................................162
Timing Diagram 8-56. (C Mode) PCI 9080 DMA Read of Chaining Parameters from Local Bus, No Wait States.............163
Timing Diagram 8-57. (C Mode) Read of DMA Chaining Parameters from PCI Bus (Local-to-PCI Transfer)....................164
Timing Diagram 8- 58. (C Mode) Single Cy cle DMA Dem and Mo de PCI- to-Loc a l..............................................................165
Timing Diagram 8-59. (C Mode) Multiple Cycle (Burst) DMA Demand Mode PCI-to-Local, No Wait States .....................165
Timing Diagram 8-60. (C Mode) DMA Demand Mode Terminated with BLAST# (Local-to-PCI) .......................................166
Timing Diagram 8-61. (C Mode) DMA Local-to-PCI, Terminated with EOT[1:0]# ..............................................................167
Timing Diagram 8-62. (C Mode) DMA PCI-to-Local, Terminated with EOT[1:0]# ..............................................................168
Timing Diagram 8-63. (C Mode) DMA PCI-to-Local with Local Pause Timer and Local Latency Timer ............................169
Timing Diagram 8-64. (J Mode) PCI 9080 Direct Slave Burst Read from Local Bus, No Wait States, Bterm Enabled......170
Timing Diagr am 8-65. (J Mode) PCI 908 0 Dir ect Slav e Burs t Write to Loc al Bus , No Wa it States, Bterm Ena bled..........171
Timing Diagram 8-66. (J Mode) PCI 9080 DMA or Direct Slave Burst Write to Local Bus, No Wait States,
Bterm Disabled................................................................................................................................172
Timing DIagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved xix
Timing Diagram 8-67. (J Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting.....173
Timing Diagram 8-68. (J Mode) Direct Slave Read v2.1 Spec ...........................................................................................174
Timing Diagram 8-69. (J Mode) Direct Slave Read No Flush Mode (Read Ahead Mode), Prefetch Mode Enabled .........175
Timing Diagram 8-70. (J Mode) Local Bus Read from PCI 9080 CFG Registers...............................................................176
Timing Diagram 8-71. (J Mode) Local Bus Write to PCI 9080 CFG Registers...................................................................176
Timing Diagram 8-72. (J Mode) Direct Master Read Access from PCI Bus (Keep PCI Bus
If Read FIFO Full Mode), No PCI Disconnects...............................................................................177
Timing Diagram 8-73. (J Mode) Local Bus Direct Master Burst Write Access to PCI Bus,
Continuous If Same Clock Rate and No PCI Disconnects .............................................................178
Timing Diagram 8-74. (J Mode) Local Bus Direct Master Lock Memory Read Access from PCI Bus
Followed by Write and Release ......................................................................................................179
Timing Diagram 8-75. (J Mode) PCI 9080 DMA Local-to-PCI, No Wait States, Bterm Enabled ........................................180
Timing Diagram 8- 76. (J Mode) PCI 908 0 DMA PCI-t o- Local Bus , No Wait Sta tes , Bterm En abl ed.................................181
Timing Diagram 8-77. (J Mode) DMA Read of Chaining Parameters, No Wait States.......................................................182
Timing Diagram 8- 78. (J Mode) PCI 908 0 Write to Loc al Bus BREQ Assert ed........................................................ ..........183
Timing Diagram 8-79. (S Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16-Bit Local Bus,
No Wait States, Bterm Enabled ......................................................................................................184
Timing Diagram 8-80. (S Mode) Local Bus Read from PCI 9080 CFG Registers..............................................................185
Timing Diagram 8-81. (S Mode) Local Bus Write to PCI 9080 CFG Registers...................................................................186
PCI 9080 Data Book v1.06
xx PLX T e c hn ology, Inc. All r ights r e s e rved
This page intentionally left blank.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved xxi
PREFACE
The informati on contai ned in this document s hould be cons idered pre liminary. Altho ugh an effort has been made t o keep
the information accurate, there may be misleading or even incorrect statements made herein. The document is being
written in parallel with actual chip development and, as such, it is subject to ch ange. This description is inte nded to be a
living document, to be updated throughout the PCI 9080 design effort. It provides a broad technical overview of the
PCI 9080.
The following is a list of additional documentation to provide the reader with further information about the PCI 9080 and
related subjects:
•
PCI Local Bus Spec if ication
, Revision 2.1
PCI Special Interest Group
5200 N.E. Elam Young Parkway, Hillsboro, OR, 97124-6497 USA
503-696-2000, http: //www. pc is ig .com
•
PCI Hot-Plug Specification
, Revision 1.0
PCI Special Interest Group
5200 N.E. Elam Young Parkway, Hillsboro, OR, 97124-6497 USA
503-696-2000, http: //www. pc is ig .com
•
PCI Power Management Interface Specification
, Revision 1.0, June 30, 1997
PCI Special Interest Group
5200 N.E. Elam Young Parkway, Hillsboro, OR, 97124-6497 USA
503-696-2000, http: //www. pc is ig .com
•
PICMG 2.0, Compac t PCI (reg ist ered) Speci fic at io n
, Revision 2.1 or greater
PCI Industrial Computer Manufacturers Group (PICMG)
301 Edgewat er Place, Su ite 220, Wak ef iel d, MA 018 80, US A
Tel: 781-224-1100, Fax: 617-224-1239, http://www.picmg.org
•
Intelligent I/O (I
2
O)
Architecture Specification
, Revi sion 1.5
I2O Special Interest Group
404 Balboa Street, Sa n Franc is co, CA 94118 USA
Tel: 415-750-8352, Fax: 415-751-4829, http://www.i2osig.com
PCI 9080 Data Book v1.06
xxii PLX Technology, Inc . All ri ghts rese rved
This page intentionally left blank.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved xxiii
REVISION HISTORY
Date Revision Comment
07/3/1997 1.0 • Initial release.
• Release timing diagrams.
• Corrected typos and matched spec.
• Changed Pin 170 to NC.
• Changed LARBR (Local/Arbi tration Register) t o MARBR (Mode/A rbitration Register).
07/10/1997 1.01 • Set up hold and output timings
• Change mechanical pack age dimension.
• Complete elect rical tabl es i n Section 6.
• Correct timing diagrams.
• Matched spec.
07/24/1997 1.02 • Changed the title of Section 7.
• Added READYo# value to Table 6-6.
• Removed WR# and RD# signals from and corrected signal LA[ 31:0] reference in Timing Diagram 8-20.
• Corrected t itl es of Timing Diagrams 8-20 and 8-68.
• Corrected t itl es of Secti ons 8. 3.3 and 8.4. 3.
08/19/1997 1.03 • Corrected Bt erm mode refe rence in Secti on 2.2.3.2.
• Corrected reference to Note in Table 4-7.
• Corrected inf ormati on for bits [ 23:20] in Table 4-75.
• Corrected pack age mechanic al dimensi on to 30. 6 x 30.6 mm in Figure 7-1.
• Corrected LBE[ 3:0] # signal inf ormat i on in Timing Diagram 8-15.
• Corrected signal LA[31:0] reference in Timing Diagram 8-21.
• Corrected all “Bt erm enabled” and “Bt erm disabled” ref erences to
“BTERM# enabled” and “BTERM# disabled” in all affected timing diagrams in Section 8.
• Applied general editi ng to regist er and pin out tables.
01/26/1998 1.04 • Corrected values in Table 3-5.
• Corrected direct i on of DEVSEL#, TRDY # signal in Figure 3-16.
• Corrected name of Figure “Typical Adapter Block Diagram” and Table 6-3.
• Changed VIL and VIH values to include both CMOS and TTL values in Table 6-4.
• Significantly rev is ed Table 6-5 and Table 6-6.
• Updated timing diagrams .
• Reversed "BTERM# enabled/ disabl ed" changes m ade in v1.03 back to "Bterm enabled/disabled."
• Corrected text f or DMATHR [31:28, 15:12] now reads "…bef ore request i ng PCI Bus
for reads" and bits [27:24, 11:8] now reads "…before request i ng PCI Bus for writes."
REVISION HISTORY
PCI 9080 Data Book v1.06
xxiv PLX Technology, Inc . All ri ghts rese rved
Date Revision Comment
09/01/1999 1.05 • Changed document t itl e from “Data S heet” t o “Data Book.”
• Added company background i nf ormat i on.
• Corrected register bit number in section 3.7.6.1.
• Corrected Seri al EEP ROM Writable capabil ity of 30h PCI CFG Register in Table 4-5.
• Corrected Bterm information on bit 23 of Table 4-39.
• Revised DMA Channel 1 number of full entries (delete divide by 2 operation) in Table 4-75.
• Updated timing diagrams .
• Added ALE Operation section after Elect ric al Specif ic ation page 101, Section 6.
• Added values in Table 6-1.
• Revised operating range temperature values in Table 6-2.
• Added values in Table 6-4 for VOH3, VOL3, VIH3, and VIL3.
• Revised LAD values in Table 6-6.
• Revised timing di agrams 8-10, 8-17, 8-30, 8-31, 8-70, and 8-71.
• Cosmetic changes (capitalizations of specific terms, etc.).
01/2000 1.06 • Applied minor format changes.
• Changed copyright dat e to 2000.
• Added primary titl e page, 800 number, discl aimer and trademarks, part number, and list of Figures,
Tables, and Timing Diagrams.
• Changed “negate” to “de-ass ert .”
• Added PCI and Local Bus information to FIgure 3-5.
PCI 9080
PCI I/O Accelerator
January 2000 I2O Compatible PCI Bus Master Interface Chip
VERSION 1.06 for Adapters and Embedded Systems
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 1
FEATURES
• PCI Specification 2.1 (v2.1) compliant Bus Master
Interface chip for adapters and embedded systems
• I2O Compatible Messaging Unit
• 3.3 or 5 volt PCI signaling, 5 volt core, low-power
CMOS in a 208-pin PQF P
• Two independent DMA channels for Local Bus
memory to and from PCI Host Bus Data transfers
• Eight programmable FIFOs for zero wait state
burst operation
• PCI Local Data transfers up to 132 MB/sec
• Programmable Local Bus supports nonmultiplexed
32-bit address/data, multiplexed 32- or 16-bit,
and Slave accesses of 32-, 16-, or 8-bit Local
Bus devices
• Local Bus runs asynchronously to the PCI Bus
• Eight 32-bit Mailbox and two 32-bit Doorbell
registers
• Performs Bi g End ian/ Lit tle Endian conver s i on
• Upward compatibility with the PCI 9060,
PCI 9060ES, and PCI 9060SD
Serial
EEPROM
PCI Bus
Local Bus
CPU
Boot
ROM Local
Memory
I/O Device
(LAN, Disk,
Video, etc.)
FIFOs
PCI 9080
Control:
- DMA
- I2O
- Unaligned
Transfer
PCI
Local
Runtime
DMA
Registers
Local Bus Interface
PCI Interface
I2O
Typical Adapter Blo ck Diagr am
Features
PCI 9080 Data Book v1.06
2PLX T e c hn ology, Inc. All r ights r e s e rved
PCI Bus
Interface
PCI Bus
State
Machines
PCI Config.
Internal
Registers
Local Config.
DMA
FIFOs
Local Bus
Interface:
- Select Bus
Width 8,16,
or 32 bit
- Endian
Conversion
- Select Muxed
or non-Muxed
Addr/Data
Local Bus
State
Machines
Serial
EEPROM
Initialization
I2O Messaging
Dir. Master Write
Dir. Master Read
Dir. Slave Write
Dir. Slave Read
DMA1 PCI/Loc
DMA1 Loc/PCI
DMA0 PCI/Loc
DMA0 Loc/PCI
Control
Logic
I2O Messaging DMA DMA Chaining Unaligned Xfer
Run-Time
PCI Target
(for Direct
Slave Xfers)
PCI Initiator
(For Ch 1
DMA Xfers)
PCI Initiator
(For Ch 0
DMA Xfers)
PCI Initiator
(for Direct
Master Xfers)
Local Master
(for Direct
Slave Xfers)
Local Master
(For Ch 1
DMA Xfers)
Local Master
(For Ch 0
DMA Xfers)
Local Slave
(for Direct
Master Xfers)
PCI 9080 Internal Block Diagram
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 3
1. GENERAL DESCRIPTIO N
1.1 Company and Product Background
PLX Technology, Inc., the world leader in PCI-to-Local
Bus I/O acceler ator chips, su pports more t han 500 OEM
customers in a wide variety of PCI applications.
Customer applications include PC workstations and
servers, PCI add-in boards, embedded PCI
communication systems such as routers and switches,
and industrial PCI implementations such as
CompactPCI , PMC, and Pas siv e Back pl ane PCI.
PLX Tec hnology, Inc ., is an activ e participa nt in industry
standard committees, including the PCI SIG, I2O SIG,
and PICMG, and maintains active developer technology
and cross-marketing partnerships with industry leaders,
such as Intel, IBM, Hewlett-Packard, Motorola,
Integrated Systems, WindRiver and others.
Focused on providing complete solutions for
PCI implementations, PLX provides design assistance to
customers in the form of Reference Design and Software
Development kits. Depending upon the application,
these kits may include reference boards, API libraries,
software debug tools, and sample device drivers with
source, ena bling custom ers to quick ly bri ng n ew d esigns
to production. New tools, application notes, FAQs, and
information updates are constantly added to the website
for the convenience of PLX customers. Our expertise
and total solutions for the PCI interface allow customers
to focus on adding value in their designs without
worrying about the complexities of implementing PCI,
I2O, and CompactPCI.
1.2 PCI 9080 Applications
1.2.1 PCI Adapter Cards
Major PCI adapter card applications for the PCI 9080
include high performance communications, networking,
disk control, multimedia, and video adapters. The
PCI 9080 moves data between the host PCI Bus and
adapter Local Bus in several ways. First, the local CPU
or host processor may program the DMA controller of
the PCI 9080 to move data between the adapter memory
and host PCI Bus. Second, the PCI 9080 can perform
Direct Master Transfers, whereby a local CPU or
controller accesses the PCI Bus directly through a
PCI Master transfer. The PCI 9080 also supports Slave
transfers in which another PCI device is the Master.
Finally, the PCI 9080 contains a complete messaging
unit wit h mai lbox re gisters , door bell regis ter s, and queue
management pointers that can be used for message
passing under the I2O protocol or a custom protocol.
1.2.2 Embedded Systems
Another application for the PCI 9080 is in embedded
systems, such as network hubs and routers, printer
engines, and industrial equipment. In this configuration,
all four of the above-mentioned Data Transfer modes are
used. In addition, the PCI 9080 supports Type 0 and
Type 1 PCI Configuration cycles, which allows
embedded CPU to act as the embedded system host
and to configure other PCI devices in the system.
1.3 Major Features
PCI 2.1 Compliant. The PCI 9080 is compliant with all
aspects of PCI Specification v2.1.
I2O Messaging Unit. The PCI 9080 incorporates an I2O
messaging unit. This enables the adapter or embedded
system to communicate with other I2O-supported
devices. The I2O messaging unit is fully compatible with
the PCI extension of the I2O specification v1.5.
Dual Independent Programmable DMA Controllers
with Programmable FIFOs. The PCI 9080 prov ides two
independently programmable DMA controllers with
programmable FIFOs for each channel. Each channel
supports Non-chaining and Chaining DMA modes,
Demand mode DMA, and End of Transfer (EOT) mode.
Direct Bus Master. The PCI 9080 supports Memory-
Mapped bursts, Transfer accesses, and I/O-Mapped
Single-Transfer accesses to the PCI Bus from the Local
Bus Master. The PCI 9080 also supports PCI Bus
Interlock (LOCK#) cycles. The Read and Write FIFOs
enable high- perf or manc e bursti ng.
PCI Host Capability. In Direct Master mode, the
PCI 9080 can generate Type 0 or Type 1
PCI Configuration cycles.
Direct Slave. The PCI 9080 supports Burst Memory-
Mapped and single I/O-Mapped accesses to the Local
Bus. The Read and Write FIFOs enable high-
performance bursting.
Programmable Local Bus Modes. The PCI 9080 is a
PCI Bus Master interface chip that connects a PCI Bus
to one of three Local Bus types, selected through mode
pins. The PCI 9080 may b e connected to any Local Bus
with a sim ilar des ign with l ittle or no glu e logic. T ab le 1-1
lists the three modes.
Section 1
General Description Compatibility with PCI 9060, PCI 9060ES, and PCI 9060SD
PCI 9080 Data Book v1.06
4PLX T e c hn ology, Inc. All r ights r e s e rved
Table 1-1. Programmable Local Bus Modes
Mode Description
C 32-bit address/32-bit data, nonmultiplexed
J 32-bit address/32-bit data, multiplexed
S 32-bit address/16-bit data, multiplexed
Interrupt Generator. The PCI 9080 can generate
PCI and Local interrupts from several sources.
Clock. The PCI 9080 Local Bus interface runs from a
local TTL clock and generates the necessary internal
clocks. This clock runs asynchronously to the PCI clock.
There is a buffered PCI clock (BPCLKo) for the Local
Bus to use. BPCLKo may be connected to LCLK.
3.3 Volt and 5 Volt Operation. The PCI 9080 core
requires 5V Vcc. The PCI 9080 provides 3.3V or 5V
signaling on the PCI Bus. The Local Bus operates at a
5V signaling level.
Serial EEPROM Interface. The PCI 9080 contains an
optional serial EEPROM interface that can be used to
load configuration information. This is useful for loading
information unique to a particular adapter (such as
Network ID or Vendor ID).
Mailbox registers. The PCI 9080 contains eight 32-bit
mailbox registers that may be accessed from the PCI or
Local Bus.
Doorbell registers. The PCI 9080 includes two 32-bit
doorbell registers. One generates interrupts from the
PCI Bus to Local Bus. The other generates interrupts
from the Local Bus to the PCI Bus.
Unaligned DMA Transfer Support. The PCI 9080 can
transfer data on any byte boundary.
Big/Little Endian Conversion. The PCI 9080 supports
dynamic switching betw een Big Endian and L ittle End ian
operations for Direct Slave, D irect Mas ter, DMA, and the
Internal register accesses on the Local Bus.
The PCI 9080 supports on-the-fly Endian conversion for
Space 0, Space 1, and Expansion ROM space. The
Local Bus can be Big/Little Endian by using the
BIGEND# input pin or programmable internal register
configuration. When BIGEND# is asserted, it overrides
the internal register configuration.
Note: The PCI Bu s is always Little Endian.
Read Ahead Mode. The PCI 9080 supports Read
Ahead mode, where prefetched data can be read from
the PCI 9080 internal FIFO instead of from the Local
Bus. Address must be subsequent to previous address
and 32-bit aligned (next address = current address + 4).
Programmabl e Bus Wait St ates. The PCI 9080 can be
programmed to keep the PCI Bus by generating a wait
state(s), thereby de-asserting TRDY#, if the Write FIFO
becomes f ull. The PCI 9080 can a lso be programmed to
keep the Local Bus. LHOLD is asserted if the Direct
Slave Write FIFO becomes empty or the Direct Slave
Read FIFO becomes full. The Local Bus is dropped in
either case when the Local Bus Latency Timer is
enabled and expires.
1.4 Compatibility with PCI 9060,
PCI 9060ES, and PCI 9060SD
The PCI 9080 is upward compatible with the PCI 9060,
PCI 9060E S and PCI 9060S D, except as noted in Table
1-2 and Section 4.1, “New Register Definitions
Summary.”
1.4.1 Pin Compatibility
When upgrading from the PCI 9060, 9060ES or 9060SD,
observe the following new pin definitions listed in
Table 1-2.
Table 1-2. Pin Compatibility
PCI 9060/9060ES/9060SD PCI 9080
Pin
#Pin
Name Description Pin
Name Description
170 CLKSEL Serial
EEPROM
Clock S elect
NC —
175 EE1MC Optional
Serial
EEPROM
Clock So urce
EESEL Ser i al EE PR O M
Select
1=93CS46
(1K bit)
0=93CS56
(2K bit)
1.4.2 Register Compatibility
All registers implemented in the PCI 9060, PCI 9060ES,
and PCI 9060SD are implemented in the PCI 9080.
There are a limited number of new bit definitions and
several new registers. Refer to Section 4.1, “New
Register Definitions Summary.”
Section 1
Comparison of PCI 9060, PCI 9060ES, PCI 9060SD, and PCI 9080 General Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 5
1.5 Compar ison of PCI 9060, PCI 9060ES, PC I 9060SD, and PCI 9080
Table 1-3. Comparison of the PCI 9060, PCI 9060E S, PCI 9060SD, and PCI 9080
Feature PCI 9060 PCI 9060ES PCI 9060SD PCI 9080
Number of DMA Channel(s) 2 0 1 2
Local Address Spaces 2 2 3 3
Direct Ma s te r Mo d e Yes Yes No Yes
Mailbox Regist ers Eight 32-bit Four 32-bit Four 32-bit Eight 32-bit
Doorbell Registers Two 32-bit Two 8-bit Two 8-bit Two 32-bit
FIFOs 8 4 4 8
FIFO Depth—Direct Slave Write, Direct Mast er
Write, DMA 0 Read and DMA 0 Write 8 Lwords
(32 bytes) 16 Lwords
(64 bytes) 16 Lwords
(64 bytes) 32 Lwords
(128 bytes)
FIFO Depth—Direct Slave Read, Direct Master
Read, DMA 1 Read and DMA 1 Write 8 Lwords
(32 bytes) 16 Lwords
(64 bytes) 16 Lwords
(64 bytes) 16 Lwords
(64 bytes)
LLOCKo# Pin for Lock Cycles No Yes Yes Yes
WAITI# Pin for Wait State Generation No Yes Yes Yes
BPCLKo Pin; Buffered PCI Clock No Yes Yes Yes
DREQ# and DACK# Pins for Demand Mode
DMA Supp o r t Yes No Yes
(Channel 1 only) Yes
Register Addresses — Ident ic al exc ept
9060ES has no
DMA regist ers and
Tables 25, 26, and 43
were added
Identical, exc ept
9060SD has one
DMA register and
Tables 4-29 and 4-30
were added
Identical except
PCI 9080 has
additional I2O related
registers and 30h,
34h, 40h, and 44h
were remapped
Pin Out
Note: The PCI 9080 includes all
changes made for PCI 9060, PCI 9060ES,
and PCI 9060SD.
—Signals deleted:
DREQ0# (pin 29)
DACK0# (pin 30)
Input signals added:
WAITI# (pin 6)
BIGEND# (pin 48)
Output signals added:
BPCLKo (pin 168)
LLOCKo# (pin 7)
Signals deleted:
BREQ (pin 21)
DMPAF# (pin 8)
DREQ0# (pin 29)
DACK0# (pin 30)
BTERMo# (pin 28)
Input signals added:
WAITI# (pin 6)
BIGEND# (pin 48)
EOT0# (pin 164 in
C mode, Pin 5 in
J and S modes)
Output signals added:
BPCLKo (pin 168)
LLOCKo# (pin 7)
Input signal added:
EOT1# (pin 163)
Signal changed:
EESEL (pin 175)
Big/Little Endian Conversion No Yes Yes Yes
PCI Specificati on v2.1 Deferred Reads No Yes Yes Yes
Programmable Prefetc h Counter No Yes Yes Yes
Write and Invalidat e Cycle No Yes Yes Yes
Additional Dev ice and Vendor ID Regist er No Yes Yes Yes
I2O Messaging Unit No No No Yes
3.3V PCI Bus Signaling No No No Yes
PCI 9080 Data Book v1.06
6PLX T e c hn ology, Inc. All r ights r e s e rved
This page intentionally left blank.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 7
2. BUS OPERATION
2.1 PCI Bus Cycles
The PCI 9080 is compliant with PCI Specification v2.1.
Refer to the PCI 2.1 spec for any specific features of the
PCI Bus.
2.1.1 PCI Target Command Codes
As a Target, the PCI 9080 allows access to its Internal
registers and the Local Bus, using the commands listed
in Table 2-1.
Table 2-1. PCI Target Command Codes
Command Type Code (C/BE[3:0]#)
I/O Read 0010 (2h)
I/O Write 0011 (3h)
Memory Read 0110 (6h)
Memory Write 0111 (7h)
Memory Read Multiple 1100 (Ch)
Memory Read Line 1110 (Eh)
Memory Write and Invalidate 1111 (Fh)
Configurati on Read 1010 (Ah)
Configuratio n Write 1011 (Bh)
All Read or Write acc ess es to t he PCI 9080 c an b e By te,
Word, or Longword (Lword) accesses. All memory
commands are aliased to the basic memory commands.
All I/O accesses to the PCI 9080 are decoded to an
Lword boundary. The byte enables are used to
determine which bytes are read or written. An I/O access
with illegal by te ena ble c omb inations is terminated with a
Target Abort.
2.1.2 PCI Master Command Codes
The PCI 9080 can access the PCI Bus to perform DMA
transfers or Direct Master Local-to-PCI Bus transfers.
During the Direct Master or DMA transfer, the command
code assigned to the PCI 9080 Internal regis ter location,
(CNTRL[15:0], is us ed as th e PC I command code . Tab le
2-2 through Table 2-5 lists the various PCI Master
Command codes.
Notes: Programmable Internal registers determine
PCI command codes when the PCI 9080 is Master.
DMA cannot perform I/O or Configuration accesses.
2.1.2.1 DMA Master Comma nd Codes
DMA controllers of the PCI 9080 can generate the
Memory cycles listed in Table 2- 2.
Table 2-2. DMA Master Command Codes
Command Type Code (C/BE[3:0]#)
Memory Read 0110 (6h)
Memory Writ e 0111 (7h)
Memory Read Multiple 1100 (Ch)
Memory Read Line 1110 (Eh)
Memory Write and Invalidate 1111 (Fh)
2.1.2.2 Direct Local-to-PCI
Command Codes
For direct Local-to-PCI Bus accesses, the PCI 9080
generates the cycles listed in Table 2-3 through
Table 2-5.
Table 2-3. Local-to-PCI Memory Access
Command Type Code (C/BE[3:0]#)
Memory Read 0110 (6h)
Memory Writ e 0111 (7h)
Memory Read Multiple 1100 (Ch)
Memory Read Line 1110 (Eh)
Table 2-4. Local-to-PCI I/O Access
Command Type Code (C/BE[3:0]#)
I/O Read 0010 (2h)
I/O Write 0011 (3h)
Table 2-5. Local-to-PCI Configuration Access
Command Type Code (C/BE[3:0]#)
Configurati on M emory Read 1010 (Ah)
Configurati on M emory Writ e 1011 (Bh)
2.1.3 PCI Arbitration
The PCI 9080 asserts output REQ# to request the
PCI Bus. The PCI 9080 can be programmed using
MARBR[23] to de-assert REQ# when it asserts FRAME#
during a Bus Master cycle, or to keep REQ# asserted for
the entire Bus Master cycle. The PCI 9080 always de-
asserts REQ# for a minimum of two PCI clocks between
Bus Master ownership that includes a Target disconnect.
Section 2
Bus Operation Local Bus Cycles
PCI 9080 Data Book v1.06
8PLX T e c hn ology, Inc. All r ights r e s e rved
The Direct Master Write Delay bits (DMPBAM[15:14])
can be programmed to delay assertion of the PCI 9080
PCI REQ# signal during a Direct Master Write cycle.
This register can be programmed to wait 0, 4, 8, or 16
PCI Bus clocks after the PCI 9080 has received its first
Write data from the Local Master and is ready to begin
the PCI Write transaction. This feature is useful in
applications where the Local Master is bursting and the
Local Bus clock is slower than the PCI Bus clock. This
allows Write data to accumulate in the Direct Master
Write FIFO of the PCI 9080, which provides for better
utilization of the PCI Bus.
2.2 Local Bus Cycles
The PCI 9080 connects a PCI Host bus to several Local
process or bus types, as liste d in Table 2-6. It o perates in
one of three modes, selected through mode pins 9 and
10, corresponding to three bus types—C, J, and S.
Table 2-6. Local Processor Bus Types
Bit 9 Bit 10 Mode Bus Type
0 0 C 32-bit nonmultipl exed
0 1 J 32-bit multipl exed
1 0 S 16-bit multipl exed
11Reserved—
2.2.1 Local Bus Arbitration
When the P C I 9080 owns the Local Bus , both its L H OLD
output and LHOLDA input are asserted. When the
PCI 9080 samples that BREQ is asserted during a DMA
transfer or Direct Slave Write transfer, it gives up the
Local Bus within two Lword transfers by de-asserting
LHOLD and floating its Local Bus outputs if:
• BREQ is gated or disabled; or
• Gating is enabled and the Local Bus Latency
Timer expires
The Local Arbiter can now grant the Local Bus to
another Local Master. After the PCI 9080 samples that
its LHOLDA is de-asserted an d its Local Pause Timer is
zero, it re-asserts LHOLD to request the Local Bus.
When the PCI 9080 receives LHOLDA, it drives the bus
and continues from where it left off.
2.2.2 Local Bus Direct Master
Local Bus cycles can be Continuous Single or Burst
cycles (programmable by way of the PCI 9080 Internal
registers). As a Local Bus Target, the PCI 9080 allows
access to it s Internal registers and th e PCI Bus.
In C and J modes, Local Bus Direct Master accesses to
the PCI 9080 must be for a 32-bit nonpipelined bus.
In S mode, Local Bus Direct Master accesses to the
PCI 9080 must be for a 16-bit nonpipelined bus.
2.2.3 Local Bus Direct Slave
PCI Bus Master Read/Write to Local Bus (the PCI 9080
is a PCI Bus Target and Local Bus Master).
2.2.3.1 Ready/Wait State Control
PCI
9080
Accessing PCI 9080
from PCI Bus
PCI 9080 de-asserts
TRDY# when waiting
on the Local Bus
PCI Bus de-asserts
IRDY# or simply end the
cycle when it’s not ready
PCI 9080
Accessing PCI Bus
PCI 9080 can be
programmed
to de-assert IRDY#
when its FIFOs are on
a Direct Master Read
PCI Bus de-asserts
TRDY# when it’s
not ready
Accessing PCI 9080
from Local Bus
PCI 9080 generates READYo
#
when data is valid on
the following clock edge
Local Processor
generates wait states
with WAITI#
PCI 9080
Accessing Local Bus
PCI 9080 generates wait
states with WAITO#
(programmable)
Local Bus can respond
to PCI 9080 requests with
READYi#
Figure 2-1. Wait St ates
Note: The fig ure represents a sequence of Bus cycles.
If READYi# input is disabled, the external READYi#
input has no effect on w a it states for a l oc al ac c ess . Wait
states between Data cycles are generated internally by
a wait state counter. Wait state counter is initialized with
its Configuration register value at the start of each
data access.
If READYi# is enabled, READYi# has no effect until the
wait state counter is 0. READYi# then controls the
number of additional wait states.
BTERM# inp ut is not s a mp led unt il the wai t s tate c oun ter
is 0. BTERM# overrides READYi# when BTERM#
is asserted.
Section 2
Local Bus Cycles Bus Operation
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 9
2.2.3.1.1 Wait State—Local Bus
With Direct Master mode and accessing the PCI 9080
registers (PCI 9080 local as Slave):
• PCI 9080 generates wait states with READYo#
• Local processor generates wait states with WAITI#
With Direc t Slave and DM A modes (PC I 9 080 Local Bus
as Master):
• The PCI 9080 generates wait states with WAITO#
• Local processor generates wait states with READYi#
• Use LBRD0[21:18, 5:2], DMAMODE0[5:2], and
DMAMODE1[5:2] to program the number of
wait states
2.2.3.1.2 Wait State—PCI Bus
When the wait state occurs on the PCI Bus, Master
throttles IRDY# and Slave throttles TRDY#.
2.2.3.2 Burst Mode and Continuous Burst
Mode (Bterm “Burst Terminate” Mode)
Table 2-7. Burst and Bterm on the Local Bus
Mode Burst Bterm Result
Single Cycle 0 0 One ADS# per data (default)
Single Cycle 0 1 Still one ADS# per data
Burst-4 1 0 One ADS# per four data
(use this mode for i960)
Burst Forever 1 1 One ADS# per BTERM#
On the Local Bus, BLAST# and BTERM# perform
the following:
• If burst is enabled (LBRD0[26,24] for non-DMA,
DMAMODE0[8] and DMAMODE1[8] for DMA), but
Bterm mode is disabled (LBRD0[7], DMAMODE0[7]
and DMAMODE1[7]), then the PCI 9080 bursts four
Lwords. BLAST# is generated at the fourth Lword
(LA[3:2]=11), new ADS# at the first Lword
(LA[3:2]=00) of the next burst.
• If BTERM# sampling is enabled and BTERM# is
low, the PCI 9080 forces a new ADS#, but does
not generate a new BLAST# signal.
• BTERM# input is valid only when the PCI 9080 is the
Master of the Local Bus (Direct Slave or
DMA modes).
• BTERM# is generated by external logic. It is input
to the PCI 9080 (and i960) and used to tell the
PCI 9080 (and i960) to break up a Burst cycle.
• BTERM# is used,
for example
, to signal that a
Memory access is crossing the page boundary.
On the PCI Bus, burst is always enabled.
Notes: If Bterm is disabled, the PCI 9080 performs
the following:
•
32-bit Local Bus—Burst up to four Lwords
•
16-bit Local Bus—Burst up to two Lwords
•
8-bit Local Bus—Burst up to one Lword
In every case, it performs four transactions.
In the following sections, Bterm refers to the PCI 9080
Internal register bit. BTERM# refers to the PCI 9080
external signal.
2.2.3.2.1 Burst Mode
If bursting is enabled and BTERM# in put is not enab led,
bursting can start on any boundary and continue up to
an address boundary, as described in Table 2-8. After
the data at the boundary is transferred, the PCI 9080
generates a new Address cycle (ADS#).
Table 2-8. Burst Mode
Bus Mode Burst
C, J 32-bit bus—Four Lwords or up to a quad Lword
boundary (LA3, LA2 = 11)
C, J 16-bit bus—Four words or up to a quad word
boundary (LA2, LA1 = 11)
C, J 8-bit bus—Four bytes or up to a quad byte
boundary (LA1, LA0 = 11)
S16-bit bus—Eight words or up to a quad Lword
boundary (LA3, LA2 = 11)
Section 2
Bus Operation Local Bus Cycles
PCI 9080 Data Book v1.06
10 PLX T e c hn ology, Inc. All r ights r e s e rved
2.2.3.2.2 Continuous Burst Mode
(Bterm “Burst Terminate” Mode)
Bterm mode enables the PCI 9080 to perform long
bursts to dev ices that can acc ept longer than four Lword
bursts. The PCI 9080 generates one Address cycle and
continues to burst data. If a device requires a new
Address cycle after a certain address boundary, it can
assert BTERM# input to cause the PCI 9080 to generate
a new Address cycle. BTERM# input acknowledges the
current Data transfer and requests that a new Address
cycle be generated ( ADS#). This address is used for the
next Data transfer. If Bterm mode is enabled, the
PCI 9080 asserts BLAST# only if its FIFOs become full
or empty, or if a transfer is complete.
Note: If BTERM # is ass erte d, BLA ST# does not as sert
until the previously described conditions are met.
2.2.3.2.3 Partial Lword Accesses
Lword accesses in which not all byte enables are
asserted are broken into Single Address and Data
cycles, as listed in Table 2-9.
Table 2-9. Partial Lword Accesses
Register Value for LBRD0
Burst Enable Bterm Enabl e
Result
(Number of Transfers)
0 0 Single Cycle (Def ault)
0 1 Single Cycle
1 0 Burst four Lwords at a time
1 1 Continuous Burst Mode
2.2.3.3 Recovery States
In J and S modes, the PCI 9080 inserts one recovery
state between the last Data transfer and next Address
cycle.
The PCI 9080 does not support the 80960J feature of
using READYi# input to add recovery states. No
additional recovery states are added if READYi# input
remains asserted during the last Data cycle.
2.2.3.4 Local Bus Read Accesses
For all Single Cycle Local Bus Read accesses,
the PCI 9080 reads only bytes corresponding to byte
enables requested by the PCI initiator. For all
Burst Cycle Bus Read accesses, the PCI 9080 reads
only Lwords.
2.2.3.5 Local Bus Write Accesses
For Local Bus writes, only the bytes specified by a
PCI Bus Master or the PCI 9080 DMA controller are
written. Access to an 8- or 16-bit bus results in the
PCI Bus Lword being broken into multiple Local Bus
transfers. For each transfer, the byte enables are
encoded as in the 80960C to provide Loc al Address bits
LA[1:0].
2.2.3.6 Direct Slave Write Accesses—8- and
16-Bit Buses
A Direct PCI access to an 8- or 16-bit bus results in the
PCI Bus Lword being broken into multiple Local Bus
transfers. For each transfer, the byte enables are
encoded as in the 80960C to provide Loc al Address bits
LA[1:0].
2.2.3.7 Local Bus Data Parity
There is one data parity pin for each byte lane of the
PCI 9080 data bus (DP[3:0]). Even data parity is
generated for each lane during L ocal Bus re ads fr om the
PCI 9080 and during PCI 9080 Master writes to the
Local Bus.
Even data parity is checked during Local Bus writes to
the PCI 9080 and during PCI 9080 reads from the Local
Bus. Parity is checked for each byte lane with an
asserted byte enable. PCHK# is asserted in the Clock
cycle following the data being checked if a parity error
is detected.
Generation or use of Local Bus data parity is optional.
Signals on data parity pins do not affect operation of
the PCI 9080. PCI Bus parity checking and generation
is independent of Local Bus parity checking
and generation.
Section 2
Local Bus Cycles Bus Operation
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 11
2.2.3.8 Local Bus Big/Little Endian
PCI Bus is a Little Endian bus (
that is
, data is Lword
aligned to the lowermost byte lane). Byte 0 (address 0)
appears in AD[7:0], Byte 1 appears in AD[15:8], Byte 2
appears in AD[23:16] and Byte 3 appears in AD[31:24].
The PCI 9080 Local Bus can be progr ammed to o perate
in Big or Little Endian mode, as listed in Table 2-10.
Table 2-10. Big/Little Endian Program Mode
BIGEND# Pin Register
1=Big, 0=Little Endian
00Big
01Big
1 0 Little
11Big
For Configuration cycles, refer to BIGEND[0]. For Direct
Master, Memory, and I/O cycles, refer to BIGEND[1]. For
Direct Slave cycles, refer to BIGEND[2], Space 0, and
BIGEND[3], Expansion ROM.
In Big Endian mode, the PCI 9080 transposes data byte
lanes. Data is trans ferred as listed in T able 2-1 1 through
Table 2-15.
2.2.3.8.1 32
-
Bit
Local Bus—Big Endian
Mode
Data is Lword aligned to the uppermost byte lane. Byte
lanes and burst orders are listed in Table 2-11 and
illustrated in Figure 2-2.
Table 2-11. Upper Lword Lane Transfer
Burst Order Byte Lane
Byte 0 appears on Local Data [31:24]
Byte 1 appears on Local Data [23:16]
Byte 2 appears on Local Data [15:8]
First Transfer
Byte 3 appears on Local Data [7:0]
Little Endian
Big Endian
BYTE 3
BYTE 0
BYTE 2
BYTE 1
BYTE 1
BYTE 2
BYTE 0
BYTE 3
31
0
0
31
Figure 2-2. Big/Little Endian—32-Bit Local Bus
2.2.3.8.2 16-Bit Local Bus—Big
Endian Mode
For a 16-bit Local Bus, the PCI 9080 can be
programmed to use the upper or lower word lane.
Byte lanes and burst order are listed in Table 2-12 and
Table 2-13 and illustrated in Figure 2-3.
Table 2-12. Upper Word Lane Transfer
Burst Order Byte Lane
Byte 0 appears on Local Data [31:24]First Transfer
Byte 1 appears on Local Data [23:16]
Byte 2 appears on Local Data [31:24]Second Transfer
Byte 3 appears on Local Data [23:16]
Table 2-13. Lower Word Lane Transfer
Burst Order Byte Lane
Byte 0 appears on Local Data [15:8]First Transfer
Byte 1 appears on Local Data [7:0]
Byte 2 appears on Local Data [15:8]Second Transfer
Byte 3 appears on Local Data [7:0]
Section 2
Bus Operation Local Bus Cycles
PCI 9080 Data Book v1.06
12 PLX T e c hn ology, Inc. All r ights r e s e rved
Little Endian
Big Endian
Big Endian
BYTE 3 BYTE 2
BYTE 0 BYTE 1
BYTE 1 BYTE 0
BYTE 0 BYTE 1
31 0
First Cycle
Second Cycle
31
15 16
0
31
15 16
0
Figure 2-3. Big/Little Endian—16-Bit Local Bus
2.2.3.8.3 8-Bit Local Bus—Big Endian Mode
For an 8-bit Local Bus, the PCI 9080 can be
programmed to use the upper or lower byte lane.
Byte lanes and burst order are listed in Table 2-14 and
Table 2-15 and illustrated in Figure 2-4.
Table 2-14. Upper Byte Lane Transfer
Burst Order Byte Lane
First transfer Byte 0 appears on Local Data [31:24]
Second transfer Byte 1 appears on Local Data [31:24]
Third transfer Byte 2 appears on Local Data [31:24]
Fourth transfer Byte 3 appears on Local Data [31:24]
Table 2-15. Lower Byte Lane Transfer
Burst Order Byte Lane
First Transfer Byte 0 appears on Local Data [7:0]
Second Transfer Byte 1 appears on Local Data [7:0]
Third Transfer Byte 2 appears on Local Data [7:0]
Fourth Transfer Byte 3 appears on Local Data [7:0]
Little Endian
Big Endian
BYTE 3 BYTE 2
BYTE 0
BYTE 0
BYTE 1 BYTE 0
BYTE 0
BYTE 0
31 0
First Cycle
Second Cycle
Third Cycle
Fourth Cycle
31
7 24
0
31
7 24
0
31
7 24
0
31
7 24
0
Figure 2-4. Big/Little Endian—8-Bit Local Bus
For each of the following transfer types, the PCI 9080
Local Bus can be independe ntly progra mmed to operate
in Little Endian or Big Endian mode:
• Local Bus accesses to the PCI 9080
Configuration registers
• Direct Slave PCI accesses to Local Address
Space 0
• Direct Slave PCI accesses to Local Address
Space 1
• Direct Slave PCI accesses to Expansion ROM
• DMA Channel 0 accesses to the Local Bus
• DMA Channel 1 accesses to the Local Bus
• Direct Master accesses to PCI Bus
For Local Bus Configuration accesses, an input pin can
be used to dynamically change the Endian mode.
Notes: The PCI Bus is always Little Endian mode.
Only byte lanes are swapped, not individual bits.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 13
3. FUNCTIONAL DESCRIPTION
Functional operation described can be changed or
modified, depending on the register configuration.
3.1 Reset
3.1.1 PCI Bus Input RST#
PCI Bus RST# input pin is a PCI Host reset. It causes all
PCI Bus outputs to float, resets the entire PCI 9080 and
causes the local reset output, LRESETo#, to be
asserted. If you have a PCI Host (PCICR[2:0]), Master
Enable, Memory Space, I/O Space is programmed by
the host after initialization is complete (CNTRL[31]=1).
(Refer to Figure 3-1.)
PCI Reset
Serial EEPROM
Initialization
Local Processor
Configures PCI 9080
Local Processor
Sets CNTRL[3]
Local Init = Done
Host Configures
PCI 9080
Figure 3-1. Reset and Initialization Process
3.1.2 Software Reset LRESETo#
When asserted, the LRESETo# Software Reset
CNTRL[30] resets the PCI 9080 Local Configuration and
Local DMA registers. However, it does not reset the
PCI Configuration and Shared Runtime registers. When
the bit is set, the PCI 9080 responds to PCI accesses,
but not to local accesses. The PCI 9080 remains in this
condition until PCI Host clears the bit. The serial
EEPROM is reloaded if CNTRL[29] is set.
3.1.3 Local Bus Input LRESETi#
When asserted, the LRESETi# input resets the Local
Bus portio n of the PCI 908 0, c le ars al l l ocal c o nfi gur at ion
and DMA registers and causes LRESETo# output to be
asserted.
3.1.4 Local Bus Output LRESETo#
LRESETo# is asserted when PCI Bus RST# input is
asserted, the LRESETi# input is asserted, or the
Software Reset bit in the Init Control register is set to 1.
3.1.5 Software Reset
A host on the PCI Bus can set the software Software
Reset bit in the Init Control re gister t o r eset t he PCI 9080
and assert the LRESETo# output. All Local
Configuration and DMA registers reset. PCI
Configuration registers do not reset. When the Software
Reset bit is s et, th e P CI 9080 res p onds t o P CI acces ses ,
but not t o Local access es. The PCI 908 0 remains in this
reset condition until the PCI Host clears the bit.
Note: The Local Bus cannot clear this reset bit
because the Loc al Bus is in a reset state.
3.2 PCI 9080 Initialization
The PCI 9080 Configuration registers can be
programmed by an optional s erial EEPROM and/or by a
Local processor, as listed in Table 3-1. The serial
EEPROM can be reloaded by setting CNTRL[29].
In general, the PCI 9080 retries all PCI cycles until the
Local Init Done bit is set or until NB# is low.
Note: The PCI Host processor can also access the
internal Configuration register after power-on.
Section 3
Functional Description Serial EEPROM
PCI 9080 Data Book v1.06
14 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 3-1. NB# and Serial EEPROM Guidelines
NB# Serial
EEPROM System Boot Co ndition
No Boot with PCI 9080 default v al ues.
Programmed Boot with serial EEPROM values.
Low
Blank Not recommended (us es default
values).
No Local processor programs t he
PCI 9080 registers, then sets Local Init
Status (CNTRL[31] = done).
Note: Some systems hang if Direct
Slave reads and writes take too long
(during initialization, the PCI Host also
performs Direc t Slave accesses). Value
of PCI Target Retry Delay Clocks
(LBRD0[31: 28] ) may res olv e this
problem.
Programmed Load serial EEPROM, but Local
processor c an reprogram t he
PCI 9080.
High
Blank Load serial EEPROM (default values ),
but Local process or can reprogram the
PCI 9080. The system can boot.
Note: The serial EEPROM can be
programmed through t he PCI 9080
after system boots in this condition.
3.2.1 Serial EEPROM Initialization
During serial EEPROM initialization, the PCI 9080
response to PCI Target accesses is Retry. During serial
EEPROM initialization, the PCI 9080 response to a Local
processor is to hold off READYo#.
3.2.2 Local Initialization
The PCI 9080 issues a Retry to all PCI accesses until
the Local Init Done bit in the Init Control register is set.
The Init Done bit is programmable through Local Bus
Configuration accesses. If this bit is not going to be set
by a Loca l process or, then NB# i nput s hould be tie d low.
Holding NB# input low externally forces the Local Init
Done bit to 1.
The PCI 9080 default values are used if a serial
EEPROM is not present and Local Init Status bit is set
to 1 by holding the NB# input low or set by the
Local processor.
3.3 Serial EEPROM
After reset, the PCI 9080 attempts to read the serial
EEPROM to determine its presence. An active low start
bit indicates the serial EEPROM is present (the
PCI 9080 supports 93CS46 (1K) or 93CS56 (2K),
selectable by way of the EESEL pin). (Refer to
manufacturer’s data sheet for particular serial EEPROM
being used.) The first word is then checked to verify the
serial EEPROM is programmed. If the first word (16 bit)
is all ones, a blank serial EEPROM the PCI 9080 uses
default values instead.
The 5V s eria l EE PRO M c loc k (EE S K, p in 173) is der iv ed
from the PCI clock. The PCI 9080 generates the serial
EEPROM clock by internally dividing the PCI clock
by 32.
The serial EEPROM can be read or programmed from
the PCI or Local Bus. Bits [27:24] of the Seri al EEPRO M
Control register (CNTRL[27:24]) control the PCI 9080
pins that ena ble the r ead ing or writ in g of s erial E EPR OM
data bits. (Refer to manufacturer’s data sheet for
particu lar ser ia l EEPRO M be ing us ed.)
The PCI 9080 has three serial EEPROM load options:
• Short Load Mode—SHORT# input pin is pulled
down and the PCI 9080 loads five Lwords from the
serial EE PR OM
• Long Load Mode—SHORT# input pin is pulled up,
bit 25 of the Local Bus Region Descriptor Register is
set to 0, and the PCI 9080 loads 17 Lwords from the
serial EEPROM (LBRDO[25])
• Extra Long Load Mode—SHORT# input pin is
pulled up, bit 25 of the Local Bus Region Descriptor
Register is set to 1 during Long Load from the serial
EEPROM, and the PCI 9080 loads 21 Lwords from
the serial EEPROM (LBRDO[25])
Section 3
Serial EEPROM Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 15
3.3.1 Short Serial EEPROM Load
The registers listed in Table 3-2 are loaded from serial
EEPROM after reset is de-asserted if SHORT# pin is
low. The serial EEPROM is organized in 16-bit words.
The PCI 9080 first loads MSW (Most Significant Word;
bits [31:16]), starting from the most significant bit [31].
The PCI 9080 then loads LSW (Least Significant Word;
bits [15:0]), starting again from the most significant bit
[15]. Therefore, the PCI 9080 loads Device ID, Vendor
ID, class code, and so forth. The five 32-bit words are
stored sequentially in the serial EEPROM.
Table 3-2. Short Ser ial EEPROM Load Registers
Serial
EEPROM
Offset
Description Sample
Serial
EEPROM
Value
0h Device ID 9080
2h Vendor ID 10B5
4h Class Code 0680
6h Class Code, Revis i on 0002
8h Maximum Latency, Mini m um Grant 0000
Ah Int errupt Pin, Interrupt Line Routing 0100
Ch MSW of Mailbox 0 (User Defined) xxxx
Eh LSW of Mailbox 0 (User Defined) xxxx
10h MSW of Mailbox 1 (User Defined) xxxx
12h LSW of Mailbox 1 (User Defined) xxxx
3.3.2 Long Serial EEPROM Load
The registers listed in LBRD0 are loaded from serial
EEPROM after reset is de-asserted if SHORT# pin is
high. The serial EEPROM is organized in 16-bit words.
The PCI 9080 first loads MSW (Most Significant Word;
bits [31:16]), starting from the most significant bit [31].
The PCI 9080 then loads LSW (Least Significant Word;
bits [15:0]), starting again from the most significant bit
[15]. Therefore, the PCI 9080 loads Device ID, Vendor
ID, class code, and so forth.
The serial EEPROM value can be entered into a DATA
I/O programmer in the order shown below. The values
shown are examples and must be modified for each
particular application. The 34 16-bit words listed in the
table are stored sequentially in the serial EEPROM.
Section 3
Functional Description Serial EEPROM
PCI 9080 Data Book v1.06
16 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 3-3. Long Serial EEPROM Load Registers
Serial EEPROM Offset Description
0h Device ID
2h Vendor ID
4h Class Code
6h Class Code, Revision
8h Maximum Latency, Minimum Grant
Ah Interrupt Pin, Interrupt Line Routing
Ch MSW of Mailbox 0 (User Defined)
Eh LSW of Mailbox 0 (User Defined)
10h MSW of Mailbox 1 (User Defined)
12h LSW of Mailbox 1 (User Defined)
14h MSW of Range for PCI-to-Local Address Space 0
16h LSW of Range for PCI-to-Local Address Space 0
18h MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0
1Ah LSW of Local Base Address (Remap) for PCI-t o-Local Address Spac e 0
1Ch MSW of Local Arbitration Register
1Eh LSW of Local Arbitrati on Register
20h MSW of Local Bus Big/Little Endian Descript or Register
22h LSW of Local Bus Big/Little Endian Descri ptor Regist er
24h MSW of Range for PCI-to-Local Expansion ROM
26h LSW of Range for PCI-to-Local Expansion ROM
28h MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM
2Ah LSW of Local Base Address (Remap) for PCI-to-Local Ex pansion ROM
2Ch MSW of Bus Region Descriptors for PCI-to-Local Accesses
2Eh LSW of Bus Region Descript ors for PCI-t o-Local Accesses
30h MSW of range for Direct Master to PCI
32h LSW of range for Direct Master to PCI
34h MSW of Local Base Address for Direct M aster t o PCI Memory
36h LSW of Local Base Address for Direct Master to PCI Memory
38h MSW of Local Bus Address for Direct Master to PCI IO/CFG
3Ah LSW of Local Bus Address for Direct Master to PCI IO/CFG
3Ch MSW of PCI Base Address (Remap) for Direct Master to PCI
3Eh LSW of PCI Base Address (Rem ap) for Direct Mast er to PCI
40h MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG
42h LSW of PCI Configuration Address Register for Direct Mast er to PCI IO/CFG
Section 3
Internal Register Access Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 17
3.3.3 Extra Long Serial EEPROM Load
An Extra Long Load mode is provided in the PCI 9080
(LBRDO) to load an additional five Lwords from the
serial EEPROM. If bit 25 is set to 1 in the Local Bus
Region Descriptor register (LBRDO), the following five
Lword registers are loaded in addition to normal Long
Load process (refer to Section 3.3.2, “Long Serial
EEPROM Load”). Bit 25 must be set to 1 during the
Long Load Process. (Refer to Table 3-4.)
Table 3-4. Extra Long Serial EEPR OM
Load Registers
Serial
EEPROM
Offset
Description
44 Subsystem ID
46 Subsystem Vendor ID
48 MSW of Range for PCI-to-Local Address Space 1
(1 MB)
4A LSW of Range for PCI-to-Loc al Address Space 1
(1 MB)
4C MSW of Local Base Address (Remap)
for PCI-to-Local Address Space 1
4E LSW of Local Base Address (Remap)
for PCI-to-Local Address Space 1
50 MSW of Bus Region Descriptors (S pace 1)
for PCI-to-Local accesses
52 LSW of Bus Region Descriptors (S pace 1)
for PCI-to-Local accesses
54 MSW of PCI Base Address for Local
Expansion ROM
56 LSW of PCI Base Address for Local Expansion
ROM
3.3.4 Recommended Serial EE PROMs
A 1K-bit (National NM93CS46 or compatible) or 2K-bit
(National NM93CS56 or compatible) device can be
used. Table 3-5 lists the recommended serial EEPROM
loads. Refer also to Table 5-2 in Section 5,
“Pin Description.”
Table 3-5. Recommended Serial EEPROM Loads
Load Unused Bytes for
CS46 (1K bit) Unused Bytes for
CS56 (2K bit)
Short 108 236
Long 60 188
Extra Long 40 168
Note: The PCI 9080 does not support serial
EEPROMs t hat do n ot support seq uentia l read a nd write
(such as the NM93C46 or NM93C56).
3.3.5 Programming the Serial EEPROM
The serial EEPROM can be written or read, using bits
[28:24] of the Serial EEPROM Control register
(CNTRL[28:24]).
3.4 Internal Register Access
The PCI 9080 chip provides several Internal registers,
allowing for maximum flexibility in bus interface design
and performanc e. The reg ister ty pes ar e acces sible from
both the PCI and Local Buses, including the following:
• PCI Configuration registers
• Local Config ur ati on regis ter s
• Mailbox registers
• Doorbell registers
• DMA registers
• Messaging queue registers (I2O)
Figure 3-2 illustrates how these registers are accessed.
Set
Clear
Local
Bus
Master
PCI
Bus
Master
Local Configuration
Registers
PCI Configuration
Registers
DMA Registers
PCI 9080
Mailbox Registers
PCI-to-Local
Doorbell Register
LocalPCI
Doorbell Register
-to-
Messaging
Queue Registers
Set
Clear
PCI Interrupt
Local Interrupt
Figure 3-2. PCI 9080 Internal Register Access
Section 3
Functional Description Internal Register Access
PCI 9080 Data Book v1.06
18 PLX T e c hn ology, Inc. All r ights r e s e rved
3.4.1 PCI Bus Access to Internal Registers
The PCI 9080 PCI Configuration registers can be
accessed from the PCI Bus with a Type 0 Configuration
cycle.
The PCI 9080 Internal registers can be accessed by a
Memory cycle, with the PCI Bus address that matches
the base address specified in the PCI Base Address 0
for Memory-Mapped Configuration register of the
PCI 9080. They can also be accessed by an I/O cycle,
with the PCI Bus address matching the base address
specified in the PCI Base Address 1 for the I/O-Mapped
Configuration register of the PCI 9080.
All PCI Read or Write accesses to the PCI 9080
registers can be Byte, Word, or Lword accesses. All
PCI Memory accesses to the PCI 9080 registers can be
Burst or Non-burst. The PCI 9080 responds with a
PCI Disconnect for all Burst I/O accesses to the
PCI 9080 registers.
3.4.2 Local Bus Access to
Internal Registers
The Loca l proces sor c an acces s all the Int ernal r egister s
of the PCI 9080 through either internal or external
address decode logic. The PCI 9080 provides an
Address Decode Mode Pin (ADMODE) that selects
whether the in ternal addres s decode log ic is used or the
designer supplies an external chip select from an
external address decoder. Figure 3-3 illustrates how dual
address decode logic works.
If the Address Decode Mode pin is set to 1, internal
PCI 9080 addres s decode logic is enabl ed. In th is m ode,
the PCI 9080 Internal registers are selected when Local
Address bits LA[31:29] match input address select pins
S[2:0]. If the Address Decode Mode pin is set to 0, the
PCI 9080 responds to Local Bus access when S0 is
asserted low through external chip select logic.
Notes: S0 must be decoded while ADS# is low.
If ADMODE is 1 LA[31:29], specify 512 MB of Local
Memory space allocated for accessing Internal registers.
All Local Read or Write accesses to the PCI 9080
registers can be Byte, Word, or Lword accesses. All
Local accesses to the PCI 9080 registers can be Burst
or Non-burst.
For C and J modes, accesses must be for a 32-bit
nonpipelined bus. The PCI 9080 READYo# indicates a
Data transfer is complete.
For S mode, ac cesses mus t be for a 16-b it nonpipelin ed
bus. The PCI 9080 READYo# indicates a Data transfer
is complete.
LA31
LA30
LA29
S2
S1
S0
Address Decode Mode Pin
10
PCI 9080
Internal Register
Chip Select
PCI 9080
Internal Register
Chip Select
PCI 9080
=
PCI 9080
compare S0
(PCI 9080
Chip Select)
Figure 3-3. Dual Address Decode Mode
Section 3
Response to Full and Empty FIFOs Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 19
3.5 Response to Full and Empty FIFOs
Table 3-6 lists the response of the PCI 9080 to full and empty FIFOs.
Table 3-6. Response to Full and Empty FIFOs
Mode Direction FIFO PCI Bus Local Bus
Full No action De-as sert READYo#Direct Master Write Local-to-PCI
Empty De-assert REQ# (off PCI Bus) No action
Full De-assert REQ# or throttle IRDY# No actionDirect Master Read PCI-to-Local
Empty No action De-assert READYo#
Full Disconnect or throttle TRDY# No actionDirect Slave Write PCI-to-Local
Empty No action De-assert LHOLD, assert BLAST#
(see Note)
Full No action De-assert LHOLD, assert BLAST#
(see Note)
Direct Slave Read Local-to-PCI
Empty Throttle TRDY# No action
Full No action De-assert LHOLD, assert BLAST#Local-to-PCI
Empty De-assert REQ# No action
Full De-assert RE Q# No action
DMA
PCI-to-Local
Empty No action De-assert LHOLD, ass ert BLAST#
Note: De-assertion of LHOLD depends on MARBR[21].
3.6 Direct Data Transfer Modes
Figure 3-4 and Figure 3-5 illustrate the direct Data
Transfer modes. Refer also to Table 3-6 for responses to
full and empty FIFOs.
PLX or
System
Chipset
Host CPU Physical
System
Memory
Local
Memory
or I/O
PCI Bus
• Address Translation
• DMA, Memory, I/O Cycle
s
• Interrupts
• Software Protocol
Local CPU
PLX
Host CPU accesses Local Memory or I/O = Direct Slave read/write
Local CPU accesses System Memory = Direct Master read/write
PCI 9080 read/write from System Memory and write/read to
Local memory = DMA read/write
Figure 3-4. Direct Master, Direct Slave, and DMA
Set Clear
Clear Set
Doorbell registers set
and clear interrupts
Mailbox registers can be read
and/or written from both sides
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Mailbox 5
Mailbox 6
Mailbox 7
PCI-to-Local
Local-to-PCI
Used for Passing
• Commands
• Pointers
• Status
Local
Bus Local
Bus
PCI
Bus PCI
Bus
Figure 3-5. Mailbox/Doorbell Message Passing
Section 3
Functional Description Direct Data Transfer Modes
PCI 9080 Data Book v1.06
20 PLX T e c hn ology, Inc. All r ights r e s e rved
3.6.1 Direct Master Operation (Local Master
to PCI Target)
The PCI 9080 supports direct access of the PCI Bus by
the Local processor or an intelligent controller. Master
mode must be enabled in the PCI Command register.
Five registers are used to define Local-to-PCI access:
• Range
• Local Base Ad dres s for Direct Master to
PCI Memory Register
• Local Base Ad dres s for Direct Master to PCI IO/CFG
Register
• PCI Configuration Address Register for Direct
Master to PCI IO/CFG
• PCI Base Address
3.6.1.1 Decode
The Range register specifies the Local Address bits to
use for decoding a Local-to-PCI access. The Local
processor can perform only Memory cycles. Therefore,
the Local Base Address for Direct Master to PCI Memory
register is used to decode an access to PCI memory
space. The Local Base Address for Direct Master to
PCI IO/CFG register is used to decode an access to
PCI I/O space or PCI Bus Configuration cycle access.
3.6.1.2 FIFOs
For Direct Master Memory access to the PCI Bus, the
PCI 9080 has a 32-Lword (128 byte) Write FIFO and a
16-Lword (64 byte) Read FIFO. The FIFOs enable the
Local Bus to operate independently of the PCI Bus and
allows high-performance bursting on the Local and
PCI Buses. In a D irec t M as ter Wr ite, the Loc a l proc es s or
(Master) writes data to the PCI (Slave). In a Direct
Master Read, the Local processor (Master) reads data
from the PCI (Slave). Figure 3-6 and Figure 3-7 illustrate
the FIFOs during a Direct Master Write and Read.
PCI
9080
Slave Master
Master Slave
REQ#
GNT#
FRAME#, C/BE#
AD (addr)
IRDY#
DEVSEL#, TRDY#
AD (data)
LA, ADS#, LBE#,
LD, LW/R#, BLAST#
READYo#
PCI Bus
Local Bus
Figure 3-6. Direct Master Write
PCI
9080
Slave Master
Master Slave
REQ#
GNT#
FRAME#, C/BE#,
AD (addr)
IRDY#
DEVSEL#, TRDY#,
AD (data)
LA, ADS#, LW/R#
Local Bus
LD, READYo#
BLAST#
PCI Bus
Figure 3-7. Direct Master Read
Note: The figures rep resent a sequen ce of Bus cycl es.
Section 3
Direct Data Transfer Modes Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 21
3.6.1.3 Memory Access
The Local processor can read or write to the
PCI memory. The PCI 9080 converts the Local
Read/Write access. The Local Address space starts
from the Direct Master Local Base Address up to the
range. Remap (PCI Base Address) defines the
PCI starting address.
Writes—The PCI 9080 continues to accept writes and
returns READYo# until the Write FIFO is full. It then
holds off READY o# until space becomes av ailable i n the
Write FIFO. A programmable Direct Master FIFO “almost
full” status output is provided (DMPAF#).
Reads—The PCI 9080 holds off READYo# while
gathering an Lword from the PCI Bus. Programmable
Prefetch modes are available if prefetch is enabled:
prefetch, 4, 8, 16, or continuous until the Direct Master
cycle ends. The Read cycle is terminated when the
Local BLAST# input is asserted. Unused Read data is
then flushed from the FIFO.
The PCI 9080 does not prefetch Read data for Single
Cycle Direct Mast er re ads (Loc al BLA ST# in put as serted
during first Data phase). In this case, the PCI 9080 reads
a single PCI Lword.
For Direct Master Single Cycle reads, the PCI 9080
asserts the same PCI Bus byte enables as asserted on
the Local Bus.
For Multiple Cycle reads, the PCI 9080 reads entire
Lwords (all PCI byte enables are asserted), regardless
of local byte enables.
If the Prefetch Limit bit DMPBAM[11] is enabled, the
PCI 9080 does not prefetch past a 4 K B boundary . Also,
the Local Bus must not cross a 4 KB boundary during a
Burst read.
The PCI 9080 never prefetches beyond the region
specified for Direct Master accesses.
3.6.1.4 IO/CFG Access
When a Local Direct Master I/O access to the PCI Bus is
made, the Configuration Enable bit of the
PCI Configuration Address register determines if I/O or
Configuration access is to be made to the PCI Bus.
Local Burst accesses are broken into Single PCI I/O
Address/Data cycles. The PCI 9080 does not prefetch
Read data for I/O and CFG reads.
For Direct Master I/O or Configuration cycles, the
PCI 9080 asserts the same PCI Bus byte enables as
asserted on the Local Bus.
3.6.1.5 I/O
If the Configuration Enable bit is clear, a single I/O
access is made to the PCI Bus. The Local Address,
remapped decode address bits and the local byte
enables are encoded to provide the address and is
output with an I/O Read or Write command during the
PCI Address cycle.
For writes, data is loaded into the Write FIFO and
READYo# returned to the Local Bus. For reads, the
PCI 9080 holds off READYo# while gathering an Lword
from the PCI Bus.
When the I/O Remap Select bit is set to a value of 1,
these PCI Address bits [31:16] ar e forced t o a value of 0
(DMPBAM[13]).
3.6.1.6 CFG (PCI Configuration Type 0 or
Type 1 Cycles)
If the Configuration Enable bit is set, a CFG access is
made to the PCI Bus. In addition to enabling the
Configurat ion bit of DMCFG A[31], the user must provide
all register information. The register number (bits [7:2])
or the device number (bits [15:11]) must be m odifie d and
a new CFG Read/Write cycle must be performed before
other registers or devices can be accessed.
If the PCI Configuration Address register selects a
Type 0 command, bits [10:0] from the register are copied
to address bits [10:0]. Bits [15:11] (device number) are
translated into a single bit being set in PCI Address bits
[31:11]. PCI Address bits [31:11] can be used as a
device select. For a Type 1 command, bits [23:0] are
copied from the register to bits [23:0] of the PCI Address.
PCI Address bits [31:24] are 0. A Configuration Read or
Write command code is output with the address during
the PCI Address cycle (DMCFGA).
For writes, Local data is loaded into the Write FIFO and
READYo# is r eturned. For r eads, the PCI 9080 holds off
READYo# while gathering an Lword from the PCI Bus.
Section 3
Functional Description Direct Data Transfer Modes
PCI 9080 Data Book v1.06
22 PLX T e c hn ology, Inc. All r ights r e s e rved
Example 1 —To perform a Type 0 Configuration cycle to
PCI devi ce on AD [21]:
1. The PCI 9080 must be configured to allow Direct
Mast er access to the PCI Bus. The PCI 9080
must also be set to respond to I/O Space accesses.
Set PCICR[2,0] as follows:
• Bit 0 = I/O Space = 1
• Bit 2 = Master Enable = 1
2. The board designer selects the Direct Master range.
For this example, use a range of 1 MB:
• 1 MB = 220 = 000FFFFFh
The value to program into the range register is the
inverse of 000FFFFFh, which is FFF00000h:
• DMRR = FFF00000h
3. The board designer determines local Base Address
for Direct Master to PCI IO/CFG. For this example,
use 40000000h:
• DMLBAI = 400000 00h
4. The PCI Address (Remap) for Direct Master to
PCI Memory register must enabl e Direct Master
I/O access. Set DMPBAM[1] as follows:
• Bit 1 = Direct Master I/ O Access E nable = 1
5. The PCI Bus must know which PCI device and
PCI Configuration register the PCI Configuration
cycle is accessing. For this example, access the
PCI device on AD[21], as well as PCIBAR0, the
PCI Base Address 0 for Memory-Mapped
Configuration register (the fourth register, counting
from 0—use Table 4-5, “PCI Configuration
Registers,” for reference). Set DMCFGA[31, 23:0]
as follows:
• Bits 1:0 = Configuration Type 0 = 00b
• Bits 7:2 = Register Number = The fourt h
register, and ther ef ore mus t pro gram a 4
into this bit, beginning with bit 2 = 000100b
• Bits 10:8 = Function Number = 000b
• Bits 15:11 = Device Number =
n
-11, where
n
is the value in AD[
n
]=21-11 = 10 = 01010b
• Bits 23:16 = Bus Number = 00000000b
• Bit 31 = Configura t io n Enabl e = 1
The Register Number (bits [7:2]) or Device Number
(bits [15:11]) must be modified and a new CFG
Read/Write cycle must be performed before other
registers or devices can be accessed.
3.6.1.7 Direct Bus Master Lock
The PCI 9080 supports direct Local-to-PCI Bus
exclusiv e access es (locked at omic operati ons). A loc ked
operation must start with the Local Bus input LLOCK#
being asserted during a Direct Master Bus Read cycle.
Refer to the timing in Section 8, “Timing Diagrams.”
3.6.1.8 Master/Target Abort
The PCI 9080 Master/Target abort logic enables a Local
Bus Master to perform a Direct Master Bus poll of
devices to determine w hether the dev ices exis t (typically
when the Loca l Bus performs Conf iguration cycles to the
PCI Bus).
If a PCI Master, Target Abort, or Retry Time-out is
encountered during a transfer, the PCI 9080 asserts
LSERR# if enabled (INTCSR[1:0]) (can be used as an
NMI). If the Local Bus Master is waiting f or a READYo#,
it is asserted along with BTERMo#. The Local Master’s
interrupt handler can take the appropriate application
specific action. It can then clear the Abort bits in the
PCI Status Configuration register (PCISR) to clear the
LSERR# inter rupt and re- enable Direct Mas ter trans fer s.
If a Local Bus Master is attempting a Burst read from a
nonresponding PCI device (Master/Target abort), it
receives the READYo# and BTERMo# for the first cycle
only. If the Local processor cannot terminate its Burst
cycle, it may cause the Local processor to hang. The
Local Bus must then be reset from the PCI Bus or by a
local watchdog timer asserting RESETi#. If the Local
Bus Master cannot terminate its cycle with BTERMo#, it
should not perform Burst cycles when attempting to
determine whether a PCI device exists.
3.6.1.9 Write and Invalidate
The PCI 9080 ca n be programm ed to perf orm Write and
Invalidate cycles to the PCI for DMA and Direct Master
transfers. The PCI 9080 supports Write and Invalidate
transfers for cache line sizes of 8 or 16 Lwords. T he size
is specif ied in the PCI Cac he Line Size re gister. If a s ize
other than 8 or 16 is specified, the PCI 9080 performs
Write transfers rather than Write and Invalidate transfers.
Section 3
Direct Data Transfer Modes Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 23
3.6.1.9.1 DMA Write and Invalidate
DMA Write and Invalidate transfers are enabled when
the Write and Inva lidate Enable bit of a DMA c ontroll er is
set in its Mode register and the Memory Write and
Invalidate Enable bit is set in the PCI Command register.
In Write and Invalidate mode, the PCI 9080 waits until
the number of Lwords required for the specified cache
line size have been read from the Local Bus before
starting the PCI access. This ensures that a complete
cache line write can be completed in one PCI Bus
ownership. If a Targ et dis connec ts befor e a c ach e line is
completed, the PCI 9080 completes the remainder of
that cache line using normal writes before resuming
Write and Invalidate transfers. If a Write and Invalidate
cycle is in progress, the PCI 9080 continues to burst if
another cache line has been read from the Local Bus
before the cycle completes. Otherwise, the PCI 9080
terminates the burst and waits for the next cache line to
be read from the Local Bus. If the final transfer is not a
complete cache line, the PCI 9080 completes the DMA
transfer, using normal writes.
3.6.1.9.2 Direct Master Write and Invalidate
Direct Master Wr ite and Invalidate transfers are enabled
when the Invalidate Enable bit is set in the PCI Base
Address (Remap) register for Direct Master to
PCI Memory and the Memory Write and Invalidate
Enable bit is set in the PCI Command register (PCICR).
In Write and Invalidate mode, if the start address of the
Direct Master transfer is on a cache line boundary, the
PCI 9080 waits until the number of Lwords required for
specified cache line size have been written from the
Local Bus before starting PCI Write and Invalidate
access. This ensures that a complete cache line write
can be completed in one PCI Bus ownership. If the start
address is not on a cache line boundary, the PCI 9080
starts a normal PCI Write access. The PCI 9080
terminates a cycle at a cache line boundary if it is
performing a normal write or if it is performing a Write
and Invalidate cycle and another cache line of data is not
available. If an entire cache line is available by the time
the PCI 9080 regains use of the PCI Bus, the PCI 9080
resumes Write and Invalidate cycles. Otherwise, it
continues with a normal write. If a Target disconnects
before a cache line is completed, the PCI 9080
completes the remainder of that cache line using
normal writes.
Section 3
Functional Description Direct Data Transfer Modes
PCI 9080 Data Book v1.06
24 PLX T e c hn ology, Inc. All r ights r e s e rved
PCI Bus
Master Local
Processor
FIFOs
32 LW Deep Write
16 LW Deep Read
Local Range for Direct Master to PCI
Local Base Address for Direct Master to PCI Memory
PCl Base Address (Remap) for Direct Master to PCI
Local Base Address for Direct Master to PCI IO/CFG
PCI CFG Address Register for Direct Master to PCI IO/CFG
PCI Command Register
1
Initialize
Local
Direct
Master
Access
Registers
Local Bus
Access
PCI Bus
Access
CFG or I/O
0 = I/O
1 = CFG CFG Type
if CFG
Enabled
32
Local Base
Address for Direct
Master to PCI
Memory Space
PCI Address
Space
PCI Base
Address Local Base
Address for
Direct Master to
PCI IO/CFG
Local
Memory
Memory
Command
I/O
Command
Range
Range
CFG Address Register
0 = I/O
1 = CFG
PCI CFG
Command
Type 0 or 1
Local Base Address
for Direct Master
to PCI Memory Space
Bit 13 = 1 PCI I/O
LA[31:16] = 0
Figure 3-8. Local Master Direct Master Access of PCI Bus
Section 3
Direct Data Transfer Modes Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 25
3.6.2 Direct Slave Operation (PCI Master to
Local Bus Access)
The PCI 9080 supports both Burst Memory-Mapped
Transfer accesses and I/O-Mapped, Single-Transfer
accesses to the Local Bus from the PCI Bus. PCI Base
Address registers are provided to set up the location of
the adapter in PCI memory and I/O space. In addition,
local mapping registers allow address translation from
PCI Address space to Local Address Space. Three
spaces are available:
• Space 0
• Space 1
• Expansion ROM space
Expansion RO M s pace is inten ded to s upport a boota ble
ROM device for the host. Each Local space can be
programmed to operat e 8-, 1 6, or 32-bit Local Bus w idth .
The PCI 9080 has an internal wait state generator and
external wait state input, READYi#, which can be
disabled or enabled with the Internal Configuration
register. The Local Bus, independent of the PCI Bus,
can:
• Burst as long as data is available
Continuous Burst (mode)
• Burst four Lwords at a time
• Perform continuous single cycle,
with or without wait state(s)
For Single Cycle Dir ect Slav e reads, the PCI 9080 re ads
a single Loca l Bus Lwor d or partia l Lword. T he P CI 9080
disconnects after one transfer for all Direct Slave
I/O accesses.
For the highest Data transfer rate, the PCI 9080
supports posted writes and can be programmed to
prefetch data during PCI Burst reads. The prefetch size,
when enabled, can be from one to 16 Lwords, or until
the PCI stops requesting. The PCI 9080 prefetches,
if enabled, and drops the Local Bus after the Prefetch
Counter is reached. In Continuous Prefetch mode, the
PCI 9080 prefetches as long as any FIFO space
is available and terminates the prefetch when the
PCI terminates the request. If Read prefetching
is disabled, the PCI 9080 disconnects after one
Read transfer.
3.6.2.1 PCI 2.1 Mode
The PCI 9080 can be programmed through the Local
Arbitration and PCI Mode register to perform delayed
reads, as specified in PCI Specification v2.1.
Spec v2.1 mode
set in
Internal registers
Data stored
in 16 Lword
Internal FIFO
PCI 9080 returns
prefetched data
immediately
PCI Bus Local Bus
PCI Read request
PCI 9080 tells
Host to “Retry”
Read cycle later
PCI Bus is free to
perform other
cycles during
this time
PCI host returns to
fetch Read data again
Read data is now
ready for the Host
PCI 9080 requests
Read data from
Local Bus
Local memory
returns requested
data to PCI 9080
Figure 3-9. PCI Specification v2.1 Delayed Reads
Note: The fig ure represents a sequence of Bus cycles.
In addition to delayed read, the PCI 9080 supports the
following PCI Specification v2.1 features:
• No write while read is pending (Retry for reads)
• Write and flush pending read
The PCI 9080 also supports Read Ahead mode (refer to
Figure 3-10), where prefetched data can be read from
the internal PCI 9080 FIFO instead of from the Local
Bus. The address must be subsequent to the previous
address and must be 32-bit aligned (next address =
current address + 4).
Section 3
Functional Description Direct Data Transfer Modes
PCI 9080 Data Book v1.06
26 PLX T e c hn ology, Inc. All r ights r e s e rved
PCI 9080
PCI Bus Local Bus
PCI Read request
Read data
Read data
PCI Master read
returns with
“Sequential Address”
PCI 9080 prefetches
data from
Local Bus device
Read Ahead mode
set via
Internal register
Prefetched data
stored in
Internal FIFO
PCI 9080 returns
prefetched data
immediately from
Internal FIFO
without reading again
from Local Bus
PCI 9080 prefetches
more data if FIFO
space is available
PCI 9080 prefetches
more data from
Local memory
Figure 3-10. PCI 9080 Read Ahead Mode
Note: The fig ure represents a sequence of Bus cycles.
The PCI 9080 can be programmed to keep the PCI Bus
by generating a wait state(s), thereby de-asserting
TRDY#, if the Write FIFO becomes full. The PCI 9080
can also be progra mmed to k eep the Local B us, ther eby
asserting LHOLD, if the Direct Slave Write FIFO
becomes emp ty or the Dir ect Slave Read FIFO becomes
full. The Local Bus is dropped in either case when the
Local Bus Latency Timer is enabled and expires. (Refer
to Figure 3-11 and Figure 3-12.)
For Direct Slave writes, the PCI (Master) writes data to
the Local Bus (Slave). Direct Slave is the “Command
from the PCI Host,” which has the hig hest priority . Direct
Slave or Direct Master pre-empts DMA; however, Direct
Slave does not pre-empt Direct Master (refer to Section
3.6.2.3.1, “Backoff”).
PCI
9080
LA, ADS#, LW/R#
IRDY#, AD (data)
PCI Bus
Local Bus
LHOLD
LHOLDA
READYi#
DEVSEL#, TRDY#
FRAME#, C/BE#,
AD (addr)
Slave Master
Master Slave
LD, BLAST#
Figure 3-11. Direct Slave Write
PCI
9080
LA, ADS#, LW/R#,
BLAST#
TRDY#, AD (data)
PCI Bus
LHOLD
LHOLDA
READYi#, LD
DEVSEL#
FRAME#, C/BE#,
AD (addr)
IRDY#
Slave Master
Master Slave
PCI Bus
Local Bus
Figure 3-12. Direct Slave Read
Note: The figures rep resent a sequen ce of Bus cycl es.
For Direct Slave r eads , t he P CI (Mas ter ) r eads d ata from
the Local Bus (Slave).
The PCI 9080 supports on-the-fly Endian conversion for
Space 0, Space 1, and Expansion ROM space. The
Local Bus can be Big/Little Endian by either using the
BIGEND# input pin or the programmable internal register
configuration. When BIGEND# is asserted, it overrides
the internal register configuration.
Note: The PCI Bu s is always Little Endian.
Section 3
Direct Data Transfer Modes Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 27
3.6.2.2 PCI-to-Local Address Mapping
Note: Not applicable if I
2
O mode.
Three Local Address spaces—Space 0, Space 1, and
Expansion ROM—are accessible from the PCI Bus.
Each is defined by a set of three registers:
• Local Addres s Range
• Local Base Ad dres s
• PCI Base Address
A fourth reg ister, Bus Region D escriptor for PCI-to- Local
Accesses, defines the Local Bus character istics for both
regions (refer to Figure 3-13).
3.6.2.2.1 Byte Enables
LBE[3:0]# (pins 139-142) are encoded based on the
configured bus width, as follows:
32-Bit Bus—For a 32-bit bus, the four byte enables
indicate which of the f our bytes are act ive during a Data
cycle.
• BE3# Byte Enable 3—LD[31:24]
• BE2# Byte Enable 2—LD[23:16]
• BE1# Byte Enable 1—LD[15:8]
• BE0# Byte Enable 0—LD[7:0]
16-Bit Bus—For a 16-bit bus, BE3#, BE1# and BE0#
are encoded to provide BHE#, LA1, and BLE#,
respectively.
• BE3# Byte High Enable (BHE#)—LD[15:8]
• BE2# not used
• BE1# Address bit 1 (LA1)
• BE0# Byte Low Enable (BLE#)— LD[7:0]
8-Bit Bus—For an 8-bit bus, BE1# and BE0# are
encoded to provide LA1 and LA0, respectively.
• BE3# not used
• BE2# not used
• BE1# Address bit 1 (LA1)
• BE0# Address bit 0 (LA0)
Each PCI-to-Local Address space is defined as part of
reset initialization as described in the next section.
3.6.2.2.2 Local Bus Initialization Software
Range—Specifies which PCI Address bits to use for
decoding a PCI access to Local Bus space. Each
Prefetch Limit bit corresponds to a PCI Address bit. Bit
31 corresponds to Addr ess bit 31. Write 1 to all bits that
must be included in decode and 0 to all others.
Remap PCI-to-Local Addresses into a Local Address
Space—Bits in this register remap (replace) the PCI
Address bits used in decode as the Local Address bits.
Local Bus Region Descriptor—Specifies the Local Bus
characteristics.
3.6.2.2.3 PCI Initialization Software
PCI reset software det ermi nes how m uch ad dress space
is required by writing a value of all ones (1) to a
PCI Base Address register and then reading back the
value. The PCI 9080 return zeroes in Don’t Care
Address bits, effectively specifying the address space
required. The PCI software then maps the Local Address
space into the PCI Address space by programming the
PCI Base Address register. (Refer to Figure 3-13.)
Section 3
Functional Description Direct Data Transfer Modes
PCI 9080 Data Book v1.06
28 PLX T e c hn ology, Inc. All r ights r e s e rved
PCI Bus
Master Local
Processor
FIFOs
32 LW Deep Write
16 LW Deep Read
Range for PCI-to-Local Address Space 0
Local Base Address (Remap) for PCI-to-Local Address Space 0
Bus Region Descriptors for PCI-to-Local Accesses
Range for PCI-to-Local Expansion ROM
Local Base Address (Remap) for PCI-to-Local Expansion ROM
PCI Base Address to Local Address Space 0
Bus Region Descriptors for PCI-to-Local Accesses
PCI Base Address to Local Expansion ROM
1
Initialize Local
Direct Access
Registers
Initialize PCI
Base Address
Registers
PCI Address
Space
PCI Base
Address
Local Bus
Access
Local
Memory
Local Base
Address
Range
PCI Bus
Access
Local Bus
Hardware
Characteristics
34
2
Figure 3-13. Direct Slave Access of Local Bus
Section 3
Direct Data Transfer Modes Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 29
Example 2—A 1 MB Local Address Space 12300000h
through 123FFFFFh is accessible from the PCI Bus at
PCI Addresses 78900000h throu gh 789FFFFFh.
a. Local initialization software sets the Range and
Local Base Ad dres s register s , as follows :
• Range—FFF00000h (1 MB, decode the upper
12 PCI Address bits)
• Local Base Address (remap)—123XXXXXh
(Local Base Address for PCI-to-Local accesses)
(bit 0, the Space Enable bit, must be set to 1 to
be recognized by the Host)
b. PCI Initialization software writes all ones to the
PCI Base Address, then reads it back again.
• The PCI 9080 returns a value FFF00000h.
The PCI software then writes to PCI Base
Address register
• PCI Base Address—789XXXXXh (PCI Base
Address for access to Local Address Space)
For PCI direct access to the Local Bus, the PCI 9080
has a 32-Lword (128 byte) Write FIFO and a 16-Lword
(64 byte) Read FIFO. The FIFOs enable the Local Bus
to operate independently of the PCI Bus. The PCI 9080
can be programmed to return a Retry response or to
throttle TRD Y# f or any PCI Bus trans act ion att emp tin g to
write to the PCI 9080 Local Bus when the FIFO is full.
For PCI Read trans acti ons from the PC I 9080 L oc al Bus ,
the PCI 9080 holds off TRDY# while gathering the Local
Bus Lword to be returned. For Read accesses mapped
to the PCI memory space, the PCI 9080 prefetches up to
16 Lwords (has Continuous Prefetch mode) from the
Local Bus. Unused Read data is flushed from the FIFO.
For Read accesses mapped to the PCI I/O space, the
PCI 9080 does not prefetch Read data. Rather, it breaks
each read of the Burst cycle into a Single Address/Data
cycle on the Local Bus.
The period of t im e th e P CI 9080 hol ds off TR DY # c an be
programmed (the Target Retry Timer) in the Local Bus
Region Descriptor register (LBRD0). The PCI 9080
issues a Retry to the PCI Bus transaction Master when
the programmed time period expires. This occurs when
the PCI 9080 cannot gain control of the Local Bus and
return TRDY# within the programmed time period.
3.6.2.3 Deadlock and BREQo
Deadlock can occur when a Master on the PCI Bus
wants to access the PCI 9080 Local Bus at the same
time a Master on the PCI 9080 Local Bus requires
access to the PCI Bus. Two types of deadlock situations
can occur:
• Partial Deadlock—Master on Local Bus is
performing a direct Bus Master access to a PCI Bus
device other than the PCI Bus device concurrently
trying to access the Local Bus.
• Full Deadlock—Master on Local Bus is performing
a direct Bus Master access to the same PCI Bus
device concurrently trying to access the Local Bus.
This applies only to Direct (“pass through”) Master and
Slave accesses through the PCI 9080. Deadlock does
not occur in transfers through the PCI 9080 DMA
controller or the mailboxes.
For partial deadlock, the PCI access to the Local Bus
times out (the Target Retry Timer, which is
programmable through the Local Bus Region Descriptor
register for PCI-to-Local accesses) and the PCI 9080
responds with a PCI Retry. PCI specification requires
that a PCI Master release its request for the PCI Bus
(de-asserts RE Q#) for a mi nimum of two PCI clocks after
receiving a Retry. This allows the PCI Bus arbiter to
grant the PCI Bus to the PCI 9080 so that it can
complete its Direct Master access and free up the Local
Bus. Possible solutions are described below for cases in
which the PCI Bus arb iter does n ot f unc tion as des c ribed
(PCI Bus architecture dependent), waiting for a time-out
is undesirable, or a full deadlock condition exists.
For full deadlock, the only solution is to back off the
Local Master.
Section 3
Functional Description Direct Data Transfer Modes
PCI 9080 Data Book v1.06
30 PLX T e c hn ology, Inc. All r ights r e s e rved
3.6.2.3.1 Backoff
The PCI 9080 contains a pin (BREQo) that indicates a
possible deadlock condition exists. The PCI 9080 starts
the BREQo timer (programmable through registers)
when it detects the following conditions:
• A Master on the PCI Bus is trying to access memory
or an I/O device on the Local Bus and is not gaining
access (
for example
, LHOLDA not received).
• A Master on the Local Bus is performing a direct Bus
Master Read access to the PCI Bus or a Master on
the Local Bus is performing a direct Bus Master
Write access to the PCI Bus and the PCI 9080
Direct Master Write FIFO cannot accept another
Write cycle.
If the timer expires and the PCI 9080 has not received
the LHOLDA signal, the PCI 9080 asserts BREQo.
External bus logic can use this as a signal to perform
Backoff.
A Backoff cycle is device/bus architecture dependent.
External logic (arbiter) can assert the necessary signals
to cause the Local Master to release the Local Bus
(Backoff) . After backing off the Local Master , it ca n grant
the bus to the PCI 9080 (by asserting LHOLDA).
Once BREQo is asserted, READYo# for the current Data
cycle is never asserted (the Local Bus Master must
perform Backoff). When the PCI 9080 detects LHOLDA,
It proceeds with the PCI Master to Local Bus access.
When this access is complete and the PCI 9080
releases the Local Bus, the external logic can release
Backoff and the Local Master can resume the cycle
interrupted by the Backoff cycle. The Write FIFO of the
PCI 9080 retains all the data it has acknowledged (
that
is
, the last data for which READYo# was asserted).
After the Backoff condition ends, the Local Master
restarts the last cycle with ADS#. For writes, the data
following this ADS# should be the data that was not
acknowledged by the PCI 9080 prior to the Backoff cycle
(for instance, the last data for which there was no
READYo# asserted).
If a PCI Read cycle is completed when the Local Bus is
backed off, the Local Bus Master receives that data if
Local Master restarts the same last cycle (data is not
read twice). A new read is performed, if the resumed
Local Bus cycle is not the same as the backed-off cycle.
3.6.2.3.2 Software/Hardware Solution for
Systems without Backoff Capability
For adapters that do not support Backoff, a possible
deadlock solution is as follows.
PCI Host software, external Local Bus hardware, general
purpose output USERO and general purpose input
(USERI) can be used by PCI Host software to prevent
deadlock. USERO can be set to request that the external
arbiter not grant the bus to any Local Bus Mas ter except
the PCI 9080. A status output from the local arbiter can
be connected to general-purpose input USERI to
indicate that no Local Bus Master owns the Local Bus.
The PCI Host to determine that no Local Bus Master
currently owns the Local Bus can read the input. PCI
Host can then perform a Direct Slave access. When the
host is done, it clears USERO. For devices that support
pre-empt, USERO can be used to pre-empt the current
Bus Master device. The current Local Bus Master device
completes its current cycle and gives up the Local Bus
(de-asserts LHOLD).
3.6.2.3.3 Software Solutions to Deadlock
PCI Host software and Local Bus software can use a
combination of mailbox registers, doorbell registers,
interrupts, direct Local-to-PCI accesses and direct
PCI-to-Local accesses to avoid deadlock.
3.6.2.4 Direct Slave Lock
The PCI 9080 supports direct PCI-to-Local Bus
exclusive accesses (locked atomic operations). A
PCI locked operation to Local Bus results in the entire
address Space 0, Space 1 and Expansion ROM space
being locked until they are released by the PCI Bus
Master. The PCI 9080 asserts LLOCKo# during the first
clock of an atomic operation (Address cycle) and de-
asserts it a minimum of one clock , following the last Bus
access for the atomic operation. LLOCKo# is de-
asserted after the PCI 9080 detects PCI FRAME# and
PCI LOCK# de-asserted at the same time. Refer to the
timing diagr ams in Sect ion 8, “Timin g Diagra ms.” Locked
operations are enabled or disabled with the Local Bus
Region Descriptor register for PCI-to-Local accesses.
It is the responsibility of external arbitration logic to
monitor the LLOCKo# pin and enforce the meaning for
an atomic operation.
For example
, if a Local Master
initiates a locked operat ion, the local arbi ter may choose
to not grant use of the Local Bus to other Masters until
the locked operation is complete.
Section 3
DMA Operation Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 31
3.6.3 Direct Slave Priority
Direct Slave accesses have higher priority than DMA
accesses.
Direct Slave accesses pre-empt DMA transfers. When
the PCI 9080 DMA controller owns the Local Bus, its
LHOLD output and LHOLDA input are asserted and its
LDSHOLD output is de-asserted. When a Direct Slave
access occurs, the PCI 9080 gives up the Local Bus
within two Lword transfers by de-asserting LHOLD and
floating its Local Bus outputs. After the PCI 9080
samples its LHOLDA input de-asserted, it requests the
Local Bus for a Direct Slave transfer by asserting
LHOLD and LDSHOLD. When the PCI 9080 receives
LHOLDA, it driv es t he b us an d per f orms the Dir ec t Slave
transfer. Upon completion of the Direct Slave transfer,
the PCI 9080 gives up the Local Bus by de-asserting
both LHOLD and LDSHOLD and floating its Local Bus
outputs. After the PCI 9080 samples its LHOLDA de-
asserted an d its loca l paus e tim er is z ero, it reques ts the
Local Bus for a DMA transfer by re-asserting LHOLD.
When it receives LHOLDA, it drives the bus and
continues with the DMA transfer.
3.7 DMA Operation
The PCI 9080 supports two independent DMA channels
capable of transferring data from the Local Bus to the
PCI Bus or from the PCI Bus to the Local Bus. Each
channel consists of a DMA controller and a
programmable FIFO. Both channels support Chaining
and Non-chaining transfers, Demand mode DMA, and
End of Transfer (EOT) pins. Master mode must be
enabled in the PCI Command register.
3.7.1 Non-Chaining Mode DMA
The host processor or the Local processor sets the Local
Address, PCI Address, transfer count and transfer
direction. The host or Local processor then sets a control
bit to initiate the transfer. The PCI 9080 arbitrates the
PCI and Local Buses and transfer data. Once the
transfer is complete, the PCI 9080 sets the Channel
Done bit to a value of 1 and gen er ates an interr up t to the
Local processor or the PCI Host (programmable). DMA
Done bit in the internal DMA register can be pooled to
indicate the status of DMA transfer.
DMA registers are accessible from the PCI Bus and
Local Bus. (Refer to Figure 3-14.)
PCI Host
Memory
Memory Block
to Transfer
Memory Block
to Transfer
Local
Memory
Mode Register
PCI Address Register
Local Address Register
Transfer Size (byte count) Register
Descriptor Pointer Register
(set direction only)
Command/Status Register
Set DMA Mode
to Non-Chaining
Set up Transfer
Parameters
Set the Enable and
Go bits in the DMA
Command/Status Register
to Initiate DMA Transfer
Figure 3-14. Non-Chaining DMA Initialization
Section 3
Functional Description DMA Operation
PCI 9080 Data Book v1.06
32 PLX T e c hn ology, Inc. All r ights r e s e rved
The Local processor or PCI requires DMA. The
PCI 9080 is Master on both the PCI and Local Buses.
Direct Slave or Direct Master pre- emp ts DMA.
The PCI 9080 releases the PCI Bus if one of the
following occurs (refer to Fi gu re 3-15):
• FIFO is full
• Terminal count is reached
• PCI Latency Timer (PCILTR[7:0]) expires—
normally programmed by the Host PCI BIOS—
and PCI GNT# de-asserts
• PCI Host asserts STOP
• Direct Master request pending
PCI
9080
LA, ADS#, LW/R#,
BLAST#
DEVSEL#, TRDY#,
AD (data) LHOLD
LHOLDA
READYi#
Slave Master
Master Slave
DMA Start
DMA Start
REQ#
GNT#
IRDY#
FRAME#, C/BE#,
AD (addr)
PCI Bus
Local Bus
Figure 3-15. DMA, PCI-to-Local
Note: The figures rep resent a sequen ce of Bus cycl es.
The PCI 9080 releases the Local Bus if one of the
following occurs (refer to Fi gu re 3-16):
• FIFO is empty
• Terminal count is reached
• Local Bus Latency Timer (MARBR[7:0]) expires
• BREQ# input is asserted
• Direct Slave request is pending
PCI
9080
LA, ADS#, LW/R#
DEVSEL#, TRDY#
PCI Bus
Local Bus
LHOLD
LHOLDA
LD
DMA StartDMA Start
REQ#
GNT#
IRDY#
AD (addr & data)
Slave Master
Master Slave
Figure 3-16. DMA, Local-to-PCI
Section 3
DMA Operation Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 33
3.7.2 Chaining Mode DMA
In Chaining mo de DMA, th e Host Proc essor or th e Local
Processor sets up descriptor blocks in local or host
memory that are composed of a PCI Address, Local
Address, transfer count, transfer direction, and address
of the next descriptor block (refer to Figure 3-18). Host
or Local Pr ocess or th en sets up the a ddress of the in itial
descriptor block in the Descriptor Pointer register of the
PCI 9080 and initiates the transfer by setting a control
bit. The PCI 9080 loads the first descriptor block and
initiates the Data transfer. The PCI 9080 continues to
load descriptor blocks and transfer data until it detects
the End of Chain bit is set in the Next Descriptor Pointer
register. The PCI 9080 can be programmed to interrupt
the Local processor by setting the Interrupt after
Terminal C ount bit or PCI Hos t upon comp letion of eac h
block transfer and after all block transfers are complete
(done) (refer to Figure 3-17). If chaining descriptors are
located in Local memory, the DMA controller can be
programmed to clear the transfer size at the completion
of each DMA (DMAMODE0[16] and DMAMODE1[16]).
Notes: In Chaining mode DMA, the descriptor includes
PCI Address, Loc al Address , Transfer Size and the Next
Descriptor Pointer (DMAPADR0-DMADPR0). The
Descriptor Pointer register contains the End of Ch ain bit,
Directio n of Tr ansfer, N ext Descr iptor Addr ess, an d Next
Descri ptor Location.
The DMA descriptor can be on Local or PCI memory, or
both (first descriptor on Local memory, and second
descriptor on PCI memory).
Set up First Descriptor
Pointer Register
(First only requires
Descriptor Pointer)
First PCI Address
First Memory Block
to Transfer
First Memory Block
to Transfer
Next Memory Block
to Transfer
Next Memory Block
to Transfer
Local or
Host
Memory
PCI Host
Memory
Mode Register
Set DMA Mode
to Chaining
Command/Status Register
Set the Enable and
Go bits in DMA
Command/Status Register
to Initiate DMA Transfer
First Local Address
First Transfer Size (byte count)
Next Descriptor Pointer
Descriptor Pointer Register PCI Address
Local Address
Transfer Size (byte count)
Next Descriptor Pointer
End of Chain
Specification Bit
Figure 3-17. Chaining DMA Initialization
Section 3
Functional Description DMA Operation
PCI 9080 Data Book v1.06
34 PLX T e c hn ology, Inc. All r ights r e s e rved
Read and Write Cycles continue...
PCI
9080
Setup chains DMA
for PCI-to-Local
PCI 9080 initiates read
from PCI Bus
PCI 9080 initiates read
from PCI Bus
PCI 9080 initiates read
from PCI Bus
PCI 9080 initiates read
from PCI Bus
PCI 9080 retrieves
chaining information
from Local memory
PCI 9080 retrieves
chaining information
from Local memory
PCI 9080 writes dat
a
to Local Bus
PCI 9080 writes dat
a
to Local Bus
PCI 9080 writes dat
a
to Local Bus
PCI 9080 writes dat
a
to Local Bus
Figure 3-18. Chaining Mode DMA from PCI-to-Local
Note: The fig ure represents a sequence of Bus cycles.
3.7.3 DMA Data Transfers
The PCI 9080 DMA controller can be programmed to
transfer data from the Local Bus side to the PCI Bus side
or from the PCI Bus side to the Local Bus side. Refer to
Figure 3-19 and Figure 3-20 for a description of the
operation.
Section 3
DMA Operation Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 35
3.7.3.1 Local-to-PCI Bus DMA Transfer
Local Bus Arbitration:PCI Bus Arbitration:
Releases control of PCI Bus
whenever FIFO becomes empty,
PCI latency timer expires and
PCI GRANT de-asserts, PCI
Disconnect is received, or Direct
Local-to-PCI Bus request is pending.
Rearbitrates for control of PCI Bus when
preprogrammed number of entries in FIFO
become available, or after two PCI clocks
if disconnect is received.
PCI
Arbitration Local Bus
Arbitration
FIFO
Unload FIFO with
PCI Bus
Write Cycles
Load FIFO with
Local Bus
Read Cycles
GNT# REQ# LHOLDA LHOLD
Chaining Mode Descriptors:
At start of each block transfer—
in Chaining mode only—loads DMA
registers by reading four Lwords
from address specified in
Next Descriptor Pointer register.
Chaining Mode Descriptors:
At start of each block transfer—in
Chaining mode only—loads DMA
registers by reading four Lwords
from address specified in
Next Descriptor Pointer register.
·
·
·
·
Local Interrupt Generation
(Programmable)
Done
Chaining: Terminal
Count for Current
Descriptor
PCI Interrupt Generation
(Programmable)
Done
Chaining: Terminal
Count for Current
Descriptor
Releases control of Local Bus whenever
FIFO becomes full, terminal count is
reached, Local latency timer expires,
BREQ input is asserted, or Direct
PCI-to-Local Bus request is pending.
Rearbitrates for control of Local Bus
when preprogrammed number of
empty entries in FIFO become
available. If Local latency timer has
expired, waits until pause timer expires.
Figure 3-19. Local-to-PCI Bus DMA Data Transfer Operation
3.7.3.2 PCI-to-Local Bus DMA Transfer
Local Bus Arbitration:PCI Bus Arbitration:
Releases control of PCI Bus
whenever FIFO becomes full,
terminal count is reached, PCI
latency timer expires and PCI GRANT
de-asserts, PCI Disconnect is received,
or Direct Local-to-PCI Bus request is pending.
Rearbitrates for control of PCI Bus when
preprogrammed number of empty entries
in FIFO become available, or after two
PCI clocks if disconnect is received.
PCI
Arbitration Local Bus
Arbitration
FIFO
Load FIFO with
PCI Bus
Read Cycles
Unload FIFO with
Local Bus
Write Cycles
Local Interrupt Generation
(Programmable)
Done
Chaining: Terminal
Count for Current
Descriptor
PCI Interrupt Generation
(Programmable)
Done
Chaining: Terminal
Count for Current
Descriptor
GNT# REQ# LHOLDA LHOLD
Releases control of Local Bus whenever
FIFO becomes empty, Local latency
timer expires, BREQ input is asserted, or
Direct PCI-to-Local Bus request is pending.
Rearbitrates for control of Local Bus
when preprogrammed number of
entries become available in FIFO or
PCI terminal count is reached. If Local
latency timer has expired, waits until
pause timer expires.
At start of each block transferin
Chaining mode only—loads DMA
registers by reading four Lwords
from address specified in
Next Descriptor Pointer register.
—
Chaining Mode Descriptors:
At start of each block transfer—in
Chaining mode only—loads DMA
registers by reading four Lwords
from address specified in
Next Descriptor Pointer register.
Chaining Mode Descriptors:
·
·
·
·
Figure 3-20. PCI-to-Local Bus DMA Data Transfer Operation
Section 3
Functional Description DMA Operation
PCI 9080 Data Book v1.06
36 PLX T e c hn ology, Inc. All r ights r e s e rved
3.7.3.3 Unaligned Transfers
For unaligned Local-to-PCI transfers, the PCI 9080
reads a p artial Lword fr om the Local Bus. It cont inues to
read Lwor ds from the Loc al Bus . Lwor ds are asse mbled,
aligned to the PCI Bus address and loaded into
the FIFO.
For PCI-to-Local transfers, Lwords are read from the
PCI Bus and loaded into the FIFO. On the Local Bus, the
Lwords are assembled from the FIFO, aligned to the
Local Bus addres s an d writ ten to t he Loc al Bus. O n both
the Local and PCI Buses, the byte enables for writes
determine LA[1:0] for the start of a transfer. For the last
transfer, the byte enables specify the by tes to be writ ten.
All reads are Lwords.
3.7.4 Demand Mode DMA
DMA Mode register bit 15 (BLAST mode for Demand
mode DMA), determines the number of Lwords
transferred after a DMA controllers DREQ[1:0]# input
is de-asserted.
If BLAST# ou tput is not re quired f or the last Lword of the
DMA transfer (bit 15 = 1), the DMA controller releases
the data bus after it receives an external READYi# or the
internal wai t state counter decre ments to a v alue of 0 for
the current Lword. If DMA controller is currently bursting
data, which is not the last Data phase for the burst,
BLAST# output is not asserted.
If BLAST# output is required for the last Lword of the
DMA transfer (bit 15 = 0), the DMA controller transfers
one or two Lwords. If DREQ[1:0]# is de-asserted during
the Address phase of the first transfer in a PCI 9080
Local Bus ownership (ADS#, LHOLDA asserted), the
DMA controller completes the current Lword. If
DREQ[1:0]# is de-asserted during any phase other than
the Address phase of the first transfer in a PCI 9080
Local Bus ownership, the DMA controller completes the
current Lword, and one additional Lword (this allows
BLAST# output to be asserted during the final Lword). If
the DMA FIFO is full or empty after the Data phase in
which DREQ[1:0]# is de-asserted, the second Lword is
not transferred. DREQ[1:0]# controls only the number of
Lword transfers. For an 8-bit bus, the PCI 9080 gives up
the bus after the last byte for the Lword is transferred.
For a 16-bit bus, the PCI 9080 gives up the bus after the
last word for the Lword is transferred.
3.7.5 DMA Priority
DMA Channel 0 priority, DMA Channel 1 priority, or
rotating priority can be specified in the DMA Arbitration
register.
3.7.6 DMA Arbitration
The PCI 9080 DMA controller releases control of the
Local Bus (de-asserts LHOLD) when one of the following
occurs:
• FIFOs are full in a Local-to-PCI transfer
• FIFOs are empty in a PCI-to-Local transfer
• Local Bus Late ncy Timer ex pires (if enabl ed)
• BREQ input is asserted (BREQ can be enabled or
disabled, or gated with a latency timer before the
PCI 9080 gives up the Local Bus)
• Direct Slave access is pending
• EOT input is received (if enabled)
The DMA controller releases control of the PCI Bus
when one of the following occurs:
• FIFOs are full or empty
• PCI Latency Timer expires and loses the
PCI GNT# signal
• Target Disconnect response is received
DMA controller de-asserts its PCI Bus request (REQ#)
for a minimum of two PCI clocks.
3.7.6.1 End of Transfer (EOT0# or
EOT1#) Input
DMA Mode register bit 15 (BLAST mode for EOT),
determines the number of Lwords transferred after a
DMA controller EOT[1:0]# input is asserted.
If BLAST# ou tput is not re quired f or the last Lword of the
DMA transfer (bit 15 = 1), the DMA controller releases
the data bus and terminates DMA after it receives an
external READYi# or the internal wait state counter
decrements to a value of 0 for the current Lword. If the
DMA controller is currently bursting data, which is not
the last Data phase for the burst, BLAST# output is not
asserted.
Section 3
Vendor and Device ID Registers Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 37
If BLAST# output is required for the last Lword of the
DMA transfer (bit 14 = 0), the DMA controller transfers
one or two Lwords. If EOT[1:0]# is asserted, the DMA
controller completes the current Lword, and one
additional Lword (this allows BLAST# output to be
asserted during the final Lword). If the DMA FIFO is full
or empty after the Data phase in which EOT[1:0]# is
asserted, the second Lword is not transferred.
The DMA controller terminates a transfer on an Lword
boundary after EOT[1:0]# is asserted. For an 8-bit bus,
the PCI 9080 terminates after the last by te for the Lword
is transferred. For a 16-bit bus, the PCI 9080 ter minates
after the last word for the Lword is transferred.
3.7.6.2 DMA Abort
A DMA transfer can be aborted. The abort process is
as follows:
1. DMA Channel must be enabled (DMACSR0[0]=1).
2. DMA Channel must be started (DMACSR0[1]=1).
3. Wait for the Channel Done bit to be set to zero
(DMACSR0[4]=0).
4. Disable the DMA Channel (DMACSR0[0] =0).
5. Abort DMA by programming the Channel Abort bit
(DMACSR0[2]=1).
6. Wait until the Channel Done bit is set
(DMACSR0[4]=1).
Note: One to two Data transfers occur after the Abort
bit is set. Aborting when no DMA cycles are in progress
causes the next DMA to abort.
3.7.6.3 Local Latency and Pause Timers
A Local Bus Latency Timer and Local Bus Pause Timer
are programmable with the DMA Arbitration register. If
the Local Latency Timer expires, the PCI 9080
completes the current Lword transfer and releases
LHOLD. After its programmable Pause Timer expires, it
reasserts LHOLD. When it receives LHOLDA, it
continues the transfer. The PCI Bus transfer continues
until the FIFO is empty for a Local-to-PCI transfer or until
it is full for a PCI-to-Local transfer.
3.8 Vendor and Device ID Registers
Three Vendor and Device ID registers are supported:
• PCIIDR, which contains the normal Device and
Vendor IDs. This register can be loaded from the
serial EEPROM or from Local processors.
• PCISVID, which contains the Subsystem and
Subvendor IDs. This register can be loaded from
the serial EEPROM or from Local processors.
• PCIHIDR, which contains the hardcoded PLX
Vendor and Device IDs.
3.9 Doorbell Registers
There are two 32-bit doorbell interrupt/status registers in
the PCI 9080. One is assigned to the PCI Bus interface
and the other is assigned to the Local Bus interface.
The Local processor can generate a PCI Bus interrupt
by writing any number other than all zeroes to the PCI-
to-Local Doorbell register (P2LDBELL).
A PCI Host can generat e a Loc al Bu s inter rupt by writ ing
any number other than all zeroes to the Local-to-
PCI Doorbell register (L2PDBELL).
3.10 Mailbox Registers
There are eight 32-bit mailbox registers in the PCI 9080
that can be written to and read from both buses. These
registers can be used to pass command and status
information directly between Local and PCI Bus devices.
A Local interru pt can be generate d, if enabled, whe n the
PCI Host writes to one of the first four mailbox registers.
3.11 User Input and Output
The PCI 9080 supports user input and output pins,
USERI[31] and USERO[27], respectively. User output
data can be logged by writing to CNTRL[16]. User input
data can be read from CNTRL[17].
Section 3
Functional Description Interrupts
PCI 9080 Data Book v1.06
38 PLX T e c hn ology, Inc. All r ights r e s e rved
3.12 Interrupts
LINTo#
DMA Ch 0 Done
DMA Ch 1 Done
Doorbells
Mailboxes
BIST
Messa
g
in
g
Queue
X9
X4
[17]
[7]
[23]
X2
OR
X3
X8
X6
OR
X7
OR
DMA Ch 1
Terminal Count
LSERR#
Master Abort
256 Retrys
Tar
g
et Abort
Parity Error
Messa
g
in
g
Queue
Doorbells
Master Abort
256 Retrys
Tar
g
et Abort
LINTi#
Messa
g
in
g
Queue
[1]
[0]
X1
OR
[12] OR
[9]
[10]
[11]
OR
[12] OR
X5
INTA#
DMA Ch 0 Done
DMA Ch 0
Terminal Count
X4
X2
OR
X3
DMA Ch 1 Done
X8
X6
OR
X7
DMA Ch 1
Terminal Count
DMA Ch 0
Terminal Count
[8]
[16]
The # represent the bit # of register (LOC [E8h])
X1 = Bits [7:6] of register (LOC [168h])
X2 = Bit 10 of register (LOC [100h])
X3 = Bit 2 of register (LOC [E110h])
X4 = Bit 18 of register (LOC [E8h]) & Bit 17 of register (LOC [100h])
X5 = Bits [5:4] of register (LOC [168h])
X7 = Bit 2 of register (LOC [124h])
X6 = Bit 10 of register (LOC [114h])
X8 = Bit 19 of register (LOC [E8h]) and Bit 17 of register (LOC [114h])
X9 = Bit 3 of register (LOC [B0h]) & Bit 3 of register (LOC [B4h])
For X4 and X8, if bit 17='0', then LINTo# is generated and
if bit 17='1', then INTA# is generated.
Figure 3-21. Interrupt and Error Sources
3.12.1 PCI Interrupts (INTA#)
A PCI 9080 PCI Interrupt (INTA#) can be generated by
one of the following:
• Local-to-PCI Doorbell register
• Local inter rupt input
• Master/Target abort status condition
• DMA Ch 0/Ch 1 Done
• DMA Ch 0/Ch 1 Terminal Count reached
• Messaging Outbound Post Queue is not empty
INTA#, or individual sources of an interrupt, can be
enabled or disabled with the PCI 9080 Interrupt
Control/Status register (INTCSR). This register also
provides interrupt status for each interrupt source.
The PCI 9080 PCI Bus i nter rupt is lev el output. Dis a bl ing
an Interrupt Enable bit or clearing the cause(s) of the
interrupt can clear an interrupt.
3.12.1.1 Local Interrupt Input
Asserting Local Bus input pin LINTi# can generate a
PCI Bus interrupt. PCI Host processor can read the
PCI 9080 Interrupt Control/Status register to determine
that an interrupt is pending due to the LINTi# pin being
asserted.
The interr upt rema ins as serte d as long as th e LI NTi# pin
is asserted and the Local interrupt input is enabled.
Adapter specific action can be taken by the PCI Host
processor to cause the Local Bus to release LINTi#.
3.12.1.2 Master/Target Abort Interrupt
The PCI 9080 sets the Master Abort or Target Abort
Status bit in the PCI Configuration register when it
detects a Master or Target abort. These status bits
cause PCI INTA# to be asserted if interrupts are
enabled.
The interrupt remains asserted as long as the Master or
Target Abort bits remain set in the PCI Status
Section 3
Interrupts Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 39
Configuration register (PCISR) and Master/Target Abort
Interrupt is enabled. Use a PCI Type 0 Configuration
access or a Local access to clear the Master Abort and
Target Abort Interrupt bits in the PCI Status
Configuration register.
Interrupt Control/Status register Bits (INTCSR[26:24])
are latched at the time of a Target abort interrupt or
Master abort interrupt. They provide information as to
who was Master when an abort occurred. The PCI 9080
updates these bits whenever an abort occurs.
3.12.2 Local interrupts (LINTo#)
A PCI 9080 Local interrupt (LINTo#) can be generated
by one of the following:
• PCI-to-Local Doorbell/Mailboxes Register access
• PCI BIST interr upt, the DM A done int er rupt
• DMA terminal count is reached
• DMA abort interr upt or the Mess ag ing Outboun d
Post Queue is not empty
LINTo#, or individual sources of an interrupt, can be
enabled or disabled with the PCI 9080 Interrupt
Control/Status register (INTCSR). The Interrupt
Control/Status register also provides interrupt status for
each source of the interrupt.
The PCI 9080 Local interrupt is a level output. An
interrupt can be c l eared by d is abl in g th e Int er rupt En able
bit of a source or by clearing the cause of an interrupt.
3.12.2.1 Local-to-PCI Doorbell Interrupt
A Local Bus Master can generate a P CI Bus interrupt by
writing to the Local-to-PCI Doorbell register
(L2PDBELL). PCI Host processor can then read the
PCI 9080 Interrupt Control/Status register (INTCSR) to
determin e th at a doorbell inter rup t is p end ing. It c a n th en
read the PCI 9080 Local-to-PCI Doorbell register.
Each bit in the Local-to-PCI Doorbell register is
individ ually contro lled. T he L ocal Bus can on ly s et b its in
the Doorbell register. From the Local Bus, writing 1 to
any bit position s ets t hat bit and wr it ing 0 to a b it position
has no effect. Bits in the Local-to-PCI Doorbell register
can only be cleared from the PCI Bus. From the
PCI Bus, writing 1 to any bit position clears that bit and
writing 0 to a bit position has no effect.
The interrupt remains asserted as long as any of the
Local-to-PCI Doorbell register bits are set and
PCI Doorbell Interrupt is enabled.
To prevent race conditions when the PCI Bus is
accessing the Doorbell register (or any Configuration
register), the PCI 9080 automatically de-asserts
READYo# to prevent Local Bus accesses.
3.12.2.2 PCI-to-Local Doorbell Interrupt
A PCI Bus Master ca n generate a Local Bus int errupt by
writing to the PCI-to-Local Doorbell register
(P2LDBELL). Local processor can then read the
PCI 9080 Interrupt Control/Status register (INTCSR) to
determin e th at a doorbell inter rup t is p end ing. It c a n th en
read the PCI 9080 PCI-to-Local Doorbell register.
Each bit in the PCI-to-Local Doorbell register is
individually controlled. The PCI Bus can only set bits in
the Doorbell r egister. F rom the PCI B us, writin g 1 to any
bit posit ion s ets tha t b it a nd wri tin g 0 to a bi t position h as
no effect. Bits in the PCI-to-Local Doorbell register can
only be c leared fr om t he L ocal Bus . F rom th e L ocal Bus,
writing 1 to a ny bi t pos iti on c l ears tha t b it a nd wri tin g 0 to
a bit position has no effect.
Note: If Local Bus cannot clear Doorbell Interrupt, do
not use the PCI-to-Local Doorbell register.
The interrupt remains asserted as long any of the
PCI-to-Local Doorbell register bits are set and the Local
Doorbell Interrupt is enabled.
To prevent race conditions when the Local Bus is
accessing the Doorbell register (or any Configuration
register), the PCI 9080 automatically issues a Retry to
the PCI Bus.
3.12.2.3 Built-In Self Test Interrupt (BIST)
A PCI Bus Master ca n generate a Local Bus int errupt by
performing a PCI Type 0 Configuration write to a bit in
the PCI BIST register. The Local processor can then
read the PCI 9080 Interrupt Control/Status register
(INTCSR) to determine that a BIST interrupt is pending.
The interrupt remains asserted as long as the bit is set
and the BIST interrupt is enabled. The Local Bus then
resets the bit w hen BIST is complete. P CI Hos t software
may fail the device if the bit is not reset after two
seconds.
Note: The PCI 9080 does not have an internal BIST.
Section 3
Functional Description I2O Compatible Message Unit
PCI 9080 Data Book v1.06
40 PLX T e c hn ology, Inc. All r ights r e s e rved
3.12.2.4 DMA Channel 0/1 Interrupts
A DMA channel can generate a PCI or Local Bus
interrupt when done (transfer complete) or after a
transfer is com plete fo r a des criptor in Cha ining mod e. A
bit in the DMA mode register determines whether to
generate a PCI or Local interrupt. The local or
PCI processor can then read the PCI 9080 Interrupt
Control/S tatus r e gis ter ( INTCSR) to de ter m ine whet her a
DMA channel int er r upt is pendi ng.
A Done Status Bit in the Control/Status register can be
used to determine whether the interrupt is
• A done interr upt
• The result of a transfer for a descriptor in a chain
that is not yet complete
The mode register of a channel enables a Done
Interrupt. In Chaining mode, a bit in the Next Descriptor
Pointer register of the channel (loaded from Local
memory) specifies whether to generate an interrupt at
the end of the transfer for the current descriptor.
A DMA channel interrupt is cleared by writing a 1 to the
Clear Interrupt bit in the DMA Command/Status register
(DMACSR0[3] and DMACSR1[3]).
3.12.3 PCI SERR# (PCI NMI)
The PCI 9080 generates an SERR# pulse if parity
checking is enabled in the PCI Command register and it
detects an address parity error or the Generate SERR#
bit in the Interrupt Control/Status register (INTCSR) is 0
and a 1 is written.
SERR# output can be enabled or disabled with the
PCI Command register.
3.12.4 Local LSERR# (Local NMI)
LSERR# interrupt output is asserted if the following
occurs:
• PCI Bus Target Abort or Master Abort Status bit is
set in the PCI Status Configuration register
• Parity Error Status bit is set in the PCI Status
Configuration register
• Messaging Outbound Free Queue overflows
If parity error checking is enabled in the PCI Command
register, the PCI 9080 sets the Master Detected Parity
Error Status bit in the PCI Status Configuration register
(PCISR) if it detects one of the following:
• Parity error during a PCI 9080 Master Read
• PCI Bus signal PERR# being asserted during
a PCI 9080 Master Write
The PCI 9080 sets a Parity Error bit in the PCI Status
Configuration register (PCISR) if it detects one of
the following:
• Data parity error during a PCI 9080 Master Read
• Data parity error during a Slave Write access to the
PCI 9080
• Address parity error
The PCI 9080 Interr upt Co ntrol/St atus reg ister ( INTC SR)
can be used to individually enable or disable LSERR#
for an abort or parity error . LSER R# is a lev el out put that
remains asserted as long as the Abort or Parity Error
Status bits are set.
3.13 I2O Compatible Message Unit
The Messaging Unit supplies two paths for messages,
two inbound FIFOs to receive messages from the
primary PCI Bus and two outbound FIFOs to pass
messages to the primary PCI Bus. Refer to
I
2
O
Architecture Specification v1.5
for details.
Figure 3-22 and Figure 3-23 illustrate information about
the I2O architec t ur e.
No hardware
changes are
required on
host side
IOP = Intelligent I/O Processor IOP Must Have
• CPU
• Memory
• Messaging Unit
Host CPU Physical
System
Memory
PCI Bus
Message Frames
Message Frames
Inbound Queue Outbound Queue
IOP
Local
Memory IOP CPU
Figure 3-22. I2O System Architecture
Section 3
I2O Compatible Message Unit Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 41
Current Architecture I O Architecture
OSM = Operating System Master
HDM = Hardware Device Module
Hardware Hardware
OSM
Messaging Layer
HDM
OS Specific
Module
Hardware
Device
Module
2
Figure 3-23. I2O Software Architecture
3.13.1 Inbound Messages
Inbound messages reside in a pool of message frames
(minimum of 64-byte frames) allocated in shared Local
Bus (IOP) memory. The Inbound Message Queue is
comprised of a pair of rotating FIFOs implemented in
Local memory. The Inbound Free List FIFO holds the
message frame addresses (MFA) of available message
frames in Local memory. The Inbound Post List FIFO
holds the message frame addresses (MFA) of all
currently posted messages.
The inbound circular FIFOs are accessed by external
PCI agents through the Inbound Queue Port location in
the PCI Address space. The Inb ound Queue Port, w hen
read by an exter nal PCI agent, retur ns the Inbound F ree
List FIFO MFA. An external PCI agent places a message
frame int o the Inbou nd Post L ist FIFO by writing i ts MFA
to the Inbound Queue Port location.
3.13.2 Outbound Messages
Outbound mes sages resi de in a pool of mes sage frames
(minimum 64-byte frames) allocated in shared PCI Bus
(Host System) memory. The Outbound Message Queue
is comprised of a pair of rotating FIFOs implemented in
Local memory. The Outbound Free List FIFO holds the
message frame addresses (MFA) of available message
frames in system memory. The Out bound Post L ist FIFO
holds the MFA of all currently posted messages.
The outbound circular FIFOs are accessed by external
PCI agents thr ou gh t he O utb ou nd Q u eue Port loca tio n in
the PCI Address space. The Outbound Queue Port,
when read by an external PCI agent, returns the
Outbound Post List FIFO MFA. An external PCI agent
places free mes sage frames into the Outbo und Free L ist
FIFO by writing the free MFA into the Outbound Queue
Port location.
Memory for the circ ular FIF Os m us t be al loc at ed in Loc al
Bus (IOP) memory. The base address of the queues is
contained in the Queue Base Address register (QBAR).
Each FIFO entry is a 32-bit data value. Each read and
write of the queue must be a single 32-bit access.
The circular FIFOs range in size from 4 KB entries to
64 KB entries . All four F IFOs mus t be c onti guous an d of
the same size. Therefore, the total amount of Local
memory needed for circular FIFO s ranges from 64 KB to
1 MB. The FIFO size is specified in the Messaging
Queue Configuration register (MQCR).
The starting address of each FIFO is based on the
Queue Base Address and the FIFO size, as listed in
Table 3-7.
Table 3-7. Queue Starting Address
FIFO Starting Address
Inbound Free List QBAR
Inbound Post List QBAR + (1 * FIFO Size)
Outbound Post List QBAR + (2 * FIFO Size)
Outbound Free List QBAR + (3 * FIFO Size)
3.13.3 I2O Pointer Management
The FIFOs always reside in shared Local Bus (IOP)
memory and are allocated and initialized by the IOP.
Before enabling I2O (Messaging Queue Configuration
register b it 0 s et to 1), t he Loc al pr ocess or must in itial ize
the following registers with the initial offset, according to
the configured FIFO size:
• Inbound Post and Fre e Head Po int er regist er s
• Inbound Post and Fre e Ta il Po int er registers
• Outbound Post and Free Head Pointer registers
• Outbound Post and Free Tail Pointer registers
The Messagin g Unit (M U) automatic ally adds th e Queue
Base Address to the offset in each head and tail pointer
register. The software can then enable I2O. After
initialization, the local software should not write to the
pointers managed by the MU hardware.
The empty flags are set if the queues are disabled
(MQCR[0] = 0) and head and tail pointers are equal.
This occurs independently of how the head and tail
pointers are set.
Section 3
Functional Description I2O Compatible Message Unit
PCI 9080 Data Book v1.06
42 PLX T e c hn ology, Inc. All r ights r e s e rved
An empty flag is clear ed, sign ifying not e mpty, on ly if the
queues are enabled and the pointers become not equal.
If an empty flag is cleared and the queues are enabled,
the empty flag is set only if the tai l po int er is inc reme nted
and the head and tail pointers become equal.
Full flags are always cleared when the queues are
disabled or the head and tail pointers are not equal.
A full flag is set when the queues are enabled, the head
pointer is incremented, and the head and tail pointers
become equal.
Each circ ular FIFO has a head pointer and a tail pointer,
which are offsets from the Queue Base Address. Writes
to a FIFO oc cur at th e he ad of th e F IFO a nd reads occ ur
from the tail. The head and tai l pointers are i ncremented
by either the Local processor or the MU hardware. The
unit that writes to the FIFO also maintains the pointer.
The pointers are incremented after a FIFO access. Both
pointers wrap around to the first address of the circular
FIFO when they reach the FIFO size, so that the head
and tail pointers “chase” each other around and around
in the circular FIFO. MU wraps the pointers automatically
for the pointers that it maintains. IOP software must wrap
the pointers that it maintains. Whenever they are equal,
the FIFO is empty. To prevent overflow conditions, I2O
specifies that the number of message frames allocated
should be less than or equal to the number of entries in
a FIFO. (Refer to Figure 3-24 for additional information.)
Each inb ound MFA is specified by I2O as the offset from
the start of shared Local Bus (IOP) memory region 0 to
the start of the message frame. Each outbound MFA is
specified as the offset from the Host memory location
0x00000000h to the start of the message frame in the
shared Host memory. Since the MFA is an actual
address, the message frames need not be contiguous.
The IOP allocates and initializes inbound message
frames in shared IOP memory using any suitable
memory allocation technique. The Host allocates and
initializes outbound message frames in shared Host
memory using any sui tab le m em or y al loc at ion tec hn iq ue.
Message frames are a minimum of 64 bytes in length.
I2O uses a “push” (write-preferred) memory model. That
means that the IOP writes messages and data to the
shared Host memory, and the Host writes messages and
data to shared IOP memory. Software should make use
of Burst and DM A tr ans f ers when ev er pos s ib le to ens ure
efficient use of the PCI Bus for message passing.
Additional information on message passing
implementation may be found in the
I
2
O Architecture
Specification v1.5
.
3.13.4 Inbound Free List FIFO
The Local processor allocates inbound message frames
in its shared memory and can place the address of a
free (available) message frame into the Inbound Free
List FIFO by writing its MFA into the FIFO location
pointed to by the Queue Base register + Inbound Free
Head Pointer register. The Local processor must then
increment the Inbound Free Head Pointer register.
A PCI Master (Host or another IOP) can obtain the MFA
of a free message frame by reading the Inbound Queue
Port Address (40h of the firs t PCI Memory B ase Addr ess
register). If the FIFO is empty (
that is
, no free inbound
message frames are currently available, and the head
and tail p ointers ar e equal) , the MU retur ns a val ue of -1
(FFFFFFFFh). If the FIFO is not empty (
that is
, the h ead
and tail pointers are not equal), the MU reads the MFA
pointed to by the Queue Base register + Inbound Free
Tail Po int er r eg ister , r eturns its v al ue a nd incr em ents t he
Inbound Free Tail Pointer register. If the Inbound Free
Queue is not empty, and queue prefetching is enabled
(QSR[3], the next entry in the FIFO is read from the
Local Bus into a prefetch register. The prefetch register
then provides the data for the next PCI read from this
queue, thus reducing the number of PCI wait states.
Section 3
I2O Compatible Message Unit Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 43
Outbound
Post
List
FIFO
Head Pointer
Tail Pointer
Incremented by local
processor
Incremented by PCI
9080 hardware
Inbound
Post
List
FIFO
Head Pointer
Tail Pointer
Incremented by PCI
9080 hardware
Incremented by local
processor
Inbound
Free
List
FIFO
Head Pointer
Tail Pointer
Incremented by local
processor
Incremented by PCI
9080 hardware
Outbound
Free
List
FIFO
Head Pointer
Tail Pointer
Incremented by PCI
9080 hardware
Incremented by local
processor
Outbound Queue
Port
Write
Read
External PCI
Agent
Inbound Queue
Port
Write
Read
External PCI
Agent
Local
Processor
Write
Read
Local
Processor
Write
Read
Low Address Local
Memory
High Address Local
Memory
Outbound
Queue
Inbound
Queue
Figure 3-24. Circular FIFO Operation
Section 3
Functional Description I2O Compatible Message Unit
PCI 9080 Data Book v1.06
44 PLX T e c hn ology, Inc. All r ights r e s e rved
3.13.5 Inbound Post List FIFO
A PCI Master (Host or another IOP) can write a
message into an available message frame in shared
Local Bus (IOP) memory. It can then post that message
by writing the message frame address (MFA) to the
Inbound Queue Port Address (40h of the first
PCI Memory Base Address register). When the port is
written, the MU writes the MFA to the Inbound Post List
FIFO location pointed to by the Queue Base register +
FIFO Size + Inbound Post Head Pointer register. After
the MU writes the MFA to the Inbound Post List FIFO, it
increments the Inbound Post Head Pointer register.
The Inbound Post Tail Pointer register points to the
Inbound Post List FIFO location which holds the MF A of
the oldest posted message. The Local processor
maintains the tail pointer. After a Local processor reads
the oldest MFA, it can remove the MFA from the Inbound
Post List FIFO by incrementing the Inbound Post Tail
Pointer register.
The PCI 9080 generates a Local interrupt when the
Inbound Post List FIFO is not empty. The Inbound Post
List FIFO Interrupt bit in the Queue Status/Control
register (QSR) indicates the interrupt status. The
interrupt clears when the Inbound Post List FIFO is
empty. The interrupt can be masked by the Inbound Post
List FIFO Interrupt Mask bit (QSR[4]).
To prevent race conditions from the time the PCI Write
transaction is received until the data is written in Local
memory and the Inbound Post Head Pointer register is
incremented, any PCI Direct Slave access to the
PCI 9080 is issued a Retry.
3.13.6 Outbound Post List FIFO
A Local Master (IOP) can write a message into an
available message fr ame in shared Host memory. It can
then post that message by writing the message frame
address (MFA) to the Outbound Post List FIFO location
pointed to by the Queue Base register + Outbound Post
Head Pointer register + (2 * FIFO Size). The Local
processor should then increment the Outbound Post
Head Point er regis t er.
A PCI Master can obtain the MFA of the oldest posted
message by reading the Outbound Queue Port Address
(44h of the first PCI Memory Base Address register). If
the FIFO is empty (
that is
, no more outbound messages
are posted, and the head and tail pointers are equal), the
MU returns a value of -1 (FFFFFFFFh). If the Outbound
Post List FIFO is not empty (
that is
, the head and tail
pointers are not equal), the MU reads the MFA pointed
to by the Queue Base register + (2 * FIFO Size) +
Outbound Post Tail Pointer register, returns its value and
increments the Outbound Post Tail Pointer register.
The PCI 9080 generates a PCI Interrupt when the
Outbound Post Head Pointer register is not equal to the
Outbound Post Tail Po inter reg ister. The O utbound P ost
List FIFO Interrupt bit of the Outbound Post List FIFO
Interrupt Status (OPLFIS) register indicates the interrupt
status. When the pointers become equal, both the
interrupt and the Outbound Post List FIFO Interrupt bit
are automatically cleared. The pointers become equal
when a PCI Master (Host or anot her IOP) reads enough
FIFO entries to e mpty t he FIFO. T he Out bound Post Lis t
FIFO Interrupt Mask (OPLFIM) register can mask
the interrupt.
3.13.7 Outbound Post Queue
To reduce read latency, prefetching from the tail of the
queue occurs whenever the q ueue is not empty and the
tail pointer is incremented (queue has been read from),
or when the queue is empty and the head pointer is
increme nted (que ue has been wr itten to). When t he host
CPU reads the Outbound Post Queue, the data is
immediately available.
3.13.8 Inbound Free Queue
To reduce read latency, prefetching from the tail of the
queue occurs whenever the q ueue is not empty and the
tail pointer is incremented (queue has been read from),
or when the queue is empty and the head pointer is
increme nted (que ue has been wr itten to). When t he host
CPU reads the Inbound Free Queue, the data is
immediately available.
3.13.9 Outbound Free List FIFO
A PCI Master (Host or other IOP) allocates outbound
message frames in its shar ed me mor y an d can pl ac e the
address of a free (available) message frame into the
Outbound Free List FIFO by writing the message frame
address (MFA) to the Outbound Queue Port Address
(44h of the first PCI Memory Base Address register).
When the port is written, the MU writes the MFA to the
Outbound Free List FIFO location pointed to by the
Queue Bas e regist er + (3 * FIFO Size) + O utbound F ree
Head Pointer register. After the MU writes the MFA to
the Outbound Free List FIFO, it increments the
Outbound Free Head Pointer register.
Section 3
I2O Compatible Message Unit Functional Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 45
When the IOP needs a free o utbound messag e frame, it
must first c h ec k wheth er any fre e fr a mes are av ailab le. If
the Outbound Free List FIFO is empty (
that is
, the
outbound fr ee head and t ail pointers are equal) , the IO P
must wait for the Host to place additional outbound free
message frames in the Outbound Free List FIFO. If the
Outbound Free List FIFO is not empty (
that is
, the head
and tail pointers are not equal), the IOP can obtain the
MFA of the oldest free outbound message frame by
reading the location pointed to by the Queue Base
register + (3 * FIFO Size) + Outbound Free Tail Pointer
register. After the IOP reads the MFA, it must increment
the Outbound Free Tail Pointer register. To prevent
overflow conditions, I2O specifies that the number of
message frames allocated should be less than or equal
to the number of entries in a FIFO. MU also checks for
overflows of the Outbound Free List FIFO. When the
head pointer is incremented and becomes equal to the
tail pointer, the Outbound Free List FIFO is full, and the
MU generates a local LSERR (NMI) interrupt. The
interrupt is recorded in the Queue Status Control (QSR)
register.
From the time that the PCI Write transaction is received
until the data is written into Local memory and the
Outbound Free Head Pointer register is incremented,
any PCI Direct Slave access to the PCI 9080 is issued
a Retry.
Table 3-8. Circular FIFO Summary
FIFO
Name PCI
Port Generate
PCI Interrupt? Generate Local
Interrupt Head Pointer
Maintained by Tail Pointer
Maintained by
Inbound Free
List FIFO Inbound Queue Port
(Host Read) No No Local processor MU hardware
Inbound Post
List FIFO Inbound Queue Port
(Host Write) No Yes, when the
Port is written MU hardware Local processor
Outbound Post
List FIFO Outbound Queue Port
(Host Read) Yes, when the FIFO
is not empty No Local processor MU hardware
Outbound Free
List FIFO Outbound Queue Port
(Host Write) No Yes, (LSE RR) when
the FIFO is full MU hardware Local proc essor
3.13.10 I2O Enable Sequence
To enable I2O, the Local processor should perform
the following:
• Initialize Space 1 address and range
• Initialize all FIFOs and message frame memory
• Set the PCI class code in PCICCR to be an I2O
device with progr a mm ing int er fac e 01h
• Set the I2O Enab le bit
• Set the Local Init Done bit
Note: NB# must be pulled up so the PCI 9080 issues
retries to all PCI accesses until the Local Init Done bit is
set in CNTRL by the Local processor.
The I2O Enable bit in the Queue Status register (QSR)
causes remapping of resources for use in I2O mode.
When this bit is set, all Memory-Mapped Configuration
registers (such as queue ports 40h and 44h) and
Space 1 share PCIBAR0. PCI accesses to offset
00h-FFh of PCIBAR0 result in accesses to the internal
Configurat io n r eg ister s of t he PCI 9080 . Ac c ess es ab ov e
offset FFh of PCIBAR0 result in Local Space accesses,
beginning at offset 100h from the Loca l Space 1 Remap
register (LAS1BA). Therefore space located at offset
00h-FFh from LAS1BA is not addressable by way
of PCIBAR0.
Programmer’s Note: Because PCI accesses to offset
00h-FFh of PCIBAR0 result in internal Configuration
accesses, Inbound Free MFAs must be greater
than FFh.
PCI 9080 Data Book v1.06
46 PLX T e c hn ology, Inc. All r ights r e s e rved
This page intentionally left blank.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 47
4. REGISTERS
4.1 New Register Definitions Summary
Refer to descriptions in the following sections for a full explanation.
Table 4-1. New Registers Definitions Summary
PCI
Offset Local
Offset Register Bits Description
23 Add PCIREQMODE output.08h or ACh 88h or 12Ch MARBR
28 Read Ahead mode.
18h 98h LBRD0 15 Single Read mode removed.
10 Extend almost full flag to five bits (fifth bit not contiguous).
11 Add CDMPFLIMIT output; do not prefetch past 4 KB boundary for
Direct Master.
12, 3 Direct Mast er Read pref etch size control.
13 I/O Remap select.
28h A8h DMPBAM
15:14 Direct Mast er wri te delay.
30h B0h OPLFIS all New Outbound Post List FIFO Interrupt Status register.
34h B4h OPLFIM all New Outbound Post List FIFO Interrupt Mask register.
40h N/A I QP all New Inbound Queue Port regist er.
44h N/A OQP all New Outbound Queue Port register.
4 Mov e DMA0INTSEL output to DMAMODE0. Change to Reserved.
5 Mov e DMA1INTSEL output to DMAMODE1. Change to Reserved.
3 Mail box i nt errupt enable on F, not on PCI 9060.
68h E8h INTCSR
31:28 Mailbox int errupts on SD, not on PCI 9060.
16 Clear byte count in chaini ng descri ptor.80h 100h DMAMODE0
17 Add C0_INTSEL output. 0=Local int., 1=PCI int.
16 Clear byte count in chaini ng descri ptor.94h 114h DMAMODE1
17 Add C1_INTSEL output. 0=Local int., 1=PCI int.
C0h 140h MQCR all New Messaging Queue Configuration register.
C4h 144h QBAR all New Queue Base Address register.
C8h 148h IFHPR all New Inbound Free Head Pointer.
CCh 14Ch IFTPR all New Inbound Free Tail Pointer.
D0h 150h IPHPR all New Inbound Post Head Pointer.
D4h 154h IPTPR all New Inbound Post Tail Pointer.
D8h 158h OFHPR all New Outbound Free Head Point er.
DCh 15Ch OFTPR all New Outbound Free Tail Pointer.
E0h 160h OPHPR all New Outbound Post Head Pointer.
E4h 164h OPTPR all New Outbound Post Tail Pointer.
E8h 168h QSR all New I2O Queue Status regist er.
F0h 170h LAS1RR all New Local Address Spac e 1 Range Register for PCI-to-Loc al .
F4h 174h LA S1BA all New Local Address Space 1 Local Base Address (Remap).
F8h 178h LBRD1 all New Local Address Space 1 Bus Region Descriptor.
Section 4
Registers New Register Definitions Summary
PCI 9080 Data Book v1.06
48 PLX T e c hn ology, Inc. All r ights r e s e rved
4.1.1 Register Di fferences between PCI 9080 and PCI 9060, PCI 9060E S, and PCI 9060SD
Table 4-2. Register Differences between PCI 9080 and PCI 9060
Register PCI/Local Offset Bits Description
PCIIDR 00/00 31:16 Default changed from PCI 9060 to PCI 9080
PCICR 04/04 4 Memory Write and Invalidate now supported
PCISR 06/06 6 User-definable bit added
PCICLSR 0C/0C 7:0 Cache line size is now used for Memory Write and Invalidate
PCIBAR0 10/10 8:6 Register Bank siz e changed from 128 to 256
PCIBAR1 14/14 8:6 Register Bank siz e changed from 128 to 256
PCIBAR3 1C/1C 31:0 Base address register for Local Address Space 1
PCISVID 2C/2C 15:0 S ubsystem Vendor ID register
PCISID 2E/2E 15:0 Subsystem ID register
31:0 Mode/Arbitration register now accessible from the PCI Bus
21 Local Bus Direct Slave Give up Bus Mode
22 Direct Slave Lock Enable
23 PCI Request Mode
24 PCI Specification v2.1 Mode
25 PCI Read/No Write Mode
26 PCI Read with Write Flush Mode
27 Get Local Bus Latency Timer with BREQ
MARBR 08, AC/88, 12C
28 PCI Read/No Flush Mode
BIGEND 0C/8C 7:0 Big/Little Endian Descriptor register
EROMBA 14/94 5 BREQo Timer Resolution control
1:0 Local Bus width now programmable in S mode
10 Read Prefetch Count Enable
14:11 Read Pref etc h Count
17:16 Local Bus width now programmable in S mode
LBRD0 18/98
25 Extra Long Serial EEPROM Load
12, 3 Direct Master Read Prefetch Size Control
10, 8:5 P rogram mable Almost Full Flag increased by two bits
11 Direct Master Prefetch Limit
13 I/O Remap select
DMPBAM 28/A8
15:14 Direct Master Write Delay
LAS1RR F0/170 31:0 Local Address Spac e 1 Range regi ster
LAS1BA F4/174 31: 0 Loc al Address Space 1 Local Base Address register (Remap)
LBRD1 F8/178 31:0 Local Address Spac e 1 Bus Region Descriptor register
MBOX0 40, 78/C0 31:0 M B OX0 moved to PCI Address 78 when Messagi ng Queue is enabled
MBOX1 44, 7C/C4 31:0 MBOX1 moved to PCI Address 7C when Messaging Queue is enabled
Section 4
New Register Definitions Summary Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 49
Table 4-2. Register Differences between PCI 9080 and PCI 9060 (continued)
Register PCI/Local Offset Bits Description
3 Mailbox Interrupt Enable
28 Mailbox 0 Interrupt Status
29 Mailbox 1 Interrupt Status
30 Mailbox 2 Interrupt Status
INTCSR 68/E8
31 Mailbox 3 Interrupt Status
PCIHIDR 70/F0 31:0 PCI Permanent Configuration ID register
PCIHREV 74/ F4 7:0 P CI Permanent Revision ID register
13 Write and Invalidate Mode for DMA Channel 0 transfers
13 DMA Write and Invalidate Mode
14 DMA EOT[1:0]# (End of Transfer) Input Pin Enable
15 DMA Stop Data Transfer Mode
16 DMA Clear Count Mode
DMAMODE0 80/100
17 DMA Interrupt Select
DMADPR0 90/110 0 DMA Descriptor Location Sel ect or (PCI or Local)
13 DMA Write and Invali dat e Mode
14 DMA EOT[1: 0]# (End of Transfer) Input Pi n Enable
15 DMA Stop Data Transfer Mode
16 DMA Cl ear Count Mode
DMAMODE1 94/114
17 DMA Interrupt Select
DMADPR1 A 4/124 0 DMA Desc ri ptor Locat i on Selector (PCI or Local)
DMACSR0 A8/128 4 DMA Channel 0 Done
DMACSR1 A9/129 4 DMA Channel 1 Done
DMATHR B0/130 15:0 Changed thresholds to accommodate 32-word Write FIFOs
OPQIS 30/B0 31:0 Outbound Post Queue Interrupt Status regist er
OPQIM 34/B4 31:0 Out bound Post Queue Interrupt Mask register
IQP 40 31:0 I nbound Queue P ort
OQP 44 31:0 Outbound Queue P ort
MQCR C0/140 31:0 Me ssaging Queue Configuration register
QBAR C4/144 31:0 Queue Base Address register
IFHPR C8/148 31:0 Inbound Free Head Pointer regist er
IFTPR CC/14C 31:0 Inbound Free Tail Pointer register
IPHPR D0/150 31: 0 I nbound P ost Head Po i nter register
IPTPR D4/154 31:0 Inbound Post Tail Pointer regi st er
OFHPR D8/158 31:0 Outbound Free Head Pointer regist er
OFTPR DC/15C 31: 0 Out bound Free Tail Pointer regist er
OFHPR E0/160 31: 0 Out bound P ost Head Poi nter regist er
OPTPR E4/164 31:0 Outbound P ost Tail Pointer register
QSR E8/168 7:0 Queue Status/Control regist er
Section 4
Registers New Register Definitions Summary
PCI 9080 Data Book v1.06
50 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-3. Register Differences between PCI 9080 and PCI 9060ES
Register PCI/Local Offset Bits Description
PCIIDR 00/00 31:16 Default changed from PCI 906E to PCI 9080
PCISR 06/06 6 User-definable bit added
PCICLSR 0C/0C 7:0 Cache line size is now used for Memory Write and Invalidate
PCIBAR0 10/10 8:6 Register Bank siz e changed from 128 to 256
PCIBAR1 14/14 8:6 Register Bank siz e changed from 128 to 256
PCIBAR3 1C/1C 31:0 Base address register for Local Address Space 1
PCISVID 2C/2C 15:0 S ubsystem Vendor ID register
PCISID 2E/2E 15:0 Subsystem ID register
20:19 DMA Channel Pri ori ty
23 PCI Request Mode
25 PCI Read/No Write Mode
26 PCI Read with Wri t e Flush Mode
27 Get Local Bus Lat ency Timer wit h BREQ
MARBR 08, AC/88, 12C
28 PCI Read/ No Flus h Mode
5 Direct Slave Big Endian Mode
6 DMA Channel 1 Big Endian Mode
BIGEND 0C/8C
7 DMA Channel 0 Big Endian Mode
EROMBA 14/94 5 BREQo Timer Resolution control
1:0 Local Bus width now programmable in S mode
15 Si ngl e Read Access Mode remov ed
17:16 Local Bus width now programmable in S mode
LBRD0 18/98
25 Extra Long Serial EEPROM Load
12, 3 Direct Master Read Prefetch Size Control
10, 8:5 P rogram mable Almost Full Flag increased by one bit
11 Direct Master Prefetch Limit
13 I/O Remap Slect
DMPBAM 28/A8
15:14 Direct Master Write Delay
LAS1RR F0/170 31:0 Local Address Spac e 1 Range regi ster
LAS1BA F4/174 31: 0 Loc al Address Space 1 Local Base Address register (Remap)
LBRD1 F8/178 31:0 Local Address Spac e 1 Bus Region Descriptor register
MBOX0 40, 78/C0 31:0 M B OX0 moved to PCI Address 78 when t he Messaging Queue is enabled
MBOX1 44, 7C/C4 31:0 MBOX1 moved to PCI Address 7C when the Messaging Queue is enabled
MBOX4 50/D0 31:0 MBOX4 added
MBOX5 54/D4 31:0 MBOX5 added
MBOX6 58/D8 31:0 MBOX6 added
MBOX7 5C/DC 31:0 MBOX7 added
P2LDBELL 60/E0 31:8 24 more Doorbell bits added to PCI-to-Local Doorbell register
L2PDBELL 64/E4 31:8 24 more Doorbell bits added to Local-to-P CI Doorbell register
INTCSR 68/E8 3 Mailbox I nterrupt Enable
Section 4
New Register Definitions Summary Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 51
Table 4-3. Register Differences between PCI 9080 and PCI 9060ES (continued)
Register PCI/Local Offset Bits Description
18 DMA Channel 0 Int errupt Enabl e
19 DMA Channel 1 Int errupt Enabl e
21 DMA Channel 0 Int errupt Stat us
22 DMA Channel 1 Int errupt Stat us
25 DMA Channel 0 active during abort
26 DMA Channel 1 active during abort
28 Mai l box 0 Inte rrupt St atus
29 Mai l box 1 Inte rrupt St atus
30 Mai l box 2 Inte rrupt St atus
INTCSR 68/E8
31 Mai l box 3 Inte rrupt St atus
3:0 Read command for DMACNTRL 6C/EC
7:4 Writ e com m and for DMA
PCIHREV 74/ F4 7:0 P CI Permanent Revision ID register
DMAMODE0 80/100 31:0 DMA Channel 0 Mode register
DMAPADR0 84/104 31:0 DMA Channel 0 PCI Address register
DMALADR0 88/108 31:0 DMA Channel 0 Local Address regi ster
DMASIZ0 8C/10C 31:0 DMA Channel 0 Size register
DMADPR0 90/110 31:0 DMA Channel 0 Descriptor Pointer register
DMAMODE1 94/114 31:0 DMA Channel 1 Mode register
DMAPADR1 98/108 31:0 DMA Channel 1 PCI Address register
DMALADR1 9C/11C 31:0 DMA Channel 1 Local Address register
DMASIZ1 A0/120 31:0 DMA Channel 1 Size register
DMADPR1 A 4/124 31:0 DMA Channel 1 Descriptor Point er register
DMACSR0 A8/128 7:0 DMA Channel 0 Command/S tatus
DMACSR1 A9/129 7:0 DMA Channel 1 Command/S tatus
DMATHR B0/130 31:0 DMA Threshold regis t er
OPQIS 30/B0 31:0 Outbound Post Queue Interrupt Status regist er
OPQIM 34/B4 31:0 Outbound Post Queue Interrupt Mask register
IQP 40 31:0 I nbound Queue P ort
OQP 44 31:0 Outbound Queue P ort
MQCR C0/140 31:0 Me ssaging Queue Configuration register
QBAR C4/144 31:0 Queue Base Address register
IFHPR C8/148 31:0 Inbound Free Head Pointer regist er
IFTPR CC/14C 31:0 Inbound Free Tail Pointer register
IPHPR D0/150 31: 0 I nbound P ost Head Po i nter register
IPTPR D4/154 31:0 Inbound Post Tail Pointer regi st er
OFHPR D8/158 31:0 Outbound Free Head Pointer regist er
OFTPR DC/15C 31: 0 Out bound Free Tail Pointer regist er
OFHPR E0/160 31: 0 Out bound P ost Head Poi nter regist er
OPTPR E4/164 31:0 Outbound P ost Tail Pointer register
QSR E8/168 7:0 Queue Status/Control regist er
Section 4
Registers New Register Definitions Summary
PCI 9080 Data Book v1.06
52 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-4. Register Differences between PCI 9080 and PCI 9060SD
Register PCI/Local Offset Bits Description
PCIIDR 00/00 31:16 Default changed from PCI 906D to PCI 9080
PCISR 06/06 6 User-definable bit added
PCIBAR0 10/10 8:6 Register Bank siz e changed from 128 to 256
PCIBAR1 14/14 8:6 Register Bank siz e changed from 128 to 256
PCISVID 2C/2C 15:0 S ubsystem Vendor ID register
PCISID 2E/2E 15:0 Subsystem ID register
31:0 Mode/Arbitration register now accessible from the PCI Bus
23 PCI Request Mode
MARBR 08, AC/88, 12C
28 PCI Read/ No Flus h Mode
1 Direct Master Big Endian ModeBIGEND 0C/8C
7 DMA Channel 0 Big Endian Mode
3:0 Direct Slave BREQo Delay Clocks
4 Local Bus BREQo Enable
EROMBA 14/94
5 BREQo Timer Resolution control
1:0 Local Bus width now programmable in S mode
15 Si ngl e Read Access Mode remov ed
LBRD0 18/98
17:16 Local Bus width now programmable in S mode
DMRR 1C/9C 31:16 Local Range register for Direct Master to PCI
DMLBAM 20/A0 31:0 Local Bus Base Address register for Direct Master to PCI Memory
DMLBAI 24/A4 31:0 Local Bus Base Address register for Direct Master to PCI IO/CFG
DMPBAM 28/A8 31: 0 PCI Base Address (Remap) register for Direct Master to PCI Memory
LAS1RR F0/170 31:0 Local Address Space 1 Range register was at 30/B0 in PCI 9060SD
LAS1BA F4/174 31: 0 Loc a l Address Space 1 Local Base Address register (Rem ap) was at 34/B4
in PCI 9060SD
LBRD1 F8/178 31:0 Local Address Spac e 1 Bus Region Descriptor register was at 38/B8 i n PCI 9060SD
LBRD1 F8/178 15 S i ngl e Read Access Mode remov ed
MBOX0 40,78/C0 31: 0 MBOX0 moved to PCI Address 78 when the Messaging Queue is enabled
MBOX1 44, 7C/C4 31:0 MBOX1 moved to PCI Address 7C when the Messaging Queue is enabled
MBOX4 50/D0 31:0 MBOX4 added
MBOX5 54/D4 31:0 MBOX5 added
MBOX6 58/D8 31:0 MBOX6 added
MBOX7 5C/DC 31:0 MBOX7 added
18 DMA Channel 0 Int errupt Enabl e
21 DMA Channel 0 Int errupt Active
24 Direct Master active duri ng abort
INTCSR 68/E8
25 DMA Channel 0 active during abort
PCIHREV 74/ F4 7:0 P CI Permanent Revision ID register
Section 4
New Register Definitions Summary Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 53
Table 4-4. Register Differences between PCI 9080 and PCI 9060SD (continued)
Register PCI/Local Offset Bits Description
DMAMODE0 80/100 31:0 DMA Channel 0 Mode register
DMAPADR0 84/104 31:0 DMA Channel 0 PCI Address register
DMALADR0 88/108 31:0 DMA Channel 0 Local Address regi ster
DMASIZ0 8C/10C 31:0 DMA Channel 0 Transf er Size register
DMADPR0 90/110 31:0 DMA Channel 0 Descriptor Pointer register
DMACSR0 A 8/128 7:0 DMA Channel 0 Command/S tatus register
DMATHR B0/130 15:0 DMA Channel 0 Threshol ds
OPQIS 30/B0 31:0 Outbound Post Queue Interrupt Status regist er
OPQIM 34/B4 31:0 Outbound Post Queue Interrupt Mask register
IQP 40 31:0 I nbound Queue P ort
OQP 44 31:0 Outbound Queue P ort
MQCR C0/140 31:0 Me ssaging Queue Configuration register
QBAR C4/144 31:0 Queue Base Address register
IFHPR C8/148 31:0 Inbound Free Head Pointer regist er
IFTPR CC/14C 31:0 Inbound Free Tail Pointer register
IPHPR D0/150 31: 0 I nbound P ost Head Po i nter register
IPTPR D4/154 31:0 Inbound Post Tail Pointer regi st er
OFHPR D8/158 31:0 Outbound Free Head Pointer regist er
OFTPR DC/15C 31: 0 Out bound Free Tail Pointer regist er
OFHPR E0/160 31: 0 Out bound P ost Head Poi nter regist er
OPTPR E4/164 31:0 Outbound P ost Tail Pointer register
QSR E8/168 7:0 Queue Status/Control regist er
Section 4
Registers Register Address Mapping
PCI 9080 Data Book v1.06
54 PLX T e c hn ology, Inc. All r ights r e s e rved
4.2 Register Address Mapping
Table 4-5. PCI Configuration Registers
To ensure software compatibility with other versions of the PCI 9080 family
and to ensure compatibility with future enhancements,
write 0 to all unused bits.
PCI CFG
Register
Address
Local
Access
(Offset
from Chip
Select
Address) 31 24 23 16 15 8 70
PCI/Local
Writable Serial
EEPROM
Writable
00h 00h Device ID Vendor ID Local Y
04h 04h Status Command Y N
08h 08h Class Code Revi si on ID Local Y
0Ch 0Ch BIST Header Type PCI Latency Timer Cache Line Size Y [15:0],
Local N
10h 10h PCI Base Address 0 for Memory-Mapped Configuration Regis ters (PCIBAR0) Y N
14h 14h PCI Base Address 1 for I/O Mapped Configuration Regist ers (PCIBA R1) Y N
18h 18h PCI Base Address 2 for Local Address Space 0 (PCIBA R2) Y N
1Ch 1Ch PCI Base Address 3 for Local Address Space 1 (PCIBAR3) Y N
20h 20h Unused Base Address (PCIBAR4) N N
24h 24h Unused Base Address (PCIBAR5) N N
28h 28h Cardbus CIS Pointer (Not Supported)NN
2Ch 2Ch Subsystem ID Subsystem Vendor ID Local Y
30h 30h PCI Base Address for Local Expansion ROM Y Y
34h 34h Reserved N N
38h 38h Reserved N N
3Ch 3Ch Max _Lat Min_Gnt Interrupt Pin Interrupt Li ne Y [7:0],
Local Y
Note: Refer to PCI Specification v2.1 for definitions of these registers.
Section 4
Register Address Mapping Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 55
Table 4-6. Local Configuration Registers
PCI
(Offset
from
Base
Address)
Local
Access
(Offset
from Chip
Select
Address)
To ensure software compatibility with other versions of the PCI 9080 family
and to ensure compatibility with future enhancements,
write 0 to all unused bits.
31 0
PCI/Local
Writable Serial
EEPROM
Writable
00h 80h Range for PCI-to-Loc al Address Space 0 Y Y
04h 84h Local Base Address (Remap) for PCI-t o-Local Address Spac e 0 Y Y
08h 88h Mode/Arbitrat i on Register Y Y
0Ch 8Ch Bi g/Little Endian Descript or Regis ter Y Y
10h 90h Range for PCI-to-Local Expansi on ROM Y Y
14h 94h Local Base Address (Remap) for PCI-t o-Local Expansion ROM and BREQo control Y Y
18h 98h Local Bus Region Descriptors
(Space 0 and Expansion ROM) for PCI-to-Local Access es YY
1Ch 9Ch Range for Direct Mast er to PCI Y Y
20h A0h Local Base Address for Di rect M aster to PCI Memory Y Y
24h A4h Local Base Address for Direct Master to PCI IO/CFG Y Y
28h A8h PCI Base Address (Remap) for Direct Master to PCI Y Y
2Ch ACh PCI Configuration A ddress Regi ster for Direct Master to PCI IO/CFG Y Y
F0h 170h Range for P CI-t o-Local Address Space 1 Y Y
F4h 174h Local Base Address (Remap) for PCI-to-Local Address Space 1 Y Y
F8h 178h Local Bus Region Desc ri ptor (Space 1) for PCI-to-Local Accesses Y Y
Section 4
Registers Register Address Mapping
PCI 9080 Data Book v1.06
56 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-7. Runtime Registers
PCI
(Offset
from Base
Address)
Local
Access
(Offset
from Chip
Select
Address)
To ensure software compatibility with other versions of the PCI 9080 family
and to ensure compatibility with future enhancements,
write 0 to all unused bits.
31 0
PCI/Local
Writable Serial
EEPROM
Writable
40h C0h Mail box Regi ster 0 (refer to Note) Y Y
44h C4h Mail box Regi ster 1 (refer to Note) Y Y
48h C8h Mailbox Register 2 Y N
4Ch CCh Mailbox Register 3 Y N
50h D0h Mailbox Register 4 Y N
54h D4h Mailbox Register 5 Y N
58h D8h Mailbox Register 6 Y N
5Ch DCh Mailbox Register 7 Y N
60h E0h PCI-to-Local Doorbell Register Y N
64h E4h Local-to-P CI Doorbell Register Y N
68h E8h Interrupt Control / Status Y N
6Ch ECh Serial EEPROM Control, PCI Command Codes, User I/O Control, Init Control Y N
70h F0h Device ID V endor ID N N
74h F4h Unused Revision I D N N
78h C0h M ai l b ox Regi ster 0 (see Note) Y N
7Ch C4h Mailbox Register (see Not e) Y N
Note: Mailbox registers 0 and 1 are always accessible at addresses 78h/C0h and 7Ch/C4. When the I
2
O feature is
disabled (QSR[0]=0), Mailbox registers 0 and 1 are also accessible at PCI Addresses 40h and 44h for PCI 9060
compatibility. When the I
2
O feature is enabled, the Inbound and Outbound Queue pointers are accessed at addresses 40h
and 44h, replacing the Mailbox registers in PCI Address space.
Section 4
Register Address Mapping Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 57
Table 4-8. DMA Registers
PCI
(Offset
from Base
Address)
Local
Access
(Offset
from Chip
Select
Address)
To ensure software compatibility with other versions of the PCI 9080 family
and to ensure compatibility with future enhancements,
write 0 to all unused bits.
31 0
PCI/Local
Writable Serial
EEPROM
Writable
80h 100h DMA Ch 0 Mode Y N
84h 104h DMA Ch 0 PCI Address Y N
88h 108h DMA Ch 0 Local Address Y N
8Ch 10Ch DMA Ch 0 Transfer Byte Count Y N
90h 110h DMA Ch 0 Descriptor Pointer Y N
94h 114h DMA Ch 1 Mode Y N
98h 118h DMA Ch 1 PCI Address Y N
9Ch 11Ch DMA Ch 1 Local Address Y N
A0h 120h DMA Ch 1 Transfer Byte Count Y N
A4h 124h DMA Ch 1 Descriptor Pointer Y N
A8h 128h Reserved DMA Channel 1
Command/Status
Register
DMA Channel 0
Command/Status
Register
YN
ACh 12Ch M ode/Arbitration Register Y N
B0h 130h DMA Threshold Register Y N
Section 4
Registers Register Address Mapping
PCI 9080 Data Book v1.06
58 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-9. Messaging Queue Registers
PCI
(Offset
from Base
Address)
Local
Access
(Offset
from Chip
Select
Address)
To ensure software compatibility with other versions of the PCI 9080 family
and to ensure compatibility with future enhancements,
write 0 to all unused bits.
31 0
PCI/Local
Writable Serial
EEPROM
Writable
30h B0h Outbound Post Queue Interrupt Status N N
34h B4h Outbound Post Queue Interrupt Mask Y N
40h — Inbound Queue Port PCI N
44h — Outbound Queue Port PCI N
C0h 140h Messaging Unit Configuration Register Y N
C4h 144h Queue Base Address Register Y N
C8h 148h I nbound Free Head Point er Regis t er Y N
CCh 14Ch Inbound Free Tail Pointer Register Y N
D0h 150h Inbound Post Head Pointer Register Y N
D4h 154h Inbound Post Tail Pointer Regist er Y N
D8h 158h Outbound Free Head Pointer Register Y N
DCh 15Ch Outbound Free Tail Pointer Register Y N
E0h 160h Outbound Post Head Pointer Regi st er Y N
E4h 164h Outbound Post Tail Pointer Regist er Y N
E8h 168h Queue Status/Cont rol Regis t er Y N
Notes: When I
2
O messagi ng is enabled (QSR [0]=1), the PCI Master (Host or anoth er IOP) uses the Inbo und Queu e Port
to read Message Frame Addresses (MFAs) from the Inbound Free List FIFO and to write MFAs to the In bound Post List
FIFO. The PCI Master (Host or another IOP) uses the Outbound Queue Port to read MFAs from the Outbound Post List
FIFO and to write MFAs to the Outbound Free List FIFO.
Each Inbound MFA is specified by I
2
O as offset from PCI Base Address 0 (programmed in register PCIBAR0 at offset 10h)
to start of message frame. This means that all inbound message frames should reside in PCI Base Address 0 memory
space.
Each Outbound Message Frame Address (MFA) is specified by I
2
O as offset from system address 0x00000000h.
The Outbound MFA is the physical 32-bit address of a frame in shared PCI system memory.
The Inbound and Outbound Queues may reside in Local Address Space 0 or 1 by programming the QSR register. The
queues need not be in shared memory.
Section 4
PCI Configuration Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 59
4.3 PCI Configuration Registers
All registers may be written to or read from in Byte, Word, or Lword accesses.
Table 4-10. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register
Bit Description Read Write Value after Reset
15:0 Vendor ID. Identifies device manufact urer. Defaul ts to PCI SIG issued vendor ID of
PLX (10B5h) if no serial EEPROM is present and pin NB# (no Local Bus
initialization) is asserted low.
Yes Local/
Serial
EEPROM
10B5h
or
0
31:16 Device ID. Identifies particular device. Defaults to PLX part number for
PCI int erfac e chi p (PCI 9080) if no serial EEPROM is present and pin NB# (no
Local Bus initialization) is asserted low.
Yes Local/
Serial
EEPROM
9080h
or
0
Table 4-11. (PCICR; PCI:04h, LOC:04h) PCI Command Register
Bit Description Read Write Value after Reset
0I/O Space. Value of 1 allows device to respond to I/O Space accesses. Value of 0
disables device from responding to I/O Space accesses. Yes Yes 0
1Memory Space. Val ue of 1 allows device t o respond to Memory S pace access es.
Value of 0 disables device from responding to Memory Space accesses. Yes Yes 0
2 Master Enable. Value of 1 allows device to behave as Bus Mast er. Value of 0
disables devi ce from generating Bus Master accesses. This bit must be set for the
PCI 9080 to perfo rm Direct Master or DMA cycles.
Yes Yes 0
3Special Cycle. Not supported. Yes No 0
4 Memory Write and Invalidate. Value of 1 enables Memory Write and Invali dat e.
Value of 0 disables Memory Writ e and Invali date. (Refer to DMA Mode Registers
for Direct Mast er, DMAMODE0, and DMAMODE1[13], as well as (DMPBAM[ 13],
DMAMODE0[13], and DMAMODE1[13], respectively).
Yes Yes 0
5VGA Palette Snoop. Not supported. Yes No 0
6Parity Error Response. Value of 0 indicates parity error is ignored and operation
continues. Val ue of 1 indicates parity checking is enabled. Yes Yes 0
7 Wait Cycle Control. Controls whet her device performs address/data stepping. Value
of 0 indicates devic e never does steppi ng. Value of 1 indicates device always does
stepping.
Note: Hardcoded to 0.
Yes No 0
8 SERR# Enable. Value of 1 enables SERR# driver. Value of 0 disables SE RR#
driver. Yes Yes 0
9Fast Back-to-B ack Enable. I ndic ates type of fast back-to-bac k transfers Master can
perform on bus. Value of 1 indicates fast back-to-back transfers can occur to any
agent on bus. Value of 0 indicates fast back-to-back transfers can only occur to
same agent as previous cycle.
Yes No 0
15:10 Reserved. Yes No 0
Section 4
Registers PCI Configuration Registers
PCI 9080 Data Book v1.06
60 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-12. (PCISR; PCI:06h, LOC:06h) PCI Status Register
Bit Description Read Write Value after Reset
5:0 Reserved. Yes No 0
6 If high, supports User Definable Features. This bit can only be written from the
Local Bus. Read-onl y from the PCI Bus. Yes Local 0
7 Fast Back-to-Back Capabl e. When set to 1, indic ates adapter can accept fast
back-to-back trans act i ons. Val ue of 0 indicates adapter cannot. Yes No 1
8Master Data Parity Error Det ect ed. This bit is set to 1 when three conditions are
met: 1) The PCI 9080 asserted PERR# itself or observed PERR# asserted; 2) The
PCI 9080 was Bus Master for operation in which error occu rred; 3) Parity E rror
Response bit in Command Register is set. Writ i ng 1 clears the bit (0).
Yes Yes/Clr 0
10:9 DEVSEL Timing. Indicates timing for DEVSEL# assertion. Value of 01 indicates
medium decode.
Note: Hardcoded to 01.
Yes No 01
11 Target Abort. When set to 1, indicates the PCI 9080 has signaled a Target abort.
Writing a 1 clears the bit (0). Yes Yes/Clr 0
12 Received Target Abort. When set to 1, indicates the PCI 9080 has received Target
abort signal. Writi ng a 1 clears the bit (0). Yes Yes/Clr 0
13 Master Abort. When set to 1, indicat es the PCI 9080 has generated Master abort
signal. Writing a 1 clears the bit (0). Yes Yes/Clr 0
14 Signaled Syst em Error. When set to 1, indicates t he PCI 9080 has reported a
system error on SERR# signal. Writ i ng a 1 clears the bit (0). Yes Yes/Clr 0
15 Detect ed Parity Error. When set to 1, indicat es the PCI 9080 has detected a
PCI Bus parity error, even if pari ty error handli n g is disabled (Parity Error Res ponse
bit in Command register is clear). One of three conditions can cause this bit to
be set. 1) The PCI 9080 detected parity error during PCI Address phase;
2) The PCI 9080 detected a data parity error when it was Target of a write;
3) The PCI 9080 detected a data parity error when performing Master Read
operation. Writi ng a 1 clears the bi t (0).
Yes Yes/Clr 0
Table 4-13. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register
Bit Description Read Write Value after Reset
7:0 Revision ID. Silic on revisi on of t he PCI 9080. Yes Local/
Serial
EEPROM
Current Rev #
Table 4-14. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register
Bit Description Read Write Value after Reset
7:0 Register Level Programm i ng Interface. 00h = Queue Ports at 40h and 44h.
01h = Queue Ports at 40h and 44h, and Int Status and Int Mask at 30h and 34h,
respectively.
Yes Local/
Serial
EEPROM
00
15:8 Subclass Code. 80h = Other Bridge Device, 00h = I2O Device. Yes Local/
Serial
EEPROM
80h
23:16 Bas e Class Code. 06h = Bridge Device, 0Eh = I2O controller. Yes Local/
Serial
EEPROM
06h
Section 4
PCI Configuration Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 61
Table 4-15. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register
Bit Description Read Write Value after Reset
7:0 System cache line size in units of 32-bit words. Yes Yes 0
Table 4-16. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register
Bit Description Read Write Value after Reset
7:0 PCI Latency Timer. Units of PCI Bus clocks that spec ify am ount of t ime the
PCI 9080, as a Bus Master, ca n burst data on the PCI Bus. Yes Yes 0
Table 4-17. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register
Bit Description Read Write Value after Reset
6:0 Configuration Layout Type. Specifies layout of bits 10h through 3Fh in configuration
space. Only one encoding 0 is defined. All other encodings are reserved. Yes Local 0
7 Header Type. Value of 1 indicates multiple f unctions. Value of 0 indic ates singl e
function. Yes Local 0
Table 4-18. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register
Bit Description Read Write Value after Reset
3:0 Value of 0 indicates device passed its test. Nonzero values indicate device failed.
Device specific f ailure codes can be encoded in nonzero value. Yes Local 0
5:4 Reserved. Device returns 0. Yes No 0
6PCI writes 1 to invoke BIST. Generates interrupt to Local Bus. Local Bus resets the
bit when BIST is complete. Software s houl d fail device if BIST is not complete after
two seconds.
Refer to Runtim e regist ers for interrupt control/st atus.
Yes Yes 0
7 Returns 1 if device supports BIST. Returns 0 if device is not BIST compatibl e. Yes Local 0
Section 4
Registers PCI Configuration Registers
PCI 9080 Data Book v1.06
62 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-19. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses
to Local, Runtime, and DMA Registers
Bit Description Read Write Value after Reset
0Memory Space Indic ator. Value of 0 indicates register maps into memory space.
Value of 1 indicates register maps into I/O space.
Note: Hardcoded to 0.
Yes No 0
2:1 Location of Regist er. Locati on values:
00—Locate anywhere in 32-bit memory address spac e
01—Locate below 1 MB memory address space
10—Locate anywhere in 64-bit memory address spac e
11—Reserved
Note: Hardcoded to 0.
Yes No 0
3 Prefetchable. Value of 1 indicates there are no side effects on reads. Does not
affect operation of t he PCI 9080.
Note: Hardcoded to 0.
Yes No 0
7:4 Memory Base Address . M em ory base address for access to Local, Runtime, and
DMA registers (def ault is 256 bytes).
Note: Hardcoded to 0.
Yes No 0
31:8 Memory B ase Address . M em o ry base address f or access to Local, Runtime, and
DMA registers. Yes Yes 0
Note: For I
2
O, Inbound message frame pool must reside in address space pointed to by PCIBAR0. Message Frame
Address (MFA) is defined by I
2
O as offset from this base address to start of message frame.
Table 4-20. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses
to Local, Runtime, and DMA Registers
Bit Description Read Write Value after Reset
0Memory Space Indic ator. Value of 0 indicates register maps into memory space.
Value of 1 indicates register maps into I/O space.
Note: Hardcoded to 1.
Yes No 1
1 Reserved. Yes No 0
7:2 I/O Base Address . Base A ddress f or I/O access to Loc al, Runtim e, and DMA
registers. (Default is 256 bytes)
Note: Hardcoded to 0.
Yes No 0
31:8 I/O Base Address. Base Address f or I/O access to Loc al, Runtim e, and DMA
registers. Yes Yes 0
Section 4
PCI Configuration Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 63
Table 4-21. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses
to Local Address Space 0
Bit Description Read Write Value after
Reset
0 Memory Space Indicator. Valu e of 0 indicates register maps into memory space.
Value of 1 indicates register maps into I/O space.
(Specified i n LAS0RR regist er.)
Yes No 0
2:1 Location of Register (If Memory Space). Location values:
00—Locate anywhere in 32-bit memory address spac e
01—Locate below 1-MB memory address spac e
10—Locate anywhere in 64-bit memory address spac e
11—Reserved
(Specified i n LAS0RR regist er.)
If I/O Space, bit 1 is always 0 and bit 2 is included in the base address.
Yes Mem: No
I/O:
No for bit 1,
Yes for bit 2
0
3 Prefetchable (If Memory Space). V al ue of 1 indicates there are no side effects on
reads. Reflect s val ue of LAS0RR[3] and provides only stat us to system. Does not
affect operation of t he PCI 9080. The prefetching features of this address s pace
are controll ed by the ass ociated Bus Region Descriptor register.
(Specified i n LAS0RR regist er.)
If I/O Space, bit 3 is included in the base address.
Yes Mem: No
I/O: Ye s 0
31:4 Memory Base Address. Memory base address for access to Local Address
Space 0. Yes Yes 0
Note: PCIBAR2 can be enabled or disabled by setting or clearing LAS0BA[0].
Table 4-22. (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses
to Local Address Space 1
Bit Description Read Write Value after
Reset
0Memory Space Indic ator. Value of 0 indicates register maps into memory space.
Value of 1 indicates register maps into I/O space.
(Specified i n LAS1RR regist er.)
Yes No 0
2:1 Location of regist er. Loc ation val ues:
00—Locate anywhere in 32-bit memory address space
01—Locate below 1-MB memory address spac e
10—Locate anywhere in 64-bit memory address spac e
11—Reserved
(Specified i n LAS1RR regist er.)
If I/O Space, bit 1 is always 0 and bit 2 is included in the base address.
Yes Mem: No
I/O:
No for bit 1,
Yes for bit 2
0
3Prefetchabl e (If Memory Space). V al ue of 1 indicates there are no side effects on
reads. Reflect s value of LAS1RR[ 3] and only provi des status to the system. Does
not affect operat i on of the PCI 9080. The prefetching features of this address s pace
are controll e d by the associ ated Bus Region Descriptor register.
(Specified i n LAS1RR regist er.)
If I/O Space, bit 3 is included in the base address.
Yes Mem: No
I/O: Ye s 0
31:4 Memory Base Address. Memory base address for access to Local Address
Space 1. Yes Yes 0
Note: PCIBAR3 can be enabled or disabled by setting or clearing LAS1BA[0]. If QSR[0] is set, PCIBAR3 returns 0.
Section 4
Registers PCI Configuration Registers
PCI 9080 Data Book v1.06
64 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-23. (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register
Bit Description Read Write Value after Reset
31:0 Reserved. Yes No 0
Table 4-24. (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register
Bit Description Read Write Value after Reset
31:0 Reserved. Yes No 0
Table 4-25. (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer Register
Bit Description Read Write Value after Reset
31:0 Cardbus Information Structure Pointer for PCMCIA. Not supported. Yes No 0
Table 4-26. (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID Register
Bit Description Read Write Value after Reset
15:0 Subsystem Vendor ID (unique add-in board Vendor ID). Yes Local/
Serial
EEPROM
10B5
Table 4-27. (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID Register
Bit Description Read Write Value after Reset
15:0 Subsystem ID (unique add-in board Device ID). Yes Local/
Serial
EEPROM
9080h
Table 4-28. (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Register
Bit Description Read Write Value after Reset
0 Address Decode Enable. Value of 1 indicates dev ic e accepts accesses to
Expansion ROM address. V alue of 0 indicat es devic e does not accept acc esses
to Expansi on ROM space. Should be set to 1 by PCI Host if Expansion ROM
is present.
Yes Yes 0
10:1 Reserved. Yes No 0
31:11 Ex pansi on ROM Base Address (upper 21 bits). Yes Yes 0
Table 4-29. (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Register
Bit Description Read Write Value after Reset
7:0 Interrupt Line Routing Value. Indicat es which input of system interrupt controller(s )
to which the interrupt li ne of device is connected. Yes Yes 0
Section 4
PCI Configuration Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 65
Table 4-30. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register
Bit Description Read Write Value after Reset
7:0 Interrupt Pin Register. Indicates which interrupt pin device uses. The following
values are decoded:
0 = No Interrupt Pin
1 = INTA#
2 = INTB#
3 = INTC#
4 = INTD#
Note: The PCI 9080 supports only one PCI interrupt pin (INTA#).
Yes Local/
Serial
EEPROM
1
Table 4-31. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register
Bit Description Read Write Value after Reset
7:0 Min_Gnt. Specifi e s how l ong a burst period device needs, ass uming clock rate of
33 MHz. Value is multipl e of 1/4 µs increm ents. Yes Local/
Serial
EEPROM
0
Table 4-32. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register
Bit Description Read Write Value after Reset
7:0 Max_Lat. Specifies how often device must gain access t o PCI Bus. Value is
multipl e of 1/4 µs increments. Yes Local/
Serial
EEPROM
0
Section 4
Registers Local Configuration Registers
PCI 9080 Data Book v1.06
66 PLX T e c hn ology, Inc. All r ights r e s e rved
4.4 Local Configur ation Registers
Table 4-33. (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI-to-Local Bus
Bit Description Read Write Value after Reset
0 Memory Space Indicator. Valu e of 0 indicates Local address Space 0 maps into
PC I memory sp ace . Value of 1 indicates address Space 0 maps i nt o PCI I/O spac e. Yes Yes 0
2:1 If mapped into memory space, enc odi ng is as follows:
2/1 Meaning
0 0 Locate anywhere in 32-bit PCI Address space
0 1 Locate below 1 MB in PCI Address space
1 0 Locate anywhere in 64-bit PCI Address space
1 1 Reserved
If mapped into I/O space, bit 1 must be set to 0.
Bit 2 is included with bits [31:3] to indicate decoding range.
Yes Yes 0
3If mapped into memory space, value of 1 indicat es reads are pref etchable (does not
affect operati on of th e PCI 9080, but is used for system status). If mapped into I/O
space, included with bits [ 31:2] to indic ate decoding range.
Yes Yes 0
31:4 Specifies which PCI Address bits t o use for decoding PCI access to Local Bus
Space 0. Each bit corres ponds to a PCI Address bit. Bit 31 corresponds to Address
bit 31. Write 1 to all bits to be included in decode and 0 to all others (used in
conjuncti on with PCI Conf iguration register 18h). Default is 1 MB.
Yes Yes FFF0000h
Notes: Range (not Range register) must be power of 2. “Range register value” is inverse of range.
User should limit all I/O spaces to 256 bytes per PCI Specification v2.1.
Table 4-34. (LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap) Register
Bit Description Read Write Value after Reset
0 Space 0 Enable. Value of 1 enables decoding of PCI Addresses for Direct Slave
access to Local Space 0. Val ue of 0 disables decoding. If set to 0, PCI BIOS may
not allocate (assi gn) base address for Space 0.
Note: Must be set to 1 for any Direct Slave access to Space 0
.
Yes Yes 0
1 Reserved. Yes No 0
3:2 If Local Space 0 is mapped into memory space, bits are not used. If mapped into
I/O space, bit is included with bits [31:4] for remappi ng. Yes Yes 0
31:4 Remap of PCI Address to Local Address Space 0 into a Local Address Space.
Remap (replace) PCI Address bits used in decode as Local Address bits. Yes Yes 0
Note: Remap Address value must be multiple of Range (not Range register).
Section 4
Local Configuration Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 67
Table 4-35. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register
Bit Description Read Write Value after Reset
7:0 Local Bus Latency Timer. Number of Local Bus Clock cycl es before de-ass ert i n g
HOLD and releasing the Local Bus. Also used with bit 27 to delay BREQ input to
give up the Local Bus only when this timer expires.
Yes Yes 00
15:8 Local Bus Pause Timer. Number of Local Bus Cl ock cycles before reass erting
HOLD after releasi ng the Local Bus.
Note: Applicable only to DMA operation.
Yes Yes 00
16 Local Bus Latency Timer Enabl e. Value of 1 enables latency timer. Yes Yes 0
17 Local Bus Pause Timer Enable. Val ue of 1 enables pause timer. Yes Y es 0
18 Local Bus BREQ Enable. Val u e of 1 enables Local Bus BREQ input. When BREQ
input is active, the PCI 9080 de-as serts HOLD and releases Local Bus. Yes Yes 0
20:19 DMA Channel Pri ori ty. Value of 00 i ndicates rot ational priority scheme. Valu e of 01
indicat es Channel 0 has pri ority. Value of 10 indicates Channel 1 has priority. Value
of 11 is reserved.
Yes Yes 0
21 Local Bus Direct Slave Give up Bus Mode. When set to 1, the PCI 9080 de-asserts
HOLD and releases the Local Bus when the Direct Slave Write FIFO becomes
empty during a Direct Slav e Write or when the Direct Slave Read FIFO becomes
full during a Direct Slave Read.
Yes Yes 1
22 Direct Slave LLOCK o# Enable. Value of 1 enables PCI Direct Slave locked
sequences. Val ue of 0 disables Direct Slave locked sequences. Yes Yes 0
23 PCI Request Mode. Value of 1 causes the PCI 9080 to de-assert REQ when it
asserts FRAME during a Master cycl e. Value of 0 causes the PCI 9080 to leave
REQ asserted for the entire Bus Master cycle.
Yes Yes 0
24 PCI Specific ation v2.1 Mode. When set to 1, the PCI 9080 operates in Delayed
Transaction mode for Direc t Slav e Reads. The PCI 9080 issues a Retry and
prefetches Read data.
Yes Yes 0
25 PCI Read No Write Mode. Value of 1 forces Retry on Writes if Read is pending.
Value of 0 allows Writes to occur while Read is pendi ng. Yes Yes 0
26 PCI Read with Writ e Flush Mode. Value of 1 submits request to flush pending a
Read cycle if a Write cycle is detect ed. Value of 0 submits request to not effect
pending Reads when a Write cycle occ urs (PCI Specification v2.1 compatibl e).
Yes Yes 0
27 Gate Local Bus Latency Timer with BREQ. If set to 0, the PCI 9080 gives up the
Local Bus during Direct Slave or DMA transfer after the current cyc l e (if enabl ed
and BREQ is sampled). If set to 1, the PCI 9080 gives up the Local Bus only if
BREQ is sampled and the Local Bus Latency Timer is enabled and expired during
a Direct Slave or DMA transf er.
Yes Yes 0
28 PCI Read No Flush Mode. Value of 1 submits a request to not flush the Read FIFO
if a PCI Read cycle com pl etes (Read Ahead mode). Value of 0 submit s a request t o
flush the Read FIFO if a PCI Read cycle compl etes.
Yes Yes 0
29 If set to 0, reads from PCI Configuration regist er address 00h and returns Device ID
and Vendor ID. If set to 1, reads from PCI Configuration Register address 00h and
returns Subsystem ID and Subsystem Vendor ID.
Yes Yes 0
31:30 Reserved. Yes No 0
Section 4
Registers Local Configuration Registers
PCI 9080 Data Book v1.06
68 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-36. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register
Bit Description Read Write Value after Reset
0Configuration Regis ter Big Endian Mode. Value of 1 specifies use of Big Endian
data ordering for Local accesses to the Configuration registers. Value of 0 specifies
Little Endian ordering. Big Endian m ode can be specified for Conf i guration Register
accesses by ass erting BIGEND# pin during Address phase of access .
Yes Yes 0
1 Direct Master Big Endian Mode. Value of 1 specifies use of Big Endian data
ordering for Direct M aster accesses. Value of 0 specifies Littl e Endian ordering.
Big Endi an mode can be specified for Direct Master acc esses by asserting the
BIGEND# input pin during Addres s phase of acc ess.
Yes Yes 0
2 Direct Slave Address Space 0 Big Endian Mode. Value of 1 specifies use of
Big Endi an data ordering for Direct Slave accesses to Local Address Space 0.
Value of 0 specifies Little Endian orderi ng.
Yes Yes 0
3 Direct Slave Address Expansion ROM 0 Big Endian Mode. Value of 1 specifies use
of Big Endian data ordering for Direct S l ave accesses to Expansion ROM. Value of
0 specifies Little Endian ordering.
Yes Yes 0
4 Big Endian Byte Lane Mode. Value of 1 specifies that in Big Endian mode, use byte
lanes [31:16] for a 16-bit Local Bus and byte lanes [31:24] fo r an 8-bit Local Bus.
Value of 0 specifies that in Big Endian mode, byte lanes [15:0] be used for a 16-bit
Local Bus and byte lanes [7: 0] for an 8-bit Local Bus.
Yes Yes 0
5Direct Slave Address Spac e 1 Big Endian Mode. Value of 1 specifies use of
Big Endi an data ordering for Di rect Slave accesses t o Local Address Space 1.
Value of 0 specifies L ittl e Endian orde ring.
Yes Yes 0
6 DMA Channel 1 Big Endian Mode. Value of 1 specifies use of Big Endian data
ordering for DMA Channel 1 acc esses to the Local Address Space. Value of 0
specifies Litt l e Endian ordering.
Yes Yes 0
7 DMA Channel 0 Big Endian Mode. Value of 1 specifies use of Big Endian data
ordering for DMA Channel 0 acc esses to the Local Address Space. Value of 0
specifies Litt l e Endian ordering.
Yes Yes 0
31:8 Reserved. Yes No 0
Section 4
Local Configuration Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 69
Table 4-37. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register
Bit Description Read Write Value after Reset
10:0 Reserved. Yes No 0
31:11 Spec ifi es which PCI Address bits t o use for decoding PCI-to-Local Bus Expansion
ROM. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to Address bit
31. Write 1 to all bits to be included in decode and 0 to all others (used in
conjuncti on with PCI Conf iguration register 30h). Default is 64 KB.
Yes Yes FFFF00h
Note: Range (not Range register) must be power of 2. “Range register value” is inverse of range.
Table 4-38. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register
and BREQo Control
Bit Description Read Write Value after Reset
3:0 Direct Slave BREQo (Backoff Request Out) Del ay Clock s. Number of Local Bus
clocks in which Direct Slave HOLD request is pending and a Local Direct Master
access is in progress and not being granted t he bus (LHOLDA) bef ore assert i ng
BREQo. Once asserted, BREQo remains asserted until the PCI 9080 receives
LHOLDA (LSB = 8 or 64 clocks).
Yes Yes 0
4Local Bus BREQo Enable. Value of 1 enables the PCI 9080 to assert
BREQo output. Yes Yes 0
5 BREQo Timer-Resolution. Value of 1 changes LSB of the BREQo timer from
8 to 64 cl ocks. Yes Yes 0
10:6 Reserved. Yes No 0
31:11 Remap of PCI Expansi o n ROM Space into a Local Address Space.
Remap (replace) PCI Address bits used in decode as Local Address bits. Yes Yes 0
Note: Remap Address value must be multiple of Range (not Range register).
Section 4
Registers Local Configuration Registers
PCI 9080 Data Book v1.06
70 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-39. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Register
Bit Description Read Write Value after Reset
1:0 Memory S pace 0 Local Bus Width. Value of 00 indicates bus width of 8 bits. Value
of 01 indicates bus widt h of 16 bits. Val ue of 10 or 11 indicates bus widt h of 32 bits. Yes Yes S = 01
J = 11
C = 11
5:2 Memory Space 0 Internal Wait St ates (data to data; 0-15 wait states). Yes Yes 0
6 Memory Space 0 Ready Input Enable. Value of 1 enables Ready input. Value of 0
disables Ready in put. Yes Yes 0
7Memory Space 0 BTERM# Input Enable. Value of 1 enables BTERM# input. Value
of 0 disables BTERM# input. If set to 0, the PCI 9080 bursts four Lword maximum
at a time.
Yes Yes 0
8Memory Space 0 Prefetc h Disabl e. If mapped into memory space, value of 0
enables Read prefetc hi ng. Value of 1 disables prefetching. If prefetc hi ng is
disabled, the PCI 9080 disc onnects after each memory read.
Yes Yes 0
9 Expansion ROM Space Prefetch Disable. Value of 0 enables Read prefetchi ng.
Value of 1 disables prefetchi ng. If prefetchi ng is dis abled, the PCI 9080 disconnects
after each memory read.
Yes Yes 0
10 Read Prefetch Count Enabl e. When set to 1 and memory prefetching is enabled,
the PCI 9080 prefetches up to the number of Lwords specified in prefetch count.
When set to 0, the PCI 9080 ignores the count and continues prefetching until
terminat ed by PCI Bus.
Yes Yes 0
14:11 Prefe tc h Counter. Number of Lwords to prefetch during Memory Read cycles
(0-15). Count of zero sel ects prefetch of 16 Lwords. Yes Yes 0
15 Reserved. Yes No 0
17:16 Ex pansion ROM Space Local Bus Width. Value of 00 indicates bus width of 8 bits.
Value of 01 indicates bus widt h of 16 bits. Value of 10 or 11 indicates bus width of
32 bits.
Yes Yes S = 01
J = 11
C = 11
21:18 Ex pansion ROM Space Int ernal Wait States (dat a to data; 0-15 wait states). Yes Yes 0
22 Expansion ROM Space Ready Input Enable. Value of 1 enables Ready input.
Value of 0 disables Ready input. Yes Yes 0
23 Expansion ROM Space Bterm Input Enable. Val ue of 1 enables BTERM# input.
Value of 0 disables Bterm input. If set to 0, the PCI 9080 bursts four Lword
maximum at a time.
Yes Yes 0
24 Memory Space 0 Burst E nabl e. Value of 1 enables bursting. Value of 0 disables
bursting. If burst is disabled, Local Bus performs continuous single cycles for Burst
PCI Read/Write cycles.
Yes Yes 0
25 Extra Long Load from Serial EEPROM. Value of 1 loads Subsystem ID and Local
Address Space 1 registers. Value of 0 indicates not to load them. Yes No 0
26 Expansion ROM Space Burst Enable. V al ue of 1 enables bursting. V al ue of 0
disables burst i ng. If burst is disabled, Local Bus performs continuous s i ngl e cycles
for Burst PCI Read/Write cycles.
Yes Yes 0
27 Direct Slave PCI Write Mode. Value of 0 indicates th e PCI 9080 shoul d disc onnect
when the Direct Slave Write FIFO is full. Value of 1 indicates the PCI 9080 should
de-assert TRDY# when the Write FIFO is full.
Yes Yes 0
31:28 PCI Target Ret ry Del ay Cl ocks. Contains value (multiplied by 8) of the number of
PCI Bus clocks after rec eivi ng PCI -to-Local Read or Write access and not
successf ul ly com pl eting a transfer. Only pertains to Direct Slave Writes when bit 27
is se t to 1.
Yes Yes 4
(32 clocks )
Section 4
Local Configuration Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 71
Table 4-40. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master to PCI
Bit Description Read Write Value after Reset
15:0 Reserved (64 KB increments ). Yes No 0
31:16 Spec ifi es whic h Local Address bit s to use for decoding Local-to-PCI Bus access.
Each bit corres ponds to a PCI Address bit. Bit 31 corresponds to Address bit 31.
Write 1 to all bits that must be included in decode and 0 to all others. Used for
Direct Mast er Memory, I/O, or Configuration accesses.
Yes Yes 0
Note: Range (not Range register) must be power of 2. “Range register value” is inverse of range.
Table 4-41. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master to PCI Memory
Bit Description Read Write Value after Reset
15:0 Reserved. Yes No 0
31:16 Assigns value to bits to use for decoding Local-to-PCI Memory access. Yes Yes 0
Note: Local Base Ad dr ess value must be mul tip le of Rang e (not Range register).
Table 4-42. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master to PCI IO/CFG
Bit Description Read Write Value after Reset
15:0 Reserved. Yes No 0
31:16 Ass i gns value to bits t o use for decoding Local -t o-PCI I/O or Configuration access.
Used for Direct Mast er I/O and Configuration accesses. Yes Yes 0
Notes: Local Bas e Ad dres s value must be mul tip le of Rang e (not Range register).
Refer to DMPBAM[13] for I/O Remap Address option.
Section 4
Registers Local Configuration Registers
PCI 9080 Data Book v1.06
72 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-43. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to PCI Memory
Bit Description Read Write Value after Reset
0Direct Mast er Memory Acc ess Enable. Value of 1 enables decode of Direct Master
Memory accesses. Value of 0 disables decode of Direct Master Memory accesses. Yes Yes 0
1 Direct Master I/O Access Enable. V al ue of 1 enables decode of Direct Mast er
I/O access es. V al ue of 0 disables dec ode of Di rect Mast er I/O acc esses. Yes Yes 0
2 LLOCK# Input Enable. Value of 1 enables LLOCK# input, enabling PCI-locked
sequences. Value of 0 disables LLOCK# input. Yes Yes 0
12, 3 Di rect Master Read Prefetch Size control. Values:
00 = The PCI 9080 continues to prefetch Read data from the PCI Bus until the
Direct Master access is finished. May result in additional four unneeded Lwords
being prefetched from the PCI Bus.
01 = Prefetch up to four Lwords from the PCI Bus
10 = Prefetch up to eight Lwords from the PCI Bus
11 = Prefetch up to 16 Lwords from the PCI Bus
If PCI memory prefetch is not wanted, perfo rms Direct Master Si ngl e cycle.
Direct Mast er Burst reads m ust not exceed program m e d limit.
Yes Yes 00
4 Direct Master PCI Read Mode. Value of 0 indicates the PCI 9080 should releas e
PCI Bus when the Read FIFO becomes full. Value of 1 indicates the PCI 9080
should keep PCI Bus and de-assert IRDY when the Read FIFO becomes full.
Yes Yes 0
10, 8:5 P rogrammable Almost Full Flag. When the number of entries in the 32-word Direct
Master Write FIFO exceeds this value, output pin DMPAF# is asserted low. Yes Yes 000
9Write and Invalidate Mode. When set to 1, the PCI 9080 waits for 8 or 16 Lwords to
be written from the Local Bus before start ing PCI access. When set, all Local Direct
Master to PCI Writ e accesses must be 8- or 16-Lword bursts.
Use in conjuncti on wit h PCICR[4] and Section 3. 6.1. 9.2, “Di rect Mast er Write and
Invalidate”).
Yes Yes 0
11 Direct Master Pref etc h Limit. If set to 1, don’t prefetch past 4 KB (4098 bytes)
boundaries. Yes Yes 0
13 I/O Remap Select. When set to 1, forc es PCI Address bits [31:16] to all zeros.
When set to 0, uses bits [31:16] of this register as PCI Address bits [31: 16]. Yes Yes 0
15:14 Direc t Master Write Delay. Used to delay PCI Bus request after Di rect Master Burst
Write cycl e has start ed. V al u es:
00 = No delay; start cycle imme di ately
01 = Delay 4 PCI clocks
10 = Delay 8 PCI clocks
11 = Delay 16 PCI clocks
Yes Yes 00
31:16 Remap of Local-to-PCI Space into PCI Address Space. Remap (replace) Local
Address bits us ed in decode as PCI Address bits. Used for Direct Master Memory
and I/O accesses.
Yes Yes 0
Note: Remap Address value must be multiple of Range (not Range register).
Section 4
Local Configuration Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 73
Table 4-44. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master to PCI IO/CFG
Bit Description Read Write Value after Reset
1:0 Configuration Type (00=Ty pe 0, 01=Type 1). Y es Yes 0
7:2 Register Number. If different register Read/Write is needed, value must be
programmed and new PCI Configuration cycle must be generated. Yes Yes 0
10:8 Function Number. Yes Yes 0
15:11 Device Number. Yes Yes 0
23:16 Bus Number. Yes Yes 0
30:24 Reserved. Yes No 0
31 Configurati on Enable. Val ue of 1 allows Loc al-to-P CI I/O accesses to be converted
to a PCI Configuration cyc l e. Parameters in this table are used to generate
PCI confi guration address.
Yes Yes 0
Note: Refer to Configuration Cycle Generation example in Section 3.6.1.6, “CFG (PCI Configuration Type 0 or Type 1
Cycles).”
Table 4-45. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI-to-Local Bus
Bit Description Read Write Value after Reset
0 Memory Space Indicator. Value of 0 indicates Local Address Spac e 1 maps into
PCI memory space. Value of 1 indicates Address Space 1 maps into PCI I/O space. Yes Yes 0
2:1 If mapped into memory space, enc odi ng is as follows:
2/1 Meaning
0 0 Locate anywhere in 32-bit PCI Address space
0 1 Locate below 1 MB in PCI Address space
1 0 Locate anywhere in 64-bit PCI Address space
1 1 Reserved
If mapped into I/O space, bit 1 must be set to 0.
Bit 2 is included with bits [31:3] to indicate decoding range.
Yes Yes 0
3 If mapped into memory space, value of 1 indicates reads are prefetchable (does not
affect operati on of th e PCI 9080, but is used for system status). If mapped into I/O
space, bit is included with bits [31:2] t o indicat e decoding range.
Yes Yes 0
31:4 Specifies which PCI Address bits t o use for decoding PCI access to Local Bus
Space 1. Each bit corres ponds to a PCI Address bit. Bit 31 corresponds to Address
bit 31. Write 1 to all bits that must be included in decode and 0 to all others (used in
conjuncti on with PCI Configuration Register Ch 1). Default is 1 MB.
Yes Yes FFF0000h
Notes: Range (not Range register) must be power of 2. “Range register value” is inverse of range.
User should limit all I/O spaces to 256 bytes per PCI Specification v2.1.
If the QSR bit 0 is set, defines PCI Base Address 0.
Section 4
Registers Local Configuration Registers
PCI 9080 Data Book v1.06
74 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-46. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Register
Bit Description Read Write Value after Reset
0Space 1 Enable. Val ue of 1 enables decoding of PCI Addresses for Direct Sl ave
access to Local Space 1. Value of 0 disables decoding. If set to 0, PCI BIOS may
not allocate (assi gn) base address for Space 1.
Note: Must be set to 1 for any Direct Slave access to Space 1.
Yes Yes 0
1 Reserved. Yes No 0
3:2 If Local Space 1 is mapped into memory space, bits are not used. If mapped into
I/O space, bit is included with bits [31:4] for remappi ng. Yes Yes 0
31:4 Remap of PCI Address to Local Address Space 1 into a Local Address Space.
Remap (replace) PCI Address bits used in decode as Local Address bits. Yes Yes 0
Note: Remap Address value must be multiple of Range (not Range register).
Table 4-47. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register
Bit Description Read Write Value after Reset
1:0 Memory S pace 1 Local Bus Width. Value of 00 indicates bus width of 8 bits. Value
of 01 indicates bus widt h of 16 bits. Val ue of 10 or 11 indicates bus widt h of 32 bits. Yes Yes S = 01
J = 11
C = 11
5:2 Memory Space 1 Internal Wait St ates (data to data; 0-15 wait states). Yes Yes 0
6 Memory Space 1 Ready Input Enable. Value of 1 enables Ready input. Value of 0
disables Ready in put. Yes Yes 0
7Memory Space 1 BTERM# Input Enable. Value of 1 enables BTERM# input. Value
of 0 disables BTERM# input. If set to 0, the PCI 9080 bursts four Lword maximum
at a time.
Yes Yes 0
8Memory Space 1 Burst Enabl e. Value of 1 enables bursting. Value of 0 disables
bursting. If burst is disabled, Local Bus performs continuous single cycles for Burst
PCI Read/Write cycles.
Yes Yes 0
9 Memory Space 1 Prefetch Disable. If mapped into memory space, value of 0
enables Read prefetc hi ng. Value of 1 disables prefetching. If prefetc hi ng is
disabled, the PCI 9080 disc onnects after each memory read.
Yes Yes 0
10 Read Prefetch Count Enabl e. When set to 1 and memory prefetching is enabled,
the PCI 9080 prefetches up to the number of Lwords specified in prefetch count.
When set to 0, the PCI 9080 ignores the count and continues prefetching until
terminat ed by PCI Bus.
Yes Yes 0
14:11 Prefe tc h Counter. Number of Lwords to prefetch during memory Read cycles
(0-15). Yes Yes 0
31:15 Reserved. Yes No 0
Section 4
Runtime Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 75
4.5 Runtime Registers
Table 4-48. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0
Bit Description Read Write Value after Reset
31:0 32-Bit Mailbox Register. Yes Yes 0
Note: Mailbox register 0 is replaced by the Inbound Queue Port when the I
2
O
feature is enabled (QSR[0] is set).
Mailbox register 0 is always accessible at PCI Address 78h and Local Address C0h.
Table 4-49. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1
Bit Description Read Write Value after Reset
31:0 32-Bit Mailbox Register. Yes Yes 0
Note: Mailbox register 1 is replaced by Outbound Queue Port when I
2
O feature is enabled (QSR[0] is set).
Mailbox register 1 is always accessible at PCI Address 7Ch and Local Address C4h.
Table 4-50. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2
Bit Description Read Write Value after Reset
31:0 32-Bit Mailbox Register. Yes Yes 0
Table 4-51. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3
Bit Description Read Write Value after Reset
31:0 32-Bit Mailbox Register. Yes Yes 0
Table 4-52. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4
Bit Description Read Write Value after Reset
31:0 32-Bit Mailbox Register. Yes Yes 0
Table 4-53. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5
Bit Description Read Write Value after Reset
31:0 32-Bit Mailbox Register. Yes Yes 0
Table 4-54. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6
Bit Description Read Write Value after Reset
31:0 32-Bit Mailbox Register. Yes Yes 0
Table 4-55. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7
Bit Description Read Write Value after Reset
31:0 32-Bit Mailbox Register. Yes Yes 0
Section 4
Registers Runtime Registers
PCI 9080 Data Book v1.06
76 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-56. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell Register
Bit Description Read Write Value after Reset
31:0 Doorbell Register. PCI Master can write to this register and generate a Local
interrupt t o the Local process or. The Local processor can then read this regist er
to determi ne whic h Doorbel l bit was asserted. PCI Master sets doorbell by writing
1 to a particular bit. Local processor can clear Doorbell bit by writing 1 to that
bit positi on.
Yes Yes/Clr 0
Table 4-57. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell Register
Bit Description Read Write Value after Reset
31:0 Doorbell Register. Local processor can write to this regist er and generate
PCI int errupt. PCI Master can then read this register to determine which Doorbell bit
was assert ed. Local process or sets doorbell by writing 1 to a particular bit.
PCI Master can clear Doorbell bi t by writing 1 to that bit position.
Yes Yes/Clr 0
Section 4
Runtime Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 77
Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register
Bit Description Read Write Value after Reset
0Enable Local Bus LSERR#. Value of 1 enables the PCI 9080 to assert LSERR#
interrupt out put when PCI B us Target Abort or Master Abort Status bit is set in
PCI Status Configuration register.
Yes Yes 0
1 Enable Local Bus LSERR# when PCI parity error occurs during a PCI 9080 Master
Transfer or a PCI 9080 Slave access or an Outbound Free List FIFO Overflow Init. Yes Yes 0
2 Generate PCI Bus SERR#. When set to 0, writing 1 generates PCI Bus SERR#. Yes Yes 0
3Mailbox Interrupt Enable. Value of 1 enables a Local interrupt to be generated when
PCI Bus writes to Mail box regist ers 0 through 3. To clear a Local interrupt, t he Local
Master must read the Mail box. Us ed in conjuncti on wit h Local int errupt enable.
Yes Yes 0
7:4 Reserved. Yes No 0
8 PCI Interrupt Enable. Value of 1 enables PCI interrupts. Yes Yes 1
9PCI Doorbell Int errupt Enable. Value of 1 enables doorbell interrupts. Used in
conjuncti on with PCI i nterrupt enable. Clearing doorbel l interrupt bits that caused
interrupt also clears i nterrupt.
Yes Yes 0
10 PCI Abort I nterrupt Enable. V al ue of 1 enables Master abort or Master detect of
Target abort to generate PCI interrupt. Used in conjunct i on with PCI i nterrupt
enable. Clearing abort st atus bits also clears PCI interrupt.
Yes Yes 0
11 PCI Loc al Interrupt Enable. V al ue of 1 enables Local interrupt input to generate a
PCI int errupt. Use in conjunction wi th PCI interrupt enable. Cleari ng t he Local Bus
cause of interrupt also cl ears interrupt .
Yes Yes 0
12 Retry Abort Enable. Val ue of 1 enables the PCI 9080 to treat 256 Master
consecutiv e retries t o a Target as a Target Abort. Value of 0 enables the PCI 9080
to attempt Master Retries indefinit ely.
Note: For diagnostic purpos es only.
Yes Yes 0
13 Value of 1 indicates PCI doorbell interrupt is active. Yes No 0
14 Value of 1 indicates PCI abort interrupt is active. Yes No 0
15 Value of 1 indicates Local int errupt is active (LINTi#). Yes No 0
16 Local Interrupt Output Enable. Value of 1 enables Local interrupt output . Yes Yes 1
17 Local Doorbell Int errupt E nabl e. Value of 1 enables doorbell int errupt s. Used in
conjuncti on with Local i nterrupt enabl e. Cleari ng l ocal doorbell i nterrupt bi ts t hat
caused interrupt also cl ears interrupt .
Yes Yes 0
18 Local DMA Channel 0 Int errupt Enable. Value of 1 enables DMA Channel 0
interrupts. Used in conjunction with Local interrupt enable. Clearing DMA status bits
also clears i nterrupt.
Yes Yes 0
19 Local DMA Channel 1 Interrupt E nable. Value of 1 enables DMA Channel 1
interrupts. Used in conjunction with Local interrupt enable. Clearing DMA status bits
also clears i nterrupt.
Yes Yes 0
20 Value of 1 indicates local doorbell interrupt is active. Yes No 0
21 Value of 1 indicates DM A Ch 0 interrupt is act iv e. Yes No 0
22 Value of 1 indicates DM A Ch 1 interrupt is act iv e. Yes No 0
23 Value of 1 indicates BIST int errupt is active. Writing 1 to bit 6 of PCI Configuration
BIST Register generates BIST (Built -I n Self-Test ) i nterrupt . Clearing bi t 6 clears
interrupt . For description of s elf -test, refer to PCI BISTR.
Yes No 0
Section 4
Registers Runtime Registers
PCI 9080 Data Book v1.06
78 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register (continued)
Bit Description Read Write Value after Reset
24 Value of 0 indicates Direct Master was Bus Master during a Master or Target abort.
(Not valid until abort occ urs.) Yes No 1
25 Value of 0 indicates DM A CH 0 was Bus Master during a Master or Target abort.
(Not valid until abort occurs.) Yes No 1
26 Value of 0 indicates DM A CH 1 was Bus Master during a Master or Target abort.
(Not valid until abort occurs.) Yes No 1
27 Value of 0 indicates Target Abort was generat ed by the PCI 9080 after
256 consecutiv e Master retries to Target. (Not valid until abort occ urs. ) Yes No 1
28 Value of 1 indicates PCI wrote dat a to MailBox #0. Enabled only if MBOXINTENB is
enabled (bit 3 high). Yes No 0
29 Value of 1 indicates PCI wrote data to MailBox #1. Enabled only if MBOXINTENB is
enabled (bit 3 high). Yes No 0
30 Value of 1 indicates PCI wrote dat a to MailBox #2. Enabled only if MBOXINTENB is
enabled (bit 3 high). Yes No 0
31 Value of 1 indicates PCI wrote dat a to MailBox #3. Enabled only if MBOXINTENB is
enabled (bit 3 high). Yes No 0
Section 4
Runtime Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 79
Table 4-59. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control,
Init Control Register
Bit Description Read Write Value after Reset
3:0 PCI Read Command Code for DMA. Sent out during DMA Read cycles. Yes Yes 1110
7:4 PCI Write Command Code for DMA. Sent out during DMA Write cycles. Yes Yes 0111
11:8 PCI Memory Read Command Code for Direct Master. Sent out during Direct Master
Read cycles. Yes Yes 0110
15:12 PCI M emory Write Command Code for Direct Master. Sent out during Direct Master
Write cycles. Yes Yes 0111
16 General Purpose Output. Value of 1 causes USERO output to go high. Value of 0
causes USER0 output to go low. Yes Yes 1
17 General Purpose Input. Value of 1 indic ates USERI input pin is high. Value of 0
indicates USERI pin is low. Yes No —
23:18 Reserved. Yes No 0
24 Serial EEPROM Clock for Local or PCI Bus Reads or Writes to Serial EEPROM.
Toggling this bit generates s eri al EEPROM clock. (Ref er to manufact urer’s data
sheet for particul ar serial EEPROM being used. )
Yes Yes 0
25 Serial EEPROM Chip S elect. For Local or PCI Bus Reads or Writes to serial
EEPROM, setting this bit to 1 provides serial EEPROM chip select. Yes Yes 0
26 Write Bit to serial EEPROM. For Writes, this output bit is input to serial EEPROM.
Clocked into serial EEPROM by serial EEPROM clock. Yes Yes 0
27 Read Serial EEPROM Data. For Reads, this input bit is output of serial EEPROM.
Clocked out of serial EEPROM by serial EEPROM clock. Yes No —
28 Serial EEPROM Present. Val ue of 1 indicates serial EEPROM is present. Y es No 0
29 Reload Configurat i on Regis t ers. When set to 0, writing 1 causes the PCI 9080 to
reload Local Configurat i o n registers from serial EEPROM. Yes Yes 0
30 PCI Adapter S oftware Reset. Value of 1 holds Local Bus logic in the PCI 9080 reset
and LRESETo# asserted. Content s of PCI Configuration regist ers and S hared Run
Time registers are not reset. Soft ware Reset can only be cleared f rom the PCI Bus.
(Local Bus remains reset until this bit is cleared.)
Yes Yes 0
31 Local Init Status. Value of 1 indicates Local Init done. Responses to PCI accesses
are Retrys until thi s bit is set. While i nput pi n NB# is assert ed low, this bit is forc ed
to 1.
Yes Yes 0
Table 4-60. (PCIHIDR; PCI:70h, LOC:F0h) PCI Permanent Configuration ID Register
Bit Description Read Write Value after Reset
15:0 Permanent Vendor ID. Identifies devi ce manufacturer.
Note: Hardcoded to PCI SI G issued vendor ID of PLX (10B5h).
Yes No 10B5h
31:16 Permanent Device ID. Identifies particular device.
Note: Hardcoded to PLX part number for PCI interface chip PCI 9080.
Yes No 9080h
Table 4-61. (PCIHREV; PCI:74h, LOC:F4h) PCI Permanent Revision ID Register
Bit Description Read Write Value after Reset
7:0 Permanent Revisi on ID.
Note: Hardcoded to silicon revision of the PCI 9080.
Yes No Current Rev #
Section 4
Registers DMA Registers
PCI 9080 Data Book v1.06
80 PLX T e c hn ology, Inc. All r ights r e s e rved
4.6 DMA Registers
Table 4-62. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register
Bit Description Read Write Value after Reset
1:0 Local Bus Width. Value of 00 indicates bus width of 8 bits. Value of 01 indicates bus
width of 16 bits. Value of 10 or 11 indicates bus width of 32 bits. Yes Yes S = 01
J = 11
C = 11
5:2 Internal Wait States (dat a to dat a). Yes Yes 0
6 Ready Input Enable. Value of 1 enables Ready input. Value of 0 disables Ready
input. Yes Yes 0
7BTERM# Input Enable. Value of 1 enables BTERM# input. Value of 0 disables
BTERM# input. If set to 0, the PCI 9080 bursts four Lword maximum at a time. Yes Yes 0
8 Local Burst Enable. Value of 1 enables bursting. Value of 0 disabl es local bursti ng.
If burst is disabled, Local Bus performs continuous single cycles for Burst PCI
Read/Write cycle s.
Yes Yes 0
9 Chaining. Value of 1 indicates Chaining mode is enabled. For Chaining mode, DMA
source address, dest i nati on address and byte count are loaded from memory in
PCI or Local Address Spaces. Val ue of 0 indicates Non-chaining mode is enabled.
Yes Yes 0
10 Done Interrupt Enable. V al ue of 1 enables interrupt when done. Val ue of 0 disables
interrupt when done. If DMA Cl ear Count mode is enabled, interrupt does not occur
until byte count is cleared.
Yes Yes 0
11 Local Addressing Mode. Value of 1 indic ates Loc al Address LA[31:2] to be held
constant . V alue of 0 indicat es Local Address i s increm ented. Yes Yes 0
12 Demand Mode. Value of 1 causes DMA controller to operate in Demand mode.
In Demand mode, DMA controller transfers data when its DREQ[1:0]# input is
asserted. Asserts DACK[1:0]# to indicate current Local Bus transfer is in response
to DREQ[1:0]# input. DMA controll er transfers Lwords (32 bits) of data. May result
in multiple transfers for 8- or 16-bit bus.
Yes Yes 0
13 Write and Invalidat e Mode for DMA Transfers. When set to 1, the PCI 9080
performs Write and Invali date cycles to PCI Bus. The PCI 9080 supports Write and
Invali date sizes of 8 or 16 Lwords. Size specif i ed in PCI Cache Line Size Register.
If size other than 8 or 16 is specified, the PCI 9080 performs Write transfers rather
than Write and Invalidate t ransf ers. Transfe rs m ust start and end at Cache Line
boundaries.
Yes Yes 0
14 DMA EOT (End of Transfer) Enable. Value of 1 enables EOT[1:0]# input pin. Value
of 0 disables EOT[1:0]# input pin. (Refer t o Section 3.7.6.1, “E nd of Transfer
(EOT0# or EOT1#) Input.”)
Yes Yes 0
15 DMA Stop Data Transfer Mode. Value of 0 sends BLAST to terminate DMA
transf er. Value of 1 indicates EOT asserted or DREQ[1:0]# de-asserted duri ng
Demand mode DMA terminates a DMA transfer. (Refer t o Secti o n 3.7. 6.1, “End of
Transfer (EOT0# or EOT1#) Input.”)
Yes Yes 0
16 DMA Clear Count Mode. When set to 1, if it is in Local memory, byte count in each
chaining desc ri ptor is cleared when corresponding DMA transfer completes.
Note: If the chaining descri pt or is in PCI memory, the count is not cleared.
Yes Yes 0
17 DMA Channel 0 Inte rrupt Sel ect. Value of 1 routes DMA Channel 0 interrupt to
PCI int errupt. Value of 0 routes DMA Channel 0 interrupt to Loc al Bus interrupt. Yes Yes 0
31:18 Reserved. Yes No 0
Section 4
DMA Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 81
Table 4-63. (DMAPADR0; PCI:84h, LOC:104h) DMA Channel 0 PCI Address Register
Bit Description Read Write Value after Reset
31:0 PCI Address Register. Indicates from where in PCI memory space the DMA
transf ers (reads or writes) start. Yes Yes 0
Table 4-64. (DMALADR0; PCI:88h, LOC:108h) DMA Channel 0 Local Address Register
Bit Description Read Write Value after Reset
31:0 Local Address Register. Indicates from where in Local memory space the DMA
transf ers (reads or writes) start. Yes Yes 0
Table 4-65. (DMASIZ0; PCI:8Ch, LOC:10Ch) DMA Channel 0 Transfer Size (Bytes) Register
Bit Description Read Write Value after Reset
22:0 DMA Transf er Size (Bytes). Indicates number of bytes to transfer during
DMA operati on. Yes Yes 0
31:23 Reserved. Yes No 0
Table 4-66. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer Register
Bit Description Read Write Value after Reset
0 Descriptor Location. Val ue of 1 indicat es PCI Address s pace. Val ue of 0 indicates
Local Address Space. Yes Yes 0
1 End of Chain. Value of 1 indicates end of chain. Value of 0 indicates not end of
chain descriptor. (Same as Non-chaini ng Mode.) Yes Yes 0
2Interrupt aft er Terminal Count. Value of 1 causes interrupt to be generated after
terminal count for this desc ri ptor is reached. Value of 0 disabl es interrupts from
being generated.
Yes Yes 0
3Directi on of Transf er. Value of 1 indic ates t ransfers from the Local Bus to PCI Bus.
Value of 0 indicates transfers from the PCI Bus to Local Bus. Yes Yes 0
31:4 Next Descriptor Address . Quad word aligned (bits [3:0] = 0000). Yes Yes 0
Section 4
Registers DMA Registers
PCI 9080 Data Book v1.06
82 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-67. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Register
Bit Description Read Write Value after Reset
1:0 Local Bus Width. Value of 00 indicates bus width of 8 bits. Value of 01 indicates bus
width of 16 bits. Value of 10 or 11 indicates bus width of 32 bits. Yes Yes S = 01
J = 11
C = 11
5:2 Internal Wait States (dat a to dat a). Yes Yes 0
6 Ready Input Enable. Value of 1 enables Ready input. Value of 0 disables Ready
input. Yes Yes 0
7BTERM# Input Enable. Value of 1 enables BTERM# input. Value of 0 disables
BTERM# input. If set to 0, the PCI 9080 bursts four Lword maximum at a time. Yes Yes 0
8 Local Burst Enable. Value of 1 enables bursting. Value of 0 disabl es local bursti ng.
If burst is disabled, Local Bus performs continuous single cycles for Burst PCI
Read/Write cycle s.
Yes Yes 0
9 Chaining. Value of 1 indicates Chaining mode enabled. For Chaining mode, DMA
source address, dest i nati on address and byte count are loaded from memory in
PCI or Local address spaces. Value of 0 indicates Non-chai ni ng mode enabled.
Yes Yes 0
10 Done Interrupt Enable. V al ue of 1 enables interrupt when done. Val ue of 0 disables
interrupt when done. If DMA Cl ear Count mode is enabled, interrupt does not occur
until byte count is cleared.
Yes Yes 0
11 Local Addressing Mode. Value of 1 indic ates Loc al Address LA[31:2] to be held
constant . V alue of 0 indicat es Local Address i s increm ented. Yes Yes 0
12 Demand Mode. Value of 1 causes DMA controller to operate in Demand mode.
In Demand mode, DMA controller transfers data when its DREQ[1:0]# input is
asserted. Asserts DACK[1:0]# to indicate current Local Bus transfer is in response
to DREQ[1:0]# input. DMA controll er transfers Lwords (32 bits) of data. May result
in multiple transfers for 8- or 16-bit bus.
Yes Yes 0
13 Write and Invalidat e Mode for DMA Transfers. When set to 1, the PCI 9080
performs Write and Invali date cycles to PCI Bus. The PCI 9080 supports Write and
Invali date sizes of 8 or 16 Lwords. Size is specified i n PCI Cache Line Size
Register. If size ot her than 8 or 16 is specified, the PCI 9080 performs Write
transfers rather than Write and Invalidate transfers. Transf ers m ust start and end
at Cache Line boundaries.
Yes Yes 0
14 DMA EOT (End of Transfer) Enable. Value of 1 enables EOT[1:0]# input pin.
Value of 0 disables EOT[1:0]# input pin. (Refer to Section 3.7.6.1, “End of Transfer
(EOT0# or EOT1#) Input.”)
Yes Yes 0
15 DMA Stop Data Transfer Mode. Value of 0 BLAST terminates DMA transfer. Value
of 1 indicates EOT. In demand DMA mode, if set to 1, assertion of EOT causes
DMA controll e r to termi nate foll owi ng current Data phase (blast may or may not be
assert ed). If not set, and EOT assert ed, DMA cont roller c omple t es current Data
phase and potentially a following Dat a phase in which blast is asserted. (Refer to
Section 3.7.6.1, “End of Transfer (EOT0# or EOT1#) Input.”)
Yes Yes 0
16 DMA Clear Count Mode. When set to 1, byte count in each chaining descript or, if it
is in Local memory, is cleared when corresponding DMA transfer completes.
Note: If a chaining descriptor is i n PCI memory, the count is not cleared.
Yes Yes 0
17 DMA Channel 1 Interrupt S el ect. Value of 1 routes DMA Channel 1 interrupt to
PCI int errupt. Valu e of 0 routes DMA Channel 1 interrupt to Local Bus int errupt. Yes Yes 0
31:18 Reserved. Yes No 0
Section 4
DMA Registers Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 83
Table 4-68. (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register
Bit Description Read Write Value after Reset
31:0 PCI Data Address Register. Indicates from where in PCI memory space the DMA
transf ers (reads or writes) start. Yes Yes 0
Table 4-69. (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register
Bit Description Read Write Value after Reset
31:0 Local Data Address Register. Indicat es from where i n Local memory s pace the
DMA transfers (reads or writes) start. Yes Yes 0
Table 4-70. (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register
Bit Description Read Write Value after Reset
22:0 DMA Transf er Size (Bytes). Indicates number of bytes to transfer during
DMA operati on. Yes Yes 0
31:23 Reserved. Yes No 0
Table 4-71. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register
Bit Description Read Write Value after Reset
0 Descriptor Location. Val ue of 1 indicat es PCI Address s pace. Val ue of 0 indicates
Local Address Space. Yes Yes 0
1 End of Chain. Value of 1 indicates end of chain. Value of 0 indicates not end of
chain descriptor. (Same as Non-chaini ng mode.) Yes Yes 0
2Interrupt aft er Terminal Count. Value of 1 causes interrupt to be generated after
terminal count for this desc ri ptor is reached. Value of 0 disabl es interrupts from
being generated.
Yes Yes 0
3Directi on of Transf er. Value of 1 indic ates t ransfers from the Local Bus to PCI Bus.
Value of 0 indicates transfers from the PCI Bus to Local Bus. Yes Yes 0
31:4 Next Descriptor Address . Quad word aligned (bits [3:0] = 0000). Yes Yes 0
Table 4-72. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register
Bit Description Read Write Value after Reset
0 Channel 0 Enable. Value of 1 enables channel to transfer data. Value of 0 disables
channel from starting DMA transf er and if in process of transferring data suspend
transfer (pause).
Yes Yes 0
1 Channel 0 Start. Value of 1 causes channel to start transferring data if channel
is enabled. No Yes/Set 0
2Channel 0 Abort. Val ue of 1 causes channel to abort current transfer. Channel
Enable bit must be cleared. Channel Compl ete bit is set when abort is compl et e. No Yes/Set 0
3 Clear Interrupt. Writi ng 1 to this bit clears Channel 0 interrupts. No Y es/Clr 0
4 Channel 0 Done. Value of 1 indicates channel’s transfer is complete. Value of 0
indicates channel’s transfer is not complete. Yes No 1
7:5 Reserved. Yes No 0
Section 4
Registers DMA Registers
PCI 9080 Data Book v1.06
84 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-73. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register
Bit Description Read Write Value after Reset
0Channel 1 Enable. Value of 1 enables channel to transfer data. Value of 0 disables
channel from starting DMA transf er and if in process of transferring data suspend
transfer (Paus e).
Yes Yes 0
1 Channel 1 Start. Value of 1 causes channel to start transferring data if channel is
enabled. No Yes/Set 0
2 Channel 1 Abort. Value of 1 causes channel to abort current transfer. Channel
Enable bit must be cleared. Channel Compl ete bit set when abort is complete. No Yes/Set 0
3 Clear Interrupt. Writi ng 1 to this bit clears Channel 1 interrupts. No Y es/Clr 0
4 Channel 1 Done. Value of 1 indicates this channel’s transfer is complete. Value of 0
indicates channel’s transfer is not complete. Yes No 1
7:5 Reserved. Yes No 0
Table 4-74. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register
Same as Mode/Arbitration register (MARBR).
Table 4-75. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register
Bit Description Read Write Value after Reset
3:0 DMA Channel 0 PCI-to-Local Almost Full (C0PLAF). Number of full entries (divided
by two, minus one) in the FIFO before requesting Local Bus for writes.
(C0PLAF+1) + (C0PLAE+1) should be ≤ FIFO Depth of 32.
Yes Yes 0
7:4 DMA Channel 0 Local-to-PCI Almost Empty (C0LPAE). Number of empty entries
(divided by two, minus one) in the FIFO before request i ng Local Bus for reads.
(C0LPAF+1) + (C0LPAE+1) should be ≤ FIFO depth of 32.
Yes Yes 0
11:8 DMA Channel 0 Local-to-PCI Al m ost Full (C0LPAF). Number of full entri es
(divided by t wo, minus one) in the FIFO before requesting PCI Bus for writes. Yes Yes 0
15:12 DMA Channel 0 PCI -to-Loc al Almost Empty (C0PLAE). Num ber of empty ent ri es
(divided by two, minus one) in the FIFO before request i n g PCI Bus for reads. Yes Yes 0
19:16 DMA Channel 1 PCI -to-Loc al Almost Full (C1PLAF). Number of full entries
(minus one) in the FIFO before requesting Local Bus for writes.
(C1PLAF+1) + (C1PLAE+1) should be ≤ FIFO depth of 16.
Yes Yes 0
23:20 DMA Channel 1 Local-to-PCI Almost Empty (C1LPAE). Number of empty entries
(minus one) in the FIFO before requesting Local Bus for reads.
(C1PLAF) + (C1PLAE) should be ≤ FIFO depth of 16.
Yes Yes 0
27:24 DMA Channel 1 Local-to-PCI Almost Full (C1LPAF). Number of full entries
(minus one) in the FIFO before requesting PCI Bus for writes. Yes Yes 0
31:28 DMA Channel 1 PCI -to-Loc al Almost Empty (C1PLAE). Num ber of empty ent ri es
(minus one) in the FIFO before requesting PCI Bus for reads. Yes Yes 0
Note: If the number of entries needed is x, then the value is one less than half the number of entries
(DMA Channel 0 only).
Section 4
Messaging Queue Register s Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 85
4.7 Messaging Queue Regist er s
Table 4-76. (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register
Bit Description Read Write Value after Reset
2:0 Reserved. Yes No 0
3 Outbound Post List FIFO Interrupt. Set when the Outbound Post List FIFO is not
empty. Not affected by the Interrupt Mask bit. Yes No 0
31:4 Reserved. Yes No 0
Table 4-77. (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register
Bit Description Read Write Value after Reset
2:0 Reserved. Yes No 0
3 Outbound Post List FIFO Interrupt Mask. Interrupt is masked when set. Yes Yes 1
31:4 Reserved. Yes No 0
Table 4-78. (IQP; PCI:40h) Inbound Queue Port Register
Bit Description Read Write Value after Reset
31:0 Value written by the PCI Master is stored into the Inbound Post List FIFO, which is
located in Local memory at an address pointed to by Queue Base Address + FIFO
Size + Inbound Post Head Pointer. From the time of a PCI write until a Local
Memory write and update of the Inbound Post Queue Head Pointer, furt her
accesses to this register result in a Retry. A Local interrupt is generated when the
Inbound Post List FIFO is not empty.
When the port is read by a PCI Master, the value is read from the Inbound Free List
FIFO, which is located in Local memory at an address pointed to by Queue Base
Address + Inbound Free Tail Pointer. If the FIFO is empty, a value of FFFFFFFh
is returned.
PCI PCI 0
Table 4-79. (OQP; PCI:44 h) Outbound Queue Port Register
Bit Description Read Write Value after Reset
31:0 Value written by the PCI Master is stored into the Outbound Free List FIFO, which
is located in Local memory at an address point ed to by Queue Base Address +
(3*FIFO Size) + Outbound Free Head Pointer. From the time of the PCI write until
the Local Memory write and update of the Outbound Free Head Pointer, further
accesses to this register result in a Retry. If the FIFO fills up, a local LSERR
interrupt is generated.
When the port is read by a PCI Master, the value is read from the Outbound Post
List FIFO, which is located in Local memory at an address pointed to by Queue
Base Address + (2*FIFO Size) + Outbound Post Tail Pointer. If the FIFO is empty,
a value of FFFFFFFh is returned. A PCI interrupt is generated if the Outbound Post
List FIFO is not empty.
PCI PCI 0
Section 4
Registers Messaging Queue Regi sters
PCI 9080 Data Book v1.06
86 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-80. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register
Bit Description Read Write Value after Reset
0Queue Enable. Value of 1 allows accesses to the Inbound and Outbound Queue
Ports. If cleared to 0, writes are ac cepted but ignored, and reads return FFFFFFFF.
Complete all point er initializ at i ons and frame alloc ations bef ore enabling t his bit.
Yes Yes 0
5:1 Circular FIFO Size. Defines size of one of the circular FIFOs. Each of the four
FIFOs are the same size. Each FIFO entry is one 32-bit word.
FIFO Size Encoding
Max entries F I F O Tot al FIFO
5:1 per FIFO Size Memory
00001 4K entries 16 KB 64 K B
00010 8K entries 32 KB 128 K B
00100 16K entries 64 KB 256 KB
01000 32K entries 128 KB 512 KB
10000 64K entries 256 KB 1 MB
Yes Yes 00001
31:6 Reserved. Yes No 0
Table 4-81. (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register
Bit Description Read Write Value after Reset
19:0 Reserved. Yes No 0
31:20 Queue Base Address. Local memory base address of Inbound and Outbound
Queues (four contiguous and equal size FIFOs). Queue base address must be
aligned on 1 MB boundary.
Yes Yes 0
Table 4-82. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register
Bit Description Read Write Value after Reset
1:0 Reserved. Yes No 0
19:2 Inbound Free Head Pointer. Local Memory Offset for the Inbound Free List FIFO.
Initialized as (0*FIFO Size) and maintained by local CPU software. Yes Yes 0
31:20 Queue Base Address. Yes No 0
Table 4-83. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register
Bit Description Read Write Value after Reset
1:0 Reserved. Yes No 0
19:2 Inbound Free Tail Pointer. Local Memory Offset for the Inbound Free List FIFO.
Initialized as (0*FIFO Size) by local CPU software. Maintained by MU hardware
and incremented modulo the FIFO size.
Yes Yes 0
31:20 Queue Base Address. Yes No 0
Section 4
Messaging Queue Register s Registers
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 87
Table 4-84. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register
Bit Description Read Write Value after Reset
1:0 Reserved. Yes No 0
19:2 Inbound Post Head Pointer. Local Memory Offset for the Inbound Post List FIFO.
Initialized as (1*FIFO Size) by local CPU software. Maintained by MU hardware
and incremented modulo the FIFO size.
Yes Yes 0
31:20 Queue Base Address. Yes No 0
Table 4-85. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register
Bit Description Read Write Value after Reset
1:0 Reserved. Yes No 0
19:2 Inbound Post Tail Pointer. Local Memory Offset for the Inbound Post List FIFO.
Initialized as (1*FIFO Size) and maintained by local CPU software. Yes Yes 0
31:20 Queue Base Address. Yes No 0
Table 4-86. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register
Bit Description Read Write Value after Reset
1:0 Reserved. Yes No 0
19:2 Outbound Free Head Pointer. Local Memory Offset for the Outbound Free
List FIFO. Initialized as (3*FIFO Size) by local CPU software. Maintained by
MU hardware and inc remented modulo the FIFO size.
Yes Yes 0
31:20 Queue Base Address. Yes No 0
Table 4-87. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register
Bit Description Read Write Value after Reset
1:0 Reserved. Yes No 0
19:2 Outbound Free Tail Pointer. Local Memory Offset for the Outbound Free List FIFO.
Initialized as (3*FIFO Size) and maintained by local CPU software. Yes Yes 0
31:20 Queue Base Address. Yes No 0
Table 4-88. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register
Bit Description Read Write Value after Reset
1:0 Reserved. Yes No 0
19:2 Outbound Post Head Poi nter. Local Memory Offset f or the Outbound Post List
FIFO. Initialized as (2*FIFO Size) and maintained by local CPU software. Yes Yes 0
31:20 Queue Base Address. Yes No 0
Section 4
Registers Messaging Queue Regi sters
PCI 9080 Data Book v1.06
88 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 4-89. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register
Bit Description Read Write Value after Reset
1:0 Reserved. Yes No 0
19:2 Outbound Post Tail Pointer. Local Memory Offset for the Outbound Post List FIFO.
Initializ ed as (2*FIFO Size). Maintained by MU hardware and incremented modulo
the FIFO size.
Yes Yes 0
31:20 Queue Base Address. Yes No 0
Table 4-90. (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register
Bit Description Read Write Value after Reset
0I
2O Decode Enable. When set, replaces Mailbox regist ers 0 and 1 with the Inbound
and Outbound Queue Port registers and redefines Space 1 as PCI Base Address 0
to be accessed by PCIBAR0. Former Space 1 registers F0, F4, and F8 should be
programmed to configure thei r shared I2O memory space, defined as PCI Base
Address 0.
Yes Yes 0
1 Queue Local Space Select. When set to 0, use Local Address Space 0 Bus Region
descriptor f or Queue access es. When set to 1, use Local Address Space 1
Bus Regi on descri ptor for Queue accesses.
Yes Yes 0
2Outbound Post List FIFO Prefetch Enable. When set, prefetchi ng occurs from the
Outbound Post List FIFO if it is not empty. Yes Yes 0
3 Inbound Free List FIFO Prefetch Enable. When set, prefetching occurs from the
Inbound Free List FIFO if it is not empty. Yes Yes 0
4 Inbound Post List FIFO Interrupt Mask. When set, Interrupt is masked. Yes Yes 1
5Inbound Post List FIFO Interrupt. Set when the Inbound Post List FIFO is not
empty. Not affected by the Interrupt Mask bit. Yes No 0
6 Outbound Free List FIFO Overflow Interrupt Mask. When set, Interrupt is masked. Yes Yes 1
7 Outbound Free List FIFO Overflow Interrupt. Set when the Outbound Free List
FIFO becomes full. A Local LSERR (NMI) interrupt is generated if enabled in the
Interrupt Control/Status register. Writing 1 clears i nterrupt.
Yes Yes/Clr 0
31:8 Unused. Yes No 0
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 89
5. PIN DESCRI PTION
5.1 Pin Summary
The tables in this section describe the PCI 9080 pins.
Table 5-2 through Table 5-5 provide pin information
common to all three Local Bus modes of operation—
C, J, and S:
• Power and Ground
• Serial EE PRO M Inter fac e
• PCI System Bus Inter fac e
• Local Bus Mod e and Proc es s or
Independent Interface
The pins in Table 5-6 through Table 5-8 correspond
to the Local Bus modes of the PCI 9080:
• C Bus Mode Interface Pin Description (32-bit
address/32- b it dat a, nonm ult ip lex ed)
• J Bus Mode Interface Pin Description (32-bit
address/ 32-b it data, multip lex ed)
• S Bu s Mode Interfa ce Pin Description (32-bit
address/ 16-b it data, multip lex ed)
The following pins have internal pull-ups:
ADMODE, BIGEND#, BTERM#, DREQ[1:0]#, EEDO,
EESEL, LINTi#, LLOCK#, LRESETi#, NB#, READYi#,
S[2:0], SHORT#, and WAITI#.
The following pins have internal pull-downs: BREQ,
LHOLDA, TEST, and USERI.
For a visual view of the chip pin out, refer to Figure 7-3
in Section 7.3, “PCI 9080 Pin Out.”
Table 5-1 lists the abbreviations used in this section to
represent the various pin types.
Table 5-1. Pin Type Abbreviations
Abbreviation Pin Type
I/O Input and output pin
I Input pin only
O Output pi n only
TS Tri-state pin
OC Open coll ector pin
TP Totem pole pin
STS Sustained tri-state pi n, driven high for one CLK
before float
DTS Driven tri-state pin, driven high for one-half CLK
before float
All Local Bus internal pull-ups go through a 2 kΩ
resistor. All Local Bus internal pull-downs go through a
100 kΩ resistor.
All local tri-state I/O pins should have external pull-ups
(use 3 kΩ - 10 kΩ).
Unspecified pins are not connected.
Note: For PCI Pins, DO NO T pull any pins up or down
unless the PCI 9080 is being used in an embedded
design. Refer to the PCI Local Bus Specification, v2.1,
page 123.
Section 5
Pin Description Pin Out Common to All Bus Modes
PCI 9080 Data Book v1.06
90 PLX T e c hn ology, Inc. All r ights r e s e rved
5.2 Pin Out Common to All Bus Modes
Table 5-2. Power and Ground Pin Description
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
TEST Tes t 1 I 49 Tes t Pin. Pull high for test, low for normal operation. When TEST is
pulled high, all outputs exc ept USERO (pin 27) are placed in tri-state.
USERO provides a NAND-TREE output when TEST is pulled high.
VDDL (Core) Power (+5V ) 6 I 53, 68, 105,
144, 157, 167 Five volt power supply pins for core.
Liberal .01 to .1 µF decoupling capacitors should be placed near the
PCI 9080.
VDDH (PCI ) Power
(+5V or +3.3V ) 3 I 38, 60, 83 Power supply pins for PCI B us pins .
Liberal .01 to .1 µF decoupling capacitors should be placed near the
PCI 9080.
VDDH
(Local) Power
(+5V ) 3 I 1, 124, 184 Power supply pins for Local Bus pins.
Liberal .01 to .1 µF decoupling capacitors should be placed near the
PCI 9080.
VSS Ground 20 I 22, 37, 45,
52, 59, 67,
75, 82, 90,
98, 104, 114,
123, 134,
143, 156,
166, 183,
193, 208
Ground pins.
Table 5-3. Serial EEPROM Interface Pin Description
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
EECS Serial EEPROM Chip
Select 1O
TP
8 mA
176 Serial EEPROM chip select.
EEDI Serial EEPROM Data
IN 1O
TP
8 mA
172 Writ e dat a to serial EEPROM.
EEDO Serial EEPROM Data
OUT 1 I 171 Read data f rom serial EEPROM.
EESK Serial Data Clock 1 O
TP
8 mA
173 Seri a l EEPROM cloc k.
SHORT# Load Short 1 I 174 When active low, only five 32-bit registers are loaded from the serial
EEPROM. When active high, all Local Configurati on registers are also
loaded from serial EEPROM.
EESEL Serial EEPROM
Select 1 I 175 When hi gh, use 93CS 46 (1K bit) serial EEPROM.
When low, use 93CS56 (2K bit) serial EEPROM.
Note: Serial EE PROM inter face opera tes at the core voltage (+5V). The PC I 908 0 requir es t he use of a ser ial EEPROM
that can operate up to 1 MHz.
Section 5
Pin Out Common to All Bus Modes Pin Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 91
Table 5-4. PCI System Bus Interface Pin Description
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
AD[31:0] Address and Data 32 I/ O
TS
PCI
32-36, 39-44,
46-47, 76-81,
84-89, 91-97
All mult iplexed on th e sa me PC I pins. Bus tra nsa ctio n con sists of an
Address phas e followed by one or more Data phases. The PCI 9080
supports bot h Read and Write bursts.
C/BE[3:0]# Bus Command and
Byte Enables 4I/O
TS
PCI
70-73 All multiplexed on the same PCI pins. During Address phase of a
transaction, C/BE[3:0]# defines the bus command. During Data phase
C/BE[3: 0]# are used as Byte Enables. Refer t o PCI Specifi cation v2.1
for further detail.
CLK Clock 1 I 54 Provides timing for all transactions on PCI and is an input to every
PCI devic e. PCI operat es up to 33 MHz.
DEVSEL# Device Select 1 I/O
STS
PCI
64 When ac tively driven, indicates driving device has decoded its
address as Target of current access. As an input, indicat es whet her
any device on bus is selected.
FRAME# Cycle Frame 1 I/O
STS
PCI
57 Driven by current Master to indicate beginni ng and durati on of
an access. FRAME# is asserted to indicate a bus transaction is
beginning. Whil e FRAME# is asserted, Data transfers conti nue.
When FRAME# is de-assert ed, transaction is in final Data phase.
GNT# Grant 1 I 51 Indicates to agent that access to bus is granted. Every Master has
its own REQ# and GNT#.
IDSEL Initialization Device
Select 1 I 63 Used as chip select duri ng configuration Read and Write transactions.
INTA# Interrupt A 1 O
OC
PCI
55 Us ed to request interrupt.
IRDY# Ini tiator Ready 1 I/O
STS
PCI
61 I ndi cates ability of initiating agent (Bus Master) to complete current
Data phase of transacti on.
LOCK# Lock 1 I/O
STS
PCI
69 I ndi cates an atomic operation that may require multiple transact ions
to comple te.
PAR Parity 1 I/O
TS
PCI
74 Even parity across AD[ 31: 0] and C/BE[ 3:0] #. All PCI agents require
parity generation. PAR is stable and valid one clock after Address
phase. For Data phases, PAR is stable and valid one clock after
either IRDY # is asserted on a Write transaction or TRDY# is asserted
on a Read transaction. Once PAR is valid, it remains val i d until one
clock after completion of current Data phase.
PERR# Parity Err or 1 I/O
STS
PCI
65 Reporting of data parity errors duri ng al l PCI transactions, except
during a Special Cycle.
REQ# Request 1 O
PCI 50 Indi cates to arbiter that this agent needs to use the bus. Every Master
has its own GNT# and REQ#.
RST# Reset 1 I 56 Used to bring PCI-specific regist ers, sequencers and signals to a
consistent state.
SERR# Systems Error 1 O
OC
PCI
66 Report s address parity errors, dat a parit y errors on Special Cycle
command, or any other system error where res ult will be catast rophi c.
STOP# Stop 1 I/O
STS
PCI
62 Indicates c urrent Target is requesting Master to stop current
transaction.
TRDY# Target Ready 1 I/O
STS
PCI
58 I ndi cates ability of Target agent (selected devic e) to complete current
Data phase of transacti on.
Section 5
Pin Description Pin Out Common to All Bus Modes
PCI 9080 Data Book v1.06
92 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 5-5. Local Bus Mode and Process or Independent Interface Pin Descri ption
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
ADMODE Address Decode
Mode 1 I 20 Determines how S[ 2:0] are used to access the PCI 9080 Internal
registers.
BIGEND # Big Endia n Se le c t 1 I 48 Can be asse rt ed during Local Bus Address phase of Direct Master
transf er or Configuration Register access to specify use of Big Endian
byte ordering. Big E ndian byt e order for Direct Master transfers or
Configurati on Register accesses is also programmable t hrough
Configurati on regi sters.
BPCLKo Buffe r e d PC I Clock
Output 1O
TP
8 mA
168 Provides a buffered PCI clock output.
BREQ Bus Request 1 I 169 Asserted to indicate a Local Bus Master requires the bus. If enabled
through the PCI 9080 Configurati on registers, the PCI 9080 rel eases
bus during a DMA transfer if this signal is asserted.
BREQo Bus Request Out 1 O
TP
8 mA
21 A ss erted to indicate the PCI 9080 requires bus to perform a direct
PCI-to -Local Bus access while a Direct Master access is pending on
Local Bus. It can be used with external l ogic to generat e Back off to a
Local Bus Master. Its operational parameters are set up through the
PCI 9080 Confi guration regis t ers.
BTERMo# Burst Terminate Out 1 O
DTS
8 mA
28 A ss e rt ed, along wit h READY o#, to request break up of a burst and
start of a new Address cycle (Abort only).
DACK[1:0]# DMA Acknowledge
Outputs 2O
TP
8 mA
25, 30 When a channel is programmed through the Configurati on registers to
operate in Demand mode, its DACK output indicates a DMA transfer
is being executed. DA CK0# corresponds to the PCI 9080 DMA Ch 0
and DACK1# to DMA Ch 1.
DMPAF# Direct Master
Programmable Almost
Full
1O
TP
8 mA
8Direct Master Write FIFO almost f ull status out put. Programm abl e
through a Configurat i o n register.
DP[3:0] Data Parity 4 I/O
TS
8 mA
12-15 Pari ty is even for each of up to four byte lanes on Local Bus. Parity is
checked for writ es to the PCI 9080 or reads by the PCI 9080. Parity is
generated for reads from the PCI 9080 or writes by the PCI 9080.
DREQ[1:0]# DMA Request Inputs 2 I 24, 29 When a channel is programmed through t he Configuration registers to
operate in Demand mode, its DREQ input serves as a DMA request.
DREQ0# corresponds to the PCI 9080 DMA Ch 0 and DREQ1# to
DMA Ch 1.
LDSHOLD Direct Slave HOLD
Request 1O
TP
8 mA
165 Ass erted concurrent with LHOLD to indicate the PCI 9080 is
requesting use of Local Bus to perform a Direct Slave transfer.
LINTi# Local Int errupt In 1 I 151 When assert ed l ow, caus es a PCI interrupt.
LINTo# Local Interrupt Out 1 O
TP
8 mA
152 Synchronous lev el output t h at remai ns asserted as long as an
interrupt condition exists. If an edge level interrupt is required,
disabling and then enabl i ng Local interrupts t hrough the Interrupt
Control/Status register (INTCSR) creates an edge if the interrupt
conditi on stil l exist s or a new interrupt c ondition occurs.
LLOCKo# Bus Lock 1 O
TP
8 mA
7 Indi cates an atomic operation for a Direct Slav e PCI-to-Loc al Bus
access m ay require multi p l e transactions to complete.
LRESETi# Local Reset Input 1 I 150 Resets Local Bus portion of the PCI 9080, Local Configuration
registers and DMA Confi gurat ion registers. Also causes local reset
output to be asserted.
Section 5
Pin Out Common to All Bus Modes Pin Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 93
Table 5-5. Local Bus Mo de a nd Processor Indepe ndent Int erface Pin Description (continued)
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
LSERR# System Err o r
Interrupt Output 1O
TP
8 mA
23 Synchronous level output asserted when PCI Bus Target Abort or
Master Abort Stat us bit is set in PCI Status Configuration regis t er.
If an edge level interrupt is required, disabl i ng and then enabli ng
LSERR# interrupt s t h rough i nterrupt /c ontrol status creates an edge
if interrupt condi t i on sti l l exist s or new interrupt condi tion occurs.
MODE[1:0] B us Mode 2 I 9, 10 Selects bus operat i o n mode of the PCI 9080:
Bit 1 Bit 0 Bus Mode
00C
01J
10S
1 1 Reserved
NB# No Local Bus
Initialization 1 I 26 Externally forces Local Init Done bit in Init Control Register to 1.
Init Done bit is also programmable through Local Bus Confi gurat ion
accesses. The PCI 9080 issues Retrys to all PCI accesses until
Local Init Done bit is set. If this bit is not going to be set by a Local
processor, tie NB# low.
PCHK# Data Parity Check 1 O
TP
8 mA
16 P ari ty is check ed for writes t o the PCI 9080 or reads by the PCI 9080.
Parity is check e d for each byte lane with its byte enable asserted.
Asserted in Clock cycle following data bei ng checked if a parity error
is detected.
S[2:0] Address Select 3 I 17-19 If ADMODE is high, internal PCI 9080 registers are selected when
LA[31:29] match S[2:0].
If ADMODE is low, internal PCI 9080 registers are selected when
S0 is asserted low.
USERI User Input 1 1 31 General -purpose input that can be read from the PCI 9080
Configurati on regi sters.
USERO User Output 1 O
TP
12 mA
27 General-purpose output control l ed from the PCI 9080 Configuration
registers.
WAITI# Wai t Input 1 I 6 Can be asserted to cause the PCI 9080 to insert wait states for Local
Direct Mast er accesses to PCI Bus. Can be thought of as a ready
input for Direct Master accesses.
WAITO# Wait Out 1 O
TS
8 mA
149 Indicates t he PCI 9080 programmable wait state generat or st atus.
WAITO# is asserted when wait states are being caused by internal
wait stat e generator. Can be thought of as an output providing Ready
Out status.
Section 5
Pin Description C Bus Mode Pin Out
PCI 9080 Data Book v1.06
94 PLX T e c hn ology, Inc. All r ights r e s e rved
5.3 C Bus Mode Pin Out
Table 5-6. C Bus Mode Interface Pin Description
C Mode Bus
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
ADS# Address Strobe 1 I/O
TS
12 mA
154 Indi cates a valid address and start of a new Bus access. Assert ed
for first clock of a Bus access.
BLAST# Burst Last 1 I/O
TS
8 mA
155 Signal driven by current Local Bus Master to indicate last transfer
in a Bus access.
BTERM# B urst Terminate 1 I 146 For processors that burst up to four Lwords. If Bterm is disabl ed
through the PCI 9080 Configurati on registers, the PCI 9080 also
bursts up to four Lwords. If enabled, t he PCI 9080 continues to burst
until a BTERM# input is assert ed. BTERM# is a ready input that
breaks up a Burst cycle and causes another Address cycle to occur.
Used in conjuncti on with the PCI 9080 programmable wait state
generator.
DEN# Dat a Enable 1 O
TS
12 mA
145 Used in conjuncti on with DT/R# to provide control for data
transceiv ers attached t o Local Bus.
DT/R# Data
Transmit/Receive 1O
TS
12 mA
138 Used i n conj unct i on wit h DEN# to provide control for data transceivers
attached to Local Bus. When asserted, signal indicates t he PCI 9080
receives data.
LW/R# Write/Read 1 I/O
TS
12 mA
137 Ass erted low for reads and high for writes.
LLOCK# Bus Lock 1 I 153 Indicates an atomic operation that may require multipl e trans actions
to complete. Used by the PCI 9080 for Direct Local access to
PCI Bus.
LA[31:2] Address Bus 30 I/O
TS
8 mA
136, 135,
133-125,
122-115,
113-106,
103-101
Carries upper 30 bits of physical address bus. During bursts, LA[ 31:2]
increment to indicate successive Data cycles.
LD[31:0] Data Bus 32 I/O
TS
8 mA
177-182,
185-192,
194-207, 2-5
Carries 32-, 16-, or 8-bit dat a quantities dependi ng on bus wi dth
configuration.
Section 5
C Bus Mode Pin Out Pin Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 95
Table 5-6. C Bus Mode Interface Pin Description (continued)
C Mode Bus
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
LBE[3:0]# Byte Enables 4 I/O
TS
12 mA
139-142 Encoded, based on configured bus width, as foll ows:
32-bit bus:
For a 32-bit bus, the four byte enables indicate whic h of the four bytes
are active duri ng a Data cycle :
BE3# Byte Enable 3—LD[31:24]
BE2# Byte Enable 2—LD[23:16]
BE1# Byte Enable 1—LD[15:8]
BE0# Byte Enable 0—LD[7:0]
16-bit bus:
For a 16-bit bus, BE3#, BE1# and BE0# are encoded to provide
BHE#, LA1, and BLE#, respectively:
BE3# Byte High Enable (BHE#)—LD[15:8]
BE2# not used
BE1# Address bit 1 (LA1)
BE0# Byte Low Enable (BLE#)—LD[7:0]
8-bit bus:
For an 8-bit bus, BE1# and BE0# are encoded to provide LA1and
LA0, respectivel y:
BE3# not used
BE2# not used
BE1# Address bit 1 (LA1)
BE0# Address bit 0 (LA0)
LCLK Loca l Pr o cesso r
Clock 1 I 160 Local clock input.
LHOLD Hold Reques t 1 O
TP
8 mA
158 Ass erted to request use of Local Bus. The Local Bus arbiter asserts
LHOLDA when control is granted.
LHOLDA Hold Acknowledge 1 I 159 Asserted by Local Bus arbiter when control is granted in response
to LHOLD. The bus should not be granted to the PCI 9080 unless
requested by LHOLD.
LRESETo# Local Bus Reset Out 1 O
TP
8 mA
11 A ss erted when the PCI 9080 chip is reset. Used to drive RESET#
input of Local processor.
READYi# Ready In 1 I 147 When the PCI 9080 is a Bus Master, indicates that Read data on bus
is valid or that a Write Data transfer is complete. Used in conjunction
with the PCI 9080 programmabl e wait state generat or.
READYo# Ready Out 1 O
DTS
8 mA
148 When a Local Bus access is made to the PCI 9080, indicates Read
data on bus is valid or a Write Data transfer is complete. READYo#
can be connected to READYi#.
EOT0# End of Transfer for
DMA Ch 0 1 I 163 Terminates current DMA Ch 0 transfer.
EOT1# End of Transfer for
DMA Ch 1 1 I 164 Terminates current DMA Ch 1 transfer.
Section 5
Pin Description J Bus Mode Pin Out
PCI 9080 Data Book v1.06
96 PLX T e c hn ology, Inc. All r ights r e s e rved
5.4 J Bus Mode Pin Out
Table 5-7. J Bus Mode Interface Pin Description
J Bus Mode
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
ALE Address Latch Enable 1 O
TS
8 mA
161 Ass erted during Address phase and de-asserted before Data phase.
ADS# Address Strobe 1 I/O
TS
12 mA
154 Indicates valid address and start of a new Bus access. Assert ed for
first cl ock of a Bus access.
BLAST# Burst Last 1 I/O
TS
8 mA
155 Si gnal driven by current Local Bus Master to indicate last transfer
in a Bus access.
BTERM# B urst Terminate 1 I 146 For processors that burst up to four Lwords. If Bterm is disabl ed
through the PCI 9080 Configurati on registers, the PCI 9080 also
bursts up to four Lwords. If enabled, t he PCI 9080 continues to burst
until a BTERM# input is assert ed. BTERM# is a ready input that
breaks up a Burst cycle and causes another Address cycle to occur.
Used in conjuncti on with the PCI 9080 programmable wait state
generator.
DEN# Dat a Enable 1 I/O
TS
12 mA
145 As an input, DEN# must only be assert ed duri ng Data phases. For
processor systems in which ADS# is not asserted during Data phase,
DEN# can be pulled high.
As an output, DT/R# is used in conjunction with DEN# to provide
control for dat a transce ivers att ached to Local Bus.
DT/R# Data
Transmit/Receive 1O
TS
12 mA
138 Used in conjuncti o n with DEN# to provide cont rol for dat a transc eivers
attached to Local Bus. When asserted, signal indicates t he PCI 9080
receives data.
LW/R# Write/Read 1 I/O
TS
12 mA
137 Ass erted low for reads and high for writes.
LABS[3:2] Address Bus Burst 2 I/O
TS
8 mA
162,163 Carries word address of 32-bit memory address. Incremented during
Burst access.
LAD[31:0] Address/Data Bus 32 I/O
TS
8 mA
136, 135,
133-125,
122-115,
113-106,
103-99
During Address phase, bus carries upper 30 bits of physical address
bus. During Data phase, bus carri es 32 bits of data.
Section 5
J Bus Mode Pin Out Pin Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 97
Table 5-7. J Bus Mode Interface Pin Description (continued)
J Mode Bus
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
LBE[3:0]# Byte Enables 4 I/O
TS
12 mA
139-142 Byte enables are encoded based on configured bus width as follows:
32-Bit Bus:
For a 32-bit bus, the four byte enables indicate whic h of the four bytes
are active duri ng a Data cycle :
BE3# Byte Enable 3—LAD[31:24]
BE2# Byte Enable 2—LAD[23:16]
BE1# Byte Enable 1—LAD[15:8]
BE0# Byte Enable 0—LAD[7:0]
16-Bit Bus:
For a 16-bit bus, BE3#, BE1# and BE0# are encoded to provide
BHE#, LA1, and BLE#, respectively:
BE3# Byte High Enable (BHE#)—LAD[15:8]
BE2# not used
BE1# Address bit 1 (LA1)
BE0# Byte Low Enable (BLE#)—LAD[7:0]
8-Bit Bus:
For an 8-bit bus, BE1# and BE0# are encoded to provide LA1and
LA0, respectivel y:
BE3# not used
BE2# not used
BE1# Address bit 1 (LA1)
BE0# Address bit 0 (LA0)
LCLK System Clock 1 I 160 Local clock input.
LHOLD Hold Reques t 1 O
TP
8 mA
158 Ass erted to request use of Local Bus. The Local Bus arbiter asserts
LHOLDA when control is granted.
LHOLDA Hold Acknowledge 1 I 159 Asserted by Local Bus arbiter when control is granted in response
to LHOLD. The bus should not be granted to the PCI 9080 unless
requested by LHOLD.
LLOCK# Bus Lock 1 I 153 Indicates an atomic operation that may require multipl e trans actions
to complete. Used by the PCI 9080 for Direct Local access to
PCI Bus.
LRESETo# Local Bus Reset Out 1 O
TP
8 mA
11 A ss erted when the PCI 9080 chip is reset.
READYi# Ready In 1 I 147 When the PCI 9080 is a Bus Master, READYi# is used to indicate
Read data on bus is valid or a Write Data transfer is complete.
READYi# is used in conjunction wit h the PCI 9080 programmable wait
state generator.
READYo# Ready Out 1 O
DTS
8 mA
148 When a Local Bus access is made to the PCI 9080, indicates that
Read data on bus is valid or that a Write Data transfer is complete.
READYo# can be connected to READYi#.
EOT0# End of Transfer for
DMA Ch 0 1 I 4 Terminat es current DMA Ch 0 transf er.
EOT1# End of Transfer for
DMA Ch 1 1 I 5 Terminat es current DMA Ch 1 transf er.
Section 5
Pin Description S Bus Mode Pin Out
PCI 9080 Data Book v1.06
98 PLX T e c hn ology, Inc. All r ights r e s e rved
5.5 S Bus Mode Pin Out
Table 5-8. S Bus Mode Interface Pin Description
S Bus Mode
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
ALE Address Latch
Enable 1O
TS
8 mA
161 Ass erted during Address phase and de-asserted before Data phase.
AS# Address Strobe 1 I/O
TS
12 mA
154 Indicates valid address and start of a new Bus access. Assert ed for
first cl ock of a Bus access.
BLAST# Burst Last 1 I/O
TS
8 mA
155 Si gnal driven by current Local Bus Master to indicate last transfer
in a Bus access.
BTERM# Burst Terminate 1 I 146 For processors that burst up to eight words and do not use BTERM#
input. If Bterm is disabled through the PCI 9080 Configuration
registers, the PCI 9080 also bursts up to eight words. If enabled,
the PCI 9080 continues to burst until a BTERM# input is asserted.
BTERM# breaks up a Burst cycl e and causes anot her Address cycl e
to occur. Used in conjunct i on with the PCI 9080 programmable wait
state generator.
DEN# Data E n abl e 1 O
TS
12 mA
145 Used i n conj unct i on with DT/R# to provide control for data
transceiv ers attached t o Local Bus.
DT/R# Data
Transmit/Receive 1O
TS
12 mA
138 Used i n conj unct i on wit h DEN# to provide control for data transceivers
attached to Local Bus. When asserted, signal indicates t he PCI 9080
is receiving data.
LA[31:16] Address Bus 16 I/O
TS
8 mA
136, 135,
133-125,
122-118
Carries upper 16 bits of address.
LABS[3:1] Address Bus Burst 3 I/O
TS
8 mA
162-164 Carries word address of 32-bit memory address. Incremented during
Burst access.
LAD[15:1],D0 Address/Data Bus 16 I/O
TS
8 mA
117-115,
113-106,
103-99
During Address phase, carries lower physical address bits. During
Data phase, carries 16 bits of data.
LBE[1:0]# Byte Enables 2 I/O
TS
12 mA
141,142 Indicate which of the two bytes are active during a Data cycle.
LCLK Local Clock 1 I 160 Loc al clock i nput.
Note: For i960
S processor systems , CLK 2 input . i9 60
S
processor’ s RESET# input must be connected to the PCI 9080
LRESETo# output. This enables the PCI 9080 to determine phase
of 2x clock processor.
LHOLD Hold Request 1 O
TP
8 mA
158 Ass erted to request use of Local Bus. The Local Bus arbiter asserts
LHOLDA when control is granted.
LHOLDA Hold Acknowledge 1 I 159 Asserted by Local Bus arbiter when control is granted in response
to LHOLD. The bus should not be granted to the PCI 9080 unless
requested by LHOLD.
Section 5
S Bus Mode Pin Out Pin Description
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 99
Table 5-8. S Bus Mode Interface Pin Description (continued)
S Bus Mode
Symbol Signal Name Total
Pins Pin
Type Pin
Number Function
LLOCK# Bus Lock 1 I 153 Indicates an atomic operation that may require multipl e trans actions
to complete. Used by the PCI 9080 for Direct Local access to
PCI Bus.
LRESETo# Local Bus Reset Out 1 O
TP
8 mA
11 A ss erted when the PCI 9080 chip is reset.
Note: For i960
S processors, this out put must be used to drive
Reset Input of i960
S processor. Enables the PCI 9080 to determine
phase of 2x clock processor
.
LW/R# Write/Read 1 I/O
TS
12 mA
137 Ass erted low for reads and high for writes.
READYi# Ready In 1 I 147 When the PCI 9080 is a Bus Master, READYi# is used to indicate
Read data on bus is valid or a Write Data transfer is complete.
READYi# is used in conjunction wit h the PCI 9080 programmable
wait stat e generator.
READYo# Ready Out 1 O
DTS
8 mA
148 When a Local Bus access is made to the PCI 9080, indicates that
Read data on bus is valid or that a Write Data transfer is complete.
READYo# can be connected to READYi#.
EOT0# End of Transfer for
DMA Ch 0 1 I 4 Terminat es current DMA Ch 0 transf er.
EOT1# End of Transfer for
DMA Ch 1 1 I 5 Terminat es current DMA Ch 1 transf er.
PCI 9080 Data Book v1.06
100 PLX T e c hn ology, Inc. All r ights r e s e rved
This page intentionally left blank.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 101
6. ELECTRICAL SPECIFICATIONS
6.1 General Specifications
Table 6-1. Absolute Maximum Ratings
Specification Maximum Rating
Storage Temperature -65 t o +150 °C
Ambient Temperature with Power Applied -55 to +125 °C
Supply Voltage to Ground -0.5 to +7.0V
Input Voltage (VIN) (5V only) VSS -0.5V , VDD +0.5V
Output Voltage (VOUT) (5V only) VSS -0.5V , VDD +0.5V
Input Voltage (VIN) (3V only) VSS -0.3V , VDD +0.3V
Output Voltage (VOUT) (3V only) VSS -0.3V , VDD +0.3V
Table 6-2. Operating Ranges
Input Voltage (VIN) Ambient
Temperature Supply Voltag e
(VDD) Min Max
5V ±5% VSS VDD
-40 to +85 °C3V ±5% VSS VDD
Table 6-3. Capacitance (sample tested only)
Parameter Test Conditions Pin Type Typical Value Units
CIN VIN = 2.0V , f = 1 MHz Input 5 pF
COUT VOUT = 2.0V , f = 1 MHz Output 10 pF
Section 6
Electrical Specifications General Specifications
PCI 9080 Data Book v1.06
102 PLX T e c hn ology, Inc. All r ights r e s e rved
Table 6-4. Electrical Characteristics Estimated over Operating Range
Parameter Description Test Conditions Min Max Units
VOH Output High
Voltage IOH = -4.0 mA 2.4 Vcc V(1)
VOL Output Low
Voltage
1.5V
IOL per Tables VSS 0.4 V (1)
VIH Input High Level Vcc — TTL = 2.0 VDD+10% V(1)
VIL I nput Low Level Vss — TTL = -0.5v TTL = 0.8v V(1)
VOH3 PCI 3.3V Output
High Voltage 1.8V IOH = -4.0 mA 0.9 Vcc Vcc V
VOL3 PCI 3.3V Output
Low Voltage 1.8V IOL per Tables Vss 0.1 Vcc V
VIH3 PCI 3.3V Input
High Level Vcc — 0.5 Vcc Vcc +0.5 V
VIL3 PCI 3.3V Input
Low Level Vss — -0.5 Vcc 0.3 Vcc V
ILI Input Leakage
Current VSS ≤ VIN ≤ VDD, VDD = Max -10 +10
µ
A
IOZ Tri-State Output
Leakage Current VDD = Max, VS S ≤ VIN ≤ VDD -10 +10
µ
A
ICC Power Supply
Current VDD=5.25V, PCLK=LCLK= 33 MHz 60 130 m A
(1)
Note: Assume Loc al = 5V PCI.
Section 6
Local Inputs Electrical Specifications
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 103
6.2 Local Inputs
Valid
TSETUP
THOLD
Inputs
Local
Clock
Figure 6-1. PCI 9080 Local Input Setup and Hold Waveform
Table 6-5. AC Electrical Characteristics (Local Inputs) Estimated over Operating Range
Signals (Synchronous Inputs)
CL = 50 pF, Vcc = 5.0 ± 5% TSETUP (ns)
(WORST CASE) THOLD (ns)
(WORST CASE)
ADS# 6 1
BIGEND 4 0
BLAST# 6 0
BREQi 7 0
BTERM# 7 1
DP[3:0] 4 0
DREQ[1:0]# 3 1
EOT0# 7 1
EOT1# 1 1
LA[31:0] 5 0
LAD 5 0
LBE[3:0]# 7 0
LD[31:0] 5 0
LHOLDA 7 2
LINTi 7 0
LLOCK 4 0
LW/R# 9 0
READYi# 8 1
S[2:0] 1 2
USERi 4 0
WAITi# 13 0
Input Clocks Min Max
Local Clock I nput Frequency 0 40 MHz
PCI Clock I nput Frequency 0 33 MHz
Section 6
Electrical Specifications Local Outputs
PCI 9080 Data Book v1.06
104 PLX T e c hn ology, Inc. All r ights r e s e rved
6.3 Local Outputs
Valid
T
VALID
T
VALID
Outputs
Local
Clock
(MIN)
(MAX)
Figure 6-2. PCI 9080 Local Output Delay
Table 6-6. AC Electrical Characteristics (Local Outputs) Estimated over Operating Range
Signals (Synchronous Outputs)
CL = 50 pF, Vcc = 5.0 ± 5% Output
TVALID (Max)
ADS# 14.5
BLAST# 16
BREQo 13
BTERMo# 15
DACK[1:0]# 14
DEN# 13
DMPAF# 17
DP[3:0] 20
DT/R# 14
LA (Address, C Mode) 15.8
LABS[3:1] 12
LAD (Address, J Mode) 12.1
LAD (Data, J Mode) 15
LD (32- and 16-Bit Data, C Mode) 15
LD (8-Bit Data, C M o de) 20
LBE[3:0]# 16
LDSHOLD 12
LHOLD 13
LINTo# 13
LLOCKo# 12
LSERR# 12
LW/R# 14
PCHK# 12
READYo# 14
USERO 11
WAITo# 18
Note: All T
VALID
(Mins) values are greater than 5 ns.
Section 6
Electrical Spec if ications
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 105
Table 6-7. ALE Operation
Signal TVALID (ns) from
Local Clock
Min./Max.
Pulse Width (ns)
Min./Max.
ALE 4.0 / 8.8 5.0 / 10.9
LAD[31:0] 5.5 / 12.1 N/ A
LCLK
ALE
LAD[31:0]
min/max
4 ns/8.8 ns
min/max
5.5 ns/12.1 ns
min/max
9 ns/19.7 ns
Figure 6-3. ALE Operation
PCI 9080 Data Book v1.06
106 PLX T e c hn ology, Inc. All r ights r e s e rved
This page intentionally left blank.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 107
7. PACKAGE, SIGNAL, AND PIN OUT SPECS
7.1 Package Mechanical Dimensions
For 208-pin PQFP, θJC = 5 °C/watt
0.2 ± 0.1
30.6 ± 0.4
156 105
52
157
53
1
208
Index
30.6 0.4±
28 0.1±
28 ± 0.1
0.5 ± 0.1
0.15 0.05±
Dimensions in millimeters
0.4/0.5/0.65
1.3
3.4 ± 0.2
Pin 1
104
0°/3.5°/7°
Figure 7-1. Package Mechanical Dimensions
Section 7
Package, Signal, and Pin Out Specs Typical PCI Bus Master Adapter
PCI 9080 Data Book v1.06
108 PLX T e c hn ology, Inc. All r ights r e s e rved
7.2 Typical PCI Bus Master Adapter
C Mode J Mode
PCI
9080
I/O
Controller
Memory
CPU
LD[31:0]
LA[31:2]
LBE[3:0]#
ADS#
LW/R#
DT/R#
DEN#
READYo#
READYi#
BLAST#
BTERM#
EOT0#
EOT1#
LHOLD
LHOLDA
LDSHOLD
LRESETi#
LRESETo#
LCLK
LINTi#
LSERR#
LINTo#
DP[3:0]
PCHK#
DREQ[1:0]#
DACK[1:0]#
WAITI#
BIGEND#
LLOCKo#
BPCLKO
BREQ
DMPAF#
WAITO#
USERO
USERI
MODE[1:0]
S[2:0]
ADMODE
NB#
LLOCK#
BREQo
BTERMo#
EECS
EEDI
EEDO
EESK
SHORT#
EESEL
LAD[31:0]
LABS[3:2]
LBE[3:0]#
ADS#
LW/R#
DT/R#
DEN#
ALE
READYo#
READYi#
BLAST#
BTERM#
EOT0#
EOT1#
LHOLD
LHOLDA
LDSHOLD
LRESETi#
LRESETo#
LCLK
LINTi#
LSERR#
LINTo#
DP[3:0]
PCHK#
DREQ[1:0]#
DACK[1:0]#
WAITI#
BIGEND#
LLOCKo#
BPCLKO
BREQ
DMPAF#
WAITO#
USERO
USERI
MODE[1:0]
S[2:0]
ADMODE
NB#
LLOCK#
BREQo
BTERMo#
EECS
EEDI
EEDO
EESK
SHORT#
EESEL
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
SERR#
REQ#
GNT#
CLK
RST#
INTA#
LOCK#
WAITI#
BIGEND#
LLOCKo#
BPCLKO
BREQ
DMPAF#
WAITO#
USERO
USERI
MODE[1:0]
S[2:0]
ADMODE
NB#
LLOCK#
BREQo
BTERMo#
EECS
EEDI
EEDO
EESK
SHORT#
EESEL
LAD[15:1],D0
LA[31:16]
LABS[3:1]
LBE[1:0]#
AS#
LW/R#
DT/R#
DEN#
ALE
READYo#
READYi#
BLAST#
BTERM#
EOT0#
EOT1#
LHOLD
LHOLDA
LDSHOLD
LRESETi#
LRESETo#
LCLK
LINTi#
LSERR#
LINTo#
DP[3:0]
PCHK#
DREQ[1:0]#
DACK[1:0]#
S Mode
Local Bus
Serial
EEPROM
PCI Bus
PCI Bus Interface
Figure 7-2. Typical PCI Bus Master Adapter
Section 7
PCI 9080 Pin Out Package, Signal, and Pin Out Specs
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 109
7.3 PCI 9080 Pin Out
Refer to Section 5, “Pin Description,” for a complete description of each pin used in C, J, and S modes.
VDDL(core)
LHOLD
LHOLDA
LCLK
ALE
LABS3
LABS2
LABS1
LDSHOLD
VSS
VDDL(core)
BPCLKO
BREQ
NC
EEDO
EEDI
EESK
SHORT#
EESEL
EECS
NC
NC
NC
NC
NC
NC
VSS
VDDH(local)
NC
NC
NC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VDDL(core)
LHOLD
LHOLDA
LCLK
ALE
LABS3
LABS2
NC
LDSHOLD
VSS
VDDL(core)
BPCLKO
BREQ
NC
EEDO
EEDI
EESK
SHORT#
EESEL
EECS
NC
NC
NC
NC
NC
NC
VSS
VDDH(local)
NC
NC
NC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VDDL(core)
LHOLD
LHOLDA
LCLK
NC
NC
EOT0#
EOT1#
LDSHOLD
VSS
VDDL(core)
BPCLKO
BREQ
NC
EEDO
EEDI
EESK
SHORT#
EESEL
EECS
LD31
LD30
LD29
LD28
LD27
LD26
VSS
VDDH(local)
LD25
LD24
LD23
LD22
LD21
LD20
LD19
LD18
VSS
LD17
LD16
LD15
LD14
LD13
LD12
LD11
LD10
LD9
LD8
LD7
LD6
LD5
LD4
VSS
VDDH(Local)
NC
NC
EOT0#
EOT1#
WAITI#
LLOCKo#
DMPAF#
MODE1
MODE0
LRESETo#
DP3
DP2
DP1
DP0
PCHK#
S2
S1
S0
ADMODE
BREQo
VSS
LSERR#
DREQ1#
DACK1#
NB#
USERO
BTERMo#
DREQ0#
DACK0#
USERI
AD31
AD30
AD29
AD28
AD27
VSS
VDDH(PCI)
AD26
AD25
AD24
AD23
AD22
AD21
VSS
AD20
AD19
BIGEND#
TEST
REQ#
GNT#
VSS
VDDH(Local)
NC
NC
EOT0#
EOT1#
WAITI#
LLOCKo#
DMPAF#
MODE1
MODE0
LRESETo#
DP3
DP2
DP1
DP0
PCHK#
S2
S1
S0
ADMODE
BREQo
VSS
LSERR#
DREQ1#
DACK1#
NB#
USERO
BTERMo#
DREQ0#
DACK0#
USERI
AD31
AD30
AD29
AD28
AD27
VSS
VDDH(PCI)
AD26
AD25
AD24
AD23
AD22
AD21
VSS
AD20
AD19
BIGEND#
TEST
REQ#
GNT#
VSS
VDDH(Local)
LD3
LD2
LD1
LD0
WAITI#
LLOCKo#
DMPAF#
MODE1
MODE0
LRESETo#
DP3
DP2
DP1
DP0
PCHK#
S2
S1
S0
ADMODE
BREQo
VSS
LSERR#
DREQ1#
DACK1#
NB#
USERO
BTERMo#
DREQ0#
DACK0#
USERI
AD31
AD30
AD29
AD28
AD27
VSS
VDDH(PCI)
AD26
AD25
AD24
AD23
AD22
AD21
VSS
AD20
AD19
BIGEND#
TEST
REQ#
GNT#
VSS
VSS
LA4
LA3
LA2
NC
NC
VSS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
VSS
AD7
AD8
AD9
AD10
AD11
AD12
VDDH(PCI)
VSS
AD13
AD14
AD15
AD16
AD17
AD18
VSS
PAR
C/BE0#
C/BE1#
C/BE2#
C/BE3#
LOCK#
VDDL(core)
VSS
SERR#
PERR#
DEVSEL#
IDSEL
STOP#
IRDY#
VDDH(PCI)
VSS
TRDY#
FRAME#
RST#
INTA#
CLK
VDDL(core)
VSS
LAD4
LAD3
LAD2
LAD1
LAD0
VSS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
VSS
AD7
AD8
AD9
AD10
AD11
AD12
VDDH(PCI)
VSS
AD13
AD14
AD15
AD16
AD17
AD18
VSS
PAR
C/BE0#
C/BE1#
C/BE2#
C/BE3#
LOCK#
VDDL(core)
VSS
SERR#
PERR#
DEVSEL#
IDSEL
STOP#
IRDY#
VDDH(PCI)
VSS
TRDY#
FRAME#
RST#
INTA#
CLK
VDDL(core)
VSS
LAD4
LAD3
LAD2
LAD1
D0
VSS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
VSS
AD7
AD8
AD9
AD10
AD11
AD12
VDDH(PCI)
VSS
AD13
AD14
AD15
AD16
AD17
AD18
VSS
PAR
C/BE0#
C/BE1#
C/BE2#
C/BE3#
LOCK#
VDDL(core)
VSS
SERR#
PERR#
DEVSEL#
IDSEL
STOP#
IRDY#
VDDH(PCI)
VSS
TRDY#
FRAME#
RST#
INTA#
CLK
VDDL(core)
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VSS
BLAST#
ADS#
LLOCK#
LINTo#
LINTi#
LRESETi#
WAITO#
READYo#
READYi#
BTERM#
DEN#
VDDL(core)
VSS
LBE0#
LBE1#
LBE2#
LBE3#
DT/R#
LW/R#
LA31
LA30
VSS
LA29
LA28
LA27
LA26
LA25
LA24
LA23
LA22
LA21
VDDH(local)
VSS
LA20
LA19
LA18
LA17
LA16
LA15
LA14
LA13
VSS
LA12
LA11
LA10
LA9
LA8
LA7
LA6
LA5
VDDL(core)
VSS
BLAST#
ADS#
LLOCK#
LINTo#
LINTi#
LRESETi#
WAITO#
READYo#
READYi#
BTERM#
DEN#
VDDL(core)
VSS
LBE0#
LBE1#
LBE2#
LBE3#
DT/R#
LW/R#
LAD31
LAD30
VSS
LAD29
LAD28
LAD27
LAD26
LAD25
LAD24
LAD23
LAD22
LAD21
VDDH(local)
VSS
LAD20
LAD19
LAD18
LAD17
LAD16
LAD15
LAD14
LAD13
VSS
LAD12
LAD11
LAD10
LAD9
LAD8
LAD7
LAD6
LAD5
VDDL(core)
VSS
BLAST#
AS#
LLOCK#
LINTo#
LINTi#
LRESETi#
WAITO#
READYo#
READYi#
BTERM#
DEN#
VDDL(core)
VSS
LBE0#
LBE1#
NC
NC
DT/R#
LW/R#
LA31
LA30
VSS
LA29
LA28
LA27
LA26
LA25
LA24
LA23
LA22
LA21
VDDH(local)
VSS
LA20
LA19
LA18
LA17
LA16
LAD15
LAD14
LAD13
VSS
LAD12
LAD11
LAD10
LAD9
LAD8
LAD7
LAD6
LAD5
VDDL(core)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PCI 9080
JC
S
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Figure 7-3. PCI 9080 Pin Out (All Modes)
PCI 9080 Data Book v1.06
110 PLX T e c hn ology, Inc. All r ights r e s e rved
This page intentionally left blank.
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 111
8. TIMI NG DIAGRAMS
PCI 9080 operates in three modes, selected through mode pins, corresponding to three bus types—C, J, and S. Timing
Diagrams are provided for each mode. For some functions, a timing diagram may only be provided for one mode of
operation. Even though a different mode is used, that timing diagram can be used to determine functionality.
8.1 Initialization
ASYNCHRONOUS
0ns 50ns 100ns 150ns 200ns
CLK
RST#
LCLK
LRESETo#
Timing Diagram 8-1. (C, J Modes) PCI RST# Asserting Local Output LRESETo#
ADDR
ADDR
DATA
0ns 25ns 50ns 75ns 100ns 125ns 150
n
LRESETo#
AS#
LA[31:16]
LAD[15:1]
LRESETo# must be used to establish Phase A relationship as shown.
Timing Diagram 8-2. (S Mode) Two Phase Clock Synchronization Using LRESETo#
Section 8
Timing Diagrams Initialization
PCI 9080 Data Book v1.06
112 PLX T e c hn ology, Inc. All r ights r e s e rved
HIGH IF DIRECT SLAVE REQUEST
MUST REMAIN HIGH UNTIL LHOLD GOES LOW
WILL NOT BE RE-ASSERTED UNITL LHOLDA GOES LOW
PCI 9080 DRIVES BUS
|--- CAN GO HIGH
0ns 250ns 500ns
LCLK
LHOLD
LDSHOLD
LHOLDA
Local Bus
Timing Diagram 8-3. PCI 9080 Local Bus Arbitration
Section 8
Initialization Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 113
1 1 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00
00
D15 D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15
BITS [31:16] CFG REGISTER 0 HEX
BITS [15:0] CFG REGISTER 0 HEX D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
BITS [31:16] OF CFG REGISTER 8 HEX
CONTINUES
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SHORT: BITS [15:0] MAILBOX 1 LOC C4 HEX
LONG: BITS [15:0] LOC REGISTER 98 HEX
EXTRA LONG: BITS [15:0] PCI Base Address for Local Expansion ROM 54 HEX
START BIT 0 INDICATES SERIAL EEPROM PRESENT ----|
INTERNALLY PULLED UP
LAST WORD EESK, EEDO, EECS FROM CFG REGISTERS
AFTER COMPLETION OF READ
CONTINUES
0us 5us 10us 15us 20us 25us
EESK
LRESETo#
EECS
EEDI
EEDO
.
EESK
EEDO
.
.
.
EESK(continues)
EECS
EEDO
Timing Diagram 8-4. PCI 9080 1K Serial EEPROM PCI Initialization
Section 8
Timing Diagrams Initialization
PCI 9080 Data Book v1.06
114 PLX T e c hn ology, Inc. All r ights r e s e rved
CMD BE
ADDR
RESPONSE ON THE PCI SIDE
DATA
[3,15]
0ns 100ns 200ns 300ns 400ns 500
n
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
INTA#
LCLK
LINTi#
Timing Diagram 8-5. Local Interrupt (LINTi#) Input Asserting PCI Output INTA#
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 115
8.2 C Mode
8.2.1 C Mode Direct Slave
ADDR
CMD=B
4
BE
Data
0ns 50ns 100ns 150ns 200ns 250ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
Timing Diagram 8-6. (C Mode) PCI Configuration Write to PCI 9080 PCI Configuration Register
123
ADDR
567
CMD=A
84
Data Read
BE
0ns 50ns 100ns 150ns 200ns 250ns 300n
s
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
Timing Diagram 8-7. (C Mode) PCI Configuration Read to PCI 9080 PCI Configuration Register
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
116 PLX T e c hn ology, Inc. All r ights r e s e rved
123
ADDR
567
CMD=7
84
BE
Data
0ns 50ns 100ns 150ns 200ns 250ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
Timing Diagram 8-8. (C Mode) PCI Memory Write to PCI 9080 Local Configuration Register
12 3
ADDR
56 7
CMD=6
84
Data Read
BE
0ns 50ns 100ns 150ns 200ns 250ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
Timing Diagram 8-9. (C Mode) PCI Memory Read to PCI 9080 Local Configuration Register
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 117
123
ADDR
5 6 7
CMD
8
BE
ADDR
Data
14
Data
4
0ns 100ns 200ns 300ns 400ns 500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
LW/R#
BLAST#
LA[31:2]
LD[31:0]
READYI#
Timing Diagram 8-10. (C Mode) Direct Slave Single Cycle Read (32-Bit Local Bus)
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
118 PLX T e c hn ology, Inc. All r ights r e s e rved
123
ADDR
567
CMD
84
BE
Data
ADDR
Data
0ns 250ns 500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
LW/R#
BLAST#
LA[31:2]
LD[31:0]
READYi#
Timing Diagram 8-11. (C Mode) Direct Slave Single Cycle Write
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 119
D0 D1 D7D4 D5 D6
A+14AA+4 A+8 A+C A+10 A+18 A+1C
D3D2
LBE
0ns 250ns 500ns
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3:0]#
LW/R#
LD[31:0]
LA[31:2]
BTERM#
READYi#
Eight Lword burst, no wait states, Burst enabled, Bterm enabled, 32-bit Local Bus.
Note: If Bterm is disabled, a new ADS cycle starts every quad Lword boundary.
Timing Diagram 8-12. (C Mode) PCI 9080 DMA or Direct Slave Burst Read from Local Bus,
No Wait States, Bterm Enabled
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
120 PLX T e c hn ology, Inc. All r ights r e s e rved
D0 D1 D10D2 D3 D4 D8 D9
A+20A A+4 A+8 A+C A+10 A+24 A+28
D5 D6 D7
A+14 A+18 A+1C
Bterm FORCES NEW ADS# -->
LBE
0ns 250ns 500ns
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3:0]#
LW/R#
LD[31:0]
LA[31:2]
BTERM#
READYi#
Eight Lword burst, no wait states, Burst enabled, Bterm enabled, 32-bit Local Bus.
Note: If Bterm is disabl ed, a new ADS# cycle starts e very quad Lword boundary.
Timing Diagram 8-13. (C Mode) DMA or Direct Slave PCI 9080 Burst Write to Local Bus, Bterm Enabled
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 121
CMD BE
ADDR D0 D1 D2 D3 D4
+4 +8 +C +10
D0 D1 D2 D3 D4 D5 D6 D7
+14 +18 +1CADDR
0ns 250ns 500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
LW/R#
BLAST#
LA[31:2]
LD[31:0]
READYi#
BTERM#
No wait states, 32-bit bus, Burst enabled, Bterm disabled.
Unused read data is flushed using with local processor.
Timing Diagram 8-14. (C Mode) Direct Slave PCI-to-Local Burst Read, Bterm Disabled
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
122 PLX T e c hn ology, Inc. All r ights r e s e rved
0001
D2 D6
ADDR A+4 A+8 A+C
D4
A+10
D0 D1 D3 D5 D7 D8
A+14 A+18 A+1C A+20
LBE = 0
0ns 100ns 200ns 300ns 400ns 500ns
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3:0]#
LW/R#
LD[31:0]
LA[31:2]
BTERM#
READYi#
No wait states, Burst enabled, Bterm disabled, 32-bit Local Bus.
Unaligned Transfer results in new ADS#.
Note: Not all byte enables asserted or a quad boundary LA[3:2]=11 results in a new ADS#.
Timing Diagram 8-15. (C Mode) PCI 9080 DMA or Direct Slave Burst Write, Bterm Disabled
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 123
CMD BE
ADDR D0 D1 D2 D3 D4
+4 +8 +10
D0 D1 D2 D3
+C
D4
ADDR
0ns 250ns 500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
LW/R#
BLAST#
LA[31:2]
LD[31:0]
READYi#
Timing Diagram 8-16. (C Mode) Direct Slave Read with Prefetch Counter Set to 5
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
124 PLX T e c hn ology, Inc. All r ights r e s e rved
DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS#
D0 D1 D2 D3 D4 D5 D6 D7 D9D8 D10
A+4 +8 +12 +16 +20 +24 +28 +32 +36 A+40
0ns 250ns 500ns 75
0
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LBE[3:0]#
LW/R#
LD[31:0]
LA[31:2]
BTERM#
READYi#
BREQ
No wait states, Burst enabled, Bterm enabled, 32-bit Local Bus.
Owned by local processor or another bus master.
DMA continues from where it left off.
Timing Diagram 8-17. (C Mode) Direct Slave or DMA Burst Write to 32-Bit Local Bus Suspended by BREQ Input
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 125
CMD BE
D4D3D2D1D0
ADDR
+4 +8 +C +10
D0 D1 D2 D3 D4 D5 D6 D7
+1C+18+14ADDR
0ns 250ns 500ns 750ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
LW/R#
BLAST#
LA[31:2]
LD[31:0]
READYi#
Five Lwords, one wait state, Burst enabled, Bterm disabled.
Unused read data is flushed with local processor.
Timing Diagram 8-18. (C Mode) Direct Slave Burst Read of Five Lwords with One Wait State
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
126 PLX T e c hn ology, Inc. All r ights r e s e rved
1 2 3
ADDR
5 6 7
CMD
84
+4
BE
DO D1 D2 D3 D4
+8 +C +10
D1 D2 D3 D4D0
A
0ns 250ns 500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LW/R#
LA[31:2]
LD[31:0]
READYi#
Five Lwords, one wait state, Burst enabled, Bterm enabled.
Timing Diagram 8-19. (C Mode) Direct Slave Burst Write of Five Lwords with One Wait State
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 127
RETRY
WRITE IS NOT ALLOWED DURING DELAYED READ
RETRY
Delayed Read Retries
READS DATA
WRITE RETRIES AND
COMPLETES
0ns 250ns 500ns 750ns 1000ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
PERR#
STOP#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LA[31:2]
LD[31:0]
LBE[3:0]#
READYi#
LW/R#
Disconnect immediately for a read.
Don't eff ect pending reads when wri te cycle occurs.
Don't flush Read FIFO if PCI read cycle completes.
Force Retry on write if read pending.
De-assert TRDY# until space is available in Direct Slave Write FIFO.
Timing Diagram 8-20. (C Mode) Direct Slave Read 2.1 Spec
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
128 PLX T e c hn ology, Inc. All r ights r e s e rved
0ns 250ns 500ns 750ns 1000ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LA[31:2]
LD[31:0]
LBE[3:0]#
READYi#
LW/R#
Timing Diagram 8-21. (C Mode) Direct Slave Read No Flush Mode (Read Ahead Mode)
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 129
CMD BE
ADDR D0 D1
AA + 4
D E F C C D E F
0ns 250ns 500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LW/R#
LA[31:2]
LBE[3:0]#
LD[31:0]
READYi#
Timing Diagram 8-22. (C Mode) Direct Slave Read of Two Lwords from 8-Bit Bus
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
130 PLX T e c hn ology, Inc. All r ights r e s e rved
A A + 4
DE FCCDEF
[7:0] [15:8] [23:16] [31:24] [15:8][7:0] [23:16] [31:24]
0ns 100ns 200ns 300ns 400ns
LHOLD
LHOLDA
ADS#
BLAST#
LA[31:2]
LBE[3:0]#
LD[31:0]
READYi#
Timing Diagram 8-23. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 8-Bit Local Bus,
No Wait States, Bterm Enabled
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 131
CMD BE
ADDR D0 D1
A
[15:0] [31:16] [31:16]
4 6 4 6
A+4
[15:0]
0ns 250ns 500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
LW/R#
BLAST#
LA[31:2]
LD[31:0]
LBE[3:0]#
READYi#
Timing Diagram 8-24. (C Mode) Direct Slave Read of Two Lwords from 16-Bit Bus
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
132 PLX T e c hn ology, Inc. All r ights r e s e rved
A A + 4
6464
D0[15:0] D0[31:16] D1[15:0] D1[31:16]
0ns 100ns 200ns 300ns
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LA[31:2]
LBE[3:0]#
LD[31:0]
READYi#
Timing Diagram 8-25. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16-Bit Local Bus,
No Wait States, Bterm Enabled
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 133
BE
AD0
AA + 4
C D
[7:0] [15:8][23:16][31:24] [7:0] [15:8][23:16]
AD1
BE
E F
[31:24]
C D E F
0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
STOP#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LW/R#
LA[31:2]
LBE[3:0]#
LD[31:0]
READYi#
Timing Diagram 8-26. (C Mode) Direct Slave Read of Two Lwords from 8-Bit I/O Local Bus, Burst Disabled
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
134 PLX T e c hn ology, Inc. All r ights r e s e rved
BE
AD0
AA + 4
CD
AD1
BE
EF
CDEF
0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns
1
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
STOP#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LW/R#
LA[31:2]
LBE[3:0]#
LD[31:0]
READYi#
Timing Diagram 8-27. (C Mode) Direct Slave Write of Two Lwords to 8-Bit I/O Local Bus, Burst Disabled
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 135
ADDR
CMD
4
BE
Data= AABBCCDD
ADDR
DDCCBBAA
01234567
67452301
LBE
0ns 100ns 200ns 300ns 400ns 500ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LCLK
LHOLD
LHOLDA
ADS#
LW/R#
BLAST#
LA[31:2]
LD[31:0]
LBE[3:0]
READYi#
Timing Diagram 8-28. (C Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
136 PLX T e c hn ology, Inc. All r ights r e s e rved
ADDR
RBYTE ENABLES
D0 D1 W-A
WBE
W-DATA
<-- CAN BE DE-ASSERTED AFTER LAST DATA
D0
ADDR
D1 D2 D3 D4
+4 +8 +12 +16 +20
D5 D6 D7
+24 +28
D8
+32
W-ADDR
DE-ASSERTED AFTER DETECTING PCI UNLOCK -
-
0ns 250ns 500ns 750ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
LOCK#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LA[31:2]
LD[31:0]
READYi#
LLOCKo#
Timing Diagram 8-29. (C Mode) Locked Direct Slave Read Followed by Write and Release (LLOCKo#)
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 137
8.2.2 C Mode Direct Master
DP0 DP1
DATA 0 DATA 1
0ns 100ns 200ns 300ns 400ns
LCLK
LA[31:2]
LD[31:0]
CS#
ADS#
LBE[3:0]#
LW/R#
BLAST#
DP[3:0]
READYo#
First READYo# will be delayed at lea st five clocks for access t o shared registers.
Timing Diagram 8-30. (C Mode) Local Bus Read from PCI 9080 CFG Registers
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
138 PLX T e c hn ology, Inc. All r ights r e s e rved
DATA 0 DATA 1
DATA 0 BYTE ENABLES DATA 1 BYTE ENABLES
0ns 100ns 200ns 300ns 400ns
LCLK
LA[31:2]
LD[31:0]
CS#
ADS#
LBE[3:0]#
LW/R#
BLAST#
READYo#
First READYo# will be delayed at least five clocks for access to shared registers
Timing Diagram 8-31. (C Mode) Local Bus Write to PCI 9080 CFG Registers
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 139
A0 D0
D0
A
CMD BE
LBE
0ns 100ns 200ns 300ns 400ns
LCLK
LA[31:2]
LW/R#
ADS#
BLAST#
READYo#
LD[31:0]
LBE[3:0]#
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]#
DEVSEL#
IRDY#
TRDY#
Timing Diagram 8-32. (C Mode) Local Bus Direct Master Single Memory Read
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
140 PLX T e c hn ology, Inc. All r ights r e s e rved
A0 D0
D0
CMD BE
LBE
A
0ns 100ns 200ns 300ns 400ns
LCLK
LA[31:2]
LW/R#
ADS#
BLAST#
READYo#
LD[31:0]
LBE[3:0]#
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]#
DEVSEL#
IRDY#
TRDY#
Timing Diagram 8-33. (C Mode) Local Bus Direct Master Single Memory Write Cycle
Section 8
C Mode Timing Diagrams
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved 141
D0 D1 D2 D3
A
D4 D5 D6 D7 D8 D9 D10 D11
ADDR
CMD BE
D0 D8 D12 D16D4
0ns 250ns 500ns 750ns
LCLK
LA[31:2]
LW/R#
ADS#
BLAST#
READYo#
LD[31:0]
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]#
DEVSEL#
IRDY#
TRDY#
Timing Diagram 8-34. (C Mode) PCI 9080 Direct Master Memory Read, 12 Lword Burst
Section 8
Timing Diagrams C Mode
PCI 9080 Data Book v1.06
142 PLX T e c hn ology, Inc. All r ights r e s e rved
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Left Center Righ
t
A
CMD
D0 D3D1 D4D2 D5 D6 D11D7 D10D8 D9
BE
A
0ns 250ns 500ns 750n
s
LCLK
LA[31:2]
LD[31:0]
LW/R#
ADS#
BLAST#
READYo#
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]#
DEVSEL#
IRDY#
TRDY#
Timing Diagram 8-35. (C Mode) PCI 9080 Direct Master Memory Write of 12 Lwords
