KIT ATION EVALU E L B A AVAIL 19-4250; Rev 2; 3/11 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Ordering Information PART MAX11043ATL+ Applications Data Acquisition Systems Industrial Controls Power-Grid Monitoring PIN-PACKAGE -40C to +125C 40 TQFN-EP* DVDD SHDN DGND AGND AOUT AVDD REFDACL REFDACH REFDAC Pin Configuration TOP VIEW Automotive Radar Systems TEMP RANGE MAX11043ATL/V+** -40C to +125C 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. *EP = Exposed pad. **Future product--contact factory for availability. REFD The MAX11043 features 4 single-ended or differential channels of simultaneous-sampling ADCs with 16-bit resolution. The MAX11043 contains a versatile filter block and programmable-gain amplifier (PGA) per channel. The filter consists of seven cascaded 2ndorder filter sections for each channel, allowing the construction of a 14th-order filter. The filter coefficients are user-programmable. Configure each 2nd-order filter as lowpass (LP), highpass (HP), or bandpass (BP) with optional rectification. Gain and phase mismatch of the analog signal path is better than -50dB. The ADC can digitize signals up to 200kHz. A 40MHz serial interface provides communication to and from the device. The SPITM interface provides throughput of 1600ksps; 4 channels at 400ksps per channel or 2 channels at 800ksps per channel. A software-selectable scan mode allows reading the ADC results while simultaneously updating the DAC. Other features of the MAX11043 include an internal (+2.5V) or external (+2.0V to +2.8V) reference, power-saving modes, and a PGA with gains of 1 to 64. The PGA includes an equalizer (EQ) function that automatically boosts lowamplitude, high-frequency signals for applications such as CW-chirp radar. The MAX11043 includes two 8-bit coarse DACs that set the high and low references for a second-stage 12-bit fine DAC, typically used for VCO control. Use software controls to write to the DAC or step the DAC up and down under hardware control in programmable steps. The device operates from a +3.0V to +3.6V supply. The MAX11043 is available in a 40-pin, 6mm x 6mm TQFN package and operates over the extended -40C to +125C temperature range. Features o 4 Single-Ended or Differential Channels of Simultaneous-Sampling, 16-Bit ADCs o 10 LSB INL, 1 LSB DNL, No Missing Codes o 93dB SFDR at 100kHz Input o PGA with Gain of 1, 2, 4, 8, 16, 32, or 64 for Each Channel o EQ Function Automatically Boosts High-Frequency, Low-Amplitude Signals o Seven-Stage Internal Programmable Biquad Filters per Channel o High Throughput, 400ksps per Channel for 4 Channels o Dual-Stage DAC Two 8-Bit Coarse Reference DACs 12-Bit Fine DAC o +2.5V Internal Reference or +2.0V to +2.8V External Reference o Single +3.3V Operation o Shutdown and Power-Saving Modes o 40-Pin, 6mm x 6mm TQFN Package o -40C to +125C Operating Temperature 30 29 28 27 26 25 24 23 22 21 AINDN 31 20 OSCOUT AINDP 32 19 OSCIN AGND 33 18 EOC REFBP 34 17 I.C. 16 SCLK I.C. 35 MAX11043 AINCN 36 15 DIN 14 DOUT AINCP 37 REFC 38 13 CS *EP + 12 CONVRUN REFB 39 11 DACSTEP AINAP 7 8 9 10 UP/DWN AINAN 6 DVREG REFA *CONNECT EP TO AGND. 5 DVDD 4 DGND 3 AGND 2 AVDD SPI is a trademark of Motorola, Inc. 1 AINBN AINBP 40 TQFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX11043 General Description MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ABSOLUTE MAXIMUM RATINGS AVDD to AGND ....................................................-0.3V to +4.0V DVDD to DGND .....................................................-0.3V to +4.0V DVREG to DGND...................................................-0.3V to +3.0V AGND to DGND.....................................................-0.3V to +0.3V Analog I/O, REFDACH, REFDACL, REFA, REFB, REFC, REFD, AOUT, REFDAC, REFBP to AGND .....-0.3V to (VAVDD + 0.3V) UP/DWN, CONVRUN, SHDN, DACSTEP, EOC, Digital I/O, OSCIN, OSCOUT to DGND....................-0.3V to (VDVDD + 0.3V) Maximum Current into Any Pin except AVDD, DVDD, DVREG, AGND, DGND...............................................................50mA Continuous Power Dissipation (TA = +70C) TQFN Multilayer Board (derate 37mW/C above +70C) ................................2963mW TQFN Single-Layer Board (derate 26.3mW/C above +70C) ..........................2105.3mW Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C Soldering Temperature (reflow) ......................................+260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10F, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1F, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SIGMA-DELTA ADC Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error 16 -16 Guaranteed monotonic OE 2 LSB -1 +1 LSB -35 +35 mV Offset-Error Drift Gain Error Bits 30 GE Trimmed with 150/330pF anti-alias filter -1 Gain Temperature Coefficient V/C +1 50 % ppm/C Channel Gain-Error Matching Complete analog signal path -0.25 +0.25 % Channel Offset Matching Complete analog signal path -60 +60 mV DYNAMIC PERFORMANCE (PGA Disabled, PGA Gain = 1 x (25kHz -1dB Full-Scale Signal)) Maximum Full-Scale Input ADC modulator gain = 1 1.2 VP-P Input-Referred Noise Spectral Density 100kHz 85 nV/Hz -80 -93 dB -80 -110 dB 77 93 dB 85 108 dB Second Harmonic to Fundamental Third Harmonic to Fundamental Spurious-Free Dynamic Range SFDR Channel-to-Channel Isolation Unused channels are shorted and unconnected Channel Phase Matching Between all channels, including complete analog signal path 2 -0.05 _______________________________________________________________________________________ +0.05 Degrees 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10F, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1F, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (PGA Enabled, PGA Gain = 8 x (25kHz -1dB Full-Scale Signal)) Maximum Full-Scale Input ADC modulator gain = 1 150 mVP-P Input-Referred Noise Spectral Density 100kHz 20 nV/Hz Second Harmonic to Fundamental -92 dB Third Harmonic to Fundamental -94 dB 92 dB 110 dB Spurious-Free Dynamic Range SFDR Channel-to-Channel Isolation Unused channels are shorted and unconnected Channel Phase Matching Between all channels, including complete analog signal path -0.05 +0.05 Degrees DYNAMIC PERFORMANCE (PGA Enabled, PGA Gain = 16 x (25kHz -1dB Full-Scale Signal)) Maximum Full-Scale Input ADC modulator gain = 1 75 mVP-P Input-Referred Noise Spectral Density 100kHz 15 nV/Hz -99 dB -93 dB 93 dB 106 dB Second Harmonic to Fundamental Third Harmonic to Fundamental Spurious-Free Dynamic Range SFDR Channel-to-Channel Isolation Unused channels are shorted and unconnected Channel Phase Matching Between all channels, including complete analog signal path -0.075 +0.075 Degrees DYNAMIC PERFORMANCE (EQ Mode (5kHz -1dB Full-Scale Signal, CONFIG_ Register Bit 3 = 1)) Maximum Full-Scale Input ADC modulator gain = 1 (Note 2) Input-Referred Noise Spectral Density 100kHz Second Harmonic to Fundamental Third Harmonic to Fundamental Spurious-Free Dynamic Range SFDR Input referred (Note 3) 800 mVP-P 6 nV/Hz -80 -90 dB -77 -98 dB 77 89 dB _______________________________________________________________________________________ 3 MAX11043 ELECTRICAL CHARACTERISTICS (continued) MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10F, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1F, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS Channel-to-Channel Isolation Unused channels are shorted and unconnected Channel Phase Matching Between all channels, including complete analog signal path MIN TYP 80 104 -0.12 MAX UNITS dB +0.12 Degrees DYNAMIC PERFORMANCE (All Modes) Conversion Rate All 4 channels 400 2 channels only 800 Minimum Throughput Power-Supply Rejection Ratio DCPSRR ksps 5 ksps 50 dB ANALOG INPUTS (AINAP/AINAN, AINBP/AINBN, AINCP/AINCN, AINDP/AINDN) Absolute Voltage Any Input (Note 4) Direct input to ADC, gain = 1 Input Impedance (Note 5) 0 DIFF = 1 25 DIFF = 0 100 Direct input to ADC, gain = 2 7 Direct input to ADC, gain = 4 or 8 7 PGA gain = 16 Input Capacitance VAVDD V k 5.5 EQ mode only 50 pF Unity-Gain Frequency Default 5 kHz Lower Transition Frequency Default, from 40dB/decade to 0dB/decade 190 kHz Upper Transition Frequency Default, from 0dB/decade to -80dB/decade 205 kHz Default 205 kHz EQ FILTER (Analog and Digital) LP FILTER -3dB Corner Frequency REFERENCE INPUT REF_ Input Voltage Range VREF_ 2 2.5 Input Current REFBP Input Voltage Range VREFBP 2 2.5 VREFDAC 1 1.25 Input Current REFDAC Input Voltage Range Input Resistance 4 17 _______________________________________________________________________________________ 2.8 V 150 A 2.8 V 700 A 1.4 V k 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10F, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1F, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25C.) PARAMETER REFDAC_ Input Voltage Range SYMBOL CONDITIONS VREFDAC_ MIN TYP 0 Input Resistance MAX 1.4 150 UNITS V k INTERNAL REFERENCE Reference Voltage VREFBP 2.45 Reference Temperature Coefficient 2.5 2.55 100 V ppm/C CRYSTAL OSCILLATOR (Max ESR 100, 22pF Load Capacitors to DGND) Maximum Crystal Operating Frequency Epson Electronics MA-505 (16MHz) 16 External Clock Input Frequency Range External clock applied to OSCIN 4 Stability Excluding crystal 25 ppm Startup Time Epson Electronics MA-505 (16MHz) 10 ms OSCIN Input Low Voltage When driven with external clock source OSCIN Input High Voltage When driven with external clock source OSCIN Leakage Current MHz 40 0.3 x VDVDD 0.7 x VDVDD MHz V V -5 +5 A DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL 0.7 x VDVDD V 0.3 x VDVDD Input Hysterisis 15 Input Leakage Current IIN Input Capacitance CIN VIN = 0V or VDVDD -1 V mV +1 15 A pF DIGITAL OUTPUTS Output-Voltage High VOH ISOURCE = 0.8mA Output-Voltage Low VOL ISINK = 1.6mA VDVDD - 0.6 V -1 0.4 V +1 A Three-State Leakage Current DOUT only Three-State Output Capacitance DOUT only 15 pF Internal use only 2.5 V VOLTAGE REGULATOR Regulated Digital Supply Voltage DVREG POWER REQUIREMENTS Analog Supply Voltage 3.0 3.6 V Digital Supply Voltage 3.0 3.6 V _______________________________________________________________________________________ 5 MAX11043 ELECTRICAL CHARACTERISTICS (continued) MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10F, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1F, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25C.) PARAMETER SYMBOL Analog Supply Current IAVDD Digital Supply Current IDVDD Shutdown Current CONDITIONS All channels selected MIN TYP MAX PGA disabled 60 80 PGA enabled 120 140 26 40 IAVDD 5 IDVDD 5 UNITS mA mA mA STATIC ACCURACY--FINE DAC (CL = 200pF, RL = 10k) Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL Bits -5 Guaranteed monotonic Offset Error +5 LSB -1 +1 LSB -70 +70 mV Offset-Error Temperature Coefficient 50 Gain Error -2 Gain-Error Temperature Coefficient V/C 0 % 20 ppm of FS/C DYNAMIC PERFORMANCE--FINE DAC (CL = 200pF, RL = 10k) Output Noise f = 0.1Hz to 1MHz 200 VRMS DAC Glitch Impulse Major carry transition 12 nV*s 25% to 75% FS Voltage-Output Settling Time 3 1% FS s 1.5 Voltage-Output Slew Rate 0.6 V/s STATIC ACCURACY--REFDACH AND REFDACL Resolution 8 Bits Integral Nonlinearity INL -0.5 +0.5 LSB Differential Nonlinearity DNL -0.2 +0.2 LSB -30 +30 mV Offset Error Offset-Error Temperature Coefficient 50 Gain Error -5 Gain-Error Temperature Coefficient V/C +5 LSB 20 ppm of FS/C FLASH MEMORY Programming Endurance Data Retention 6 TA = +85C 10,000 Cycles 15 Years _______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10F, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1F, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI INTERFACE SCLK Clock Period tCP 25 ns SCLK Pulse-Width High tCH 10 ns SCLK Pulse-Width Low tCL SCLK Rise to DOUT Transition tDOT CS Fall to SCLK Rise Setup Time tCSS SCLK Rise to CS Rise Setup Time 10 CLOAD = 20pF 1 ns 15 ns 10 ns ns tCSH 5 DIN to SCLK Rise Setup Time tDS 10 ns DIN to SCLK Rise Hold Time tDH 0 ns CS Pulse-Width High tCSPWH 10 CS Rise to DOUT Disable tDOD CLOAD = 20pF CS Fall to DOUT Enable tDOE CLOAD = 20pF EOC Fall to CS Fall tRDS ns 20 ns 1 ns 10 ns Note 1: Devices 100% production tested at TA = +125C. Guaranteed by design and characterization to TA = -40C. Note 2: Full scale in analog EQ mode decreases with increasing frequency at a rate of 20dB/decade from 8kHz. If digital EQ is also used, full scale decreases with increasing frequency at 40dB/decade from 5kHz. Note 3: SFDR in the EQ mode is normalized to the input by subtracting the analog EQ gain at each frequency (20dB/decade) from the FFT results. Note 4: The absolute input voltage range is 0 to AVDD. For optimal performance, use a common-mode voltage of AVDD/2. Note 5: Switched capacitor input impedance is proportional to 1/fC. Where f is the sampling frequency and C is the input capacitance. Typical Operating Characteristics (VAVDD = +3.3V, VDVDD = +3.0V, fSCLK = fEXCLK = 19.2MHz, VREFBP, VREF_ = +2.5V, common-mode input voltage = VAVDD/2, TA = +25C, unless otherwise noted.) 1 0 -1 -2 -3 -40 -60 -80 -100 16384 32768 CODE (LSB) 49152 65536 -40 -60 -80 -120 -120 0 fIN = 50kHz GAIN = 1 -20 -100 -4 -5 0 MAX11043 toc03 -20 AMPLITUDE (dBFS) INL (LSB) 2 fIN = 50kHz GAIN = 1 AMPLITUDE (dBFS) 3 0 MAX11043 toc02 LP MODE GAIN = 1 MAX11043 toc01 5 4 800ksps FFT LP MODE 400ksps FFT LP MODE INL vs. CODE -140 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) _______________________________________________________________________________________ 7 MAX11043 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VAVDD = +3.3V, VDVDD = +3.0V, fSCLK = fEXCLK = 19.2MHz, VREFBP, VREF_ = +2.5V, common-mode input voltage = VAVDD/2, TA = +25C, unless otherwise noted.) 400ksps FFT EQ MODE 800ksps FFT EQ MODE -60 -80 MAX11043 toc06 70 60 -40 50 SINAD (dB) AMPLITUDE (dBFS) -60 -80 40 50kHz 30 20 1kHz 10 -100 10kHz 0 -100 -120 -120 -140 0 20 40 60 80 100 120 140 160 180 200 -10 -20 0 200 400 -90 -80 -70 -60 -50 -40 -30 -20 -10 FREQUENCY (kHz) FREQUENCY (kHz) INPUT AMPLITUDE (dBFS) FINE DAC DNL vs. CODE FINE DAC INL vs. CODE FINE DAC SETTLING 25% TO 75% FS STEP 0.8 0.6 4 3 2 0.2 1 INL (LSB) 0.4 0 MAX11043 toc09 5 MAX11043 toc07 1.0 500mV/div 0 -0.2 -1 -0.4 -2 -0.6 -3 -0.8 -4 0V -5 -1.0 0 1024 2048 3072 4096 0 1024 2048 3072 4096 CODE (LSB) CODE (LSB) FINE DAC SETTLING 75% TO 25% FS STEP FINE DAC SETTLING 1% STEP-UP MAX11043 toc10 MAX11043 toc11 20mV/div 500mV/div 1200mV 0V 1s/div 8 0 MAX11043 toc08 AMPLITUDE (dBFS) -40 fIN = 100kHz VINP-P = 1.4mV -20 80 MAX11043 toc05 fIN = 5kHz VINP-P = 560mV -20 SINAD vs. INPUT AMPLITUDE 0 MAX11043 toc04 0 DNL (LSB) MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC _______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC 1.0 0dBm MAX11043 toc14 MAX11043 toc13 MAX11043 toc12 CODES 3 TO 255 0.8 0.6 20mV/div DNL (LSB) 0.4 20dBm/div DACH 0.2 MAX11043 Typical Operating Characteristics (continued) (VAVDD = +3.3V, VDVDD = +3.0V, fSCLK = fEXCLK = 19.2MHz, VREFBP, VREF_ = +2.5V, common-mode input voltage = VAVDD/2, TA = +25C, unless otherwise noted.) COARSE DAC DNL FINE DAC SETTLING vs. CODE FINE DAC NOISE FLOOR 1% STEP-DOWN 0 -0.2 DACL -0.4 1200mV -0.6 -0.8 -1.0 0 1s/div COARSE DAC INL vs. CODE 128 CODE (LSB) COARSE DAC SETTLING TIME, POSITIVE STEP COARSE DAC SETTLING TIME, NEGATIVE STEP 256 MAX11043 toc17 MAX11043 toc15 CODES 3 TO 255 0.4 192 FREQUENCY (kHz) MAX11043 toc16 0.5 0.3 0.2 200mV/div 0.1 200mV/div DACH 0 -0.1 DACL -0.2 -0.3 -0.4 -0.5 64 128 256 192 2ms/div 2ms/div CODE (LSB) 2.369 2.0 2.367 2.366 2.365 2.364 ANALOG SUPPLY 1.8 1.6 SUPPLY VOLTAGE (V) 2.368 MAX11043 toc19 POWER-ON RESET vs. TEMPERATURE DVREG VOLTAGE vs. TEMPERATURE MAX11043 toc18 0 DVREG VOLTAGE (V) INL (LSB) 64 0 20 40 60 80 100 120 140 160 180 200 1.4 1.2 DIGITAL SUPPLY 1.0 0.8 0.6 0.4 2.363 0.2 0 2.362 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) _______________________________________________________________________________________ 9 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Pin Description 10 PIN NAME FUNCTION 1 AINBN 2 REFA Channel A Reference Bypass. Bypass REFA with a nominal 1F capacitor to AGND. 3 AINAN Channel A Analog Negative Input Channel A Analog Positive Input Channel B Analog Negative Input 4 AINAP 5, 26 AVDD Analog Supply. Bypass each AVDD with a nominal 1F capacitor to AGND. 6, 24, 33 AGND Analog Ground. Connect AGND inputs together. 7, 23 DGND Digital Ground. Connect DGND inputs together. 8, 22 DVDD Digital Supply. Bypass each DVDD with a nominal 1F capacitor to DGND. 9 DVREG 10 UP/DWN DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled. 11 DACSTEP DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising edge of the system clock. 12 CONVRUN Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when CONVRUN is low. Regulated Digital Core Supply. Bypass DVREG to DGND with a 10F capacitor. 13 CS 14 DOUT Serial-Interface Data Out. Data transitions on the rising edge of SCLK. 15 DIN Serial-Interface Data In. Data is sampled on the rising edge of SCLK. 16 SCLK 17, 35 I.C. Internally Connected. Connect to either AGND or DGND. 18 EOC Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready. 19 OSCIN 20 OSCOUT 21 SHDN Active-High Shutdown Input. Drive high to shut down the MAX11043. 25 AOUT Buffered 12-Bit Fine DAC Output 27 REFDACL 28 REFDACH 29 REFDAC 30 REFD Channel D Reference Bypass. Bypass REFD with a nominal 1F capacitor to AGND. 31 AINDN Channel D Analog Negative Input 32 AINDP Channel D Analog Positive Input 34 REFBP Main Reference Bypass. Bypass REFBP with a nominal 1F capacitor to AGND. 36 AINCN Channel C Analog Negative Input 37 AINCP Channel C Analog Positive Input 38 REFC Channel C Reference Bypass. Bypass REFC with a nominal 1F capacitor to AGND. 39 REFB Channel B Reference Bypass. Bypass REFB with a nominal 1F capacitor to AGND. 40 AINBP Channel B Analog Positive Input -- EP Active-Low Serial-Interface Chip Select Serial-Interface Clock Crystal Oscillator/External Clock Input Crystal-Oscillator Output. Leave unconnected when using external clock. Fine DAC Low Reference Bypass. Bypass REFDACL with a nominal 1F capacitor to AGND. Fine DAC High Reference Bypass. Bypass REFDACH with a nominal 1F capacitor to AGND. Coarse DAC Reference Bypass. Bypass REFDAC with a nominal 1F capacitor to AGND. Exposed Pad. Connect EP to a ground plane on the PCB to enhance thermal dissipation. Internally connected to AGND. Not intended as an electrical connection point. ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC AVDD DVDD AINAP UP/DWN PGA EQ PROGRAMMABLE DIGITAL FILTER SIGMA-DELTA ADC AINAN DACSTEP CONVRUN EOC SERIAL INTERFACE SHDN REFA SCLK DOUT AINBP DIN PGA EQ PROGRAMMABLE DIGITAL FILTER SIGMA-DELTA ADC AINBN FLASH REFB MAX11043 AINCP PGA EQ PROGRAMMABLE DIGITAL FILTER SIGMA-DELTA ADC AINCN POR REFC DIGITAL SUPPLY AINDP INTERNAL REGULATOR +2.5V AINDN PROGRAMMABLE DIGITAL FILTER SIGMA-DELTA ADC PGA EQ DVREG CLOCK CRYSTAL OSCILLATOR AND CLOCK BUFFER REFD R +2.5V VOLTAGE REFERENCE 8-BIT DAC OSCOUT OSCIN 12-BIT DAC R 2x REFBP REFDAC REFDACL REFDACH AOUT AGND DGND ______________________________________________________________________________________ 11 MAX11043 Functional Diagram MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Detailed Description The MAX11043 features 4 single-ended or differential channels of simultaneous-sampling ADCs with 16-bit resolution. The MAX11043 contains a versatile filter block and PGA per channel. The filter consists of seven cascaded 2nd-order filter sections for each channel allowing the construction of a 14th-order filter. The filter coefficients are user-programmable. Configure each 2nd-order filter as a LP filter, HP filter, or BP filter with optional rectification. Gain and phase mismatch of the analog signal path is better than -50dB. The ADCs can digitize signals up to 200kHz. A 40MHz serial interface provides communication to and from the device. The SPI interface provides throughput of 1600ksps; 4 channels at 400ksps per channel or 2 channels at 800ksps per channel. A software-selectable scan mode allows reading the ADC results while simultaneously updating the DAC. Other features of the MAX11043 include an internal (+2.5V) or external (+2.0V to +2.8V) reference, power-saving modes, and a PGA with gains of 1 to 64. The PGA includes an EQ function that automatically boosts low-amplitude, highfrequency signals for applications such as CW-chirp radar. The MAX11043 includes two 8-bit coarse DACs that set the high and low references for a second-stage 12-bit fine DAC, typically used for VCO control. Use software controls to set the DAC, or step the DAC up and down using hardware control in programmable steps. IN MODULATOR WITH GAINS OF 1, 2, OR 4 PGA AND FILTER SINC 5 FILTER AND DECIMATE BY 12 MAX11043 Signal Path Each of the 4 ADC channels features a PGA and filter block that feeds the signal to the sigma-delta modulator. The PGA can either be bypassed, which provides a gain of 1, set to a gain of 8, a gain of 16, or set to analog EQ mode. For more amplification, set the ADC modulator gain to one, two, or four. After the modulator, the result passes through the sinc 5 filter and decimator. Seven biquad programmable digital filters isolate the band of interest. Read the result using the 40MHz SPI interface. See Figure 1. Analog-to-Digital Converter The MAX11043 features a quad sigma-delta ADC architecture with 4 differential input channels. For singleended operation, connect the N input to the common-mode voltage or bypass to AGND with a 10F capacitor. All inputs feature a programmable bias generator; see the CONFIG_ Register (0Ch-0Fh) section. All four ADCs convert simultaneously with a maximum modulator sampling rate of 9.6Msps; decimated by 12 or 24 for output rates of 800ksps and 400ksps, respectively. The SPI bus limits the maximum output data rate to 40Mbps. Sinc 5 Filter The sinc 5 filter removes high-frequency noise from the output of the sigma-delta modulator and sets the upper frequency response of the ADC. It also decimates the modulator data by a factor of 12, providing a maximum of 800ksps to the programmable filters when the modulator is operating at 9.6Msps. Figure 2 shows the frequency characteristics of the sinc 5 filter with the CHAN X FINE GAIN DECSEL DECIMATE RANGE: -4 TO +4 0 2 TOTAL DECIMATION 24 RESOLUTION = 16 BITS 1 1 12 FINE GAIN ADJUST BIQUAD FILTER 1 DECIMATE BY 1 OR 2 BIQUAD FILTER 7 7 BIQUAD FILTERS IN SERIES PGA AND FILTER MODES PDPGA PGAG EQ GAIN MODG1 MODG0 BYPASS 1 X X 1 0 0 LP FILTER BIQUAD MODES LP FILTER AND GAIN 8X 0 0 0 2 0 1 LP FILTER AND GAIN 16X 0 1 0 4 1 0 EQUALIZER 0 X 1 4 1 1 FILT RAM 1 POR VALUES EQUALIZER 0 POR VALUES USER DEFINED X USER VALUES Figure 1. Signal Path 12 ______________________________________________________________________________________ SPI 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Equalizer (EQ) The EQ matches the frequency/gain characteristics of CW-chirp radar systems where the distance to the target is proportional to the measured frequency. Distant targets not only have a higher frequency, they have a weaker signal. Hence, higher frequencies need more amplification than lower frequencies. The EQ provides gain proportional to frequencies up to 190kHz, at which point the gain rolls off at 80dB/decade. The EQ consists of an analog section in the PGA and a digital EQ created from the biquad filters. The analog EQ (PGA) provides 20dB/decade of gain and the default digital EQ provides an additional 20dB/decade of gain. Together they provide 40dB/decade of gain up to 190kHz with a gain of 0dB at 5kHz. Variations in the manufacturing process affect the gain and phase of the analog filter. Compensation for these variations include adjustments to the digital filter during the manufacture of the MAX11043. Use the analog and digital EQs together for optimal performance. Conversion and ADC Reading Drive CONVRUN high to initiate a continuous conversion on all 4 channels. Keep CONVRUN high for the entire conversion process. Do not pulse CONVRUN. EOC asserts low when new data is available. Initiate a data read prior to the next rising edge of EOC or the result is overwritten. EOC asserts high upon read completion of all active channels. Use ConfigA, ConfigB, ConfigC, and ConfigD registers to read single channel data. Concatenated data is available in the ADCAB, ADCCD, and ADCABCD registers. Use concatenated registers to ensure simultaneous results are read. See the Register Functions section for more details. A software-selectable scan mode automatically sends the result from selected channels following the CS falling edge and allows other registers to be simultaneously updated. To enable scan mode, set SCHAN_ bits high. See the Configuration Register (08h) section for a detailed description. The ADC output is presented in two's complement format (Figure 3). Digital Filter Seven cascaded, individually configurable, 2nd-order filter elements make up the digital filter. Figure 4 shows the structure of a single filter section. Configure these elements as LP, BP, HP, or all pass (AP) filters with optional rectification. Filter configuration is transferred from the flash to coefficient RAM (C-RAM) on power-up. Store custom filters permanently in the flash or write directly to C-RAM each time on power-up. Two separate sets of programmable coefficients exist for each filter. Dual coefficient sets allow rapid filter reconfiguration. These filter coefficients are programmed to LP and EQ modes at the factory. Multiple flash memory pages exist so that custom filters can be created while preserving factory-programmed filter coefficients. SINC 5 FILTER AT 9.6Msps -20 -40 0111 1111 1111 1110 0111 1111 1111 1101 BINARY OUTPUT CODE ATTENUATION (dB) 0111 1111 1111 1111 MAX11043 fig02 0 -60 -80 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 -100 1000 0000 0000 0010 1000 0000 0000 0001 -120 0 400 800 1200 1600 FREQUENCY (kHz) 2000 1000 0000 0000 0000 -FS -1 0 +1 +FS INPUT VOLTAGE (LSB) Figure 2. Sinc 5 Filter Frequency Response Figure 3. Two's Complement Transfer Function ______________________________________________________________________________________ 13 MAX11043 modulator running at 9.6Msps. Operating the modulator at a lower sample rate causes a proportional reduction in the frequency response of the sinc 5 filter. The total attenuation of the MAX11043 is the sum of the analog filtering, the sinc 5 filter, and the seven stages of programmable filters. Filter coefficients A1 and B1 are always 1. B3 is limited to -1, 0, and 1. Filter coefficients A2, A3, and B2 are stored as 16-bit two's complement values in the range of -4 to +4. Filter coefficients A2 and A3 are stored as -A2 and -A3. Gain is limited to the following values 24, 22, 20, 2-2, 2-4, 2-6, 2-8, and 2-10. For better gain resolution, adjust the RECT + 1/A1 B1 + G ABS SINC 5 FILTER OUTPUT OUT 2500 MAX11043 fig05 IN Fine Gain A/B/C/D Registers at the input of each filter set. Fine gain adjustment has a resolution of 16 bits and a gain range of -4 to +4. Set the RECT bit to rectify the filter output. Figures 5-8 show the response to a step input of the default filters used for ADC trimming. 2000 Z-1 OUTPUT (LSB) MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC X + -A2 B2 + 1500 1000 500 Z-1 0 Y -A3 0 B3 2 4 6 8 10 SAMPLE Figure 5. Sinc 5 Filter Response to a Step Input Figure 4. Single Programmable 2nd-Order Filter Section Table 1. Default Filter Coefficients DEFAULT LOWPASS FILTER COEFFICIENTS STAGE B1 B2 B3 A1 A2 A3 GAIN 1 1 + 2.0 (typ) +1.0000 1 +0.468 (typ) +0.607 (typ) +0 2 1 +1.9509 +1.0000 1 +0.6874 +0.1317 -2 3 1 +1.6139 +1.0000 1 +0.5936 +0.2015 -2 4 1 +1.1488 +1.0000 1 +0.4395 +0.3258 +0 5 1 +0.7415 +1.0000 1 +0.2715 +0.4851 +0 6 1 +0.4651 +1.0000 1 +0.1310 +0.6685 +0 7 1 +0.3296 +1.0000 1 +0.0493 +0.8788 +0 GAIN DEFAULT EQUALIZER COEFFICIENTS 14 STAGE B1 B2 B3 A1 A2 A3 1 1 + 2.0 (typ) +1.0000 1 +0.468 (typ) +0.607 (typ) +0 2 1 +1.9401 +1.0000 1 +0.6886 +0.1359 +0 3 1 +1.5458 +1.0000 1 +0.5803 +0.2275 -2 4 1 +1.0518 +1.0000 1 +0.4139 +0.3887 +0 5 1 +0.6785 +1.0000 1 +0.2563 +0.5966 +0 6 1 -1.0000 +0.0000 1 +0.0039 -0.0000 +4 7 1 +0.4902 +1.0000 1 +0.1649 +0.8489 +2 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC the step size. The UP/DWN input sets the direction of the step. Drive UP/DWN high to step up, drive low to step down. The coarse 8-bit, dual tap DAC generates the high and low reference values for the fine DAC. Obtain the coarse DAC reference from the main reference or by driving the REFDAC input externally. The main reference, REFBP, is divided by two before the coarse DAC. When driving REFDAC, REFDACH, or REFDACL directly, ensure the voltage to the fine DAC does not exceed AVDD/2 to prevent the output amplifier from saturating. LP FILTER OUTPUT Digital-to-Analog Converter The fine DAC register contains the current value of the output. The output value changes by writing to this register or by the rising edge of the DACSTEP input. The DAC register updates on the next rising edge of the system clock following the rising edge of the DACSTEP input. The programmable DACSTEP register contains MAX11043 fig07 2000 OUTPUT (LSB) The MAX11043 features a 12-bit fine DAC with high and low reference inputs set by the 8-bit, dual tap coarse DAC or driven externally. The output buffer of the fine DAC has a gain of two and can drive 10k and 200pF in parallel. Bypass the REFDACH and REFDACL with a 1F capacitor when using the coarse DAC to set the reference values, or power down the buffers and drive REFDACH and REFDACL with external references. Alternatively drive one of the fine DAC references using the coarse DAC and the other using an external reference. 2500 1500 1000 500 0 0 40 60 80 100 SAMPLE Figure 7. LP Filter Response to a Step Input STAGE 1 FILTER OUTPUT EQ FILTER OUTPUT 30,000 25,000 MAX11043 fig08 3500 MAX11043 fig06 35,000 3000 2500 OUTPUT (LSB) 20,000 OUTPUT (LSB) 20 15,000 10,000 5000 0 -5000 2000 1500 1000 500 -10,000 0 -15,000 -500 -20,000 0 20 40 60 80 SAMPLE Figure 6. EQ Filter Response to a Step Input 100 0 10 20 30 40 50 SAMPLE Figure 8. Stage 1 Default Filter Response to a Step Input ______________________________________________________________________________________ 15 MAX11043 Programmable Gain Amplifier Each ADC channel features an input buffer with input impedance of at least 5k and programmable gain of eight or 16. When set to a gain of one, the signal bypasses the PGA to reduce noise. The PGA features an optional 20dB/decade analog EQ mode, with a gain of 0dB near 8kHz and attenuation above 190kHz to reduce out-of-band noise. Using the digital EQ filter adds another 20dB/decade of gain and sets the 0dB frequency to 5kHz. Control the EQ and PGA gain from their respective CONFIG_ registers. For additional filtering and equalization, use the integrated digital filters. MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Reference (REFBP) The MAX11043 features an internal 2.5V bandgap reference. Bypass REFBP with a 1F capacitor or power down the buffer amplifier and drive REFBP with an external reference. In internal reference mode, REFBP provides the main reference voltage for the MAX11043. Refer to www.maxim-ic.com/references for a list of available precision references. In addition to the integrated main reference, there are seven separate references derived from REFBP, one for each ADC channel, one for the coarse DAC, and two (one high and one low) for the fine DAC. When using the main reference, bypass each of the references with a 1F capacitor or set the appropriate bits (7-0), in the reference (10h) register, to power down the references and drive externally. Use external references capable of driving a 700A or total load. Clock Sources The MAX11043 features an internal 16MHz oscillator that supports either an external crystal or ceramic resonator. For highest performance, set bit 15 in the configuration register to 1 and use an external clock (EX clock) source, up to 40MHz, to drive OSCIN. A programmable clock divider divides the EX clock by 2, 3, 4, or 6 to generate the ADC sample clock. The system clock, used for all digital timing, is twice the ADC sample clock. Ensure that the minimum EX clock high or low time is greater than 25ns when using the divide-by2 or divide-by-3 mode. The system clock, used for all internal timing, is derived from the clock divider setting and the input clock. For optimal performance, derive the SPI clock and system clock from the same source. Power Saving The MAX11043 features an active-high power-down input, as well as an SPI-controlled power-down bit that places the MAX11043 in low-power mode. In addition, the MAX11043 features an independent, SPI-controlled, power-down for each ADC channel, the DAC, and the oscillator. See the Configuration Register (08h) section for more details. Serial Communication The SPI-compatible interface allows synchronous serial data transfers up to 40Mbps. The bandwidth is divided between the DACs and the ADC. Maximum conversion throughput depends on which read commands are used. The highest conversion rates are obtained by using the scan mode. The second highest rate is obtained by reading concatenated registers. The slowest method is to read the results individually. Configure the SPI master for SCLK to idle low (SCLK is low when CS is asserted). The data at DIN is latched on the rising edge of SCLK. Data at DOUT transitions immediately after the rising edge of SCLK. All SPI transactions start with a command byte. The command byte selects the address of the register and the mode of operation (read/write). SPI Command Byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 START ADR4 ADR3 ADR2 ADR1 ADR0 R/W 0 START<7>: Start bit. This bit must be 0 for normal operation. ADR_<6:2>: Device register address bits. See the register map in Table 2. 16 R/W<1>: Read/write bit. 1 = read from device. 0 = write to device. ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC tCSH tCH tDH CS MAX11043 tCP tDS tCSS tCL SCLK DIN START X ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 R/W = 0 0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE HIGH IMPEDANCE DOUT Figure 9. SPI 8-Bit Write Operation tCSS tDOD tDOT tCP tDS tDOE tCH tDH CS tCL SCLK DIN DOUT X START ADR 4 ADR 3 ADR 2 HIGH IMPEDANCE ADR 1 ADR 0 R/W = 1 X 0 D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 HIGH IMPEDANCE Figure 10. SPI 8-Bit Read Operation ______________________________________________________________________________________ 17 MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Register Map Table 2. SPI Register Map ADDRESS 18 REGISTER NAME FUNCTION BITS 00h ADCA ADC channel A result register 16/24 01h ADCB ADC channel B result register 16/24 02h ADCC ADC channel C result register 16/24 03h ADCD ADC channel D result register 16/24 04h ADCAB ADC channels A and B results register 32/48 05h ADCCD ADC channels C and D results register 32/48 06h ADCABCD ADC channels A, B, C, and D results register 64/96 07h Status Status register 8 08h Configuration Configures the device 16 09h DAC Fine DAC value 16 0Ah DACSTEP Step size for DAC increment/decrement function 16 0Bh DACH/DACL High and low coarse DAC values 0Ch ConfigA ADC channel A configuration 8+8 16 0Dh ConfigB ADC channel B configuration 16 0Eh ConfigC ADC channel C configuration 16 0Fh ConfigD ADC channel D configuration 16 10h Reference/Delay Sets the operation state of the reference and buffers 16 11h AGain Channel A fine gain 16 12h BGain Channel B fine gain 16 13h CGain Channel C fine gain 16 14h DGain Channel D fine gain 16 15h Filter coefficient address Selects the filter coefficient to read or write. This autoincrements each time the coefficient data register is accessed. 8 16h Filter coefficient data out Coefficient RAMs output data 32 17h Filter coefficient data in Filter coefficient data 32 18h Flash mode Flash mode selection register 8 19h Flash addr Flash address register 16 1Ah Flash data in Flash data in register 16 1Bh Flash data out Flash data out register 1Ch Reserved 16 -- -- 1Dh Reserved -- -- 1Eh Reserved -- -- 1Fh Reserved -- -- ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ADCA, ADCB, ADCC, and ADCD Result Registers (00h-03h) The ADC channel A, B, C, and D result registers provide the result data from the 4 ADC channels. EOC asserts low when new data is available. Initiate a data read prior to the next rising edge of EOC or the result is overwritten. Set bit 5 of the configuration register 08h high to read the data out in 24-bit resolution or set bit 5 low to read the data out in 16-bit resolution. ADCAB, ADCCD, and ADCABCD Result Registers (04h-06h) Registers ADCAB, ADCCD, and ADCABCD contain concatenated ADC results ensuring simultaneous results are read. This reduces the risk of reading samples delayed by one cycle from channel to channel. Set bit 5 of the configuration register 08h high to read the data out in 24-bit resolution or set bit 5 low to read the data out in 16-bit resolution. Status Register (07h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X Flash Busy BOOT OFLGA OFLGB OFLGC OFLGD The status register contains the channel overflow flags and POR bits. X<7:6>: Don't-care bits. BOOT<4>: Power-on reset flag. OFLG_<3:0>: Channel overflow flag, one per channel. Flash Busy<5>: Do not start a new flash operation until this is 0. Configuration Register (08h) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 EXTCLK CLKDIV1 CLKDIV0 PD PDA PDB PDC PDD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PDDAC PDOSC 24BIT SCHANA SCHANB SCHANC SCHAND DECSEL EXTCLK<15>: External clock select. 1 = logic-level clock supplied on OSCIN. 0 = crystal or resonator connected between OSCIN and OSCOUT (default). CLKDIV1:CLKDIV0<14:13>: Clock divider ratio (EX clock : ADC sample clock). 00 = 1:2 clock divider. 01 = 1:3 clock divider. 10 = 1:4 clock divider. 11 = 1:6 clock divider (default). PD<12>: Power-down analog circuitry (reference and SPI interface remains active). 1 = low-power mode. 0 = normal operation (default). PD_<11:8>: ADC power-down for each channel (A, B, C, and D). 1 = powers down analog signal path. 0 = normal operation (default). PDDAC< 7>: DAC power-down. 1 = fine DAC buffer powered down. 0 = normal operation (default). PDOSC<6>: Oscillator power-down. 1 = oscillator powered down (disconnects EX clock in EX clock mode). 0 = normal operation (default). 24BIT<5>: ADC output data format. 1 = ADC data output as 24 bits. 0 = ADC data output as 16 bits (default). Use the 24-bit ADC output in conjunction with external digital filtering to improve signal-to-noise ratio. ______________________________________________________________________________________ 19 MAX11043 Register Functions MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC SCHAN_<4:1>: Automatic ADC result output for each channel (A, B, C, and D). 1 = ADC channel data is output on DOUT each time a new result is valid in the sequence, A, B, C, and D. 0 = ADC data is not presented automatically for this channel (default). When SCHAN_ = 1, the selected ADC channel data is automatically presented on DOUT each time EOC asserts low in the sequence A, B, C, and D with the unselected channels omitted. The data transitions on the rising edge of SCLK. Force CS low to initiate transmission. CS can go high between results. The MSB of the first selected ADC channel outputs immediately after the falling edge of EOC. EOC goes high after the last bit of the selected channels clocks out or one clock cycle before the next result is ready. Insufficient SCLK pulses result in truncated data. Extra clock pulses give an undefined output. In scan mode, keep DIN high or write data to the MAX11043 as usual. In scan mode, the MAX11043 ignores requests for data reads. DECSEL<0>: Decimate select. 1 = decimate by 12. 0 = decimate by 24 (default). Set DECSEL high to decimate the ADC result by 12, doubling the number of samples. The SPI interface is limited to 40Mbps. Fine DAC Register (09h) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 X X X X DAC11 DAC10 DAC9 DAC8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 X<15:12>: Don't-care bits. DAC_<11:0>: Contains current fine DAC output value. When using the DACSTEP input to change the DAC value, this register updates to the new value on the next rising edge of the system clock following the rising edge of DACSTEP. The power-on default is 0. DACSTEP Register (0Ah) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 X X X X DACSTEP11 DACSTEP10 DACSTEP9 DACSTEP8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DACSTEP7 DACSTEP6 DACSTEP5 DACSTEP4 DACSTEP3 DACSTEP2 DACSTEP1 DACSTEP0 X<15:12>: Don't-care bits. DACSTEP11:DACSTEP0<11:0>: Provides the size of the DAC step. The value is positive only and the UP/DWN input is used to set the direction. The value in the fine DAC register updates on the next rising edge of the system clock following the rising edge of the DACSTEP input. The power-on default is 0. Coarse DACH/DACL Register (0Bh) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 DACH7 DACH6 DACH5 DACH4 DACH3 DACH2 DACH1 DACH0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DACL7 DACL6 DACL5 DACL4 DACL3 DACL2 DACL1 DACL0 DACH7:DACH0<15:8>: High coarse DAC value. DACL7:DACL0<7:0>: Low coarse DAC value. 20 Coarse DAC sets high and low references for the fine DAC. The power-on default is 0. ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 CONFIG_ Register (0Ch-0Fh) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 X X X BDAC3 BDAC2 BDAC1 BDAC0 DIFF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EQ MODG1 MODG0 PDPGA FILT PGAG ENBIASP ENBIASN This register sets the input gain of each ADC channel and selects one of the default filters or EQ function. EQ<7>: EQ function. 1 = analog EQ enabled. X<15:13>: Don't-care bits. BDAC3:BDAC0<12:9>: Sets the input bias voltage for AC-coupled signals when ENBIAS_ is set to 1. 0 = analog EQ disabled (default). MODG1:MODG0<6:5>: ADC modulator gain. 00 = 1 (default). 01 = 2. 0000 = 33% of AVDD. 0001 = 35% of AVDD. 0010 = 38% of AVDD. 0011 = 40% of AVDD. 0100 = 42% of AVDD. 0101 = 44% of AVDD. 0110 = 46% of AVDD. 0111 = 48% of AVDD. 1000 = 50% of AVDD. 1001 = 52% of AVDD. 1010 = 54% of AVDD. 1011 = 56% of AVDD. 1100 = 58% of AVDD. 1101 = 60% of AVDD. 1110 = 62% of AVDD. 1111 = 65% of AVDD. DIFF<8>: Input mode select bit. 1 = normal operation in all modes. 0 = use for a 2x input signal range in LP, gain = 1 mode. Note that THD degrades. 10 = 4. 11 = 4. PDPGA<4>: PGA power-down control. 1 = PGA powered down, gain = 1. 0 = PGA powered, PGA gain set by PGAG (default). FILT<3>: Programmable filter select. 1 = use preprogrammed LP filter. 0 = use preprogrammed EQ filter (default). PGAG<2>: High PGA gain setting. 1 = PGA, gain = 16. 0 = PGA, gain = 8 (default). ENBIASP<1>: Positive input bias enable. Bias voltage set by BDAC3:BDAC0. 1 = selfbiasing enabled. 0 = selfbiasing disabled (default). ENBIASN<0>: Negative input bias enable. Bias voltage set by BDAC3:BDAC0. 1 = selfbiasing enabled. 0 = selfbiasing disabled (default). ______________________________________________________________________________________ 21 MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Reference Register (10h) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 0 0 0 PURGE4 PURGE3 PURGE2 PURGE1 PURGE0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EXTREF EXBUFA EXBUFB EXBUFC EXBUFD EXBUFDAC EXBUFDACH EXBUFDACL Reserved<15:13>: Reserved. Set to 0. PURGE4:PURGE0<12:8>: Filter purge interval. Straight binary. 00h = first available sample is presented (default). 1Fh = 31 results are discarded. Digital filters retain a history of past input data. At power-up and when changing the signal path, old data requires purging before new output data is valid. PURGE4(MSB):PURGE0 determine the number of samples to discard before a new result is valid. Each time CONVRUN is taken high, N results are discarded before EOC asserts low (where N is the decimal equivalent of the binary representation of PURGE4:PURGE0). Results prior to N+1 are overwritten. EOC asserts for results N+1, N+2, N+3, etc., as long as CONVRUN remains high. Taking CONVRUN low and then high invokes another purge. EXTREF<7>: Main reference selection. 1 = external reference applied to REFBP, internal reference buffer powered down. 0 = internal reference, bypass REFBP with 1F to AGND (default). Purging of the sinc 5 filter requires five readings if DECSEL (configuration register 08h, bit 0) = 1 and three readings if DECSEL = 0. The minimum total purge interval of the seven cascaded filters is one reading if not used. If the filters are used, the total latency of the programmable filters is the sum of the latency caused by each stage. Set the appropriate delay for filter purging and settling time. EXBUFDACH<1>: High reference for fine DAC. EXBUF_<6:3>: ADC reference selection for each channel. 1 = external reference applied to REF_ input, internal switch open. 0 = using main internal reference, bypass REF_ with 1F to AGND (default). EXBUFDAC<2>: Coarse DAC reference selection. 1 = external reference applied to REFDAC, internal reference buffer powered down. 0 = using main internal reference, bypass REFDAC with 1F to AGND (default). 1 = external reference applied to REFDACH, internal reference buffer powered down. 0 = using high output from coarse DAC as reference, bypass REFDACH with 1F to AGND (default). EXBUFDACL<0>: Low reference for fine DAC. 1 = external reference applied to REFDACL, internal reference buffer powered down. 0 = using low output from coarse DAC as reference, bypass REFDACL with 1F to AGND (default). 22 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Fine Gain A/B/C/D Registers (11h-14h) Fine gain for each channel is a two's complement binary value (8192 x desired gain). FINE GAIN REGISTER GAIN 7FFFh (4 - 1/8192) 4000h 2 2001h 8193/8192 2000h 1 (default) 1FFFh 8191/8192 1000h 0.5 0800h 0.25 Filter Coefficient Address Register (15h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CHAN1 CHAN0 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 CHAN_<7:6>: Channel selection. 00 = channel A (default). 01 = channel B. 10 = channel C. Filter Coefficient Data Out Register (16h) This is a 32-bit register that contains the data from a C-RAM read operation. Filter Coefficient Data In Register (17h) 11 = channel D. ADR5:ADR0<5:0>: Address pointer for C-RAM containing filter coefficients (default = 0). This is a 32-bit register that contains the data for a C-RAM write operation. Default = 0. ______________________________________________________________________________________ 23 MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Flash Mode Register (18h) BIT 7 BIT 6 BIT 5 FM2 (Flashmode2) FM1 (Flashmode1) FM0 (Flashmode0) BIT 4 0 BIT 3 X BIT 2 BIT 1 BIT 0 X Flash busy (read only) X Write allowed only if flash busy bit is zero. FM2:FM0<7:5>: Flash operation (default 0). 000 = no operation. 110 = transfer data from flash to C-RAM. 111 = no operation. Reserved<4>: Reserved. Set to 0. 001 = write data in flash data in register to flash. 010 = erase data in the selected page. 011 = mass erase the flash. 100 = no operation. X<3:1>: Don't-care bits. Flash busy<0>: Flash busy flag. 1 = flash busy. 0 = flash ready. 101 = read data from flash into data out register. Flash Address Register (19h) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 X X X X X PAGE2 PAGE1 PAGE0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADR7 ADR6 ADR5 ADR5 ADR3 ADR2 ADR1 ADR0 Write allowed only if flash busy bit is zero (18h bit 0 or status register) (default = 0). X<15:11> : Don't-care bits. PAGE2:PAGE0<10:8>: Page selection. 000 = page 0 (default). 001 = page 1. 010 = page 2. 24 011 = page 3. 100 = page 4. 101 = page 5. 110 = page 6. 111 = page 7. ADR7:ADR0<7:0>: Address pointer flash word containing filter coefficients (default = 0). ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC This is a 16-bit register that contains the data for a flash write operation. Default = 0. Flash Data Out Register (1Bh) This is a read-only register. Data is valid only if flash busy is zero. This is a 16-bit register that contains the data for a flash read operation. Flash and C-RAM Register Map The flash memory consists of 2048 words by 16 bits. The 3 MSBs of the flash address select one of eight pages of 256 words each. Page zero contains the default filter coefficients for channels A and B. Page one contains the default filter coefficients for channels C and D. Use pages two and three for the coefficients of custom filters. When the first word on page two contains a nonzero value, the MAX11043 loads these pages into C-RAM at power-up instead of the default values from pages zero and one. Flash pages zero and one include trim data. Unique trim data optimizes the performance of each MAX11043. Coefficients for the stage 1 filters and ADC gain are individually programmed at the factory to com- pensate for manufacturing variations in the analog portion of the IC. These coefficients vary depending on the PGA gain setting and if the analog equalizer is used. To allow for these different modes, several sets of stage 1 coefficients are stored in flash. Bits in the CONGIF register select which set of stage 1 coefficients are used. Table 3 shows the C-RAM addresses used for each CONFIG setting. To maintain optimum performance when using custom filters, copy the trim data from flash pages zero and one to the corresponding locations in flash pages two and three or to C-RAM when writing directly to C-RAM. For custom filters, use stages 2-7 first, and only change the stage 1 coefficients when all seven stages require customization. To load the coefficients directly to C-RAM, create a 32bit data word by concatenating the data in adjacent flash locations as shown in Table 3. The C-RAM addresses below are for channel A; for channel B add 40h, for channel C add 80h, and for channel D add C0h. Multiple addresses exist for some stage 1 filter coefficients as shown in Table 4. The address accessed by the filter depends on the configuration bits as shown in Table 3. Table 3. Stage 1 Filter Selection STAGE 1 COEFFICIENT ADDRESS EQ PDPGA MODG PGAG EQ filter stage 1 (C-RAM address 03h-05h) 1 0 XX X LP filter for ADC gain of 1, 2, and 4; stage 1 (C-RAM address 1Dh-1Fh) X 1 XX X LP filter for ADC gain of 8; stage 1 (C-RAM address 3Dh-3Fh) 0 0 00 0 LP filter for ADC gain of 16; stage 1 (C-RAM address 23h-25h) 0 0 XX 1 Table 4. C-RAM and Flash Memory Map for Channel A Flash Page One* C-RAM ADDRESS 00h 01h 02h 03h FLASH ADDRESS MSB FOR C-RAM 00h 01h* -- -- 06h* 07h* -- Not used User trim for EQ gain, default = 2000h 04h 05h Not used EQ gain trim for gain = 1 02h 03h LSB FOR C-RAM -- Not used -- Not used -- -- EQ filter coefficient -A2 for filter stage 1 EQ filter gain for filter stage 1 -- *For channel B add 80h, for channel C add 100h, and for channel D add 180h. To write to pages two and three of flash, add 200h to these values. ______________________________________________________________________________________ 25 MAX11043 Flash Data In Register (1Ah) Write allowed only if flash busy bit is zero. MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 4. C-RAM and Flash Memory Map (continued) C-RAM ADDRESS 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 26 FLASH ADDRESS 08h 09h* 0Ah* 0Bh* 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh MSB FOR C-RAM -- LSB FOR C-RAM Not used EQ filter coefficient -A3 for filter stage 1 -- -- EQ filter coefficient B3 and rectify bit for filter stage 1 EQ filter coefficient B2 for filter stage 1 -- -- EQ filter gain for filter stage 2 EQ filter coefficient -A2 for filter stage 2 -- -- Not used EQ filter coefficient -A3 for filter stage 2 -- -- EQ filter coefficient B3 and rectify bit for filter stage 2 EQ filter coefficient B2 for filter stage 2 -- -- EQ filter gain for filter stage 3 EQ filter coefficient -A2 for filter stage 3 -- -- Not used EQ filter coefficient -A3 for filter stage 3 -- -- EQ filter coefficient B3 and rectify bit for filter stage 3 EQ filter coefficient B2 for filter stage 3 -- -- EQ filter gain for filter stage 4 EQ filter coefficient -A2 for filter stage 4 -- -- Not used EQ filter coefficient -A3 for filter stage 4 -- -- EQ filter coefficient B3 and rectify bit for filter stage 4 EQ filter coefficient B2 for filter stage 4 -- -- EQ filter gain for filter stage 5 EQ filter coefficient -A2 for filter stage 5 -- -- Not used EQ filter coefficient -A3 for filter stage 5 -- -- EQ filter coefficient B3 and rectify bit for filter stage 5 EQ filter coefficient B2 for filter stage 5 -- -- EQ filter gain for filter stage 6 EQ filter coefficient -A2 for filter stage 6 -- -- Not used EQ filter coefficient -A3 for filter stage 6 -- -- EQ filter coefficient B3 and rectify bit for filter stage 6 EQ filter coefficient B2 for filter stage 6 -- -- EQ filter gain for filter stage 7 EQ filter coefficient -A2 for filter stage 7 -- EQ filter coefficient -A3 for filter stage 7 -- Not used -- ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC C-RAM ADDRESS 17h 18h 19h 1Ah 1Bh 1Ch FLASH ADDRESS MSB FOR C-RAM 2Eh 2Fh -- -- -- -- -- -- 3Bh* -- 3Dh* -- Not used -- Not used -- LP filter gain for filter stage 1, gain = 1, 2, or 4 LP filter coefficient -A2 for filter stage 1, gain = 1, 2, or 4 3Ch 1Eh -- Not used EQ gain trim for gain = 4 3Ah* 1Dh -- Not used EQ gain trim for gain = 2 38h 39h* Not used ADC gain trim for gain = 4 36h 37h* -- ADC gain trim for gain = 2 34h 35h* EQ filter coefficient B3 and rectify bit for filter stage 7 ADC gain trim for gain = 1 32h 33h* LSB FOR C-RAM EQ filter coefficient B2 for filter stage 7 30h 31h* -- -- Not used LP filter coefficient -A3 for filter stage 1, gain = 1, 2, or 4 3Eh* -- MAX11043 Table 4. C-RAM and Flash Memory Map (continued) -- LP filter coefficient B3 and rectify bit for filter stage 1, gain = 1, 2, or 4 1Fh 3Fh* 20h 21h 22h 40h 41h* 43h -- 45h 47h* 49h* 4Ah* Not used -- Not used User trim for ADC gain, default = 2000h 44h 48h 24h -- -- ADC gain trim for gain = 16 42h 46h* 23h LP filter coefficient B2 for filter stage 1, gain = 1, 2, or 4 -- -- Not used Not used -- -- LP filter gain for filter stage 1, gain = 16 LP filter coefficient -A2 for filter stage 1, gain = 16 -- LP filter coefficient -A3 for filter stage 1, gain = 16 -- -- Not used -- LP filter coefficient B3 and rectify bit for filter stage 1, gain = 16 25h 4Bh* 26h 4Ch 4Dh LP filter coefficient B2 for filter stage 1, gain = 16 -- LP filter coefficient -A2 for filter stage 2 -- LP filter gain for filter stage 2 -- ______________________________________________________________________________________ 27 MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 4. C-RAM and Flash Memory Map (continued) C-RAM ADDRESS 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 28 FLASH ADDRESS MSB FOR C-RAM 4Eh 4Fh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 74h 75h* -- LP filter coefficient B3 and rectify bit for filter stage 6 -- LP filter gain for filter stage 7 -- Not used -- LP filter coefficient B3 and rectify bit for filter stage 7 -- -- Not used -- Not used -- Not used Not used 72h 73h -- Not used LP filter coefficient B2 for filter stage 7 70h 71h LP filter gain for filter stage 6 LP filter coefficient -A3 for filter stage 7 6Eh 6Fh -- LP filter coefficient -A2 for filter stage 7 6Ch 6Dh -- LP filter coefficient B3 and rectify bit for filter stage 5 LP filter coefficient B2 for filter stage 6 6Ah 6Bh -- Not used LP filter coefficient -A3 for filter stage 6 68h 69h LP filter gain for filter stage 5 LP filter coefficient -A2 for filter stage 6 66h 67h -- LP filter coefficient B2 for filter stage 5 64h 65h -- LP filter coefficient B3 and rectify bit for filter stage 4 LP filter coefficient -A3 for filter stage 5 62h 63h -- Not used LP filter coefficient -A2 for filter stage 5 60h 61h -- LP filter gain for filter stage 4 LP filter coefficient B2 for filter stage 4 5Eh 5Fh LP filter coefficient B3 and rectify bit for filter stage 3 LP filter coefficient -A3 for filter stage 4 5Ch 5Dh -- LP filter coefficient -A2 for filter stage 4 5Ah 5Bh -- Not used LP filter coefficient B2 for filter stage 3 58h 59h -- LP filter gain for filter stage 3 LP filter coefficient -A3 for filter stage 3 56h 57h LP filter coefficient B3 and rectify bit for filter stage 2 LP filter coefficient -A2 for filter stage 3 54h 55h -- LP filter coefficient B2 for filter stage 2 52h 53h Not used LP filter coefficient -A3 for filter stage 2 50h 51h LSB FOR C-RAM -- Not used -- ADC gain trim for gain = 8 -- ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC C-RAM ADDRESS 3Bh 3Ch FLASH ADDRESS 76h 77h* 78h 79h* 7Ah* 3Dh 7Bh* 7Ch 3Eh 7Dh* 7Eh* MSB FOR C-RAM LSB FOR C-RAM -- Not used ADC gain trim for gain = 32 -- -- Not used ADC gain trim for gain = 64 -- -- LP filter gain for filter stage 1, gain = 8 LP filter coefficient -A2 for filter stage 1, gain = 8 -- -- Not used LP filter coefficient -A3 for filter stage 1, gain = 8 -- MAX11043 Table 4. C-RAM and Flash Memory Map (continued) -- LP filter coefficient B3 and rectify bit for filter stage 1, gain = 8 3Fh 7Fh* LP filter coefficient B2 for filter stage 1, gain = 8 -- *Recommended copy to C-RAM or flash for optimum custom-filter performance. Flash Erase and Programming When erasing or programming the flash, maintain the system clock between 14MHz and 27MHz to satisfy flash timing requirements and ensure CONVRUN = 0. The system clock used for all digital timing is twice the ADC sample clock (2 x EX clock/divider). Always erase the flash page before writing new data. The procedure for flash mass erase is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write 0000h to the flash address register (19h). 3) Write 60h to the flash mode register (18h). 4) Wait 200ms for erase to complete. 5) FFFFh = flash erased state. The procedure for flash single page erase is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write page address, set word address to 00h in the flash address register (19h). 3) Write 40h to the flash mode register (18h). 4) Wait 20ms for page erase to complete. 5) FFFFh = flash erased state. The procedure for flash single word write is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write page and word address to the flash address register (19h). 3) Write the data to the flash data in register (1Ah). 4) Write 20h to the flash mode register (18h). 5) Read the flash mode register (18h); proceed when the LSB is zero (approx. 40s). The procedure for flash single word read is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write page and word address to the flash address register (19h). 3) Write A0h to the flash mode register (18h). 4) Read the flash mode register (18h); proceed when the LSB is zero (approx. 1s). 5) Read the data from the flash data out register (1Bh). The procedure for flash to C-RAM transfer is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write C0h to the flash mode register (18h). 3) Read the flash mode register (18h); proceed when the LSB is zero (approx. 1ms). 4) The content of flash is transferred to C-RAM. ______________________________________________________________________________________ 29 MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Digital Filter Coefficients Table 5. Typical Filter Coefficients Register Map (LP Filter Channel A, Stage 3) COEFFICIENT FLASH ADDRESS FUNCTION 52h Gain for channel A, stage 3 53h A2 coefficient for channel A, stage 3 54h Not used; set to 0 55h A3 coefficient for channel A, stage 3 56h B3 coefficient and rectify flag (RECT) for channel A, stage 3 57h B2 coefficient for channel A, stage 3 Format for Filter Stage Gain (52h) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 X GAIN2 GAIN1 GAIN0 X X X X BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X X X X X X X X<15>: Don't-care bit. Not used. GAIN2:GAIN0<14:12>: Filter gain. 24 000 = = 16. 001 = 22 = 4. 010 = 20 = 1. 011 = 30 2-2 100 = 2-4 = 0.0625. 101 = 2-6 = 0.015625. 110 = 2-8 = 0.00390625. 111 = 2-10 = 0.0009765625. X<11:0>: Don't-care bits. Not used. = 0.25. ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Example 1: N = 2.381 A2 = int (2.381 x 213) MAX11043 A2, A3, and B2 Filter Coefficient Format (52h, 54h, 56h) Filter coefficients A2, A3, and B2 are stored as 16-bit two's complement values in the -4 to (4 - 2-13) range. The transfer function equation is as follows: A2 = int (N x 213) where N is the decimal coefficient value. The following are two examples of the transfer function equation: A2 = int (19505.152) A2 = 19505 = 4C31h (two's complement) Example 2: N = -2.381 A2 = int (-2.381 x 213) A2 = int (-19505.152) A2 = -19505 = B3CFh (two's complement) B3 Coefficient (56h) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 B31 B30 RECT X X X X X BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X X X X X X X B31:B30<15:14>: Filter coefficient B3. 11 = -1. X<13>: Don't-care bit. Not used. RECT<12>: Rectify bit. 00 = 0. 01 = 1. 0 = bipolar output. 1 = output rectified. All samples positive. 10 = 0. X<11:0>: Don't-care bits. Not used. Power Supplies, Layout, and Bypassing Considerations For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and do not run digital lines underneath the MAX11043 package. Use a single-point analog ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to this star ground point. Do not connect other digital system grounds to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. Bypass all supplies to ground with high quality capacitors as close as possible to the device. ______________________________________________________________________________________ 31 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Typical Operating Circuit TO DIGITAL SUPPLY ECHO+ TO ANALOG SUPPLY AINAP DVDD *SEE NOTE AINAN ECHO- REFA AVDD RADAR FRONT END ECHO+ AINBP AGND *SEE NOTE AINBN ECHO- REFB ECHO+ *SEE NOTE MAX11043 CS UP/DWN DACSTEP CONVRUN EOC SHDN SCLK DOUT DIN OSCIN AINCP AINCN ECHO- REFC ECHO+ *SEE NOTE DSP AINDP AINDN DGND ECHOREFD DVREG AOUT REFBP REFDAC REFDACH REFDACL EXT REF *NOTE: CONNECT TO AGND FOR SINGLE-ENDED OPERATION. Package Information Chip Information PROCESS: BiCMOS 32 For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 40 TQFN-EP T4066+5 21-0141 90-0055 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC REVISION NUMBER REVISION DATE 0 8/08 Initial release 1 3/10 Updated Ordering Information with automotive grade information and clarified/amended data sheet 2 3/11 Updated the Flash Erase and Programming section DESCRIPTION PAGES CHANGED -- 1, 2-7, 12-15, 21, 25, 30 29 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 (c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX11043 Revision History