Hardware User Manual
TCM-BF537 v1.x
TCM-BF537BP v1.x
TCM‐BF537v1.x‐HardwareUserManual 2
Contact
Bluetechnix Mechatronische Systeme GmbH
Lainzerstraße 162/3
A-1130 Vienna
AUSTRIA/EUROPE
office@bluetechnix.at
http://www.bluetechnix.com
Document No.: 100-1225-1.4
Document Revision 20
Date: 2010-11-30
TCM‐BF537v1.x‐HardwareUserManual 3
Table of Contents
BLACKFIN Products .............................................................................................................................................................................. 6
BLACKFIN Design Service ................................................................................................................................................................... 7
1Introduction .................................................................................................................................................................................. 8
1.1Overview ............................................................................................................................................................................... 8
1.2Versions ................................................................................................................................................................................. 9
1.3Key Features ........................................................................................................................................................................ 9
1.4Target Applications ........................................................................................................................................................... 9
1.5Further Information .......................................................................................................................................................... 9
2Specification ............................................................................................................................................................................... 10
2.1Functional Specification ................................................................................................................................................ 10
2.2Boot Mode .......................................................................................................................................................................... 11
2.3Flash Memory Map*) ...................................................................................................................................................... 11
2.3.1Asynchronous Memory Banks ........................................................................................................................... 12
2.4SDRAM Memory Map ..................................................................................................................................................... 12
2.5Electrical Specification ................................................................................................................................................... 12
2.5.1Supply Voltage ........................................................................................................................................................ 12
2.5.2Supply Voltage Ripple .......................................................................................................................................... 13
2.5.3Input Clock Frequency ......................................................................................................................................... 13
2.5.4Real Time Clock Crystal ........................................................................................................................................ 13
2.5.5Supply Current ........................................................................................................................................................ 13
2.6Environmental Specification ........................................................................................................................................ 13
2.6.1Temperature ............................................................................................................................................................ 13
2.6.2Humidity.................................................................................................................................................................... 13
3TCM-BF537C (Connector Version) ....................................................................................................................................... 13
3.1Mechanical Outline ......................................................................................................................................................... 13
3.2Footprint ............................................................................................................................................................................. 15
3.3Schematic Symbol of Connector Version ................................................................................................................ 16
3.4Connectors PIN Assignment ........................................................................................................................................ 17
3.4.1Connector X1 – (1-60) ........................................................................................................................................... 17
3.4.2Connector X2 – (61-120) ...................................................................................................................................... 18
4TCM-BF537B (Border Pad and BGA Versions) .................................................................................................................. 20
4.1Mechanical Outline ......................................................................................................................................................... 20
4.2Footprint of Border Pad Baseboard ........................................................................................................................... 21
4.3Schematic Symbol of Border Pad Version ............................................................................................................... 22
4.4Border Pad Pin Assignment .......................................................................................................................................... 23
TCM‐BF537v1.x‐HardwareUserManual 4
4.5BGA PAD Numbering ..................................................................................................................................................... 25
4.6Footprint of BGA Baseboard ........................................................................................................................................ 25
4.7Schematic Symbol of BGA Version ............................................................................................................................ 26
4.8BGA Pin Assignment ....................................................................................................................................................... 27
4.9Reset circuit ....................................................................................................................................................................... 31
4.10Flash Memory Extension PINS ..................................................................................................................................... 31
4.10.1PINS FA20 to FA24 ................................................................................................................................................. 31
4.10.2WP_FLASH ................................................................................................................................................................ 31
5Application Example Schematics ........................................................................................................................................ 32
5.1Schematic Example for Connecting a Physical Ethernet Chip ......................................................................... 32
5.2Schematic Example for Connecting a USB 2.0 Chip ............................................................................................. 33
6Software Support ...................................................................................................................................................................... 34
6.1BLACKSheep ...................................................................................................................................................................... 34
6.2uClinux ................................................................................................................................................................................ 34
7Anomalies .................................................................................................................................................................................... 34
8Production Report .................................................................................................................................................................... 35
9Product Changes ....................................................................................................................................................................... 36
10Document Revision History .............................................................................................................................................. 36
AList of Figures and Tables ....................................................................................................................................................... 37
TCM‐BF537v1.x‐HardwareUserManual
5
© Bluetechnix Mechatronische Systeme GmbH 2010
All Rights Reserved.
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights of technical change reserved.
We hereby disclaim any warranties, including but not limited to warranties of non-infringement, regarding circuits,
descriptions and charts stated herein.
Bluetechnix makes and you receive no warranties or conditions, express, implied, statutory or in any
communication with you. Bluetechnix specifically disclaims any implied warranty of merchantability or fitness for a
particular purpose.
Bluetechnix takes no liability for any damages and errors causing of the usage of this board. The user of this board is
responsible by himself for the functionality of his application. He is allowed to use the board only if he has the
qualification. More information is found in the General Terms and Conditions (AGB).
Information
For further information on technology, delivery terms and conditions and prices please contact Bluetechnix
(http://www.bluetechnix.com).
Warning
Due to technical requirements components may contain dangerous substances.
The Core Modules and development systems
contain ESD (electrostatic discharge) sensitive
devices. Electro-static charges readily
accumulate on the human body and
equipment and can discharge without
detection. Permanent damage may occur on
devices subjected to high-energy discharges.
Proper ESD precautions are recommended to
avoid performance degradation or loss of
functionality. Unused Core Modules and
Development Boards should be stored in the
protective shipping
TCM‐BF537v1.x‐HardwareUserManual 6
BLACKFIN Products
Core Modules:
TCM-BF518: The new Core Module CM-BF518 is powered by Analog Devices' single core ADSP-
BF518 processor; up to 400MHz, 32MB SDRAM, up to 8MB flash. The 2x60 pin expansion
connectors are backwards compatible with other Core Modules.
CM-BF527: The new Blackfin Processor Module is powered by Analog Devices' single core ADSP-
BF527 processor; key features are USB OTG 2.0 and Ethernet. The 2x60 pin expansion
connectors are backwards compatible with other Core Modules.
CM-BF533: Blackfin Processor Module powered by Analog Devices' single core ADSP-BF533
processor; up to 600MHz, 32MB SDRAM, 2MB flash, 2x60 pin expansion connectors and
a size of 36.5x31.5mm.
TCM-BF537: Blackfin Processor Module powered by Analog Devices' single core ADSP-BF537
processor; up to 500MHz, 32MB SDRAM, 8MB flash, a size of 28x28mm, 2x60 pin
expansion connectors, Ball Grid Array or Border Pads for reflow soldering, industrial
temperature range -40°C to +85°C.
CM-BF537E: Blackfin Processor Module powered by Analog Devices' single core ADSP-BF537
processor; up to 600MHz, 32MB SDRAM, 4MB flash, integrated TP10/100 Ethernet
physical transceiver, 2x60 pin expansion connectors and a size of 36.5x31.5mm.
CM-BF537U: Blackfin Processor Module powered by Analog Devices' single core ADSP-BF537
processor; up to 600MHz, 32MB SDRAM, 4MB flash, integrated USB 2.0 Device, 2x60 pin
expansion connectors and a size of 36.5x31.5mm.
CM-BF548: The new Blackfin Processor Module is powered by Analog Devices' single core ADSP-
BF548 processor; key features are 64MB DDR SD-RAM 2x100 pin expansion connectors.
CM-BF561: Blackfin Processor Module powered by Analog Devices' dual core ADSP-BF561
processor; up to 2x 600MHz, 64MB SDRAM, 8MB flash, 2x60 pin expansion connectors
and a size of 36.5x31.5mm.
eCM-BF561: Blackfin Processor Module powered by Analog Devices' dual core ADSP-BF561
processor; up to 2x 600MHz, 128MB SDRAM, 8MB flash, 2x100 pin expansion connectors
and a size of 44x33mm.
TCM‐BF537v1.x‐HardwareUserManual 7
Development Boards:
EVAL-BF5xx: Low cost Blackfin processor Evaluation Board with one socket for any Bluetechnix
Blackfin Core Module. Additional interfaces are available, e.g. an SD-Card.
DEV-BF5xxDA-Lite: Get ready to program and debug Bluetechnix Core Modules with this tiny development
platform including an USB-Based Debug Agent. The DEV-BF5xxDA-Lite is a low cost
starter development system including a VDSP++ Evaluation Software License.
DEV-BF548-Lite: Low-cost development board with one socket for Bluetechnix CM-BF548 Core Module.
Additional interfaces are available, e.g. an SD-Card, USB and Ethernet.
DEV-BF548DA-Lite: Get ready to program and debug Bluetechnix CM-BF548 Core Module with this tiny
development platform including an USB-Based Debug Agent. The DEV-BF548DA-Lite is
a low-cost starter development system including a VDSP++ Evaluation Software
License.
EXT-Boards: The following Extender Boards are available: EXT-BF5xx-AUDIO, EXT-BF5xx-VIDEO, EXT-
BF5xx-CAM, EXT-BF5xx-EXP-TR, EXT-BF5xx-USB-ETH2, EXT-BF5xx-AD/DA, EXT-BF548-
EXP and EXT-BF518-ETH. Furthermore, we offer the development of customized
extender boards for our customers.
Software Support:
BLACKSheep: The BLACKSheep VDK is a multithreaded framework for the Blackfin processor family
from Analog Devices that includes driver support for a variety of hardware extensions. It
is based on the real-time VDK kernel included within the VDSP++ development
environment.
LabVIEW: LabVIEW embedded support for Bluetechnix Core Modules is done by Schmid-
Engineering AG: http://www.schmid-engineering.ch
uClinux: All the Core Modules are fully supported by uClinux. The required boot loader and
uClinux can be downloaded from: http://blackfin.uClinux.org.
Upcoming Products and Software Releases:
Keep up-to-date with all the changes to the Bluetechnix product line and software updates at:
http://www.bluetechnix.com .
BLACKFIN Design Service
Based on more than five years of experience with Blackfin, Bluetechnix offers development assistance as well as
custom design services and software development.
TCM‐BF537v1.x‐HardwareUserManual 8
1 Introduction
The TCM-BF537 is a chip size Core Module designed for industrial temperature range and volume production. It
combines power supply, RAM and FLASH into a module as small as a chip package. Different connector options (Ball
Grid Array (BGA), Border Pads (BP) and Connectors) provides solutions for all possible requirements.
1.1 Overview
The Core Module TCM-BF537 consists of the following components shown in Figure 1-1.
Figure 1-1: Main Components of the TCM-BF537 Core Module
Analog Devices Blackfin Processor BF537
o ADSP-BF537BBCZ-5A, 500MHz (-40°-85°C)
32 MB SDRAM
o SDRAM Clock up to 133MHz
o See chapter 8 Production Report
Up to 64 MB of Byte Addressable Flash
o See chapter 8 Production Report
o Additional flash memory upon request: It can be connected through the expansion board as
parallel flash using asynchronous chip select lines or as SPI flash.
Low Voltage Reset Circuit
o Resets module if power supply goes below 2.93V.
Dynamic Core Voltage Control
o Core voltage adjustable by setting software registers on the Blackfin processor
o Core voltage range: 0.8 – 1.32V
TCM‐BF537v1.x‐HardwareUserManual 9
Peripherals available on all Core Module versions
o SPORT 0
o JTAG
o UART0/UART1
o CAN
o TWI (I2C compatible)
o SPI (Serial Port Interface)
o PPI (Parallel Port Interface)
o Boot Mode Pins
o GPIO’s
Peripherals available on the Connector and BGA version only.
o Data Bus
o Address Bus
o Further GPIO’s
o Memory Control Signals
1.2 Versions
TCM-BF537: Connector Version 2x60 connector pins
TCM-BF537BGA: 169 BGAs 1.5 mm pitch for volume production
TCM-BF537BP: 76 Border Pads, no Data- and Address bus on border pads
1.3 Key Features
The TCM-BF537, measuring only 28x28mm is the smallest core module available.
An extended temperature range, suitable for industrial production.
Allows integration on a two layer baseboard.
Reduces development costs, fast time to market.
Very cost effective for small and medium volumes
1.4 Target Applications
Generic high performance signal processor module
Industrial Automation
1.5 Further Information
Further information, and document updates are available on the product homepage:
http://www.bluetechnix.com/goto/tcm-bf537
TCM‐BF537v1.x‐HardwareUserManual 10
2 Specification
2.1 Functional Specification
Figure 2-1: Detailed Block Diagram
Figure 2-1 shows a detailed block diagram of the TCM-BF537 module. Beside the SDRAM and a few other control
pins, the TCM-BF537 has most pins of the Blackfin processor on its two 60 pin connectors, or its BGA, or its Border
Pads.
Dynamic voltage control allows reducing power consumption to a minimum adjusting the core voltage and the
clock frequency dynamically in accordance to the required processing power.
A low voltage reset circuit guarantees a power on reset and resets the system when the input voltage drops below
2.93V for at least 140ms.
32 Mbyte
SDRam
256Mx16
Up to
64 Mbyte
Flash
BF537
@
500MHz
Dynamic
Core Voltage
Control
Low Voltage
Reset
20 Bit Address Bus
16 Bit Data Bus
Clock
Mem. Control, Boot Mode, JTAG, Ethernet
Data & Address Bus
Clock-out PPI, SPORT0, UART, SPI, TWI, CAN, GPIO
3V3 Power , Reset
TCM‐BF537v1.x‐HardwareUserManual 11
2.2 Boot Mode
By default the boot mode = 000 (BMODE2 = Low, BMODE1 = Low, BMODE0=Low). All BMODE pins have on board
pull down resistors.
SwitchSettings
BM2,BM1,BM0
Description
000Executefrom16‐bitexternalmemory(bypassbootROM)
001Bootfrom8‐bitor16‐bitmemory(EPROM/flash)
010Reserved
011BootfromserialSPImemory(EEPROM/flash)
100BootfromSPIHost(slavemode)
101BootfromserialTWImemory(EEPROM/flash)
110BootfromTWIhost(slavemode)
111BootfromUARThost(slavemode)
Table 2-1: Boot Mode TCM-BF537
Connect BMODE0 to Vcc and leave BMODE1, BMODE2 pins open for Boot Mode 001 equals to 8 or 16 bit
PROM/FLASH boot mode. This is the default boot mode for the BLACKSheep software.
2.3 Flash Memory Map*)
Blackfin
StartAddr.
Blackfin
EndAddr.
FA24
(PG15)
**)
FA23
(PG14)
**)
FA22
(PG13)
**)
FA21
(PF5)
FA20
(PF4)
Flash
StartAddr.
Flash
EndAddr.
0x200000000x201FFFFF000000x000000000x001FFFFF
0x200000000x201FFFFF000010x002000000x003FFFFF
0x200000000x201FFFFF000100x004000000x005FFFFF
0x200000000x201FFFFF000110x006000000x007FFFFF
0x200000000x201FFFFF001000x008000000x009FFFFF
0x200000000x201FFFFF001010x00A000000x00BFFFFF
0x200000000x201FFFFF001100x00C000000x00DFFFFF
0x200000000x201FFFFF001110x00E000000x00FFFFFF
0x200000000x201FFFFF010000x010000000x011FFFFF
0x200000000x201FFFFF010010x012000000x013FFFFF
0x200000000x201FFFFF010100x014000000x015FFFFF
0x200000000x201FFFFF010110x016000000x017FFFFF
0x200000000x201FFFFF011000x018000000x019FFFFF
0x200000000x201FFFFF011010x01A000000x01BFFFFF
0x200000000x201FFFFF011100x01C000000x01DFFFFF
0x200000000x201FFFFF011110x01E000000x01FFFFFF
0x200000000x201FFFFF100000x020000000x021FFFFF
0x200000000x201FFFFF100010x022000000x023FFFFF
0x200000000x201FFFFF100100x024000000x025FFFFF
0x200000000x201FFFFF100110x026000000x027FFFFF
0x200000000x201FFFFF101000x028000000x029FFFFF
0x200000000x201FFFFF101010x02A000000x02BFFFFF
0x200000000x201FFFFF101100x02C000000x02DFFFFF
0x200000000x201FFFFF101110x02E000000x02FFFFFF
0x200000000x201FFFFF110000x030000000x031FFFFF
0x200000000x201FFFFF110010x032000000x033FFFFF
0x200000000x201FFFFF110100x034000000x035FFFFF
TCM‐BF537v1.x‐HardwareUserManual 12
0x200000000x201FFFFF110110x036000000x037FFFFF
0x200000000x201FFFFF111000x038000000x039FFFFF
0x200000000x201FFFFF111010x03A000000x03BFFFFF
0x200000000x201FFFFF111100x03C000000x03DFFFFF
0x200000000x201FFFFF111110x03E000000x03FFFFFF
Table 2-2: Memory Map
The flash memory is subdivided into addressable banks with 2 MByte size.
The pin-connections for FA22-FA24 can be customized. Please contact Bluetechnix Support for more information.
*) Be aware that you have to unlock the flash before starting an erase process!
**) Only valid if 64 MByte flash mounted (see chapter 8 Production Report)
2.3.1 Asynchronous Memory Banks
The maximum amount of memory addressable by a single asynchronous memory bank, of the Blackfin processor is
1MB. On this module, each 2MB segment of Flash is addressed over 2 asynchronous memory banks. In order to be
able to use more than 2MB without using more than 2 banks, 2 GPIOs (PF4, PF5) are used to select which 2MB
section of the FLASH is visible in the memory window of the Blackfin processor. This frees up the remaining banks
for the user.
Aside from the first 2 async memory banks, which are used for FLASH addressing, the core module has 2 banks of
the Asynchronous Memory interface available, these can be addressed through the following addresses:
BankStartAddressEndAddressSizeComment
00x20000000 0x200FFFFF 1MB (AddressesFLASH)
10x20100000 0x201FFFFF 1MB (AddressesFLASH)
20x20200000 0x202FFFFF 1MB UsenAMS2
30x20300000 0x203FFFFF 1MB UsenAMS3
Table 2-3: Asynchronous memory banks
These memory banks can be used to access various memory mapped devices or peripherals.
*There are 19 address lines (A1 to A19) (The A0 signal is produced through addressing logic on ABE0 and ABE1), this
allows the entire 1MB to be addressable bytewise.
See section 5.6, Flash Memory Extension PINS.
2.4 SDRAM Memory Map
StartAddr.EndAddr.SizeComment
0x000000000x01FFFFFF 32MByte16BitMemoryinterface
Table 2-4: SDRAM memory map
2.5 Electrical Specification
2.5.1 Supply Voltage
3.3V DC +/-10%
TCM‐BF537v1.x‐HardwareUserManual 13
2.5.2 Supply Voltage Ripple
100mV peak to peak 0-20 MHz
2.5.3 Input Clock Frequency
25MHz
The Blackfin Processor Input Clock frequency is 25 MHz, this frequency is derived from the on-board
crystal/oscillator and drives the Blackfin Processor’s Clock generator. This frequency is also provided on the
connector as pin 78 (CLKBUF).
2.5.4 Real Time Clock Crystal
32.768kHz
2.5.5 Supply Current
Maximum current: 300mA at 3.3V
Typical operating conditions at 25°C environment temperature:
o Processor running at 500MHz, Core Voltage 1.2V, SDRAM 50% bandwidth utilization at 125MHz;
150mA at 3.3V
o Processor running at 250MHz, Core Voltage 0.85V SDRAM 50% bandwidth utilization at 83,3MHz; ;
Ethernet Idle: 85mA at 3.3V
2.6 Environmental Specification
2.6.1 Temperature
Operating at full 500MHz:: -40 to + 85° C
2.6.2 Humidity
Operating: 10% to 90% (non condensing)
3 TCM-BF537C (Connector Version)
3.1 Mechanical Outline
Figure 3-1 shows the top view of the Core Module. All dimensions are given in millimeters!
TCM‐BF537v1.x‐HardwareUserManual 14
Figure 3-1: Mechanical Outline (top view)
Figure 3-2 shows the bottom view of the Core Module (connector version).
Figure 3-2: Mechanical Outline (bottom view)
Figure 3-3 shows a side view of the Core Module with mounted connectors.
TCM‐BF537v1.x‐HardwareUserManual 15
Figure 3-3: Side View with Connectors mounted
The total minimum mounting height including receptacle at the motherboard is 5.8mm.
3.2 Footprint
For the Connector version (2x Hirose 0.6mm pitch) the footprint for the base board looks like that as shown in
Figure 3-4.
For the baseboard the following connectors have to be used.
BaseboardPartManufacturerManufacturerPartNo.
X1,X2HiroseFX8‐60S‐SV
Table 3-1: Baseboard connector types
The Connectors on the TCM-BF537 are of the following type:
PartManufacturerManufacturerPartNo.
X1,X2Hirose3mmheightFX8‐60P‐SV
Table 3-2: Core Module connector types
Figure 3-4: Recommended Footprint for Base Board (top view)
TCM‐BF537v1.x‐HardwareUserManual 16
3.3 Schematic Symbol of Connector Version
Figure 3-5: Schematics Symbol of Connector Version of the TCM-BF537
RSCLK0 / TACLK2
1
DR0PRI / TACLK4
2
TSCLK0 / TACLK1
3
DT0PR I / SPI_SSEL2
4
Vin 3V3
9
Vin 3V3
10
PG0 / PPI1D0
11
PG2 / PPI1D2
12
PG4 / PPI1D4
13
PG6 / PPI1D6
14
PG8 / PPI1D8 / DR 1SEC
15
PG10 / PPI1D10 / R SC LK1
16
PG12 / PPI1D12 / DR 1PRI
17
PG14 / PPI1D14 / TFS 1
18
PPI1S y3 / PF7 / TMR2
19
PPI1S y1 / PF9 / TMR 0
20
MDC
21
PF3 / Rx1 / TMR6 / TAC I6
22
PF 1 / DMAR 1 / TACI1 / Rx0
23
PF11 / SPI_MOSI
24
PF13 / SPI_SCK
25
Bmode0
26
GND
27
TCK
28
TDI
29
TRST
30
EMU
31
TMS
32
TDO
33
Bmode2
34
MDIO
35
Bmode1
36
PF12 / SPI_MISO
37
PF 0 / DMAR 0 / Tx0
38
PF14 / SPI_SS
39
PF 2 / Tx1 / TMR7
40
PPI1Clk / PF15 / TMRCLK
41
PPI1S y2 / PF8 / TMR 1
42
PG15 / PPI1D15 / DT1PRI
43
PG13 / PPI1D13 / TSC LK1
44
PG11 / PPI1D11 / R FS1
45
PG9 / PPI1D9 / DT1S EC
46
PG7 / PPI1D7
47
PG5 / PPI1D5
48
PG3 / PPI1D3
49
PG1 / PPI1D1
50
GND
51
GND
52
DT0SEC / SPI_SSEL7 / CAN_Tx
57
TFS0 / SPI_SSEL3
58
DR0SEC / TACI0 / CAN_Rx
59
RFS0 / TACLK3
60 A1 61
A3 62
A5 63
A7 64
A9 65
A11 66
A13 67
A15 68
A17 69
A19 70
GND 79
AMS3 80
AWE 81
CLKOUT 82
D0 83
D2 84
D4 85
D6 86
D8 87
D10 88
D12 89
D14 90
D15 91
D13 92
D11 93
D9 94
D7 95
D5 96
D3 97
D1 98
RESET 99
AOE 100
ARE 101
AMS2 102
A18 112
A16 113
A14 114
A12 115
A10 116
A8 117
A6 118
A4 119
A2 120
TCM-BF537
PH15 / MIICRS
5
SDA
6
PH 7 / COL
7
PH6 / MIIPHYINT
8PF6 / TMR3 / SPI_SSEL4
54
PF10 / SPI_SSEL1
55
SCL
56
CLKBUF 78
ABE1 71
ABE0 111
ERXER / PH14 104
ERxCLK / PH13 77
ERxDV / PH12 105
ARDY 76
VDD-RTC 103
ERxD3 / PH11 106
ERxD1 / PH9 107
ETxEN / PH4 108
ETxD2 / PH2 109
ETxD0 / PH0 110
ETxD1 / PH1 72
ETxD3 / PH3 73
ERxD0 / PH8 74
ERxD2 / PH10 75
PH5 / MIITxCLK
53
Connectors
SPORT 0
PPI /
SPORT 1
UARTs
SPI
JTAG
CAN
TWI
Powe
r
GPIO
Data
Bus
A
dd
r
.
Bus
Control
Signals
Ethernet /
GPIO
Connecto
r
Symbol
TCM‐BF537v1.x‐HardwareUserManual 17
3.4 Connectors PIN Assignment
Please mind the mounted pull up and pull down resistors on the Core Module. See the third column of Table 3-3
and Table 3-4.
3.4.1 Connector X1 – (1-60)
PinNo.SignalSignalType.
1 RSCLK0 / TACLK2 I/O
2 DR0PRI /
T
ACLK4 O
3
T
SCLK0 / TACLK1 I/O
4 DT0PRI / SPI_SSEL2 I
5 PH15 / MIICRS I/O
6 SDA I/O
7 PH7 / COL I/O
8 PH6 / MIIPHYIN
T
I/O
9 Vin 3.3 V PWR
10 Vin 3.3V PWR
11 PG0 / PPI1D0 I/O
12 PG2 / PPI1D2 I/O
13 PG4 / PPI1D4 I/O
14 PG6 / PPI1D6 I/O
15 PG8 / PPI1D8 / DR1SEC I/O
16 PG10 / PPI1D10 / RSCLK1 I/O
17 PG12 / PPI1D12 / DR1PRI I/O
18 PG14 / PPI1D14 / TFS1 I/O
19 PPI1SY3/PF7/TMR2 I/O
20 PPI1SY1/PF8/TMR1 I/O
21 MDC I/O
22 PF3 / Rx1 / TMR6 / TACI6 I/O
23 PF1 / DMAR1 / TACI1 / Rx0 I/O
24 PF11 / SPI_MOSI I/O
25 PF13 / SPI_SC
K
I/O
26 BMODE0 I – 10k pull down
27 GND PWR
28
T
C
K
I – 10k pull up
29
DI I – 10k pull up
30 TRST
I – 4k7 pull down
31 EMU
O
32
T
MS I – 10k pull up
33
T
DO O
34 BMODE2 I – 10k pull down
35 MDIO I/O – 10k pull up
36 BMODE1 I – 10k pull down
37 PF12 / SPI_MISO I/O
38 PF0 / DMAR0 / Tx0 I/O
39 PF14 / SPI_SS I/O
40 PF2 / Tx1 / TMR7 I/O
41 PPI1Clk / PF15 / TMRCL
K
I/O
TCM‐BF537v1.x‐HardwareUserManual 18
42 PPI1Sy2 / PF8 / TMR1 I/O
43 PG15 / PPI1D15 / DT1PRI I/O
44 PG13 / PPI1D13 / TSCLK1 I/O
45 PG11 / PPI1D11 / RFS1 I/O
46 PG9 / PPI1D9 / D
T
1SEC I/O
47 PG7 / PPI1D7 I/O
48 PG5 / PPI1D5 I/O
49 PG3 / PPI1D3 I/O
50 PG1 / PPI1D1 I/O
51 GND PWR
52 GND PWR
53 PH5 / MIITxCL
K
I/O
54 PF6 / TMR3 / SPI_SSEL4 I/O
55 PF10 / SPI_SSEL1 I
56 SCL I/O
57 DT0SEC / CANTX / SPI_SSEL7 O
58
T
FS0
/
SPI_SSEL3 I/O
59 DR0SEC / TACI0 / CANRX I
60 RFS0 / TACLK3 I/O
Table 3-3: Connector X1 pin assignment
Note: The processor pins PF4 and PF5 are used for flash addressing on the Core Module. They are not available on
the connectors.
Signal names correspond to those of the Blackfin processor unless otherwise stated.
3.4.2 Connector X2 – (61-120)
PinNo. SignalSignalType.
61 A1 O
62 A3 O
63 A5 O
64 A7 O
65 A9 O
66 A11 O
67 A13 O
68 A15 O
69 A17 O
70 A19 O
71 ABE1
/ SDQM1 O
72 PH1/ETxD1 I/O
73 PH3/ETxD3 I/O
74 PH8/ERxD0 I/O
75 PH10/ERxD2 I/O
76 ADR
Y
I – 10k pull up
77 PH13/ERxCL
K
I/O
78 CLKBUF O
79 GND PWR
TCM‐BF537v1.x‐HardwareUserManual 19
80 AMS3
O
81 AWE
O
82 CLKOUT (SCLK) I
83 D0 I/O
84 D2 I/O
85 D4 I/O
86 D6 I/O
87 D8 I/O
88 D10 I/O
89 D12 I/O
90 D14 I/O
91 D15 I/O
92 D13 I/O
93 D11 I/O
94 D9 I/O
95 D7 I/O
96 D5 I/O
97 D3 I/O
98 D1 I/O
99 Reset
I - see chapter 0
100 AOE
O
101 ARE
O
102 AMS2
O
103 VDD-RTC PWR
104 PH14/ERXER I/O
105 PH12/ERxDV I/O
106 PH11/ERxD3 PWR
107 PH9/ERxD1 I/O
108 PH4/ETxEN I/O
109 PH2/ETxD2 I/O
110 PH0/ETxD0 I/O
111 ABE0
/ SDQM0 O
112 A18 O
113 A16 O
114 A14 O
115 A12 O
116 A10 O
117 A8 O
118 A6 O
119 A4 O
120 A2 O
Table 3-4: Connector X2 pin assignment
Signal names correspond to those of the Blackfin processor unless otherwise stated.
TCM‐BF537v1.x‐HardwareUserManual 20
4 TCM-BF537B (Border Pad and BGA Versions)
4.1 Mechanical Outline
The two figures below shows the top and bottom view of the Core Module. All dimensions are given in millimeters!
Figure 4-1: Mechanical Outline (top view)
Figure 4-2: Mechanical Outline (bottom view)
TCM‐BF537v1.x‐HardwareUserManual 21
Figure 4-3 shows a side view of the Core Module with border pads.
Figure 4-3: Side View of the Border Pads
The total minimum mounting height of the Border Pad version is only 3.1mm!
4.2 Footprint of Border Pad Baseboard
Figure 4-4 shows the pin assignment of the Border Pad Version. The pin Numbering is clockwise ascending. The Pins
No. 10 and 48 are not present.
Figure 4-4: Border Pad Footprint for the Base Board (top view)
Note: Conducting paths and vias within the footprint must be solder resistant. Do not place any component
within the footprint either.
TCM‐BF537v1.x‐HardwareUserManual 22
4.3 Schematic Symbol of Border Pad Version
RSCLK0 / TACLK2
6
DR0PRI / TACLK4
8
TSCLK0 / TACLK1
12
DT0PRI / SPI_SSEL2
14
Vin 3V3
28
Vin 3V3
49
PG0 / PPI1D0
42
PG2 / PPI1D2
44
PG4 / PPI1D4
46
PG6 / PPI1D6
50
PG8 / PPI1D8 / DR1SEC
52
PG10 / P PI1D10 / RSCLK1
54
PG12 / P PI1D12 / DR1P RI
56
PG14 / PPI1D14 / TFS1
58
PPI1Sy3 / PF7 / TMR2
39
PPI1Sy1 / PF9 / TMR0
41
PF3 / Rx1 / T MR6 / TACI6
31
PF1 / DMAR1 / TACI1 / Rx0
27
PF11 / SPI_MOSI
34
PF13 / S PI_SCK
36
Bmode0
19
TCK
20
TDI
22
TRST
24
EMU
25
TMS
23
TDO
21
Bmode2
17
Bmode1
18
PF12 / SPI_MISO
35
PF0 / DMAR0 / Tx0
26
PF14 / S PI_SS
37
PF2 / Tx1 / TMR7
30
PPI1Clk / PF15 / TMRCLK
38
PPI1Sy2 / PF8 / TMR1
40
PG15 / P PI1D15 / DT1PRI
59
PG13 / P PI1D13 / TS CLK1
57
PG11 / PPI1D11 / RFS1
55
PG9 / PPI1D9 / DT1SEC
53
PG7 / PPI1D7
51
PG5 / PPI1D5
47
PG3 / PPI1D3
45
PG1 / PPI1D1
43
DT0SEC / SP I_ SSEL7 / C AN_Tx
13
T FS0 / SPI_SSEL3
11
DR0SEC / TACI0 / CAN_Rx
7
RFS0 / TACLK3
5
RESET 15
TCM-BF537
SDA
3
PF6 / TMR3 / SPI_SSEL4
32
PF10 / S PI_SSEL1
33
SCL
4
CLKBUF 1
VDD-RTC 9
GND
67
GND
29
Borderpads
MDC
2
MDIO
16
PH15 / MIICRS
76
PH6 / MIIPHYINT
66
PH5 / MIITxCLK
65
ER XER / PH14 75
ERxCLK / PH13 74
ERxDV / PH12 73
ERxD3 / PH11 72
ERxD1 / PH9 70
ETx EN / PH4 64
ET xD2 / PH2 62
ET xD0 / PH0 60
ET xD1 / PH1 61
ET xD3 / PH3 63
ERxD0 / PH8 69
ERxD2 / PH10 71
PH7 / COL
68
U?
T-CM-BF537
Figure 4-5: Schematics of the Border Pad Version of the TCM-BF537BP
TCM‐BF537v1.x‐HardwareUserManual 23
4.4 Border Pad Pin Assignment
PinNo.SignalType
1CLKBUFO
2MDCO
3SDAI/O
4SCLI/O
5RFS0/TACLK3 I/O
6RSCLK0/TACLK2 I/O
7DR0SEC/TACI0 /CAN_Rx I
8DR0PRI/TACLK4 I
9VDD‐RTCPWR
10notavailable
11TFS0/SPI_SSEL3 I/O
12TSCLK0/TACLK1 I/O
13DT0SEC/SPI_SSEL7/CAN_Tx O
14DT0PRI/SPI_SSEL2 O
15RESETI
–
seechapter0
16MDIOI/O
–
10kpullup
17BMODE2I
–
10kpulldown
18BMODE1I
–
10kpulldown
19BMODE0I
–
10kpulldown
20TCKI
–
10kpullup
21TDOO
22TDII
–
10kpullup
23TMSI
–
10kpullup
24TRSTI
–
4k7pulldown
25EMUO
26PF0/DMAR0 /Tx0 I/O
27PF1/DMAR1 /TACI1 /Rx0 I/O
28Vin3.3VPWR
29GNDPWR
30PF2/Tx1/TMR7 I/O
31PF3/Rx1/TMR6 /TACI6 I/O
32PF6/TMR3 /SPI_SSEL4 I/O
33PF10/SPI_SSEL1 I/O
34PF11/SPI_MOSI I/O
35PF12/SPI_MISO I/O
36PF13/SPI_SCK I/O
37PF14/SPI_SS I/O
38PPI1Clk/PF15 /TMRCLK I/O
39PPI1Sy3/PF7 /TMR2 I/O
40PPI1Sy2/PF8 /TMR1 I/O
41PPI1Sy1/PF9 /TMR0 I/O
42PG0/PPI1D0 I/O
43PG1/PPI1D1 I/O
44PG2/PPI1D2 I/O
45PG3/PPI1D3 I/O
TCM‐BF537v1.x‐HardwareUserManual 24
46PG4/PPI1D4 I/O
47PG5/PPI1D5 I/O
48notpresent ‐
49Vin3.3VPWR
50PG6/PPI1D6 I/O
51PG7/PPI1D7 I/O
52PG8/PPI1D8 /DR1SEC I/O
53PG9/PPI1D9 /DT1SEC I/O
54PG10/PPI1D10 /RSCLK1 I/O
55PG11/PPI1D11 /RFS1 I/O
56PG12/PPI1D12 /DR1PRI I/O
57PG13/PPI1D13 /TSCLK1 I/O
58PG14/PPI1D14 /TFS1 I/O
59PG15/PPI1D15 /DT1PRI I/O
60PH0/ETxD0 I/O
61PH1/ETxD1 I/O
62PH2/ETxD2 I/O
63PH3/ETxD3 I/O
64PH4/ETxEN I/O
65PH5/MIITxCLK I/O
66PH6/MIIPHYINT I/O
67GNDPWR
68PH7/COLI/O
69PH8/ERxD0 I/O
70PH9/ERxD1 I/O
71PH10/ERxD2 I/O
72PH11/ERxD3 I/O
73PH12/ERxDV I/O
74PH13/ERxCLK I/O
75PH14/ERXER I/O
76PH15/MIICRS I/O
Table 4-1: Border pin assignment
Signal names correspond to those of the Blackfin processor unless otherwise stated.
Not: Please mind the mounted pull up and pull down resistors on the Core Module. See the third column of Table
4-1.
TCM‐BF537v1.x‐HardwareUserManual 25
4.5 BGA PAD Numbering
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
D1 D2 D3 D15 D16 D17
E1 E2 E3 E15 E16 E17
F1 F2 F3 F15 F16 F17
G1 G2 G3 G15 G16 G17
H1 H2 H3 H15 H16 H17
J1 J2 J3 J15 J16 J17
K1 K2 K3 K15 K16 K17
L1 L2 L3 L15 L16 L17
M1 M2 M3 M15 M16 M17
N1 N2 N3 N15 N16 N17
P1 P2 P3 P15 P16 P17
R1 R2 R3 R15 R16 R17
T1 T2 T3
U1 U2 U3
R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14
T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
Figure 4-6: BGA Pad Numbering (top view)
4.6 Footprint of BGA Baseboard
Figure 4-7 shows the top view of the BGA footprint for your base board.
Figure 4-7: Recommended BGA Footprint for the Base Board (top view)
TCM‐BF537v1.x‐HardwareUserManual 26
4.7 Schematic Symbol of BGA Version
RSCL K0 / TACLK2
F3
DR0PRI / TACLK4
F1
TSCLK 0 / TA CL K1
E2
DT0PRI / SPI_SSEL2
D3
PG0 / PPI1D0
U9
PG2 / PPI1D2
U8
PG4 / PPI1D4
U7
PG6 / PPI1D6
U6
PG8 / PPI1D8 / DR1SEC
U5
PG10 / PPI1D1 0 / R SCL K 1
U4
PG12 / PPI1D1 2 / DR 1 PR I
U3
PG14 / PPI1D1 4 / TFS 1
U2
PPI1S y3 / PF7 / TMR 2
T12
PPI1S y1 / PF9 / TMR 0
T13
MDC
H1
PF3 / Rx 1 / TMR6 / TACI6
T17
PF1 / DMAR1 / TACI1 / Rx0
R16
PF11 / SPI_MOSI
U15
PF13 / SPI_SCK
U14
Bmode0
L16
TCK
M16
TDI
N16
TRST
P16
EMU
P17
TMS
N17
TDO
M17
Bmode2
L17
MDIO
H2
Bmode1
L15
PF12 / SPI_MISO
T15
PF0 / DMAR0 / Tx 0
R17
PF14 / SPI_SS
T14
PF2 / Tx 1 / TMR7
U17
PPI1Cl k / PF15 / TMR C L K
U13
PPI1S y2 / PF8 / TMR 1
U12
PG15 / PPI1D1 5 / DT1PR I
U1
PG13 / PPI1D1 3 / TS C L K 1
T3
PG11 / PPI1D1 1 / R FS 1
T4
PG9 / PPI1D9 / DT1SEC
T5
PG7 / PPI1D7
T6
PG5 / PPI1D5
T7
PG3 / PPI1D3
T8
PG1 / PPI1D1
T9
DT0S E C / S PI_S S E L 7 / C AN_Tx
E1
TFS0 / SPI_SSEL3
E3
DR0SE C / TACI0 / CAN_Rx
F2
RFS0 / TACLK3
G1 A1 A7
A3 C7
A5 B8
A7 B9
A9 A10
A11 C10
A13 C11
A15 B12
A17 A13
A19 C13
GND J3
AMS3 A3
AWE A5
MEMCLK A2
D0 A17
D2 C16
D4 D16
D6 E16
D8 F16
D10 G16
D12 H16
D14 J16
D15 J17
D13 H17
D11 G17
D9 F17
D7 E17
D5 D17
D3 C17
D1 B17
RESET D1
AOE B4
ARE B5
AMS2 B3
A18 B13
A16 C12
A14 A12
A12 A11
A10 B10
A8 C9
A6 C8
A4 A8
A2 B7
TCM-BF537
PH15 / MIICRS
J1
SDA
G3
PH7 / CO L
N1
PH6 / MIIPHYINT
N2 PF6 / TMR3 / SPI_SSEL4
U16
PF10 / SPI_SSEL1
T16
SCL
G2
CLKBUF A1
ABE1 A6
ABE0 B6
ERXER / PH14 J2
ERxCLK / PH13 K1
ERxDV / PH12 K2
ARDY A4
VDD-RTC H3
ERxD3 / PH11 L1
ERxD1 / PH9 M1
ETxEN / PH4 P2
ETxD2 / PH2 R2
ETxD0 / PH0 T2
ETxD1 / PH1 T1
ETxD3 / PH3 R1
ERxD0 / PH8 M2
ERxD2 / PH10 L2
PH5 / MIITxCLK
P1
BGA
Vcc R10
Vcc R11
Vcc T10
Vcc T11
Vcc U10
Vcc U11
GND
R7
GND
R8
GND
R9
GND
R12
GND
R13
GND
R14
GND
C3
GND
C6
GND
A9
GND
B11
GND
C14
GND
C15
GND
A16
GND
B16
GND
D15
GND
G15
GND
K15
GND
N15
BR C1
BGH B2
BG C2
WP_Flash B1
NMI D2
FA22 H15
FA23 J15
FA24 K16
Figure 4-8: Schematics Symbol of the BGA Version of the TCM-BF537BGA
TCM‐BF537v1.x‐HardwareUserManual 27
4.8 BGA Pin Assignment
PinNo. SignalSignalType.
A1CLKBUFO
A2MEMCLKO
A3AMS3O
A4ARDYI
–
10kpullup
A5AWE
O
A6ABE1
O
A7A1O
A8A4O
A9GNDPWR
A10A9O
A11A12O
A12A14O
A13A17O
A14n.c.‐
A15n.c. ‐
A16GNDPWR
A17D0I/O
B1WP_Flash
I
–
10kpullup
B2BGH
O
B3AMS2
O
B4AOE
O
B5ARE
O
B6ABE0
O
B7A2O
B8A5O
B9A7O
B10A10O
B11GNDPWR
B12A15O
B13A18O
B14n.c. ‐
B15n.c.‐
B16GNDPWR
B17D1I/O
C1BR
I
–
10kpullup
C2BG
O
C3GNDPWR
C4n.c.‐
C5n.c. ‐
C6GNDPWR
C7A3O
C8A6O
C9A8O
C10A11O
C11A13O
TCM‐BF537v1.x‐HardwareUserManual 28
C12A16O
C13A19O
C14GNDPWR
C15GNDPWR
C16D2I/O
C17343I/OI/O
D1Reset
I
–
seechapter0
D2NMI
I
–
10kpullup
D3DT0PRI/SPI_SSEL2 O
D15GNDPWR
D16D4I/O
D17D5I/O
E1DT0SEC/CANTX/SPI_SSEL7 O
E2TSCLK0/TACLK1 I/O
E3TFS0/SPI_SSEL3 I/O
E15n.c. ‐
E16D6I/O
E17D7I/O
F1DR0PRI/TACLK4 I
F2DR0SEC/TACI0/CANRX I
F3RSCLK0/TACLK2 I/O
F15n.c. ‐
F16D8I/O
F17D9I/O
G1RFS0/TACLK3 I/O
G2SCLI/O
G3SDAI/O
G15GNDPWR
G16D10I/O
G17D11I/O
H1MDCI/O
H2MDIOI/O
–
10kpullup
H3VDD‐RTCPWR
H15FA22I
–
10kpulldown
H16D12I/O
H17D13I/O
J1PH15/MIICRS I/O
J2PH14/ERXER I/O
J3GNDPWR
J15FA23I
–
10kpulldown
J16D14I/O
J17D15I/O
K1PH13/ERxCLK I/O
K2PH12/ERxDV I/O
K3n.c.‐
K15GNDPWR
K16FA24I
–
10kpulldown
TCM‐BF537v1.x‐HardwareUserManual 29
K17n.c. ‐
L1PH11/ERxD3 PWR
L2PH10/ERxD2 I/O
L3n.c.‐
L15BMODE1I
–
10kpulldown
L16BMODE0I
–
10kpulldown
L17BMODE2I
–
10kpulldown
M1PH9/ERxD1 I/O
M2PH8/ERxD0 I/O
M3n.c.‐
M15n.c. ‐
M16TCKI
–
10kpullup
M17TDOO
N1PH7/COLI/O
N2PH6/MIIPHYINT I/O
N3n.c.‐
N15GNDPWR
N16TDII
–
10kpullup
N17TMSI
–
10kpullup
P1PH5/MIITxCLK I/O
P2PH4/ETxEN I/O
P3n.c.‐
P15n.c. ‐
P16TRST
I
–
4k7pulldown
P17EMUO
R1PH3/ETxD3 I/O
R2PH2/ETxD2 I/O
R3n.c.‐
R4n.c. ‐
R5n.c.‐
R6n.c. ‐
R7GNDPWR
R8GNDPWR
R9GNDPWR
R10VccPWR
R11VccPWR
R12GNDPWR
R13GNDPWR
R14GNDPWR
R15n.c.‐
R16PF1/DMAR1/TACI1/Rx0 I/O
R17PF0/DMAR0/Tx0 I/O
T1PH1/ETxD1 I/O
T2PH0/ETxD0 I/O
T3PG13/PPI1D13/TSCLK1 I/O
T4PG11/PPI1D11/RFS1 I/O
T5PG9/PPI1D9/DT1SEC I/O
TCM‐BF537v1.x‐HardwareUserManual 30
T6PG7/PPI1D7 I/O
T7PG5/PPI1D5 I/O
T8PG3/PPI1D3 I/O
T9PG1/PPI1D1 I/O
T10VccPWR
T11VccPWR
T12PF7/PPI1SY3/TMR2 I/O
T13PF9/PPI1SY1/TMR0 I/O
T14PF14/SPI_SS I/O
T15PF12/SPI_MISO I/O
T16PF10/SPI_SSEL1 I/O
T17PF3/Rx1/TMR6/TACI6 I/O
U1PG15/PPI1D15/DT1PRI I/O
U2PG14/PPI1D14/TFS1 I/O
U3PG12/PPI1D12/DR1PRI I/O
U4PG10/PPI1D10/RSCLK1 I/O
U5PG8/PPI1D8/DR1SEC I/O
U6PG6/PPI1D6I/O
U7PG4/PPI1D4I/O
U8PG2/PPI1D2I/O
U9PG0/PPI1D0 I/O
U10VccI/O
U11VccI/O
U12PF8/PPI1_SY2/TMR1 I/O
U13PF15/PPI1CLK/TMRCLK I/O
U14PF13/SPI_SCLK I/O
U15PF11/SPI_MOSI I/O
U16PF6/TMR3/SPI_SSEL4 I/O
U17PF2/Tx1/TMR7 I/O
Table 4-2: BGA Version Pin Assignment
Signal names correspond to those of the Blackfin processor unless otherwise stated.
Note: Please mind the mounted pull up and pull down resistors on the Core Module. See the third column of Table
4-2.
TCM‐BF537v1.x‐HardwareUserManual 31
4.9 Reset circuit
The reset of the flash and the processor are connected to a power monitoring IC. The output can be used as power
on reset for external devices, see Figure 4-9.
Figure 4-9: Schematic of reset circuit on the Core Module
4.10 Flash Memory Extension PINS
4.10.1 PINS FA20 to FA24
Flashpin Blackfinpin
FA20 PF4
FA21 PF5
FA22 PG13
FA23 PG14
FA24 PG15
Table 4-3: Pins FA20 to FA24
All pins are pulled down by default.
The signals FA20 and FA21 are used to address the (first) 8MB of Flash memory. These signals are connected directly
with the Blackfin pins PF4 (FA20) and PF5 (FA21) (see chapter 2.3) so you cannot use FA20 or FA21 for your own
purposes! The signals FA22-FA24 can be used to address up to 64MByte of Flash memory (if installed on the Core
Module). The signals FA22-FA23 are connected through a 0R resistor array with the Blackfin signals PG13 (FA22),
PG14 (FA23) and PG15 (FA24). If you need the signals PG13-PG15 for your own purposes (for example to use the
SPORT1 interface) AND you want to address up to 64MByte Flash memory, so you can remove the 0R resistor array
and use other GPIOs for FA22-FA24 (in this case you must connect these GPIOs externally to FA22-F24). Please
contact Bluetechnix Support for further informations.
4.10.2 WP_FLASH
Is pulled high by default so flash is unprotected. To write protect the flash connect this pin to GND.
3.3V
RESET
470R
R12
GND
1
VDD
3
RESET 2
TCM809SENB713
U5
RESET of ADSP-BF5xx
GND
99
RESET of Flash
CoreModule
Exte rnal
TCM‐BF537v1.x‐HardwareUserManual 32
5 Application Example Schematics
In the following two examples connection of a Physical Ethernet chip and a USB 2.0 chip to the Core Module are
provided.
5.1 Schematic Example for Connecting a Physical Ethernet Chip
Since the ADSP-BF537 Blackfin Chip from Analog Devices already has Ethernet functionality only a physical Ethernet
chip needs to be connected to the TCM-BF537 Core Module in order to make use of this feature.
Figure 5-1: Configuration with Physical Chip
Designato
r
V
alue Part Numbe
r
Description Quantity
C4, C5, C6 10u C0805C106K9PAC Capacitor non-polarized 3
C7, C8, C9 100n 2238 246 19876 Capacitor non-polarized 3
L1, L2 600Z 74279265 Ferrite 2
R2 10R MC 0.063W 0603 1% 10R Resistor 1
R3, R4, R8, R9 49R9 MC 0.063W 0603 1% 49R9 Resistor 4
R5, R6, R11 27R MC 0.063W 0603 1% 27R Resistor 3
R7 6k49 MC 0.063W 0603 1% 6K49 Resistor 1
R10, R12 220R MC 0.063W 0603 1% 220R Resistor 2
R13 2k43 MULTICOMP Resistor 1
U2 KSZ8721BLI-LQFP48L 10/100BASE Physical Layer
Transceiver
1
V1, V2 USBLC6-2P6
T
SV-Diode for USB 2.0 2
X3 RJLBC-060TC1 RJ45-Connector with LEDs 1
Table 5-1: Bill of Material of Sample Schematic
MDC
MDIO
ETxD0
ETxD1
ETxD2
ETxD3
ETxEN
ERxD0
ERxD1
ERxD2
ERxD3
ERxDV
ERxCLK
ERxER
MII_CRS
MII_TxCLK
MII_PHYINT
COL
nRESET_ETH1
2.5V
2.5V_PLL
LED_S PEE D
LED_A CT
Rx+
Rx‐
Tx‐
Tx+
2.5V_VA
2.5V_VA
2.5V_VA
10u
C4
10u
C5
10u
C6
FXSD/FXEN 34
REXT 37
GND
44
GND
8
Vdd 7
PD
30
Vdd_CORE 13
GND
12
SPEED100/FEF 27
COLLISION/NWAYEN 29
VddPLL 47
ACTIVITY/TEST 26
FDUPLEX 28
GND
23
XTAL2 45
CLKIN/XTAL1 46
GND
35
RESET
48
MDIO
1MDC
2
GND
43
RxD3/PHYAD
3
RxD2/PHYAD2
4
RxD1/PHYAD3
5
RxD0/PHYAD4
6
Rx_DV/CRSDV/PCS_LBPK
9
Rx_CLK
10
Rx_ER/ISO
11
GND
36
Tx_ER/TXD4
14 Tx_CLK/REFCLK
15 Tx_EN
16
GND
39
TxD0
17 TxD1
18
Vdd 24
TxD2
19 TxD3
20
INT/PHYAD0
25
COL/RMII
21 CRS/RMII_BTB
22
Tx- 40
Tx+ 41
VddRX 31
Rx- 32
Rx+ 33
VddRCV 38
VddTX 42
U2 KS8721
49R9
R3
49R9
R4
49R9
R9 49R9
R8
ERxD[3..0]
ETxD[3..0]
xRx+
xRx‐
xTx‐
xTx+
27R
R6 27R
R5
2.5V_VA
220R
R10
220R
R12
3V3
CLKBUF
GND
GND
ETxD[3..0]
ERxD[3..0]
MII_TxCLK
ERxDV
ERxCLK
ERxER
MII_CRS
COL
MDIO
MII_PHYINT
MDC
nRESET_ETH1
CLKBUF
ETxEN
100n
C9
GND
100n
C8
GND
GND
GND
6k49
R7
3V3
3V3
3V3
nPD
nPD
3V3
27R
R11
3
Td-
2
Rd-
8
Td+
1
1413
Rd+
7
9
11
10
12
RJ45 1:1LE D
X3
1
3
25
4
6
D‐TVS‐USB2.0‐>InvNr:10549
V1
1
3
2 5
4
6
D‐TVS‐USB2.0‐>InvNr:10549
V2
GND
GND2.5V_VA
2.5V_VA
GND
100n
C7
10R
R2
2k43
R13
600Z L1
600Z
L2
TCM‐BF537v1.x‐HardwareUserManual 33
5.2 Schematic Example for Connecting a USB 2.0 Chip
The following example shows how to connect a USB 2.0 chip to the TCM-BF537 core Module.
Figure 5-2: Configuration with USB 2.0 Chip
DesignatorValuePartNumber Description Quantity
C1u, C2u 12p 2238 867 15129 Capacitor non-polarized 2
C3u, C4u, C5u, C9u, C11u 10n 2238 916 15636 Capacitor non-polarized 5
C6u, C10u, C12u 100n 2238 246 19876 Capacitor non-polarized 3
C7u, C8u 10u C0805C106K9PAC Capacitor non-polarized 2
L1u, L2u 220R 74279263 Ferrite 2
R1u, R3u, R11u, R12u 10k MC 0.063W 0603 1% 10
K
Resistor 4
R2u 10k 2350 025 11003 4-Resistor Array 1
R4u 1k MC 0.063W 0603 1% 1k Resistor 1
R5u, R6u 39R MC 0.0654W 0603 1% 39R Resistor 2
R7u 2k43 MULTICOMP Resistor 1
R8u 1k5 MC 0.063W 0603 1% 1K5 Resistor 1
R9u 47k MC 0.063W 0603 1% 47k Resistor 1
R10u 1M MC 0.063W 0603 1% 1M Resistor 1
U1u NET2272REV1A-LF USB 2.0 Peripheral
Controller TQPF
1
V1u CDS3C05GTA 1
X1u 2411 01 USB-Device Normal 1
Y1u Q 30.0-JXS32-12-10/20 Crystal Oscillator 1
Table 5-2: Bill of Material of Sample Schematic
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A1
A2
A3
A4
USBD+
USBD‐
VBUS
USB‐nIRQ
ALE
10k
1
2
3
4
8
7
6
5
R17
2k43
R22
nARE
USB-nAMS
USB-nRESET
nAWE
A[7..0]
D[15..0]
47k
R24
39R
R20
39R
R21
1k5
R23
GND
GND
3V3
GND
3V3
GND
3V3
GND
220Z
L4
220Z
L3
12p
C10
12p
C11
GND
A0
USB-nIRQ
2V5 2V5A
VCC
1
USBD-
2
USBD+
3
GND
4
5
6
X4
USB‐B
GND
V4
GND
10n
C12
1M
R25
A[7..0]
USB‐nRESET
D[15..0]
10u
C17
10n
C14
10n
C15
10n
C19
10n
C23
100n
C20
100n
C21
100n
C16
10u
C18
GNDGND
3V3 2V5 2V5A
NET2272REV 1A‐LF
LD0 19
COM
16
RSDM 9
GND
4
RSDP 5
GND
10
VDDC 1
DREQ 62
LD1 20
AVSS
12
DM 8
VDD33 7
DP 6
AVSS
14
IOW
60
VBUS
64
LD3 22
LD2 21
AVDD 15
PVDD 11
VDD25 3
RESET
58
CS
61
IOR
59
XOUT
26
VSSC
56
LD4 23
RREF
13
RPU 2
IRQ 63
VDDIO 27
VSSC
24
XIN
25
LA3
29
VDDIO 55
TEST
18
TMC2
17 LCLKO 57
EOT
52
ALE
53
LA4
28
LA2
30
LD7 37
LD9 39
VDDIO 42
LD12 45
DACK
51
VSSIO
33
LA0
32
LA1
31
LD6 36
LD8 38
TRST
40
LD10 43
DMARD
50
LD15 49
VSSIO
54
LD5 35
DMAWR
34
VSSIO
41
LD11 44
LD13 46
LD14 47
VDDC 48
U3
3V3
GND GND
2V5
XC6204‐2V5
Vin
1Vout 5
GND 2
CE
3
U4
1u
C22
3V3
1 3
4
2
30MHz
Y1
GND 1
3
2 5
4
6
D‐TVS‐USB2.0‐>InvNr:10549
V3
3V3GND
100n
C13
GND
3V3
1k5
R19
GND
10k
1
2
3
4
8
7
6
5
R14
DREQ
DREQ
TCM‐BF537v1.x‐HardwareUserManual 34
6 Software Support
6.1 BLACKSheep
The Core Module is delivered with a pre-flashed basic version of the BLACKSheep VDK multithreaded framework. It
contains a boot-loader for flashing the Core Module via the serial port.
Please consult the software development documents.
6.2 uClinux
The Core Module is fully supported by the open source platform at http://blackfin.uclinux.org. Since the Core
Modules are pre-flashed with BLACKSheep you have to flash uBoot first. To flash uBoot you can use the
BLACKSheep boot-loader.
To use the Ethernet functionality of the TCM-BF537 Core Modules you need the EXT-BF5xx-ETH-USB Blackfin
Extension Board.
7 Anomalies
For the latest information regarding anomalies for this product, please consult the product home page:
http://www.bluetechnix.com/goto/tcm-bf537
DateRevisionsDescription
24.10.2007V1.1
V1.2
V1.3
RTC‐Problem:TheClockaccuracyoftheRTCismuchlessthanspecifiedbythe
crystal(20ppm).Duetolayoutissuesthemeasuredinaccuracyisabout7‐9sec.
/Hour.TheRTCBugaffectsboththeBGAandBorderPadVersions.Foraccurate
timemeasurementspleaseusethemaincrystaloranexternalRTC.
Table 8-7-1: Anomalies
TCM‐BF537v1.x‐HardwareUserManual 35
8 Production Report
For the latest information regarding the productions for this product, please consult the product home page:
https://support.bluetechnix.at/wiki/Revision_Report_TCM-BF537x
TCM‐BF537v1.x‐HardwareUserManual 36
9 Product Changes
For the latest product change information please consult the product web-page at:
http://www.bluetechnix.com/goto/tcm-bf537
Version Changes
V1.1.X Border Pad and BGA Versions added with 64MB flash addressing option,
28mmx28mm outline
V1.2.X Component placement changed (connector version)
V1.3.X Mount option for 64MB flash addressing (connector version)
V1.4.X Correction of RTC inaccurateness
10 Document Revision History
Version Date Document Revision
20 2010-11-30 Changed product picture
19 2010-08-31 Complete document revision
18 2010-02-03 Redesign Manual
17 2009-05-25
T
able 4.2 L14 -> J16
Symbol BGA updated
16 2009-03-19
T
able 8.2 new version added
15 2009-01-19 Chapter 5-1 new schematic, new part list
14 2008-12-02 Chapter 4.9 added
Pull up/down information added
Correction of the BGA-Pin assignment table
13 2008-10-21 Pin 48 not available instead of 49
12 2008-09-05 Footprints and mechanical drawings updated
11 2008-08-11 English checked for spelling, grammar and clarity
10 2008-08-06 Fixed memory map
9 2008 03 27 Production Report Added
8 2007 24 10 RTC Problem in the Anomaly List added
7 2007 06 04 Unlock flash hint, Document Revision History Table
6 2007 04 17 BP and BGA symbols corrected; Rx1 and Tx1 were mixed up
5 2007 04 04 Corrections of the description of the BP and BGA versions.
4 2007 01 08 Corrected Typo in page 7 Table 2-2: PF5 one time instead of two times PF4
3 2006 10 02 Release V1.1 of TCM Boards
Main updates: Separate Connector, Border and BGA pad version
Border Pads: 76 Border pads without Data and Address bus pins
Connector Version: As in version V1.0
BGA Version: Additional Processor pins, added Flash addressing flexibility
Removed limited address range, all 8MB addressable
2 2006 04 26 Updated anomaly list: only 4MB addressable.
2 2006 04 26 Updated document: Connector symbol, fixed Bug naming of pin 22 and pin
40 (connector version) Rx and Tx was flipped.
1 2006 03 07 First release V1.0 of the Document
Table 10-1: Revision History
TCM‐BF537v1.x‐HardwareUserManual 37
A List of Figures and Tables
Figures
Figure 1-1: Main Components of the TCM-BF537 Core Module ........................................................................................................ 8
Figure 2-1: Detailed Block Diagram ........................................................................................................................................................... 10
Figure 3-1: Mechanical Outline (top view) .............................................................................................................................................. 14
Figure 3-2: Mechanical Outline (bottom view) ...................................................................................................................................... 14
Figure 3-3: Side View with Connectors mounted ................................................................................................................................. 15
Figure 3-4: Recommended Footprint for Base Board (top view) ..................................................................................................... 15
Figure 3-5: Schematics Symbol of Connector Version of the TCM-BF537 .................................................................................... 16
Figure 4-1: Mechanical Outline (top view) .............................................................................................................................................. 20
Figure 4-2: Mechanical Outline (bottom view) ..................................................................................................................................... 20
Figure 4-3: Side View of the Border Pads ................................................................................................................................................. 21
Figure 4-4: Border Pad Footprint for the Base Board (top view) ..................................................................................................... 21
Figure 4-5: Schematics of the Border Pad Version of the TCM-BF537BP ...................................................................................... 22
Figure 4-6: BGA Pad Numbering (top view) ........................................................................................................................................... 25
Figure 4-7: Recommended BGA Footprint for the Base Board (top view) .................................................................................... 25
Figure 4-8: Schematics Symbol of the BGA Version of the TCM-BF537BGA ................................................................................ 26
Figure 4-9: Schematic of reset circuit on the Core Module ............................................................................................................... 31
Figure 5-1: Configuration with Physical Chip ......................................................................................................................................... 32
Figure 5-2: Configuration with USB 2.0 Chip .......................................................................................................................................... 33
Tables
Table 2-1: Boot Mode TCM-BF537 .............................................................................................................................................................. 11
Table 2-2: Memory Map ................................................................................................................................................................................. 12
Table 2-3: Asynchronous memory banks ................................................................................................................................................ 12
Table 2-4: SDRAM memory map ................................................................................................................................................................. 12
Table 3-1: Baseboard connector types ..................................................................................................................................................... 15
Table 3-2: Core Module connector types ................................................................................................................................................. 15
Table 3-3: Connector X1 pin assignment ................................................................................................................................................. 18
Table 3-4: Connector X2 pin assignment ................................................................................................................................................. 19
Table 4-1: Border pin assignment .............................................................................................................................................................. 24
Table 4-2: BGA Version Pin Assignment ................................................................................................................................................... 30
Table 4-3: Pins FA20 to FA24 ........................................................................................................................................................................ 31
Table 5-1: Bill of Material of Sample Schematic ..................................................................................................................................... 32
Table 5-2: Bill of Material of Sample Schematic ..................................................................................................................................... 33
Table 8-7-1: Anomalies .................................................................................................................................................................................. 34
Table 10-1: Revision History ......................................................................................................................................................................... 36
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