1/38November 2003
M25P10-A
1 Mbit, Low Voltage, Serial Flash Memory
With 40 MHz SPI Bus Interface
FEATURES SUMMARY
1 Mbit of Flash Memory
Page Program (up to 256 Bytes) in 1.4ms
(typical)
Sector Eras e (256 Kbit) in 0.8s ( typical)
Bulk Erase (1 Mbit) in 2.5s (typical)
2.7 to 3.6V Single S upply Volta ge
SPI Bus Compatible Serial Interface
40MHz Clock Rate (maximum)
Deep Power-down Mode 1 µA (ty p ica l)
Electronic Signature (10h)
More than 100,000 Erase/Program Cycles per
Sector
More than 20 Year Data Retention
Figure 1. Packages
ENHANCED VERSI ON OF T HE M25P10
This device is an enhanced version of the
M25P10. The enhanced features include: larger
page size, shorter progr ammi ng t ime, higher clock
frequency.
SO8 (MN)
150 mil width
8
1
VDFPN8 (MP)
(MLP8)
M25P10-A
2/38
TABLE OF CONT ENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ENHANCE D VERSIO N OF THE M25P10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic D iagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO and VDFPN Conne ction s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNA L DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Se lect (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus Master and Memory Dev ices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. SPI Modes Supporte d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Pr ogrammin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Sec tor Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Po lling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active Power, Stand-by Power and Deep Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Protecte d Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Table 3. Memory Organizat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Figure 7. Blo ck Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3/38
M25P10-A
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Write Enable (WREN) Instruction Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Figure 9. Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequenc e. . . . . . . 14
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Write Status Register (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Protecti on Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
Figure 12. Read Data Bytes (READ) Instruction Sequence and Dat a-Out Sequ ence . . . . . . . . . . 17
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out
Seq uenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Data Bytes at High er Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Pag e Program (PP) Instruction Sequenc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page Pr ogram (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Sector Erase (SE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Sec tor Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Bulk Erase (BE) Instruction Sequen ce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. Deep Po wer-down (DP) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Deep Power-do wn (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Seq uenc e and Data-Out Seque nce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Rele ase from D e e p P o wer - d own and R e a d E l e c tronic Signatu r e ( R ES) . . . . . . . . . . . . . . . . . 23
Figure 19. Release from Deep P ower-down (RES) Instruction Sequence . . . . . . . . . . . . . . . . . . . 24
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Power-u p Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5
Table 7. Power-Up Timing and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
M25P10-A
4/38
Table 8. Absolute Maxim um Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8
Table 9. Operating Conditi ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 21. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
Table 13. AC Characteristics (25MHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. AC Characteristics (40MHz Operation, upon request - contact nearest ST sales office) 30
Figure 22. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD= 1 . . . . . . . . . . . . . . 32
Figure 24. Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3
Figure 25. Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4
Figure 26. SO 8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Out line. . . . 34
Table 15. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Pac kage Mechanical Data
34
Figure 27. VDFP N8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Package Outline . . . . . 35
Table 16. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Package M echanical Data
35
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Orderin g Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 18 . Document Revision Hi story. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5/38
M25P10-A
SUMMARY DESCRIPTION
The M 25P 10-A is a 1 Mbit (128K x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, acces se d by a high speed SPI -compatible
bus.
The memory can be programmed 1 to 256 bytes at
a time, using the Page P rogram instruc tion.
The mem ory is organi ze d as 4 s ectors, eac h con-
taining 128 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 512 pages, or 131,072 byt es.
The whole mem ory can b e erased using t he Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
Figure 2. Logic Diagram
Figu re 3. S O and VDFPN C on ne ctions
Note : 1. There is an exposed die paddle on t he underside of the
MLP8 package. This is pulled, internally, to VSS, and
must not be allowed to be c onnected to any other voltage
or si gnal line on the PCB.
2. See page 34 (onwards) for package dimensions, and how
to identify pin-1.
Table 1. Sign al Names
AI05760
S
VCC
M25P10-A
HOLD
VSS
W
Q
C
D
1
AI05761B
2
3
4
8
7
6
5DVSS C
HOLDQ
SV
CC
W
M25P10-A
C Serial Clock
D Serial Data Input
Q Serial Data Outp ut
SChip Select
W Write Protect
HOLD Hold
VCC Supply Voltage
VSS Ground
M25P10-A
6/38
SIGNAL DESCRIPTION
Serial Data O utp ut (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data In put (D). Thi s input signal is used to
transfer data serial ly into t he device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clo ck (C). This input signal provides the
timing of the s erial interface. Instructions , address-
es, or data present at Serial Data Input (D) are
latched on the ris ing edge of Serial Clock (C) . Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Selec t (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Pro-
gram, Erase or Write Status Register cycle is in
progress, the device will b e in the Standby mode
(this is not the Deep Power-down mode). Driving
Chip S ele c t (S) Low enables the device, placing it
in the active power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communi cations with the device
without deselecti ng the device.
During the Hold condition, the Serial Data Ou tput
(Q) is hig h impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hol d condit ion, t he device must be se-
lected, with C hip S ele c t ( S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of m em-
ory that is protected against program or erase
instructions (as specified by the values in the BP1
and BP0 bits of the Status Register).
7/38
M25P10-A
SPI MODES
These dev ices can be drive n by a microcont roller
with its SPI peripheral running in ei ther of the two
following modes:
CP OL= 0, CPHA=0
CP OL= 1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
C re mains at 0 for (CP O L=0, CPHA=0 )
C re mains at 1 for (CP O L=1, CPHA=1 )
Figure 4. B us Master and Memo ry Devi ces on the SPI Bus
No te : 1. The W ri te Protect (W) and Hold (HOL D) signals should be dr i ven, High or Lo w as appropriate.
Figu re 5. S PI Modes S up ported
AI03746D
Bus Master
(ST6, ST7, ST9,
ST10, Others) SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M25P10-A
8/38
OPERATING FEATURES
Page P rogramm i ng
To program one data byte, t wo instructions are re-
quired: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which con-
sists of four bytes plus data. This is f ollowed by the
internal Program cycle (of duration tPP).
To spread this ove rhead, the Page P rogram (PP)
instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), pro-
vided that they lie in consecutive addresses on the
same page of memory.
Sector Erase and Bul k Erase
The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memo ry need to hav e been erased to a ll
1s (FFh). Thi s can be achieved either a s ector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Erase cycle (of duration tSE or tBE).
The Erase instruction must be preceeded by a
Write Enabl e (WREN) instruct ion.
Polling Duri ng a Wri te, Program or Erase Cycle
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst
case delay (tW, tPP, tSE, or tBE). The Write In
Progress (WIP) bit is provided in t he Status Regis-
ter so that the application program can monitor its
value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is com-
plete.
Active Power, St a nd - by Po wer an d De ep
Power- Down Modes
When Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode.
When Chip Select (S) is High, the device is dis-
abled, but could remain in the Active Power mode
until all internal cycles have com pleted (Program,
Erase, Write Status Register). The device then
goes in t o the Stand-by P ower mode. T he dev ice
consump tion drops to ICC1.
The Deep Power-down mode is entered when the
specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device
consump tion drops further to ICC2. T he de vic e re-
mains in this mode until another specific instruc-
tion (the Release from Deep Power-down Mode
and Read Elect ro nic Sig nature (RES) i nstruction)
is executed.
All other instructions are igno re d while the device
is in the Deep Power-down mode. This can be
used as an ext ra soft ware protection mecha nism,
when the device is not in active use, to protect the
device from inadvertant Write, Program or Erase
instructions.
Status Register
The Status Register contains a number of status
and control bits, as shown in Table 5, that can be
read or set (as appropriate) by specific instruc-
tions.
WIP bit. The Writ e In Progress (WIP) bit indic ates
whether the memory is busy with a Write Status
Register, Program or Era se cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the int ernal Write Enable Latch.
BP1, BP0 b its. The Block Protect (BP1, B P0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-v ol atile bits
of t he Status Register (SRWD, BP1, BP0) become
read-only bits.
9/38
M25P10-A
P rotec t i on Modes
The environments where non-vol atile memory de-
vices are used can be very noisy. No SPI device
can operate correct ly i n the presence of excessive
noise. T o hel p com bat t his, t he M 25P 10-A b oas ts
the following data protection mech anism s:
Power-On Reset and an i nternal timer (tPUW)
can provide protection against inadvertant
change s while the power supply is outside the
operating specification.
Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, bef ore they are accepted for execution.
All instructions that modify data mus t be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction
completion
Page Program (PP) instruction com pletion
Sector Erase (SE) instruction completion
Bul k Eras e (BE) instru ction completion
The Bl ock Protect (B P1, BP0) bits allow part of
the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
The Write Protect (W) signal, in co-operation
with t he Stat us Register Wri te Di sabl e (SRWD)
bit, allows the Block Protect (BP1, BP0) bits and
Status Regi ster Write Disable (SRWD) bit to be
write-protected. This is the Hardware Protected
Mode (HPM).
In addition to the low power con sumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instruc tions , as all
instructions are ignored except one particular
instruction (the Release from Deep Power-
down instruction).
Table 2. Pro tected Area Sizes
Note: 1. The device is ready to accept a Bul k E rase inst ruction if, and only if, both Block Protect (BP1 , B P0) are 0.
Status Regis ter
Content Memory Content
BP1 Bit BP0 Bit Protected Area Unprotected Area
0 0 none All sectors1 (four sectors: 0, 1, 2 and 3)
0 1 Upper quarter (Sector 3) Lower three-quarters (three sectors: 0 to 2)
1 0 Upper half (two sectors: 2 and 3) Lower half (Sectors 0 and 1)
1 1 All sectors (four sectors: 0, 1, 2 and 3) none
M25P10-A
10/38
Hold Condition
The Hold (HOLD ) s ignal is used to pause any se-
rial communication s with the device without rese t-
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently
in progress.
To enter the Hold condition, the device must be
sele c te d , wit h C h ip Select (S) Low.
The Hold condit ion starts on the falling edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) bei ng L ow (as shown i n Fig-
ure 6).
The Hold condition ends on the rising edge of t he
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condi tion starts af-
ter S erial Cl ock (C) nex t goes Low. S imilarl y, i f the
rising edge does not coinci de wi th Serial Clock (C)
being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (T his is shown in Figure
6).
During the Hold condition, the Serial Data Ou tput
(Q) is hig h impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip
Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure th at the state of
the internal logic remains unchanged from the mo-
ment of entering the Hold condition.
If Chip Select (S) go es High whil e the device is in
the Hold condition, this has the effect of reset ting
the internal logic of the device. To restart commu-
nication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Sel ect
(S) Low. This prevent s t he device from going back
to the Hold condition.
Figure 6. Hold Condition Activ ation
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
11/38
M25P10-A
MEM ORY OR GANIZA TI ON
The memory is organized as :
131,072 byt es (8 bits each)
4 sec tors (256 Kbits, 32768 bytes each)
512 pages (256 bytes each).
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
Table 3. Memory Organization
Figu re 7. Blo ck D ia gra m
Sector Address Range
3 18000h 1FFFFh
2 10000h 17FFFh
1 08000h 0FFFFh
0 00000h 07FFFh
AI03747D
HOLD
S
WControl Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
C
D
Q
Status
Register
00000h
08000h
10000h
18000h
1FFFFh
000FFh
Size of the
read-only
memory area
M25P10-A
12/38
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in t o the device, most signif icant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Seri al Clock (C).
The instruction set is listed in Tab le 4.
Every instruction sequence s tarts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address byt es, or by data
bytes, or by both or none. Chip Select (S) must be
driven High after the last bit of the i nstruction se-
quence has been shifted in.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR) or Release from Deep
Power-down, and Read Electronic Signature
(RES) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the
data-out sequen ce is being shifted out.
In the c ase of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Select (S) must be driven High exactly at a
byte bounda ry, otherwise the instruction is reject-
ed, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses
after Chip Select (S) being driven Low is an ex act
multiple of eight.
All at tempts t o access the mem ory arra y du ring a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Regist er cycle, Program cycle or Erase cy-
cle cont i nues unaf fected.
Table 4. Instructi on Set
Instruction Description One-byte Instruction Code Address
Bytes Dummy
Bytes Data
Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDSR Read Status Register 0000 0101 05h 0 0 1 to
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RES Release from Deep Power-down,
and Read Electronic Signature 1010 1011 ABh 0 3 1 to
Release from Deep Power-down 0 0 0
13/38
M25P10-A
Figure 8. Write En able (WRE N) Instruction Sequenc e
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8)
sets the Write Enable Latc h (WEL) bit.
The Write Enabl e Latch (WEL) bi t must be set pri-
or to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 9. Write Disable (WRDI) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9)
resets the Write Enable Latch (WEL ) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S ) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write S tatus Register (WRSR) instruction com-
pletion
P age P rogram (PP) instruction completion
Sect or Erase (SE) instruction completion
B ulk Erase (BE) instruction completion
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M25P10-A
14/38
Figure 10. Read Status Register (RDSR) Instruct ion Sequence and Data-Out Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycl es i s in progress,
it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the
device. It is also poss ible to read the S tatus Reg-
ister continuously, as shown in Figure 10.
Table 5. Status Register Format
The status and cont rol bits of the Stat us Register
are as follows :
WIP bit. The Writ e In Progress (WIP) bit indic ates
whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1,
such a cycle is in progress, when reset to 0 no
suc h cycle is in pro gr es s.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the int ernal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, whe n set to 0 the i nternal Write Enabl e La tch
is reset and no Write Status Reg ister, Program or
Erase instruction is accepted.
BP1, BP0 b its. The Block Protect (BP1, B P0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions. These bits are written with the Write
Status Register (WRSR) instruction. W hen one or
both of the Block Protect (B P1, B P0) bits i s set t o
1, the relevant memory area (as defined in Table
2) becomes protected against Page Program (PP)
and Sector Erase (SE) instructions. The Block
Protect (BP1, BP0) bits can be written provided
that the Hardware Protected mode has not been
set. The Bulk Erase (BE) i nstruct ion is executed if,
and only if, both Block Protect (BP1, BP0) bits are
0.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Wri te Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bit s and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
15/38
M25P10-A
Figure 11. Wri te Status Regi ster (WRSR) Instructi on Sequenc e
Write Status Regist er (WRSR)
The Write Status Register (WRSR) instruction al-
lows new val ues to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Wri te Enable (WREN) instruction
has been d ecoded and ex ecuted, the de vice se ts
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the dat a byt e on Serial
Data Input (D).
The instruct ion sequence is shown in Figure 11.
The Write Stat us Register (WRSR) instruct ion has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are alway s read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the W rite Status Register (WRSR) instruction
is not executed. As soon as Chip Select (S) is driv-
en Hig h, th e self -timed Write S tatus Register cycle
(whose du ration is t W) is init iated . While the Writ e
Status Register cycle is in progress, the Status
Register may still be read to check t he value of the
Write In P rogress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. At
some unspecified time before the cycle is compl et -
ed, the Write Enab le Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that i s to be treated as rea d-only, as defined
in Table 2. The Write Status Register (WRSR) in-
struction also allows the user to set or reset the
Status Register Write Disable (SRWD) bit in ac-
cordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the devi ce to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) in struction is n ot execut-
ed once the Hardware Protected Mode (HPM) is
entered.
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M25P10-A
16/38
Table 6. Pro tection M ode s
Note: 1. As def i ned by th e values in the Block Pr otect (B P1, BP0) bi ts of the Status Regist er, as sh own in Tab l e 2.
The prot ection f eat ures of the device are summ a-
rized in T able 6.
When the Status Register Write Disab le (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Regi ster
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, rega rdless o f the wh ether W rite Protect
(W) is driven High or Low.
When the Status Register Write Disab le (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered , depending on t he state of
Write Protect (W):
I f Write Protect (W) is driven High, it is possible
to write to the Status Regis ter provided that the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
I f Write Protect (W) is driven Low, it is
not
pos-
sible to write to th e Status Register
even
if the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
(Attempts t o write to the Status Register are re-
jected, and are no t accepted for ex ecution). As
a consequence, all the data bytes in the memo-
ry area that are sof tware protected (SPM) by the
Block Protect (BP1, BP0) bits of the Stat us Reg-
ister, are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be ent ered:
by setting the Status Register Write Disable
(SRWD) bi t after driving Writ e Protect (W) Low
or by dri ving Write Protect (W) Low after setting
the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using t he Bloc k Protect (B P1, BP0) bi ts of
the Stat us Register, can be used.
W
Signal SRWD
Bit Mode Write Protection of the
Status Register
Memory Content
Protected Area1Unprotected Area1
10
Software
Protected
(SPM)
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the SRWD,
BP1 and BP0 bits can be
changed
Protected again st Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector
Erase instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP1 and BP0 bits cannot
be changed
Protected again st Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector
Erase instructions
17/38
M25P10-A
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Seque nce
Note: 1. Address bits A23 to A17 are Don’t Care.
Read Data Bytes (READ)
The de vice is f irst s el ected by driving Chip Sele ct
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Cl ock (C). T hen t he mem-
ory contents , at that address, is shi fted out on Se-
rial Data Output (Q), eac h b it bein g shift ed out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruct ion sequence is shown in Figure 12.
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift -
ed out. T he whole memory c an, th erefore, be read
with a singl e Read Data Byt es (READ) i nstruction.
When the highes t address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chi p Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rej ected without having any ef fects on
th e cycle tha t is i n progr es s.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
M25P10-A
18/38
Figure 13. Read Data Bytes at Hi gher Speed (FAST_READ) Instruction Sequence and Data-Out
Sequence
Note: 1. Address bits A23 to A17 are Don’t Care.
Read Data Bytes at H igher Speed
(FAST_READ)
The de vice is f irst s el ected by driving Chip Sele ct
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the
rising edge of S erial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency fC, during the falling edg e of
Serial Clock (C).
The instruct ion sequence is shown in Figure 13.
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift -
ed out. T he whole memory c an, th erefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_REA D) instruction is terminated by driving
Chip Select ( S) Hi gh. Chip Select (S) can be driv-
en High at any time during data outp ut. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
19/38
M25P10-A
Figure 14. P age Program (PP) Instruction Sequence
Note: 1. Address bits A23 to A17 are Don’t Care.
Page Program (PP)
The Page Pr ogram (PP) instruction allows bytes to
be programmed in t he memory (changing bits from
1 to 0). Before i t can be ac cept ed, a Wri te Enable
(WREN) instruction must previously have been ex-
ecuted. After the Wri te Enable (WREN) instruction
has been decoded , the device sets the Write En-
able Latch (WEL).
The Page Pro gram (PP) instru ction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted dat a that goes beyond the end
of the current page are programmed from the star t
address of the same page (from the address
whose 8 l east si gnificant bits (A7-A0) are all zero).
Chip Select ( S) must be driven Low for the entire
duration of the seq uenc e.
The instruct ion sequence is shown in Figure 14.
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data bytes are guaranteed to be programmed cor-
rectly within the sam e pag e. If less than 256 Data
bytes are sent to device, they are correctly pro-
grammed at the request ed addresses without hav-
ing any effects on the other bytes of the same
page.
Chip Select (S) must be driven High after the
eighth bi t of the last data byte has been l atched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S ) is driv en H i gh , t h e se lf -
timed Pa ge Program cycle (whose durati o n i s tPP)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit .
The Write In Progress ( WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) instruction applied to a page
which is prot ected by the Block Protect (BP1, BP0)
bits (see Table 3 and Table 2) is not executed.
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
M25P10-A
20/38
Figure 15. Sector Erase (SE) Instructi on Sequence
Note: 1. Address bits A23 to A17 are Don’t Care.
Sector Erase (SE)
The Sector E rase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address bytes on Serial
Data Input (D). Any address inside the Sector (see
Table 3) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruct ion sequence is shown in Figure 15.
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (S) is driven
High, t he self-timed Sector E rase cycle (whose du-
ration i s tSE) is initiated. While the Sector Erase cy-
cle is in progress, the Status Register may be read
to check the value of the Wri te In Progres s (WIP)
bit. The Wri t e In Progress (WI P) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Sec tor E ras e (SE ) instruction applie d to a page
which is prot ected by the Block Protect (BP1, BP0)
bits (see Table 3 and Table 2) is not executed.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
21/38
M25P10-A
Figure 16. Bulk Erase (BE) Instru ction Sequence
Bulk Eras e ( BE)
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enab le
(WREN) instruction must previously have been ex-
ecuted. After the Wri te Enable (WREN) instruction
has been decoded , the device sets the Write En-
able Latch (WEL).
The Bulk Erase (BE) instruction i s entered by dri v-
ing Chip Select (S) Low, followed by t he ins truction
code on Serial Data Input (D). Chip Select (S)
must be driven Low for the entire duration of the
sequence.
The instruct ion sequence is shown in Figure 16.
Chip Select (S) must be driven High after the
eighth bi t of the instruction code has been latched
in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip Select (S) is driven High,
th e s elf -time d Bu l k Era se cycl e (wh ose duratio n is
tBE) is initiated. While the Bulk Erase cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit .
The Write In Progress ( WIP) bit is 1 during the self-
timed Bulk Erase cycle, and is 0 when it is com-
plet ed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is
reset.
The Bulk Erase (BE) instruction is executed only if
both Block Pr otect (BP 1, BP0) bi ts are 0. The Bulk
Erase (BE) instruction is ignored if one, or more,
sectors are protected.
C
D
AI03752D
S
21 345670
Instruction
M25P10-A
22/38
Figure 17. Deep Power-down (DP) Instruction Sequence
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in t he lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism , while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Eras e instructions.
Driving Chip Select (S) High deselects the device,
and puts the dev ice in the S tandby m ode (if there
is no internal cycle currently in progress). But this
mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instru ction,
to reduce the standby current (from ICC1 to I CC2,
as specified in Table 12).
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. This releases
the device from this mode. The Release from
Deep Power-down and Read Electronic Signature
(RES) instructio n also allows the Electronic Signa-
ture of the device to be output on Serial Data Out-
put (Q).
The Deep P ower-down m ode automatically stops
at Power-down, and the device always Powers-up
in the Standby mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Inp ut (D ). Chip Se-
lect (S) m ust be d riven Low for the entire duration
of the seq uence.
The instruct ion sequence is shown in Figure 17.
Chip Select (S) must be driven High after the
eighth bi t of the instruction code has been latched
in, otherwise t he Deep Power-down (DP) instruc-
tion is not executed. As soon as Chip Select (S) i s
driven High, it requires a delay of tDP before the
supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without h aving an y e ffec ts o n the cycl e th a t
is in progr ess.
C
D
AI03753D
S
21 345670 t
DP
Deep Power-down Mode
Stand-by Mode
Instruction
23/38
M25P10-A
Figure 18. Rel ease from Deep Po wer-d ow n and Read Electro nic Sign atur e (RES) Instruction
Sequence and Data -O u t Se qu e nce
Note: T he val ue of the 8-bit Electro ni c S i gnature, for the M2 5P10-A , i s 10h.
Release from Deep Power-do wn and Read
Electronic Signature (RES)
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. Executing this
instruction takes the device out of the Deep Pow-
er-down mode.
The instruction can also be used to read, on Ser ial
Data Output (Q), the 8-bit Electronic Signature,
whose value for the
M25P10-A
is
10h
.
Except while an Erase, Program or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Electronic Signature
(RES) instruction always provides access to the 8-
bit Electronic Signa ture of th e device, and can be
applied even if the Deep Power-down mode has
not been entered.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in
progress, is not decoded, and has no effect on the
cycle that is in progress.
The de vice is f irst s el ected by driving Chip Sele ct
(S) Low. The instruction code is followed by 3
dummy bytes, each bit being latched-in on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Then, the 8-bit Electronic Signature,
stored in the memory, is shift ed out on Serial Data
Output (Q), each bit being shifted out during the
falling edge of Serial Clock (C).
The instruct ion sequence is shown in Figure 18.
The Release from Deep Power-down and Read
Electronic Si gnature (RES) instruct ion is terminat -
ed by driving Chip Sele ct (S) High after the Elec-
tronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S) is dr iven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select (S) i s dr iven Hig h, the de vic e is
put in the Stand-by Power mode. If the device was
not previously in the Deep Power-down mode, the
transition to t he S t and-by Power m ode is im m edi-
ate. If the device was previousl y in t he Deep Pow-
er-down mode, though, the transition to the Stand-
by Power mode i s delayed by tRES2, and Chi p Se-
lect ( S ) must remain High for at least tRES2(max),
as specified in Table 13. Once in the Stand-by
Power mode, the device waits to be selected, so
that it can receive, decode and execute instruc-
tions.
C
D
AI04047C
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
765432 0
1
High Impedance Electronic Signature Out
Instruction 3 Dummy Bytes
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
tRES2
M25P10-A
24/38
Figure 19. Rel ease from Deep Po wer-d ow n (RES) Instruction S eq uen ce
Driving Chip Select (S) High after the 8-bi t instruc-
tion byte has been received by the device, but be-
fore the whole of the 8-bit Electronic Signature has
been transmit ted for the first time (as shown in Fig-
ure 19), still insures that the device is put into
Stand-by P ower mode. I f the d evice was not pre-
viously in the Deep Power-down mode, the transi-
tion to the Stand-by Power mode is immediate. If
the device was previously in the Deep Power-
down mode, though, the transition to the Stand-by
Power mode is delayed by tRES1, and Chip Select
(S) must remain High for at least tRES1(max), as
specified in Table 13. Once in the St and-by Power
mode, the device waits to be selected, so that it
can receive, decode and execut e instructions.
C
D
AI04078B
S
21 345670 t
RES1
Stand-by Mode
Deep Power-down Mode
QHigh Impedance
Instruction
25/38
M25P10-A
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the volt age appl ied on VCC) until VCC reaches the
correct value:
–V
CC(min) at Power-up, and then for a further de-
lay o f tVSL
–V
SS at Power-down
Usually a simple pull-up resistor on Chip Select (S)
can be used to insure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write
operations during power up, a Power On Reset
(POR) circuit is included. The logic inside the
device is held reset while VCC is less than the POR
threshold value, VWI all operations are disabled,
and the device does not respond to any
instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Se ctor Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of tPUW has
elapsed after the moment that VCC rises above the
VWI threshold. However, the correct operation of
the device is not guaranteed if, by t his t ime, VCC is
still below VCC(min). No Write Status Register,
Program or Erase instructions should be sent until
the later of:
–t
PUW af ter VCC passed the VWI threshold
–t
VSL afterVCC pass ed the VCC(min) level
These values are specified in Table 7.
If the delay, tVSL, has elapsed, after VCC has risen
above VCC(min), the device can be selected for
READ instructions even if the tPUW delay is not yet
fully elapsed.
At Power-up, the dev ice is in the f ollowing state:
The device is in the Standby mode (not the
Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail
decoupling, to stabl ise the V CC fe ed. Ea ch device
in a syst em should have t he VCC rail decoupled by
a suitable capacitor close to the package pins.
(Generally, this capacitor is of the order of 0.1µF) .
At Power-down, when VCC drops from the
operating voltage, to below the POR threshold
value, VWI, all operations are disabled and the
device does not respond to any instruction. (The
designer needs to be aw are that if a Power-down
occurs while a Write, Program or Erase cycle is in
progress, some data corruption can result.)
Figure 20. P ower-up Timing
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
M25P10-A
26/38
Table 7. Power-Up Timing and VWI Th re shold
No te : 1. Thes e param eters are character i zed only.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains FFh). T he Status Register contains 00h (all Stat us
Register bits are 0).
Symbol Parameter Min. Max. Unit
tVSL1VCC(min) to S low 10 µs
tPUW1Time delay to Write instruction 1 10 ms
VWI1Write Inhibit Voltage 1 2 V
27/38
M25P10-A
MAX I MUM R A TI N G
Stressing the device ab ove t he rati ng l isted in t he
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at t hes e or
any other con ditions ab ove those i ndicated i n the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute M axim um Ratings
No te : 1. Compliant wi th the ECOPAC K® 71 91395 specifii cation fo r lead-f ree soldering pr ocesse s
2. Not ex ceedin g 250°C for more than 30 se conds, and peaking at 260°C
3. JE DEC Std J ESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering1SO
VDFPN 260 2
260 2°C
VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V
VCC Supply Voltage –0.6 4.0 V
VESD Electrostatic Discharge Voltage (Human Body model) 3–2000 2000 V
M25P10-A
28/38
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Des igners shoul d c heck that the operating
conditions i n their circuit match the meas urement
conditions when relying on the quoted parame-
ters.
Table 9. Operating Conditions
Table 10. A C Measurem en t Condition s
Note: 1. Out put Hi-Z i s defined as the point where data out is no l onger dri ven.
Figure 21. AC Measurement I/O Waveform
Table 11. Capacitance
Note: Samp l ed only, not 100% tested, at TA= 25°C and a frequency of 20 MHz.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.6 V
TAAmbient Operati ng Temperatur e –40 85 °C
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Volta ges VCC / 2 V
Symbol Parameter Test Condition Min.Max.Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
0.5VCC
29/38
M25P10-A
Table 12. DC Characteristics
Table 13. AC Characteristic s (25M Hz Operati on)
Symbol Parameter Test Condition
(in addition to those in Table 9) Min. Max. Unit
ILI Input Leaka ge Curren t ± 2 µA
ILO Output Leakage Current ± 2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC A
I
CC3 Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 40MHz,
Q = open 8mA
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open 4mA
I
CC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 15 mA
ICC6 Operating Current (SE) S = VCC 15 mA
ICC7 Operating Current (BE) S = VCC 15 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Volta ge 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 µAV
CC–0.2 V
Test conditions specified in Table 9 and Table 10
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfCClock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDSR, WRSR D.C. 25 MHz
fRClock Fre quen cy for READ instruc tions D.C. 20 MH z
tCH 1tCLH Clock High Time 18 ns
tCL 1tCLL Clock Low Tim e 18 ns
tCLCH 2Clock Rise Time3 (peak to peak) 0.1 V/ns
tCHCL 2Clock Fall Time3 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 10 ns
tCHSL S Not Active Hold Time (relative to C) 10 ns
tDVCH tDSU Data In Setup Time 5 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 10 ns
tSHCH S Not Active Setup Time (relative to C) 10 ns
tSHSL tCSH S Dese lect Time 100 ns
M25P10-A
30/38
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by charact erization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicab l e as a constra i nt for a WRS R instruction wh en S RWD is set at 1.
Table 14. A C Character istics (40MHz Operati on , upon request - contact nearest ST sales office)
tSHQZ 2tDIS O utput Disable Time 15 ns
tCLQV tVClock Low to Output Valid 15 ns
tCLQX tHO O utput Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 10 ns
tCHHH HOLD Hold Time (relative to C) 10 ns
tHHCH HOLD Setup Time (relative to C) 10 ns
tCHHL HOLD Hold Time (relative to C) 10 ns
tHHQX 2tLZ HOLD to Output Low-Z 15 ns
tHLQZ 2tHZ HOLD to Output High-Z 20 ns
tWHSL 4Write Protect Setup Time 20 ns
tSHWL 4Write Protect Hold Time 100 ns
tDP 2S High to Deep Power-down Mode 3 µs
tRES1 2S High to Standby Mode without Electronic
Signature Read 3µs
tRES2 2S High to Standby Mode with Electronic
Signature Read 1.8 µs
tWWrite Status Register Cycle Time 5 15 ms
tPP Page Program Cycle Time 1.4 5 ms
tSE Sector Erase Cycle Time 0.8 3 s
tBE Bulk Erase Cycle Time 2.5 6 s
Test conditions specified in Table 9 and Table 10
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfCClock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDSR, WRSR D.C. 40 MHz
fRClock Fre quen cy for READ instruc tions D.C. 20 MH z
tCH 1tCLH Clock High Time 1 1 ns
tCL 1tCLL Clock Low Tim e 11 ns
tCLCH 2Clock Rise Time3 (peak to peak) 0.1 V/ns
tCHCL 2Cl ock Fall Time3 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns
Test conditions specified in Table 9 and Table 10
Symbol Alt. Parameter Min. Typ. Max. Unit
31/38
M25P10-A
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by charact erization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicab l e as a constra i nt for a WRS R instruction wh en S RWD is set at 1.
tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S Dese lect Time 100 ns
tSHQ Z 2tDIS O utput Disable Time 9 ns
tCLQV tVClock Low to Output Valid 9 ns
tCLQX tHO O utput Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (relative to C) 5 ns
tCHHL HOLD Hold Time (relative to C) 5 ns
tHHQX 2tLZ HOLD to Output Low-Z 9 ns
tHLQZ 2tHZ HOLD to Output High-Z 9 ns
tWHSL 4Write Protect Setup Time 20 ns
tSHWL 4Write Protect Hold Time 100 ns
tDP 2S High to Deep Power-down Mode 3 µs
tRES1 2S High to Standby Mode without Electronic
Signature Read 3µs
tRES2 2S High to Standby Mode with Electronic
Signature Read 1.8 µs
tWWrite Status Register Cycle Time 5 15 ms
tPP Page Program Cycle Time 1.4 5 ms
tSE Sector Erase Cycle Time 0.8 3 s
tBE Bulk Erase Cycle Time 2.5 6 s
Test conditions specified in Table 9 and Table 10
Symbol Alt. Parameter Min. Typ. Max. Unit
M25P10-A
32/38
Figure 22. S erial Input Timing
Figu re 23. W ri te Pr ote ct Se tup a n d H ol d Ti m in g du rin g WR S R wh e n S RW D=1
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
33/38
M25P10-A
Figu re 24 . Hol d T im i ng
Figure 25. Output Timing
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
C
Q
AI01449D
S
LSB OUT
DADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
M25P10-A
34/38
PACKAGE MECHANICAL
Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width , Packag e Outlin e
Not e: Drawing is not to scale.
Table 15. SO8 narrow – 8 l ead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α
N8 8
CP 0.10 0.004
SO-a
E
N
CP
Be
A
D
C
LA1 α
1H
h x 45˚
35/38
M25P10-A
Figure 27. V DFPN8 (ML P8) 8-lead Very thin Dual Flat Package No lead, Package Outline
Not e: Drawing is not to scale.
Table 16. VDF P N8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Packag e Mechan ical Data
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
D1 5.75 0.2264
D2 3.40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.20 0.1575 0.1496 0.1654
e 1.27 0.0500
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
θ12° 12°
D
E
VDFPN-01
A2
A
A3
A1
E1
D1
eE2
D2
L
b
θ
M25P10-A
36/38
PART NUMBERING
Table 17. Ordering Information Scheme
No te : 1. Avail able for SO8 package only
2. Available f or M LP package only
For a list of available options (speed, package,
etc.) or for further information on any aspect of this device, please con tact your nearest ST S ales Of-
fice.
Example: M25P10-A V MN 6 T P
Device Type
M25P
Device Function
10-A = 1 Mbit (128K x 8) Enhanced Techology in line with
the M25P05-A, M25P20, M25P40, M25P80
Operating Voltage
V = VCC = 2.7 to 3.6V
Package
MN = SO8 (150 mil width)
MP = VDFPN8 (MLP8)
Temperature Range
6 = –40 to 85 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P1 = Pb-Free, RoHS compliant
G2 = Green package
37/38
M25P10-A
RE VISION HISTORY
Table 18. Document Revisio n History
Date Rev. Description of Revision
25-Feb-2001 1.0 Document written
12-Sep-2002 1.1 VFQFPN8 package (MLP8) added. Clarification of descriptions of entering Stand-by Power
mode from Deep Power-down mode, and of terminating an instruction sequence or data-out
sequence
13-Dec-2002 1.2 Typical Page Program time improved. Write Protect setup and hold times specified, for
applications that switch Write Protect to exit the Hardware Protection mode immediately before
a WRSR, and to enter the Hardware Protection mode again immediately after
21-Feb-2003 1.3 Erroneous address ranges corrected in Memory Organisation table
24-Nov-2003 2.0 Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.
40MHz AC Characteristics table included as well as 25MHz. ICC3(max), tSE(typ) and tBE(typ)
values improved. Change of naming for VDFPN8 package
M25P10-A
38/38
Info rm atio n fur ni shed is bel i eved to be accurate an d rel i able. However, STMicro el ectro ni cs assumes no responsibility for t he consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cation or oth erwise under any pat ent or paten t rights of STMi croel ectroni cs. Specificat i ons me ntioned i n this publ ication are subj ect
to change without notice. This publication supersedes and replaces all information previously s upplied. STMicroelectronics products are not
authorized for use as c ri tical components in lif e support devices or systems wi t hout express wri t ten approval of STM i croelectronics.
The ST l ogo is a registered tra dem ark of STM i croelectron ic s.
All other names are th e prope rt y of their respectiv e owners
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