Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 4 1Publication Order Number:
2N5060/D
2N5060 Series
Preferred Device
Sensitive Gate
Silicon Controlled Rectifiers
Reverse Blocking Thyristors
Annular PNPN devices designed for high volume consumer
applications such as relay and lamp drivers, small motor controls, gate
drivers for larger thyristors, and sensing and detection circuits.
Supplied in an inexpensive plastic TO-226AA (TO-92) package
which is readily adaptable for use in automatic insertion equipment.
Sensitive Gate Trigger Current — 200 µA Maximum
Low Reverse and Forward Blocking Current — 50 µA Maximum,
TC = 110°C
Low Holding Current — 5 mA Maximum
Passivated Surface for Reliability and Uniformity
Device Marking: Device Type, e.g., 2N5060, Date Code
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Peak Repetitive Off–State Voltage(1)
(TJ =
*
40 to 110°C, Sine W ave,
50 to 60 Hz, Gate Open) 2N5060
2N5061
2N5062
2N5064
VDRM,
VRRM 30
60
100
200
Volts
On-State Current RMS
(180° Conduction Angles; TC = 80°C) IT(RMS) 0.8 Amp
*Average On-State Current
(180° Conduction Angles)
(TC = 67°C)
(TC = 102°C)
IT(AV)
0.51
0.255
Amp
*Peak Non-repetitive Surge Current,
TA = 25°C
(1/2 cycle, Sine W ave, 60 Hz)
ITSM 10 Amps
Circuit Fusing Considerations (t = 8.3 ms) I2t 0.4 A2s
*Forward Peak Gate Power
(Pulse Width
v
1.0 µsec; TA = 25°C) PGM 0.1 Watt
*Forward Average Gate Power
(TA = 25°C, t = 8.3 ms) PG(AV) 0.01 Watt
*Forward Peak Gate Current
(Pulse Width
v
1.0 µsec; TA = 25°C) IGM 1.0 Amp
*Reverse Peak Gate Voltage
(Pulse Width
v
1.0 µsec; TA = 25°C) VRGM 5.0 Volts
*Operating Junction Temperature Range TJ–40 to
+110 °C
*Storage Temperature Range Tstg –40 to
+150 °C
*Indicates JEDEC Registered Data.
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings
apply for zero or negative gate voltage; however, positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
SCRs
0.8 AMPERES RMS
30 thru 200 VOLTS
Preferred devices are recommended choices for future use
and best overall value.
http://onsemi.com
TO–92 (TO–226AA)
CASE 029
STYLE 10
3
2
1
PIN ASSIGNMENT
1
2
3
Gate
Anode
Cathode
K
G
A
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
2N5060 Series
http://onsemi.com
2
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
*Thermal Resistance, Junction to Case(1) RθJC 75 °C/W
Thermal Resistance, Junction to Ambient RθJA 200 °C/W
*Lead Solder Temperature
(Lead Length
q
1/16 from case, 10 s Max) +230* °C
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
*Peak Repetitive Forward or Reverse Blocking Current(2)
(VAK = Rated VDRM or VRRM)T
C = 25°C
TC = 110°C
IDRM, IRRM
10
50 µA
µA
ON CHARACTERISTICS
*Peak Forward On–State Voltage(3)
(ITM = 1.2 A peak @ TA = 25°C) VTM 1.7 Volts
Gate Trigger Current (Continuous dc)(4)
*(VAK = 7 Vdc, RL = 100 Ohms) TC = 25°C
TC = –40°C
IGT
200
350
µA
Gate Trigger Voltage (Continuous dc)(4) TC = 25°C
*(VAK = 7 Vdc, RL = 100 Ohms) TC = –40°CVGT
0.8
1.2 Volts
*Gate Non–Trigger Voltage
(VAK = Rated VDRM, RL = 100 Ohms) TC = 110°CVGD 0.1 Volts
Holding Current(4) TC = 25°C
*(VAK = 7 Vdc, initiating current = 20 mA) TC = –40°CIH
5.0
10 mA
Turn-On Time
Delay T ime
Rise T ime
(IGT = 1 mA, VD = Rated VDRM,
Forward Current = 1 A, di/dt = 6 A/µs
td
tr
3.0
0.2
µs
Turn-Off Time
(Forward Current = 1 A pulse,
Pulse Width = 50 µs,
0.1% Duty Cycle, di/dt = 6 A/µs,
dv/dt = 20 V/µs, IGT = 1 mA) 2N5060, 2N5061
2N5062, 2N5064
tq
10
30
µs
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Off–State Voltage
(Rated VDRM, Exponential) dv/dt 30 V/µs
*Indicates JEDEC Registered Data.
(1) This measurement is made with the case mounted “flat side down” on a heat sink and held in position by means of a metal clamp over the
curved surface.
(2) RGK = 1000 is included in measurement.
(3) Forward current applied for 1 ms maximum duration, duty cycle
p
1%.
(4) RGK current is not included in measurement.
2N5060 Series
http://onsemi.com
3
+ Current
+ Voltage
VTM
IDRM at VDRM
IH
Symbol Parameter
VDRM Peak Repetitive Off State Forward Voltage
IDRM Peak Forward Blocking Current
VRRM Peak Repetitive Off State Reverse Voltage
IRRM Peak Reverse Blocking Current
VTM Peak on State Voltage
IHHolding Current
Voltage Current Characteristic of SCR
Anode +
on state
Reverse Blocking Region
(off state)
Reverse Avalanche Region
Anode –
Forward Blocking Region
IRRM at VRRM
(off state)
120
50
60
70
80
90
100
110
0 0.1 0.2 0.3 0.4
130
0.5
IT(AV), A VERAGE ON-STATE CURRENT (AMP)
a
dc
110
30
50
70
90
130
dc
α
0 0.1 0.2 0.3 0.4
IT(AV), A VERAGE ON-STATE CURRENT (AMP)
TC, MAXIMUM ALLOW ABLE CASE TEMPERATURE ( C)
°
TA, MAXIMUM ALLOWABLE AMBIENT
°
TEMPERATURE ( C)
α = 30°
α = 30°60°90°
90°
120°
120°180°
CASE MEASUREMENT
POINT – CENTER OF
FLAT PORTION
60°
180°
TYPICAL PRINTED
CIRCUIT BOARD
MOUNTING
α = CONDUCTION ANGLE
α = CONDUCTION ANGLE
Figure 1. Maximum Case Temperature Figure 2. Maximum Ambient Temperature
CURRENT DERATING
2N5060 Series
http://onsemi.com
4
P(AV), MAXIMUM AVERAGE POWER
DISSIPATION (WATTS)
5.0
0.05
0.01
0.02
0 0.5 1.0 1.5 2.0
3.0
2.5
vT, INST ANTANEOUS ON-STATE VOLTAGE (VOLTS)
0.07
0.03
0.1
0.2
0.3
0.5
0.7
1.0
2.0
5.0
25°C
TJ = 110°C
30
7.0
1.0
3.0
2.0
10
1.0 2.0 3.0 5.0 7.0 10 20 50 70 100
0
0.2
0.4
0.6 a
0.1 0.4
dc
0.8
0 0.2 0.5
α = CONDUCTION ANGLE
0.3
NUMBER OF CYCLES
IT(AV), A VERAGE ON-STATE CURRENT (AMP)
iT, INSTANT ANEOUS ON-STA TE CURRENT (AMP)
ITSM, PEAK SURGE CURRENT (AMP)
α = 30°
60°90°120°180°
Figure 3. Typical Forward Voltage
Figure 4. Maximum Non–Repetitive Surge Current
Figure 5. Power Dissipation
0.02 0.2 20105.02.01.00.050.010.002 0.005 0.5
0.02
0.01
0.5
0.1
0.05
0.1
0.2
t, TIME (SECONDS)
1.0
r(t), TRANSIENT THERMAL RESISTANCE NORMALIZED
Figure 6. Thermal Response
CURRENT DERATING
2N5060 Series
http://onsemi.com
5
0.7
0.3
0.4
0.5
0.6
0.8 VAK = 7.0 V
RL = 100
RGK = 1.0 k
3.0
0.8
0.4
0.6
1.0
2.0
500–75 –50 –25
4.0
25 10075 110
TJ, JUNCTION TEMPERATURE (°C)
2N5060,61
100
VAK = 7.0 V
RL = 100
RGK = 1.0 k
0.2
0.5
1.0
2.0
5.0
10
20
50
200 VAK = 7.0 V
RL = 100
2N5062-64
2N5060-61
TYPICAL CHARACTERISTICS
50075 –50 –25 25 10075 110
TJ, JUNCTION TEMPERATURE (°C) 500–75 –50 –25 25 10075 110
TJ, JUNCTION TEMPERATURE (°C)
VG, GATE TRIGGER VOLTAGE (VOL TS)
IGT, GATE TRIGGER CURRENT (NORMALIZED)
IH, HOLDING CURRENT (NORMALIZED)
Figure 7. Typical Gate Trigger Voltage Figure 8. Typical Gate Trigger Current
Figure 9. Typical Holding Current
2N5062-64
2N5060 Series
http://onsemi.com
6
TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A
H
F1 F2
P2 P2
P1 P
D
W
W1
L1
W2
H2B H2B
T1
T
T2
H4 H5
H1
L
Figure 10. Device Positioning on Tape
Specification
Inches Millimeter
Symbol Item Min Max Min Max
DTape Feedhole Diameter 0.1496 0.1653 3.8 4.2
D2 Component Lead Thickness Dimension 0.015 0.020 0.38 0.51
F1, F2 Component Lead Pitch 0.0945 0.110 2.4 2.8
HBottom of Component to Seating Plane .059 .156 1.5 4.0
H1 Feedhole Location 0.3346 0.3741 8.5 9.5
H2A Deflection Left or Right 0 0.039 0 1.0
H2B Deflection Front or Rear 0 0.051 0 1.0
H4 Feedhole to Bottom of Component 0.7086 0.768 18 19.5
H5 Feedhole to Seating Plane 0.610 0.649 15.5 16.5
LDefective Unit Clipped Dimension 0.3346 0.433 8.5 11
L1 Lead Wire Enclosure 0.09842 2.5
PFeedhole Pitch 0.4921 0.5079 12.5 12.9
P1 Feedhole Center to Center Lead 0.2342 0.2658 5.95 6.75
P2 First Lead Spacing Dimension 0.1397 0.1556 3.55 3.95
TAdhesive Tape Thickness 0.06 0.08 0.15 0.20
T1 Overall Taped Package Thickness 0.0567 1.44
T2 Carrier Strip Thickness 0.014 0.027 0.35 0.65
WCarrier Strip Width 0.6889 0.7481 17.5 19
W1 Adhesive Tape Width 0.2165 0.2841 5.5 6.3
W2 Adhesive Tape Position .0059 0.01968 .15 0.5
NOTES:
1. Maximum alignment deviation between leads not to be greater than 0.2 mm.
2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 1 1 mm.
3. Component lead to tape adhesion must meet the pull test requirements.
4. Maximum non–cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches.
5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive.
6. No more than 1 consecutive missing component is permitted.
7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component.
8. Splices will not interfere with the sprocket feed holes.
2N5060 Series
http://onsemi.com
7
ORDERING & SHIPPING INFORMATION: 2N5060 Series packaging options, Device Suffix
U.S. Europe
Equivalent Shipping Description of TO92 Tape Orientation
2N5060,61,62,64
2N5060,61,62,64RLRA
2N5060,64RLRM 2N5060RL1
Bulk in Box (5K/Box)
Radial Tape and Reel (2K/Reel)
Radial Tape and Fan Fold Box (2K/Box)
N/A, Bulk
Round side of TO92 and adhesive tape visible
Flat side of TO92 and adhesive tape visible
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
R
A
P
J
L
B
K
G
H
SECTION X–X
C
V
D
N
N
XX
SEATING
PLANE DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.45 5.20
B0.170 0.210 4.32 5.33
C0.125 0.165 3.18 4.19
D0.016 0.021 0.407 0.533
G0.045 0.055 1.15 1.39
H0.095 0.105 2.42 2.66
J0.015 0.020 0.39 0.50
K0.500 ––– 12.70 –––
L0.250 ––– 6.35 –––
N0.080 0.105 2.04 2.66
P––– 0.100 ––– 2.54
R0.115 ––– 2.93 –––
V0.135 ––– 3.43 –––
1
STYLE 10:
PIN 1. CATHODE
2. GATE
3. ANODE
TO–92 (TO–226AA)
CASE 029–11
ISSUE AJ
2N5060 Series
http://onsemi.com
8
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “T ypicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Af firmative Action Employer.
PUBLICATION ORDERING INFORMATION
CENTRAL/SOUTH AMERICA:
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–spanish@hibbertco.com
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
001–800–4422–3781
Email: ONlit–asia@hibbertco.com
JAPAN: ON Semiconductor , Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2745
Email: r14525@onsemi.com
ON Semiconductor Website : http://onsemi.com
For additional information, please contact your local
Sales Representative.
2N5060/D
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich T ime)
Email: ONlit–german@hibbertco.com
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy , England, Ireland