UPD75P0016CU - RENESAS TECHNOLOGY

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The mark shows major revised points.

The

PD75P0016 replaces the

PD750008’s internal mask ROM with a one-time PROM and features expanded

ROM capacity.

Because the

PD75P0016 supports programming by users, it is suitable for use in prototype testing for system

development using the

PD750004, 750006, or 750008 products, and for use in small-lot production.

Detailed information about product features and specifications can be found in the following document

PD750008 User's Manual: U10740E

FEATURES

• Compatible with

PD750008

• Memory capacity:

• PROM : 16384 × 8 bits

• RAM : 512 × 4 bits

• Can operate in same power supply voltage as the mask ROM version

PD750008

• VDD = 2.2 to 5.5 V

• Supports QTOP™ microcontroller

Remark QTOP Microcontroller is the general name for a total support service that includes imprinting, marking,

screening, and verifying one-time PROM single-chip microcontrollers offered by NEC Electronics.

ORDERING INFORMATION

Part number Package ROM (× 8 bits)

PD75P0016CU 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 16384

PD75P0016CU-A 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 16384

PD75P0016GB-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) 16384

PD75P0016GB-3BS-MTX-A 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) 16384

Caution On-chip pull-up resistors by mask option cannot be provided.

Remark Products with “-A” at the end of the part number are lead-free products.

PD75P0016

MOS INTEGRATED CIRCUIT

4-BIT SINGLE-CHIP MICROCONTROLLER

Document No. U10328EJ3V3DS00 (3rd edition)

Date Published August 2005 N CP(K)

Printed in Japan

DATA SHEET

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

PD75P0016

2Data Sheet U10328EJ3V3DS

FUNCTION LIST

Item Function

Instruction execution time • 0.95, 1.91, 3.81, 15.3

s (main system clock: at 4.19 MHz operation)

•0.67, 1.33, 2.67, 10.7

s (main system clock: at 6.0 MHz operation)

• 122

s (subsystem clock: at 32.768 kHz operation)

On-chip memory PROM 16384 × 8 bits

RAM 512 × 4 bits

General register • In 4-bit operation: 8 × 4 banks

•In 8-bit operation: 4 × 4 banks

I/O port CMOS input 8 Connection of on-chip pull-up resistor specifiable by software: 7

CMOS I/O 18 Direct LED drive capability

Connection of on-chip pull-up resistor specifiable by software: 18

N-ch open drain I/O 8 Direct LED drive capability

13 V withstand voltage

Total 34

Timer 4 channels

•8-bit timer/event counter: 1 channel

•8-bit timer counter: 1 channel

•Basic interval timer/watchdog timer: 1 channel

•Watch timer: 1 channel

Serial interface • 3-wire serial I/O mode ... Switching of MSB/LSB-first

•2-wire serial I/O mode

•SBI mode

Bit sequential buffer (BSB) 16 bits

Clock output (PCL) • Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)

•Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)

Buzzer output (BUZ) • 2, 4, 32 kHz (main system clock: at 4.19 MHz operation or subsystem clock:

at 32.768 kHz operation)

•2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation)

Vectored interrupt External: 3 Internal: 4

Test input External: 1 Internal: 1

System clock oscillation circuit • Main system clock oscillation ceramic/crystal oscillation circuit

•Subsystem clock oscillation crystal oscillation circuit

Standby function STOP/HALT mode

Operating ambient temperature TA = –40 to +85˚C

Supply voltage VDD = 2.2 to 5.5 V

Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)

PD75P0016

Data Sheet U10328EJ3V3DS

TABLE OF CONTENTS

1. PIN CONFIGURATION ........................................................................................................................ 4

2. BLOCK DIAGRAM ............................................................................................................................. 6

3. PIN FUNCTIONS ................................................................................................................................ 7

3.1 Port Pins ..................................................................................................................................................... 7

3.2 Non-port Pins ............................................................................................................................................. 8

3.3 I/O Circuits for Pins ................................................................................................................................... 9

3.4 Handling of Unused Pins ........................................................................................................................ 11

4. SWITCHING BETWEEN MK I AND MK II MODES .......................................................................... 12

4.1 Differences between Mk I Mode and Mk II Mode ................................................................................... 12

4.2 Setting of Stack Bank Selection (SBS) Register ................................................................................... 13

5. DIFFERENCES BETWEEN

PD75P0016 AND

PD750004, 750006, AND 750008 ...................... 14

6. MEMORY CONFIGURATION ........................................................................................................... 15

7. INSTRUCTION SET .......................................................................................................................... 17

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28

8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 28

8.2 Steps in Program Memory Write Operation .......................................................................................... 29

8.3 Steps in Program Memory Read Operation ........................................................................................... 30

8.4 One-Time PROM Screening .................................................................................................................... 31

9. ELECTRICAL SPECIFICATIONS .....................................................................................................32

10. CHARACTERISTIC CURVES (REFERENCE VALUE) .................................................................... 46

11. PACKAGE DRAWINGS .................................................................................................................... 48

12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50

APPENDIX A. FUNCTION LIST OF

PD75008, 750008, 75P0016 ....................................................... 52

APPENDIX B. DEVELOPMENT TOOLS................................................................................................. 54

APPENDIX C. RELATED DOCUMENTS ................................................................................................ 58

PD75P0016

4Data Sheet U10328EJ3V3DS

P72/KR6 1P13/TI0

P71/KR5 2P00/INT4

P70/KR4 3P01/SCK

P63/KR3 4P02/SO/SB0

P62/KR2 5P03/SI/SB1

P61/KR1 6P80

P60/KR0 7P81

P53/D7 8P30/MD0

P52/D6 9P31/MD1

P51/D5 10 P32/MD2

P50/D4 11 P33/MD3

P73/KR7

P20/PTO0

P43/D3

P21/PTO1

P42/D2

P22/PCL

P41/D1

P23/BUZ

P40/D0

VDD

VSS

VPPNote

XT1

P10/INT0

XT2

P11/INT1

RESET

P12/INT2

1. PIN CONFIGURATION (Top View)

•42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

PD75P0016CU

PD75P0016CU-A

Note Directly connect VPP to VDD in the normal operation mode.

• 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)

PD75P0016GB-3BS-MTX

PD75P0016GB-3BS-MTX-A

Note Directly connect VPP to VDD in the normal operation mode.

XT1 1VSS

XT2 2P40/D0

RESET 3P41/D1

X1 4P42/D2

X2 5P43/D3

P33/MD3 6P50/D4

P32/MD2 7P51/D5

P31/MD1 8P52/D6

P30/MD0 9P53/D7

P81 10 P60/KR0

P80 11 P61/KR1

P03/SI/SB1 12 P62/KR2

P02/SO/SB0 13 P63/KR3

P01/SCK 14 P70/KR4

P00/INT4 15 P71/KR5

P13/TI0 16 P72/KR6

P12/INT2 17 P73/KR7

P11/INT1 18 P20/PTO0

P10/INT0 19 P21/PTO1

VPPNote 20 P22/PCL

VDD 21 P23/BUZ

PD75P0016

Data Sheet U10328EJ3V3DS

PIN IDENTIFICATIONS

P00-P03 : Port0 SCK : Serial Clock

P10-P13 : Port1 SI : Serial Input

P20-P23 : Port2 SO : Serial Output

P30-P33 : Port3 SB0, SB1 : Serial Data Bus 0,1

P40-P43 : Port4 RESET : Reset

P50-P53 : Port5 TI0 : Timer Input 0

P60-P63 : Port6 PTO0, PTO1 : Programmable Timer Output 0, 1

P70-P73 : Port7 BUZ : Buzzer Clock

P80, P81 : Port8 PCL : Programmable Clock

KR0-KR7 : Key Return 0-7 INT0, 1, 4 : External Vectored Interrupt 0, 1, 4

VDD : Positive Power Supply INT2 : External Test Input 2

VSS : Ground X1, X2 : Main System Clock Oscillation 1, 2

VPP : Programming Power Supply XT1, XT2 : Subsystem Clock Oscillation 1, 2

NC : No Connection MD0-MD3 : Mode Selection 0-3

D0-D7 : Data Bus 0-7

PD75P0016

6Data Sheet U10328EJ3V3DS

BIT SEQ.

BUFFER (16)

PORT0 P00-P034

PORT1

PORT2 4

PORT3 P30/MD0-P33/MD34

PORT4 P40/D0-P43/D34

PORT5 P50/D4-P53/D74

PORT6 P60-P634

VSSVDD RESETVPP

CPU CLOCK

STAND BY

CONTROL

X2X1XT2XT1

SYSTEM CLOCK

GENERATOR

MAINSUB

CLOCK

DIVIDER

CLOCK

OUTPUT

CONTROL

fx/2N

PCL/P22

GENERAL

DATA

MEMORY

(RAM)

512 × 4 BITS

BANK

SBS

SP (8)

ALU

PROGRAM

COUNTER (14)

PROGRAM

MEMORY

(PROM)

16384 × 8 BITS DECODE

AND

CONTROL

BASIC INTERVAL

TIMER/

WATCHDOG

TIMER

TI0/P13

INTBT

8-BIT

TIMER/EVENT

COUNTER #0

PTO0/P20

INTT0

8-BIT TIMER

COUNTER

INTT1

CLOCKED

SERIAL

INTERFACE

SI/SB1/P03

INTERRUPT

CONTROL

INT0/P10

SO/SB0/P02

SCK/P01

INT1/P11

INT2/P12

INT4/P00

KR0/P60-

KR7/P73

WATCH

TIMER

8PORT7 P70-P734

PORT8 P80, P812

P10-P134

P20-P23

PTO1/P21

INTCSI

INTW

BUZ/P23

TOUT0

2. BLOCK DIAGRAM

PD75P0016

Data Sheet U10328EJ3V3DS

3. PIN FUNCTIONS

3.1 Port Pins

Pin name I/O Shared by Function 8-bit When I/O circuit

I/O reset type Note 1

P00 I INT4 This is a 4-bit input port (PORT0). ×Input

For P01 to P03, on-chip pull-up resistor connections

P01 I/O SCK are software-specifiable in 3-bit units. <F>-A

P02 I/O SO/SB0 <F>-B

P03 I/O SI/SB1 <M>-C

P10 I INT0 This is a 4-bit input port (PORT1). ×Input -C

On-chip pull-up resistor connections are software-

P11 INT1 specifiable in 4-bit units.

P10/INT0 can select noise elimination circuit.

P12 INT2

P13 TI0

P20 I/O PTO0 This is a 4-bit I/O port (PORT2). ×Input E-B

On-chip pull-up resistor connections are software-

P21 PTO1 specifiable in 4-bit units.

P22 PCL

P23 BUZ

P30 I/O MD0 This is a programmable 4-bit I/O port (PORT3). ×Input E-B

Input and output can be specified in single-bit

P31 MD1 units. On-chip pull-up resistor connections are

software-specifiable in 4-bit units.

P32 MD2

P33 MD3

P40

Note 2 I/O D0 This is an N-ch open-drain 4-bit I/O port (PORT4). High

In the open-drain mode, withstands up to 13 V. impedance M-E

P41

Note 2 D1

P42

Note 2 D2

P43

Note 2 D3

P50

Note 2 I/O D4 This is an N-ch open-drain 4-bit I/O port (PORT5). High

In the open-drain mode, withstands up to 13 V. impedance M-E

P51

Note 2 D5

P52

Note 2 D6

P53

Note 2 D7

P60 I/O KR0 This is a programmable 4-bit I/O port (PORT6). Input <F>-A

Input and output can be specified in single-bit units.

P61 KR1 On-chip pull-up resistor connections are software-

specifiable in 4-bit units.

P62 KR2

P63 KR3

P70 I/O KR4 This is a 4-bit I/O port (PORT7). Input <F>-A

On-chip pull-up resistor connections are software-

P71 KR5 specifiable in 4-bit units.

P72 KR6

P73 KR7

P80 I/O — This is a 2-bit I/O port (PORT8). ×Input E-B

On-chip pull-up resistor connections are software-

P81 — specifiable in 2-bit units.

Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.

2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.

PD75P0016

8Data Sheet U10328EJ3V3DS

3.2 Non-port Pins

Pin name I/O Shared by Function When I/O circuit

reset type Note 1

TI0 I P13 External event pulse input to timer/event counter Input -C

PTO0 O P20 Timer/event counter output Input E-B

PTO1 P21 Timer counter output

PCL P22 Clock output

BUZ P23 Outputs any frequency (for buzzer or system clock trimming)

SCK I/O P01 Serial clock I/O Input <F>-A

SO/SB0 P02 Serial data output <F>-B

Serial data bus I/O

SI/SB1 P03 Serial data input <M>-C

Serial data bus I/O

INT4 I P00 Edge-triggered vectored interrupt input

(Detects both rising and falling edges).

INT0 I P10 Edge-triggered vectored interrupt input With noise eliminator Input -C

(detected edge is selectable). /asynch selectable

INT0/P10 can select noise elimination

INT1 P11 circuit. Asynch

INT2 P12 Rising edge-triggered testable input Asynch

KR0-KR3 I P60-P63 Falling edge-triggered testable input Input <F>-A

KR4-KR7 I P70-P73 Falling edge-triggered testable input Input <F>-A

X1 I — Ceramic/crystal resonator connection for main system clock. — —

If using an external clock, input it to X1 and input the

X2 — inverted clock to X2.

XT1 I — Crystal resonator connection for subsystem clock. — —

If using an external clock, input it to XT1 and input the invert-

XT2 — ed clock to X2. XT1 can be used as a 1-bit (test) input.

RESET I — System reset input (low level active) —

MD0-MD3 I P30-P33 Mode selection for program memory (PROM) write/verify. Input E-B

D0-D3 I/O P40-P43 Data bus pin for program memory (PROM) write/verify. Input M-E

D4-D7 P50-P53

VPP Note 2 —— Programmable voltage supply in program memory (PROM) — —

write/verify mode.

In normal operation mode, connect directly to VDD.

Apply +12.5 V in PROM write/verify mode.

VDD —— Positive power supply — —

VSS —— Ground potential — —

Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.

2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin.

PD75P0016

Data Sheet U10328EJ3V3DS

3.3 I/O Circuits for Pins

The I/O circuits for the

PD75P0016’s pin are shown in schematic diagrams below.

P-ch

N-ch

P-ch

N-ch

OUT

Data

Output

disable

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Type D

Output

disable

P.U.R. : Pull-Up Resistor

Type A

P-ch P.U.R.

enable

P.U.R.

P.U.R. : Pull-Up Resistor

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Type D

Output

disable

P.U.R. : Pull-Up Resistor

Type B

CMOS standard input buffer

Push-pull output that can be set to high impedance output

(with both P-ch and N-ch OFF).

Schmitt trigger input with hysteresis characteristics.

(

Continued

)

TYPE A TYPE D

TYPE E-BTYPE B

TYPE B-C TYPE F-A

PD75P0016

10 Data Sheet U10328EJ3V3DS

P.U.R.

P-ch

P.U.R. : Pull-Up Resistor

data

output

disable

IN/OUT

VDD

P.U.R.

enable

N-ch

TYPE M-E

TYPE M-C

TYPE F-B

P.U.R.

P-ch

IN/OUT

N-ch

P-ch

VDD

P.U.R.

enable

data

output

disable

output

disable

(N)

output

disable

(P)

P.U.R. : Pull-Up Resistor

VDD

N-ch

(+13 V)

IN/OUT

P-ch

VDD

Note Pull-up resistor that operates only when an input

instruction has been executed. (Current flows

from VDD to the pins when at low level)

data

output

disable

Input

instruction

(+13 V)

P.U.R.Note

Voltage

limitation

circuit

PD75P0016

Data Sheet U10328EJ3V3DS

Input mode : individually connect to VSS or VDD

via resistor

Output mode : open

3.4 Handling of Unused Pins

Table 3-1. Handling of Unused Pins

Pin Recommended connection

P00/INT4 Connect to VSS or VDD

P01/SCK Individually connect to VSS or VDD via resistor

P02/SO/SB0

P03/SI/SB1 Connect to VSS

P10/INT0-P12/INT2 Connect to VSS or VDD

P13/TI0

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

P30/MD0-P33/MD3

P40/D0-P43/D3 Connect to VSS

P50/D4-P53/D7

P60/KR0-P63/KR3

P70/KR4-P73/KR7

P80, P81

XT1Note Connect to VSS

XT2Note Open

VPP Make sure to connect directly to VDD

Note When the subsystem clock is not used, set SOS. 0 to 1 (not to use the internal feedback resistor).

Input mode : individually connect to VSS or VDD

via resistor

Output mode : open

PD75P0016

12 Data Sheet U10328EJ3V3DS

4. SWITCHING BETWEEN MK I AND MK II MODES

Setting a stack bank selection (SBS) register for the

PD75P0016 enables the program memory to be switched

between the Mk I mode and the Mk II mode. This capability enables the evaluation of the

PD750004, 750006, or 750008

using the

PD75P0016.

When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of

PD750004, 750006, and 750008)

When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of

PD750004, 750006, and 750008)

4.1 Differences between Mk I Mode and Mk II Mode

Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the

PD75P0016.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Item Mk I mode Mk II mode

Program counter PC13-0

Program memory (bytes) 16384

Data memory (bits) 512 × 4

Stack Stack bank Selectable from memory banks 0 and 1

Stack bytes 2 bytes 3 bytes

Instruction BRA !addr1 None Provided

CALLA !addr1

Instruction CALL !addr 3 machine cycles 4 machine cycles

execution time CALLF !faddr 2 machine cycles 3 machine cycles

Supported mask ROM versions and Mk I mode of

PD750004, 750006, and Mk II mode of

PD750004, 750006, and

mode 750008 750008

Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This

mode enhances the software compatibility with products which have more than 16K bytes.

When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call

instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when

a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle.

Therefore, when more importance is attached to RAM utilization or throughput than software

compatibility, use the Mk I mode.

PD75P0016

Data Sheet U10328EJ3V3DS

SBS3 SBS2 SBS1 SBS0F84H

Address 3 2 1 0

SBS

Symbol

Stack area specification

Memory bank 0

Memory bank 1

0Be sure to set 0 for bit 2.

Mk II mode

Mk I mode

Mode selection specification

Setting prohibited

4.2 Setting of Stack Bank Selection (SBS) Register

Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format

for doing this.

The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode,

be sure to initialize the stack bank selection register to 100×B Note at the beginning of the program. When using the Mk

II mode, be sure to initialize it to 000×B Note.

Note Set the desired value for ×.

Figure 4-1. Format of Stack Bank Selection Register

Caution SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When using

instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the instructions.

PD75P0016

14 Data Sheet U10328EJ3V3DS

5. DIFFERENCES BETWEEN

PD75P0016 AND

PD750004, 750006, AND 750008

The

PD75P0016 replaces the internal mask ROM in the

PD750004, 750006, and 750008 with a one-time PROM

and features expanded ROM capacity. The

PD75P0016’s Mk I mode supports the Mk I mode in the

PD750004, 750006,

and 750008 and the

PD75P0016’s Mk II mode supports the Mk II mode in the

PD750004, 750006, and 750008.

Table 5-2 lists differences among the

PD75P0016 and the

PD750004, 750006, and 750008. Be sure to check the

differences between corresponding versions beforehand, especially when a PROM version is used for debugging or

prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production.

Please refer to the

PD750008 User's Manual (U10740E) for details on CPU functions and on-chip hardware.

Table 5-1. Differences between

PD75P0016 and

PD750004, 750006, and 750008

Item

PD750004

PD750006

PD750008

PD75P0016

Program counter 12-bit 13-bit 14-bit

Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM

4096 6144 8192 16384

Data memory (× 4 bits) 512

Mask options Pull-up resistor for Yes (On-chip/not on-chip can be specified.) No (On-chip not

port 4 and port 5 possible)

Wait time when Yes (217/fx or 215/fx) Note

No (fixed at 2

/fx)

Note

RESET

Feedback resistor Yes (can select usable or unusable.) No (usable)

for subsystem clock

Pin connection Pins 6-9 (CU) P33-P30 P33/MD3-P30/MD0

Pins 23-26 (GB)

Pin 20 (CU) IC VPP

Pin 38 (GB)

Pins 34-37 (CU) P53-P50 P53/D7-P50/D4

Pins 8-11 (GB)

Pins 38-41 (CU) P43-P40 P43/D3-P40/D0

Pins 13-16 (GB)

Other Noise resistance and noise radiation may differ due to the different circuit complexities and

mask layouts.

Note 217/fx : 21.8 ms @ 6.0 MHz, 31.3 ms @ 4.19 MHz

215/fx : 5.46 ms @ 6.0 MHz, 7.81 ms @ 4.19 MHz

Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using

a mask ROM version instead of the PROM version for processes between prototype development and

full production, be sure to fully evaluate the CS of the mask ROM version (not ES).

PD75P0016

Data Sheet U10328EJ3V3DS

6. MEMORY CONFIGURATION

Figure 6-1. Program Memory Map

Note Can be used only at Mk II mode.

Remark For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to

branch to addresses with changes in the PC’s lower 8 bits only.

MBE

RBE

Internal reset start address (higher 6 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (higher 6 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (higher 6 bits)

INT0 start address (lower 8 bits)

INT1 start address (higher 6 bits)

INT1 start address (lower 8 bits)

INTCSI start address (higher 6 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (higher 6 bits)

INTT0 start address (lower 8 bits)

INTT1 start address (higher 6 bits)

INTT1 start address (lower 8 bits)

Reference table for GETI instruction

0000H

0002H

0004H

0006H

0008H

000AH

000CH

0020H

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH

CALLF

!faddr instruction

entry address

Branch address for

the following instructions

Branch/call

address

by GETI

BR $addr instruction

relative branch address

(–15 to –1,

+2 to +16)

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

76 0

• BR BCDE

• BR BCXA

• BR !addr

• CALL !addr

• BRA !addr1

• CALLA !addr1

Note

PD75P0016

16 Data Sheet U10328EJ3V3DS

(32 × 4)

256 × 4

(224 × 4)

256 × 4

128 × 4

000H

01FH

020H

0FFH

100H

1FFH

F80H

FFFH

General

area

Data area

static RAM

(512 × 4)

Stack area

Peripheral hardware area

Data memory Memory bank

Unimplemented

Note

Figure 6-2. Data Memory Map

Note For the stack area, one memory bank can be selected from memory bank 0 or 1.

PD75P0016

Data Sheet U10328EJ3V3DS

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s

operand representations (for further description, refer to the RA75X Assembler Package User’s Manual [EEU-1363]).

When there are several codes, select and use just one. Upper-case letters, and + and – symbols are key words that should

be entered as they are.

For immediate data, enter an appropriate numerical value or label.

Instead of mem, fmem, pmem, bit, etc, a register flag symbol can be described as a label descriptor. (For further

description, refer to the

PD750008 User's Manual [U10740E]) Labels that can be entered for fmem and pmem are

restricted.

Representation Coding format

reg X, A, B, C, D, E, H, L

reg1 X, B, C, D, E, H, L

rp XA, BC, DE, HL

rp1 BC, DE, HL

rp2 BC, DE

rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’

rp’1 BC, DE, HL, XA’, BC’, DE’, HL’

rpa HL, HL+, HL–, DE, DL

rpa1 DE, DL

n4 4-bit immediate data or label

n8 8-bit immediate data or label

mem 8-bit immediate data or label Note

bit 2-bit immediate data or label

fmem FB0H-FBFH, FF0H-FFFH immediate data or label

pmem FC0H-FFFH immediate data or label

addr 0000H-3FFFH immediate data or label

addr1 0000H-3FFFH immediate data or label (in Mk II mode only)

caddr 12-bit immediate data or label

faddr 11-bit immediate data or label

taddr 20H-7FH immediate data (however, bit0 = 0) or label

PORTn PORT0-PORT8

IEXXX IEBT, IECSI, IET0, IET1, IE0-IE2, IE4, IEW

RBn RB0-RB3

MBn MB0, MB1, MB15

Note When processing 8-bit data, only even addresses can be specified.

PD75P0016

18 Data Sheet U10328EJ3V3DS

(2) Operation legend

A: A register; 4-bit accumulator

B: B register

C: C register

D: D register

E: E register

H: H register

L: L register

X: X register

XA : Register pair (XA); 8-bit accumulator

BC : Register pair (BC)

DE : Register pair (DE)

HL : Register pair (HL)

XA’ : Expansion register pair (XA’)

BC’ : Expansion register pair (BC’)

DE’ : Expansion register pair (DE’)

HL’ : Expansion register pair (HL’)

PC : Program counter

SP : Stack pointer

CY : Carry flag; bit accumulator

PSW : Program status word

MBE : Memory bank enable flag

RBE : Register bank enable flag

PORTn : Port n (n = 0 to 8)

IME : Interrupt master enable flag

IPS : Interrupt priority select register

IE××× : Interrupt enable flag

RBS : Register bank select register

MBS : Memory bank select register

PCC : Processor clock control register

.: Delimiter for address and bit

(××): Contents of address ××

××H: Hexadecimal data

PD75P0016

Data Sheet U10328EJ3V3DS

(3) Description of symbols used in addressing area

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

MB = 0 (000H-07FH)

MB = 15 (F80H-FFFH)

MB = MBS

MBS = 0, 1, 15

MB = MBE • MBS

MBS = 0, 1, 15

MB = 0

MBE = 1 :

MBE = 0 :

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

addr = 0000H-3FFFH

addr, addr1 =

*7 (Current PC) –15 to (Current PC) –1

(Current PC) +2 to (Current PC) +16

caddr = 0000H-0FFFH (PC

= 00B) or

1000H-1FFFH (PC

= 01B) or

2000H-2FFFH (PC

= 10B) or

3000H-3FFFH (PC

= 11B)

faddr = 0000H-07FFH

taddr = 0020H-007FH

addr1 = 0000H-3FFFH (Mk II mode only)

*10

*11

Program memory

addressing

Data memory

addressing

PD75P0016

20 Data Sheet U10328EJ3V3DS

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as

shown below.

• No skip .......................................................................... S = 0

• Skipped instruction is 1-byte or 2-byte instruction......... S = 1

• Skipped instruction is 3-byte instruction Note ................. S = 2

Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1

Caution The GETI instruction is skipped for one machine cycle.

One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.

PD75P0016

Data Sheet U10328EJ3V3DS

Group Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

bytes cycle area

condition

Transfer MOV A, # n4 1 1 A ← n4 String-effect A

reg1, # n4 2 2 reg1 ← n4

XA, # n8 2 2 XA ← n8 String-effect A

HL, # n8 2 2 HL ← n8 String-effect B

rp2, # n8 2 2 rp2 ← n8

A, @HL 1 1 A ← (HL) *1

A, @HL+ 1 2 + S A ← (HL), then L ← L + 1 *1 L = 0

A, @HL– 1 2 + S A ← (HL), then L ← L – 1 *1 L = FH

A, @rpa1 1 1 A ← (rpa1) *2

XA, @HL 2 2 XA ← (HL) *1

@HL, A 1 1 (HL) ← A*1

@HL, XA 2 2 (HL) ← XA *1

A, mem 2 2 A ← (mem) *3

XA, mem 2 2 XA ← (mem) *3

mem, A 2 2 (mem) ← A*3

mem, XA 2 2 (mem) ← XA *3

A, reg 2 2 A ← reg

XA, rp’ 2 2 XA ← rp’

reg1, A 2 2 reg1 ← A

rp’1, XA 2 2 rp’1 ← XA

XCH A, @HL 1 1 A ↔ (HL) *1

A, @HL+ 1 2 + S A ↔ (HL), then L ← L + 1 *1 L = 0

A, @HL– 1 2 + S A ↔ (HL), then L ← L – 1 *1 L = FH

A, @rpa1 1 1 A ↔ (rpa1) *2

XA, @HL 2 2 XA ↔ (HL) *1

A, mem 2 2 A ↔ (mem) *3

XA, mem 2 2 XA ↔ (mem) *3

A, reg1 1 1 A ↔ reg1

XA, rp’ 2 2 XA ↔ rp’

Table MOVT XA, @PCDE 1 3 XA ← (PC13-8 + DE)ROM

reference XA, @PCXA 1 3 XA ← (PC13-8 + XA)ROM

XA, @BCDE 1 3 XA ← (BCDE)ROM Note *6

XA, @BCXA 1 3 XA ← (BCXA)ROM Note *6

Note As for the B register, only the lower 2 bits are valid.

PD75P0016

22 Data Sheet U10328EJ3V3DS

Group Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

bytes cycle area

condition

Bit transfer MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4

CY, pmem.@L 2 2 CY ← (pmem7-2 + L3-2.bit(L1-0)) *5

CY, @H + mem.bit 2 2 CY ← (H + mem3-0.bit) *1

fmem.bit, CY 2 2 (fmem.bit) ← CY *4

pmem.@L, CY 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← CY *5

@H + mem.bit, CY 2 2 (H + mem3-0.bit) ← CY *1

Operation ADDS A, #n4 1 1 + S A ← A + n4 carry

XA, #n8 2 2 + S XA ← XA + n8 carry

A, @HL 1 1 + S A ← A + (HL) *1 carry

XA, rp’ 2 2 + S XA ← XA + rp’ carry

rp’1, XA 2 2 + S rp’1 ← rp’1 + XA carry

ADDC A, @HL 1 1 A, CY ← A + (HL) + CY *1

XA, rp’ 2 2 XA, CY ← XA + rp’ + CY

rp’1, XA 2 2 rp’1, CY ← rp’1 + XA + CY

SUBS A, @HL 1 1 + S A ← A – (HL) *1 borrow

XA, rp’ 2 2 + S XA ← XA – rp’ borrow

rp’1, XA 2 2 + S rp’1 ← rp’1 – XA borrow

SUBC A, @HL 1 1 A, CY ← A – (HL) – CY *1

XA, rp’ 2 2 XA, CY ← XA – rp’ – CY

rp’1, XA 2 2 rp’1, CY ← rp’1 – XA – CY

AND A, #n4 2 2 A ← A ^ n4

A, @HL 1 1 A ← A ^ (HL) *1

XA, rp’ 2 2 XA ← XA ^ rp’

rp’1, XA 2 2 rp’1 ← rp’1 ^ XA

OR A, #n4 2 2 A ← A v n4

A, @HL 1 1 A ← A v (HL) *1

XA, rp’ 2 2 XA ← XA v rp’

rp’1, XA 2 2 rp’1 ← rp’1 v XA

XOR A, #n4 2 2 A ← A v n4

A, @HL 1 1 A ← A v (HL) *1

XA, rp’ 2 2 XA ← XA v rp’

rp’1, XA 2 2 rp’1 ← rp’1 v XA

PD75P0016

Data Sheet U10328EJ3V3DS

Group Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

bytes cycle area

condition

Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An

manipulate NOT A 2 2 A ← A

Increment/ INCS reg 1 1 + S reg ← reg + 1 reg = 0

decrement rp1 1 1 + S rp1 ← rp1 + 1 rp1 = 00H

@HL 2 2 + S (HL) ← (HL) + 1 *1 (HL) = 0

mem 2 2 + S (mem) ← (mem) + 1 *3 (mem) = 0

DECS reg 1 1 + S reg ← reg – 1 reg = FH

rp’ 2 2 + S rp’ ← rp’ – 1 rp’ = FFH

Compare SKE reg, #n4 2 2 + S Skip if reg = n4 reg = n4

@HL, #n4 2 2 + S Skip if (HL) = n4 *1 (HL) = n4

A, @HL 1 1 + S Skip if A = (HL) *1 A = (HL)

XA, @HL 2 2 + S Skip if XA = (HL) *1 XA = (HL)

A, reg 2 2 + S Skip if A = reg A = reg

XA, rp’ 2 2 +S Skip if XA = rp’ XA = rp’

Carry flag SET1 CY 1 1 CY ← 1

manipulate CLR1 CY 1 1 CY ← 0

SKT CY 1 1 + S Skip if CY = 1 CY = 1

NOT1 CY 1 1 CY ← CY

PD75P0016

24 Data Sheet U10328EJ3V3DS

Group Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

bytes cycle area

condition

Memory bit SET1 mem.bit 2 2 (mem.bit) ← 1*3

manipulate fmem.bit 2 2 (fmem.bit) 1 *4

pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) 1 *5

@H + mem.bit 2 2 (H + mem3-0.bit) ← 1*1

CLR1 mem.bit 2 2 (mem.bit) 0 *3

fmem.bit 2 2 (fmem.bit) 0 *4

pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) 0 *5

@H + mem.bit 2 2 (H + mem3-0.bit) ← 0*1

SKT mem.bit 2 2 + S Skip if(mem.bit) = 1 *3 (mem.bit) = 1

fmem.bit 2 2 + S Skip if(fmem.bit) = 1 *4 (fmem.bit) = 1

pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 *5 (pmem.@L) = 1

@H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 1 *1

(@H + mem.bit) = 1

SKF mem.bit 2 2 + S Skip if(mem.bit) = 0 *3 (mem.bit) = 0

fmem.bit 2 2 + S Skip if(fmem.bit) = 0 *4 (fmem.bit) = 0

pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 0 *5 (pmem.@L) = 0

@H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 0 *1

(@H + mem.bit) = 0

SKTCLR fmem.bit 2 2 + S Skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1

pmem.@L 2 2 + S

Skip if(pmem7-2 + L3-2.bit (L1-0)) = 1 and clear

*5 (pmem.@L) = 1

@H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 1 and clear *1

(@H + mem.bit) = 1

AND1 CY, fmem.bit 2 2 CY ← CY ^ (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY ^ (pmem7-2 + L3-2.bit(L1-0)) *5

CY, @H + mem.bit 2 2 CY ← CY ^ (H + mem3-0.bit) *1

OR1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY v (pmem7-2 + L3-2.bit(L1-0)) *5

CY, @H + mem.bit 2 2 CY ← CY v (H + mem3-0.bit) *1

XOR1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY v (pmem7-2 + L3-2.bit(L1-0)) *5

CY, @H + mem.bit 2 2 CY ← CY v (H + mem3-0.bit) *1

←

PD75P0016

Data Sheet U10328EJ3V3DS

Group Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

bytes cycle area

condition

Branch BR Note 1 addr — — PC13-0 ← addr *6

Assembler selects the most

appropriate instruction among

the following:

• BR !addr

• BRCB !caddr

• BR $addr

addr1 — — PC13-0 ← addr1 *11

Assembler selects the most

appropriate instruction among

the following:

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

!addr 3 3 PC13-0 ← addr *6

$addr 1 2 PC13-0 ← addr *7

$addr1 1 2 PC13-0 ← addr1

PCDE 2 3 PC13-0 ← PC13-8 + DE

PCXA 2 3 PC13-0 ← PC13-8 + XA

BCDE 2 3 PC13-0 ← BCDE Note 2 *6

BCXA 2 3 PC13-0 ← BCXA Note 2 *6

BRA Note 1 !addr1 3 3 PC13-0 ← addr1 *11

BRCB !caddr 2 2 PC13-0 ← PC13, 12 + caddr11-0 *8

Notes 1. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

2. As for the B register, only the lower 2 bits are valid.

PD75P0016

26 Data Sheet U10328EJ3V3DS

Group Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

bytes cycle area

condition

Subroutine CALLA Note !addr1 3 3 (SP – 5) ← 0, 0, PC13,12 *11

stack control (SP – 6)(SP – 3)(SP – 4) ← PC11-0

(SP – 2)

←

×, ×, MBE, RBE

PC13–0

←

addr1, SP

←

SP – 6

CALL Note !addr 3 3 (SP

–

4)(SP

–

1)(SP

–

←

PC11-0 *6

(SP

–

←

(MBE, RBE, PC13, 12)

PC13–0

←

addr, SP

←

SP – 4

4(SP – 5) ← 0, 0, PC13,12

(SP – 6)(SP – 3)(SP – 4) ← PC11-0

(SP

–

←

×, ×, MBE, RBE

PC13-0

←

addr, SP

←

–

CALLF Note !faddr 2 2 (SP

–

4)(SP

–

1)(SP

–

←

PC11-0 *9

(SP

–

←

(MBE, RBE, PC13, 12)

PC13-0

←

000 + faddr, SP

←

SP – 4

3(SP – 5) ← 0, 0, PC13,12

(SP – 6)(SP – 3)(SP – 4) ← PC11-0

(SP – 2)

←

×, ×, MBE, RBE

PC13-0

←

000 + faddr,SP

←

SP – 6

RET Note 13(MBE, RBE, PC13, 12)

←

(SP + 1)

PC11-0

→ (SP)(SP + 3)(SP + 2)

←

SP + 4

×, ×, MBE, RBE

←

(SP + 4)

0, 0, PC13-12

←

(SP + 1)

PC11-0

←

(SP)(SP + 3)(SP + 2)

←

SP + 6

RETS Note 13 + S (MBE, RBE, PC13, 12)

←

(SP + 1) Unconditional

PC11-0

←

(SP)(SP + 3)(SP + 2)

←

SP + 4

then skip unconditionally

×, ×, MBE, RBE

←

(SP + 4)

0, 0, PC13-12

←

(SP + 1)

PC11-0

←

(SP)(SP + 3)(SP + 2)

←

SP + 6

then skip unconditionally

RETI Note 13MBE, RBE, PC13, 12

←

(SP + 1)

PC11-0

←

(SP)(SP + 3)(SP + 2)

PSW

←

(SP + 4)(SP + 5), SP

←

SP + 6

0, 0, PC13, 12

←

(SP + 1)

PC11-0

←

(SP)(SP + 3)(SP + 2)

PSW

←

(SP + 4)(SP + 5), SP

←

SP + 6

Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

PD75P0016

Data Sheet U10328EJ3V3DS

- - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Group Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

bytes cycle area

condition

Subroutine PUSH rp 1 1 (SP – 1)(SP – 2)

←

rp, SP

←

SP – 2

stack control BS 2 2

(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2

POP rp 1 1 rp

←

(SP + 1)(SP), SP

←

SP + 2

BS 2 2

MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2

Interrupt EI 2 2 IME(IPS.3)

←

control IE××× 22IE×××

←

DI 2 2 IME(IPS.3)

←

IE××× 22IE×××

←

I/O IN Note 1 A, PORTn 2 2 A

←

PORTn (n = 0 - 8)

XA, PORTn 2 2 XA

←

PORTn+1, PORTn (n = 4, 6)

OUT Note 1 PORTn, A 2 2 PORTn

←

A (n = 2 - 8)

PORTn, XA 2 2 PORTn+1, PORTn

←

XA (n = 4, 6)

CPU control HALT 2 2 Set HALT Mode(PCC.2

←

STOP 2 2 Set STOP Mode(PCC.3

←

NOP 1 1 No Operation

Special SEL RBn 2 2 RBS

←

n (n = 0 - 3)

MBn 2 2 MBS

←

n (n = 0, 1, 15)

GETI

Note 2, 3

taddr 1 3 • When using TBR instruction *10

PC13-0

←

(taddr)5-0 + (taddr + 1)

• When using TCALL instruction

(SP – 4)(SP – 1)(SP – 2)

←

PC11-0

(SP – 3)

←

MBE, RBE, PC13, 12

PC13-0

←

(taddr)5-0 + (taddr + 1)

←

SP – 4

• When using instruction other than Determined by

TBR or TCALL referenced

Execute (taddr)(taddr + 1) instructions instruction

13• When using TBR instruction *10

PC13-0

←

(taddr)5-0 + (taddr + 1)

4• When using TCALL instruction

(SP – 5)

←

0, 0, PC13, 12

(SP – 6)(SP – 3)(SP – 4)

←

PC11-0

(SP

–

←

×, ×, MBE, RBE

PC13-0

←

(taddr)5-0 + (taddr + 1)

←

SP – 6

3• When using instruction other than Determined by

TBR or TCALL referenced

Execute (taddr)(taddr + 1) instructions instruction

Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.

2. TBR and TCALL are assembler directives for the GETI instruction’s table definitions.

3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

PD75P0016

28 Data Sheet U10328EJ3V3DS

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory in the

PD75P0016 is a 16384 × 8-bit electronic write-enabled one-time PROM. The pins listed

in the table below are used for this PROM’s write/verify operations. Clock input from the X1 pins is used instead of address

input as a method for updating addresses.

Pin name Function

VPP Pin (usually VDD) where programming voltage is applied during

program memory write/verify

X1, X2 Clock input pin for address updating during program memory

write/verify. Input the X1 pin’s inverted signal to the X2 pin.

MD0/P30-MD3/P33 Operation mode selection pin for program memory write/verify

D0/P40-D3/P43 (lower 4) 8-bit data I/O pin for program memory write/verify

D4/P50-D7/P53 (higher 4)

VDD Pin where power supply voltage is applied. Power voltage

range for normal operation is 2.2 to 5.5 V. Apply 6.0 V for

program memory write/verify.

Caution Pins not used for program memory write/verify should be processed as follows.

• All unused pins except XT2 ...... Connect to Vss via a pull-down resistor

• XT2 pin ........................................ Leave open

8.1 Operation Modes for Program Memory Write/Verify

When +6 V is applied to the

PD75P0016’s VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes

are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown

below.

Operation mode specification Operation mode

VPP VDD MD0 MD1 MD2 MD3

+12.5 V +6 V H L H L Zero-clear program memory address

LHHHWrite mode

LLHHVerify mode

H×HHProgram inhibit mode

Remark ×: L or H

PD75P0016

Data Sheet U10328EJ3V3DS

VPP

VDD

VDD + 1

VDD

VPP

VDD

D0/P40-D3/P43

D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

X repetitions

Write Verify Additional

write Address increment

Data input

Data output

Data input

8.2 Steps in Program Memory Write Operation

High-speed program memory write can be executed via the following steps.

(1) Pull down unused pins to VSS via resistors. Set the X1 pin to low.

(2) Apply +5 V to the VDD and VPP pins.

(3) Wait 10

(4) Zero-clear mode for program memory addresses.

(5) Apply +6 V to VDD and +12.5 V power to VPP.

(6) Write data using 1-ms write mode.

(7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7).

(8) X [= number of write operations from steps (6) and (7)] × 1 ms additional write

(9) 4 pulse inputs to the X1 pin updates (increments +1) the program memory address.

(10) Repeat steps (6) to (9) until the last address is completed.

(11) Zero-clear mode for program memory addresses.

(12) Apply +5 V to the VDD and VPP pins.

(13) Power supply OFF

The following diagram illustrates steps (2) to (9).

PD75P0016

30 Data Sheet U10328EJ3V3DS

8.3 Steps in Program Memory Read Operation

The

PD75P0016 can read out the program memory contents via the following steps.

(1) Pull down unused pins to VSS via resistors. Set the X1 pin to low.

(2) Apply +5 V to the VDD and VPP pins.

(3) Wait 10

(4) Zero-clear mode for program memory addresses.

(5) Apply +6 V power to VDD and +12.5 V to VPP.

(6) Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based

on a cycle of four pulse inputs.

(7) Zero-clear mode for program memory addresses.

(8) Apply +5 V power to the VDD and VPP pins.

(9) Power supply OFF

The following diagram illustrates steps (2) to (7).

+ 1

D0/P40-D3/P43

D4/P50-D7/P53 Data output Data output

MD0/P30

MD2/P32

MD3/P33

MD1/P31 “L”

PD75P0016

Data Sheet U10328EJ3V3DS

8.4 One-Time PROM Screening

Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC Electronics. Therefore, NEC

Electronics recommends the screening process, that is, after the required data is written to the PROM and the PROM is

stored under the high- temperature conditions shown below, the PROM should be verified.

Storage temperature Storage time

125˚C 24 hours

At present, a fee is charged by NEC Electronics for one-time PROM after-programming imprinting, screening, and

verify service for the QTOP Microcontroller. For details, contact an NEC Electronics sales representative.

PD75P0016

32 Data Sheet U10328EJ3V3DS

9. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25˚C)

Parameter Symbol Conditions Ratings Unit

Supply voltage VDD –0.3 to + 7.0 V

PROM supply voltage VPP –0.3 to + 13.5 V

Input voltage VI1 Other than port 4, 5 –0.3 to VDD + 0.3 V

VI2 Port 4, 5 (N-ch open drain) –0.3 to + 14 V

Output voltage VO–0.3 to VDD + 0.3 V

High-level output current IOH Per pin –10 mA

Total of all pins –30 mA

Low-level output current IOL Per pin 30 mA

Total of all pins 220 mA

Operating ambient TA–40 to + 85 ˚C

temperature

Storage temperature Tstg –65 to + 150 ˚C

Caution If the absolute maximum rating of even one of the parameters is exceeded even momentarily,

the quality of the product may be degraded. The absolute maximum ratings are therefore values

which, when exceeded, can cause the product to be damaged. Be sure that these values are

never exceeded when using the product.

Capacitance (TA = 25˚C, VDD = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input capacitance CIN f = 1 MHz 15 pF

Output capacitance COUT Pins other than tested pins: 0 V 15 pF

I/O capacitance CIO 15 pF

PD75P0016

Data Sheet U10328EJ3V3DS

Main System Clock Oscillation Circuit Characteristics (TA = – 40 to +85˚C)

Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit

constants

Ceramic Oscillation frequency VDD = 2.2 to 5.5 V 1.0

6.0

Note 2

MHz

resonator (fX) Note 1

Oscillation After VDD has 4 ms

stabilization time Note 3 reached MIN. value of

oscillation voltage

range

Crystal Oscillation frequency VDD = 2.2 to 5.5 V 1.0

6.0

Note 2

MHz

resonator (fX) Note 1

Oscillation VDD = 4.5 to 5.5 V 10 ms

stabilization time Note 3

VDD = 2.2 to 5.5 V 30 ms

External X1 input frequency VDD = 1.8 to 5.5 V 1.0

6.0

Note 4

MHz

clock (fX) Note 1

X1 input high-, VDD = 1.8 to 5.5 V 83.3 500 ns

low-level widths

(tXH, tXL)

Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation

circuit only. For the instruction execution time, refer to AC Characteristics.

2. If the oscillation frequency is 4.7 MHz < fX ≤ 6.0 MHz at 2.2 V ≤ VDD < 2.7 V of the supply voltage, please

do not set processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle is less than

0.85

s, falling short of the rated value of 0.85

3. The oscillation stablilization time is the time required for oscillation to be stabilized after VDD has been

applied or STOP mode has been released.

4. If the X1 input frequency is 4.19 MHz < fx ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V of the supply voltage, please

do not set PCC = 0011. If PCC = 0011, one machine cycle time is less than 0.95

s, falling short of the

rated value of 0.95

Caution When using the main system clock oscillation circuit, wire the portion enclosed in the dotted

line in the above figure as follows to prevent adverse influences due to wiring capacitance:

·Keep the wiring length as short as possible.

·Do not cross the wiring with other signal lines.

·Do not route the wiring in the vicinity of a line through which a high alternating current flows.

·Always keep the ground point of the capacitor of the oscillation circuit at the same potential

as VDD.

Do not ground to a power supply pattern through which a high current flows.

·Do not extract signals from the oscillation circuit.

X1 X2

C1 C2

X1 X2

C1 C2

X1 X2

PD75P0016

34 Data Sheet U10328EJ3V3DS

XT1 XT2

Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85˚C)

Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit

constants

Crystal Oscillation frequency VDD = 2.2 to 5.5 V 32 32.768 35 kHz

resonator (fXT) Note 1

Oscillation VDD = 4.5 to 5.5 V 1.0 2 s

stabilization time Note 2

VDD = 2.2 to 5.5 V 10 s

External XT1 input frequency VDD = 1.8 to 5.5 V 32 100 kHz

clock (fXT) Note 1

XT1 input high-, VDD = 1.8 to 5.5 V 5 15

low-level widths

(tXTH, tXTL)

Notes 1. The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the

instruction execution time, refer to AC Characteristics.

2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been

applied.

Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line

in the above figure as follows to prevent adverse influences due to wiring capacitance:

·Keep the wiring length as short as possible.

·Do not cross the wiring with other signal lines.

·Do not route the wiring in the vicinity of a line through which a high alternating current flows.

·Always keep the ground point of the capacitor of the oscillation circuit at the same potential

as VDD.

Do not ground to a power supply pattern through which a high current flows.

·Do not extract signals from the oscillation circuit.

The subsystem clock oscillation circuit has a low amplification factor to reduce current

dissipation and is more susceptible to noise than the main system clock oscillation circuit.

Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit.

RECOMMENDED OSCILLATION CIRCUIT CONSTANT

Main System Clock: Ceramic Resonator (TA = –40 to +85˚C)

Oscillation Circuit Oscillation Voltage

Manufacturer Part Number Frequency Constant (pF) Range (VDD)Remark

(MHz) C1 C2 MIN. (V) MAX. (V)

TDK Corp. CCR4.0MC32 4.0 10 10 2.3 5.5 —

Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable

oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit

requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency

of the resonator in the application circuit. For this, it is necessary to directly contact the

manufacturer of the resonator being used.

XT1 XT2

C3 C4

PD75P0016

Data Sheet U10328EJ3V3DS

DC Characteristics (TA = –40 to + 85˚C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Low-level IOL Per pin 15 mA

output current Total of all pins 150 mA

High-level input VIH1 Ports 2, 3, 8 2.7 ≤ VDD ≤ 5.5 V 0.7 VDD VDD V

voltage 2.2 ≤ VDD ≤ 2.7 V 0.9 VDD VDD V

VIH2 Ports 0, 1, 6, 7, RESET 2.7 ≤ VDD ≤ 5.5 V 0.8 VDD VDD V

2.2 ≤ VDD ≤ 2.7 V 0.9 VDD VDD V

VIH3 Ports 4, 5 (N-ch open drain) 2.7 ≤ VDD ≤ 5.5 V 0.7 VDD 13 V

2.2 ≤ VDD ≤ 2.7 V 0.9 VDD 13 V

VIH4 X1, XT1 VDD–0.1 VDD V

Low-level input VIL1 Ports 2-5, 8 2.7 ≤ VDD ≤ 5.5 V 0 0.3 VDD V

voltage 2.2 ≤ VDD ≤ 2.7 V 0 0.1 VDD V

VIL2 Ports 0, 1, 6, 7, RESET 2.7 ≤ VDD ≤ 5.5 V 0 0.2 VDD V

2.2 ≤ VDD ≤ 2.7 V 0 0.1 VDD V

VIL3 X1, XT1 0 0.1 V

High-level output VOH SCK, SO, ports 2, 3, 6-8 VDD–0.5 V

voltage IOH = –1.0 mA

Low-level output VOL1 SCK, SO, IOL = 15 mA, VDD = 4.5 to 5.5 V 0.2 2.0 V

voltage ports 2-8 IOL = 1.6 mA 0.4 V

VOL2 SB0, SB1 N-ch open drain 0.2 VDD V

Pull-up resistor ≥ 1 kΩ

High-level input ILIH1 VIN = VDD Pins other than X1 and XT1 3

leakage current ILIH2 X1, XT1 20

ILIH3 VIN = 13 V Ports 4, 5 (N-ch open drain) 20

Low-level input ILIL1 VIN = 0 V Pins other than ports 4, 5, X1 and XT1 –3

leakage current ILIL2 X1, XT1 –20

ILIL3 Ports 4, 5 (N-ch open drain) When –3

input instruction is not executed

Ports 4, 5 (N-ch –30

open drain)

When input VDD = 5.0 V –10 –27

instruction is

VDD = 3.0 V –3 –8

executed

High-level output ILOH1 VOUT = VDD SCK, SO/SB0, SB1, Ports 2, 3, 6-8 3

leakage current ILOH2

VOUT = 13 V

Ports 4, 5 (N-ch open drain) 20

Low-level output ILOL VOUT = 0 V –3

leakage current

Internal pull-up RLVIN = 0 V Ports 0-3, 6-8 (except P00 pin) 50 100 200 kΩ

resistor

PD75P0016

36 Data Sheet U10328EJ3V3DS

DC Characteristics (TA = –40 to + 85˚C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply current

Note 1

IDD1 VDD = 5.0 V ± 10 %

Note 3

3.7 11.0 mA

VDD = 3.0 V ± 10 %

Note 4

0.73 2.2 mA

IDD2 VDD = 5.0 V ± 10 % 0.92 2.6 mA

VDD = 3.0 V ± 10 % 0.3 0.9 mA

IDD1 VDD = 5.0 V ± 10 %

Note 3

2.7 8.0 mA

VDD = 3.0 V ± 10 %

Note 4

0.57 1.7 mA

IDD2 VDD = 5.0 V ± 10 % 0.9 2.5 mA

VDD = 3.0 V ± 10 % 0.28 0.8 mA

IDD3 VDD = 3.0 V ± 10 % 42 126

VDD = 2.5 V ± 10 % 23 69

VDD = 3.0 V, TA = 25 ˚C 42 84

VDD = 3.0 V ± 10 % 39 117

VDD = 3.0 V, TA = 25 ˚C 39 78

IDD4

VDD = 3.0 V ± 10 %

8.5 25

VDD = 2.5 V ± 10 %

5.0 15

VDD = 3.0 V, TA = 25 ˚C

8.5 17

VDD = 3.0 V ± 10 %

3.5 12

VDD = 3.0 V, TA = 25 ˚C

3.5 7

IDD5 VDD = 5.0 V ± 10 % 0.05 10

VDD = 3.0 V ± 10 % 0.02 5

TA = 25 ˚C 0.02 3

Notes 1. The current flowing through the internal pull-up resistor is not included.

2. Including the case when the subsystem clock oscillates.

3. When the device operates in high-speed mode with the processor clock control register (PCC) set to

0011.

4. When the device operates in low-speed mode with PCC set to 0000.

5. When the device operates on the subsystem clock, with the system clock control register (SCC) set to

1001 and oscillation of the main system clock stopped.

6. When the suboscillation circuit control register (SOS) is set to 0000.

7. When SOS is set to 0010.

8. When SOS is set to 00×1, and the suboscillation circuit feedback resistor is not used (×: don’t care).

6.0 MHz

Note 2

crystal oscillation

C1 = C2

= 22 pF

4.19 MHz

Note 2

crystal oscillation

C1 = C2

= 22 pF

Low current

consumption

mode

Note 7

Low current

dissipation

mode

Note 7

XT1 = 0V

Note 8

STOP

mode

32.768

kHz

Note 5

crystal oscillation

HALT

mode

HALT

mode

HALT

mode

Low-

voltage

mode

Note 6

Low-

voltage

mode

Note 6

PD75P0016

Data Sheet U10328EJ3V3DS

AC Characteristics (TA = –40 to + 85˚C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

CPU clock cycle tCY VDD = 2.7 to 5.5 V 0.67 64

timeNote 1 0.85 64

(minimum instruction VDD = 2.7 to 5.5 V 0.67 64

execution time = 1 VDD = 1.8 to 5.5 V 0.95 64

machine cycle) Operates with subsystem clock 114 122 125

TI0 input frequency fTI VDD = 2.7 to 5.5 V 0 1.0 MHz

0275 kHz

TI0 high-, low-level tTIH, tTIL VDD = 2.7 to 5.5 V 0.48

widths 1.8

Interrupt input high-, tINTH,INT0 IM02 = 0 Note 2

low-level widths tINTL IM02 = 1 10

INT1, 2, 4 10

KR0-KR7 10

RESET low-level width

tRSL 10

Notes 1. The cycle time of the CPU clock (Φ) is determined by the oscillation frequency of the connected resonator

(and external clock), the system clock control register (SCC), and processor clock control register (PCC).

The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device

operates with the main system clock.

2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).

with external

clock

with ceramic

oscillator or

crystal resonator

Operates with

main system

clock

0.5 0

Supply voltage V

[V]

Cycle time t

( s)

12 3456

(with main system clock)

vs V

0.95

0.85

0.67

1.8 2.2 2.7

5.5

Operation guaranteed range

Remark Shaded area indicates o

eration when external clock is used.

PD75P0016

38 Data Sheet U10328EJ3V3DS

Serial Transfer Operation

2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85°C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY1 VDD = 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-, low-level widths tKL1,VDD = 2.7 to 5.5 V

tKCY1/2–50

tKH1

tKCY1/2–150

SINote 1 setup time tSIK1 VDD = 2.7 to 5.5 V 150 ns

(vs. SCK ↑)500 ns

SINote 1 hold time tKSI1 VDD = 2.7 to 5.5 V 400 ns

(vs. SCK ↑)600 ns

SCK ↓ → SONote 1 output tKSO1 RL = 1 kΩNote 2 VDD = 2.7 to 5.5 V 0 250 ns

delay time CL = 100 pF 0 1000 ns

Notes 1. Read as SB0 or SB1 when using the 2-wire serial I/O mode.

2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.

2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85°C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY2 VDD = 2.7 to 5.5 V 800 ns

3200 ns

SCK high-, low-level widths tKL2,VDD = 2.7 to 5.5 V 400 ns

tKH2 1600 ns

SINote 1 setup time tSIK2 VDD = 2.7 to 5.5 V 100 ns

(vs. SCK ↑)150 ns

SINote 1 hold time tKSI2 VDD = 2.7 to 5.5 V 400 ns

(vs. SCK ↑)600 ns

SCK ↓ → SONote 1 output tKSO2 RL = 1 kΩ Note 2 VDD = 2.7 to 5.5 V 0 300 ns

delay time CL = 100 pF 0 1000 ns

Notes 1. Read as SB0 or SB1 when using the 2-wire serial I/O mode.

2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.

PD75P0016

Data Sheet U10328EJ3V3DS

SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85°C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY3 VDD = 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-, low-level widths tKL3 VDD = 2.7 to 5.5 V

tKCY3/2–50

tKH3

tKCY3/2–150

SB0, 1 setup time tSIK3 VDD = 2.7 to 5.5 V 150 ns

(vs. SCK ↑)500 ns

SB0, 1 hold time (vs. SCK ↑)tKSI3 tKCY3/2 ns

SCK ↓ → SB0, 1 output tKSO3 RL = 1 kΩ Note VDD = 2.7 to 5.5 V 0 250 ns

delay time CL = 100 pF 0 1000 ns

SCK ↑ → SB0, 1 ↓tKSB tKCY3 ns

SB0, 1 ↓ → SCK ↓tSBK tKCY3 ns

SB0, 1 low-level width tSBL tKCY3 ns

SB0, 1 high-level width tSBH tKCY3 ns

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.

SBI mode (SCK ··· external clock input (slave)): (TA = –40 to +85°C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY4 VDD = 2.7 to 5.5 V 800 ns

3200 ns

SCK high-, low-level widths tKL4 VDD = 2.7 to 5.5 V 400 ns

tKH4 1600 ns

SB0, 1 setup time tSIK4 VDD = 2.7 to 5.5 V 100 ns

(vs. SCK ↑)150 ns

SB0, 1 hold time (vs. SCK ↑)tKSI4 tKCY4/2 ns

SCK ↓ → SB0, 1 output tKSO4 RL = 1 kΩ Note VDD = 2.7 to 5.5 V 0 300 ns

delay time CL = 100 pF 0 1000 ns

SCK ↑ → SB0, 1 ↓tKSB tKCY4 ns

SB0, 1 ↓ → SCK ↓tSBK tKCY4 ns

SB0, 1 low-level width tSBL tKCY4 ns

SB0, 1 high-level width tSBH tKCY4 ns

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.

PD75P0016

40 Data Sheet U10328EJ3V3DS

(MIN.)

(MAX.)

(MIN.)

(MAX.)

(MIN.)

(MAX.)

(MIN.)

(MAX.)

AC Timing Test Points (except X1 and XT1 inputs)

Clock timing

TI0 timing

1/f

TIL

TIH

TI0

1/f

– 0.1 V

0.1 V

X1 input

1/f

XTL

XTH

– 0.1 V

0.1 V

XT1 input

PD75P0016

Data Sheet U10328EJ3V3DS

Serial Transfer Timing

3-wire serial I/O mode

2-wire serial I/O mode

SCK

SB0, 1

tKCY1, 2

tKL1, 2 tKH1, 2

tKSO1, 2

tSIK1, 2 tKSI1, 2

KCY1, 2

SCK

Output data

Input data

SIK1, 2

KSO1, 2

KL1, 2

KH1, 2

KSI1, 2

PD75P0016

42 Data Sheet U10328EJ3V3DS

Serial Transfer Timing

Bus release signal transfer

Command signal transfer

Interrupt input timing

RESET input timing

SCK

SB0, 1

tKCY3, 4

tSIK3, 4

tKSO3, 4

tKSI3, 4tSBKtSBHtSBLtKSB

tKH3, 4tKL3, 4

SCK

SB0, 1

tKCY3, 4

tSIK3, 4

tKSO3, 4

tKL3, 4 tKH3, 4

tKSI3, 4tSBKtKSB

INT0, 1, 2, 4

KR0-7

INTL

INTH

RESET

tRSL

PD75P0016

Data Sheet U10328EJ3V3DS

STOP mode

Data retention mode

Internal reset operation

Operation mode

STOP instruction execution

HALT mode

VDD

RESET

tWAIT

tSREL

STOP mode

Data retention mode

Operation mode

HALT mode

SREL

WAIT

STOP instruction execution

Standby release signal

(interrupt request)

Data Retention Characteristics of Data Memory in STOP Mode and at Low Supply Voltage

(TA = –40 to +85˚C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Release signal setup time tSREL 0

Oscillation stabilization tWAIT Released by RESET 215/fxms

wait time Note 1 Released by interrupt request Note 2 ms

Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent

unstable operation when oscillation is started.

2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)

BTM3 BTM2 BTM1 BTM0 Wait Time

fx = 4.19 MHz fx = 6.0 MHz

–0002

20/fx (approx. 250 ms) 220/fx (approx. 175 ms)

–0112

17/fx (approx. 31.3 ms) 217/fx (approx. 21.8 ms)

–1012

15/fx (approx. 7.81 ms) 215/fx (approx. 5.46 ms)

–1112

13/fx (approx. 1.95 ms) 213/fx (approx. 1.37 ms)

Data retention timing (when STOP mode released by RESET)

Data retention timing (standby release signal: when STOP mode released by interrupt signal)

PD75P0016

44 Data Sheet U10328EJ3V3DS

DC Programming Characteristics (TA = 25 ± 5°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input voltage, high VIH1 Other than X1, X2 pins 0.7 VDD VDD V

VIH2 X1, X2

VDD – 0.5

VDD V

Input voltage, low VIL1 Other than X1, X2 pins 0 0.3 VDD V

VIL2 X1, X2 0 0.4 V

Input leakage current ILI VIN = VIL or VIH 10

Output voltage, high VOH IOH = – 1 mA

VDD – 1.0

Output voltage, low VOL IOL = 1.6 mA 0.4 V

VDD supply current IDD 30 mA

VPP supply current IPP MD0 = VIL, MD1 = VIH 30 mA

Cautions 1. Keep VPP to within +13.5 V, including overshoot.

2. Apply VDD before VPP and turn it off after VPP.

AC Programming Characteristics (TA = 25 ± 5°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)

Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit

Address setup time Note 2 tAS tAS 2

(vs. MD0 ↓)

MD1 setup time (vs. MD0 ↓)tM1S tOES 2

Data setup time (vs. MD0 ↓)tDS tDS 2

Address hold time Note 2 tAH tAH 2

(vs. MD0 ↑)

Data hold time (vs. MD0 ↑)tDH tDH 2

MD0 ↑ → data output float tDF tDF 0130 ns

delay time

VPP setup time (vs. MD3 ↑)tVPS tVPS 2

VDD setup time (vs. MD3 ↑)tVDS tVCS 2

Initial program pulse width tPW tPW 0.95 1.0 1.05 ms

Additional program pulse width

tOPW tOPW 0.95 21.0 ms

MD0 setup time (vs. MD1 ↑)tM0S tCES 2

MD0 ↓ → data output delay time

tDV tDV MD0 = MD1 = VIL 1

MD1 hold time (vs. MD0 ↑)tM1H tOEH tM1H + tM1R ≥ 50

MD1 recovery time (vs. MD0 ↓)

tM1R tOR 2

Program counter reset time tPCR —10

X1 input high-, low-level width

tXH, tXL —0.125

X1 input frequency fX—4.19 MHz

Initial mode set time t1—2

MD3 setup time (vs. MD1 ↑)tM3S —2

MD3 hold time (vs. MD1 ↓)tM3H —2

MD3 setup time (vs. MD0 ↓)tM3SR —When program memory is read 2

Address Note 2 → data output tDAD tACC When program memory is read 2

delay time

Address Note 2 → data output tHAD tOH When program memory is read 0 130 ns

hold time

MD3 hold time (vs. MD0 ↑)tM3HR —When program memory is read 2

MD3 ↓ → data output float tDFR —When program memory is read 2

delay time

Notes 1. Symbol of corresponding

PD27C256A

2. The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not

connected to a pin.

PD75P0016

Data Sheet U10328EJ3V3DS

D0/P40-D3/P43

D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

Data output

VPS

VDS

DAD

HAD

DFR

M3HR

PCR

M3SR

Data output

D0/P40-D3/P43

D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

Data input

VPS

VDS

M1R

M0S

OPW

M1S

M1H

PCR

tM3S

M3H

Data input Data input

Data output

Program Memory Write Timing

Program Memory Read Timing

PD75P0016

46 Data Sheet U10328EJ3V3DS

10. CHARACTERISTICS CURVES (REFERENCE VALUE)

5.0

1.0

0.5

0.1

0.05

0.01

0.005

0.00101234

Volta

e V

(

)

vs V

(Main system clock : 6.0 MHz crystal resonator)

Supply Current I

(mA)

5678

PCC = 0011

PCC = 0010

PCC = 0001

PCC = 0000

Main system clock HALT mode

+32-kHz oscillation

Subsystem clock operation mode

(SOS.1 = 0)

Subsystem clock HALT mode

(SOS.1 = 0) and main system

clock STOP mode +32-kHz

oscillation (SOS.1 = 0)

Subsystem clock HALT mode

(SOS.1 = 1) and main system

clock STOP mode +32-kHz

oscillation (SOS.1 = 1)

Crystal resonator

6.0 MHz

Crystal resonator

32.768 kHz

X2 XT1

330 kΩ

22 pF22 pF22 pF 22 pF

XT2

= 25°C)

PD75P0016

Data Sheet U10328EJ3V3DS

5.0

1.0

0.5

0.1

0.05

0.01

0.005

0.001012345678

PCC = 0011

PCC = 0010

PCC = 0001

PCC = 0000

X1 X2 XT1

330 kΩ

22 pF22 pF22 pF 22 pF

XT2

Supply Voltage V

(V)

vs V

(Main system clock : 4.19 MHz crystal resonator)

Supply Current I

(mA)

Main system clock HALT mode

+32-kHz oscillation

Subsystem clock operation mode

(SOS.1 = 0)

Subsystem clock HALT mode

(SOS.1 = 0) and main system

clock STOP mode +32-kHz

oscillation (SOS.1 = 0)

Subsystem clock HALT mode

(SOS.1 = 1) and main system

clock STOP mode +32-kHz

oscillation (SOS.1 = 1)

Crystal resonator

4.19 MHz

Crystal resonator

32.768 kHz

= 25°C)

PD75P0016

48 Data Sheet U10328EJ3V3DS

11. PACKAGE DRAWINGS

42PIN PLASTIC SHRINK DIP (600 mil)

ITEM MILLIMETERS INCHES

39.13 MAX.

1.778 (T.P.)

3.2±0.3

0.51 MIN.

4.31 MAX.

1.78 MAX.

0.17

15.24 (T.P.)

5.08 MAX.

0.9 MIN.

1.541 MAX.

0.070 MAX.

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.600 (T.P.)

0.007

0.070 (T.P.)

P42C-70-600A-1

NOTES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

D0.50±0.10 0.020

M 0.25 0.010

+0.10

–0.05

0~15° 0~15°

+0.004

–0.003

+0.004

–0.005

L13.2 0.520

2) Item "K" to center of leads when formed parallel.

PD75P0016

Data Sheet U10328EJ3V3DS

44 PIN PLASTIC QFP ( 10)

S44GB-80-3BS

ITEM MILLIMETERS INCHES

Q0.125±0.075

0.10

2.7

0.004

0.106

0.005±0.003

NOTE

Each lead centerline is located within 0.16 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

A13.2±0.2 0.520+0.008

–0.009

B10.0±0.2 0.394+0.008

–0.009

C10.0±0.2 0.394+0.008

–0.009

D13.2±0.2 0.520+0.008

–0.009

1.0

0.37

1.0 0.039

0.039

0.015+0.003

–0.004

0.8 (T.P.)

1.6±0.2

0.16 0.007

0.031 (T.P.)

0.063±0.008

L0.8±0.2 0.031+0.009

–0.008

M0.17 0.007+0.002

–0.003

S3.0 MAX. 0.119 MAX.

R3°3°+7°

–3°

+0.08

–0.07

+0.06

–0.05

+7°

–3°

detail of lead end

34 22

112

PD75P0016

50 Data Sheet U10328EJ3V3DS

12. RECOMMENDED SOLDERING CONDITIONS

The

PD75P0016 should be soldered and mounted under the following recommended conditions.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

Table 12-1. Surface Mounting Type Soldering Conditions

(1)

PD75P0016GB-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

Recommended

Soldering method Soldering conditions Condition

Symbol

Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. IR35-00-3

(at 210˚C or higher), Count: Three times or less

VPS Package peak temperature: 215˚C, Time: 40 seconds max. VP15-00-3

(at 200˚C or higher), Count: Three times or less

Wave soldering Solder bath temperature: 260˚C max., Time: 10 seconds max., Count: Once WS60-00-1

Preheating temperature: 120˚C max. (package surface temperature)

Partial heating Pin temperature: 350˚C max., Time: 3 seconds max. (per pin row) –

Caution Do not use different soldering methods together (except for partial heating).

Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales

representative.

(2)

PD75P0016GB-3BS-MTX-A: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

Recommended

Soldering method Soldering conditions Condition

Symbol

Infrared reflow Package peak temperature: 260˚C, Time: 60 seconds max. IR60-207-3

(at 220˚C or higher), Count: Three times or less,

Exposure limit: 7 daysNote (after that, prebake at 125˚C for 20 to 72 hours)

Wave soldering For details, contact an NEC Electronics sales representative. –

Partial heating Pin temperature: 350˚C max., Time: 3 seconds max. (per pin row) –

Note After opening the dry pack, store it at 25˚C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remarks 1. Products with “-A” at the end of the part number are lead-free products.

2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics

sales representative.

PD75P0016

Data Sheet U10328EJ3V3DS

Table 12-2. Insertion Type Soldering Conditions

PD75P0016CU: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

PD75P0016CU-A: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

Soldering Method Soldering Conditions

Wave soldering (pin only) Solder bath temperature: 260˚C max., Time: 10 seconds max.

Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (for each pin)

Caution Apply wave soldering to pins only. See to it that the jet solder does not contact with the chip

directly.

Remarks 1. Products with “-A” at the end of the part number are lead-free products.

2. For soldering methods and conditions other than those recommended above, contact an NEC

Electronics sales representative.

PD75P0016

52 Data Sheet U10328EJ3V3DS

APPENDIX A. FUNCTION LIST OF

PD75008, 750008, 75P0016

(1/2)

Item

PD75008

PD750008

PD75P0016

Program memory Mask ROM Mask ROM One-time PROM

0000H - 1F7FH 0000H - 1FFFH 0000H - 3FFFH

(8064 × 8 bits) (8192 × 8 bits) (16384 × 8 bits)

Data memory 000H - 1FFH

(512 × 4 bits)

CPU 75X Standard CPU 75XL CPU

General register 4 bits × 8 or 8 bits × 4 (4 bits × 8 or 8 bits × 4) × 4 banks

Instruction When main system • 0.95, 1.91, 15.3

s• 0.95, 1.91, 3.81, 15.3

s (at 4.19 MHz operation)

execution clock is selected (at 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7

s (at 6.0 MHz operation)

time When subsystem 122

s (at 32.768 kHz operation)

clock is selected

Stack SBS register None Yes SBS.3 = 1: Mk I mode selected

SBS.3 = 0: Mk II mode selected

Stack area 000H - 0FFH n00H - nFFH (n = 0, 1)

Stack operation of 2-byte stack In Mk I mode: 2-byte stack

subroutine call In Mk II mode: 3-byte stack

instruction

Instructions BRA !addr1 Unusable In Mk I mode: Unusable

CALLA !addr1 In Mk II mode: Usable

MOVT XA, @BCDE Usable

MOVT XA, @BCXA

BR BCDE

BR BCXA

CALL !addr 3 machine cycles Mk I mode: 3 machine cycles

Mk II mode: 4 machine cycles

CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles

Mk II mode: 3 machine cycles

Timer 3 channels 4 channels

• Basic interval timer: • Basic interval timer/watchdog timer: 1 channel

1 channel • 8-bit timer/event counter: 1 channel

• 8-bit timer/event counter: • 8-bit timer counter: 1 channel

1 channel • Watch timer: 1 channel

• Watch timer: 1 channel

Clock output (PCL) • Φ, 524, 262, 65.5 kHz • Φ, 524, 262, 65.5 kHz

(main system clock: (main system clock: at 4.19 MHz operation)

at 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz

(main system clock: at 6.0 MHz operation)

BUZ output (BUZ) • 2 kHz • 2, 4, 32 kHz

(main system clock: at 4.19 MHz operation)

• 2.93, 5.86, 46.9 kHz

(main system clock: at 6.0 MHz operation)

PD75P0016

Data Sheet U10328EJ3V3DS

(2/2)

Item

PD75008

PD750008

PD75P0016

Serial interface Compatible with 3 kinds of mode

• 3-wire serial I/O mode ... MSB/LSB-first can be switched

• 2-wire serial I/O mode

• SBI mode

SOS register Feedback resistor On-chip feedback resistor On chip

cut flag (SOS.0) specifiable by mask option

Sub oscillator current None On chip

cut flag (SOS.1)

(RBS)

Standby release by INT0 Not possible Possible

Vectored interrupt External: 3 Internal: 3 External: 3 Internal: 4

Processor clock control register PCC = 0, 2, 3 can be used PCC = 0 to 3 can be used

(PCC)

Supply voltage VDD = 2.7 to 6.0 V VDD = 2.2 to 5.5 V

Operating ambient temperature TA = –40 to +85˚C

Package • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

• 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)

PD75P0016

54 Data Sheet U10328EJ3V3DS

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are provided for system development using the

PD75P0016. The 75XL series uses

a common relocatable assembler, in combination with a device file matching each machine.

RA75X relocatable assembler Host machine Part number

OS Supply medium (product name)

PC-9800 series MS-DOSTM 3.5" 2HD

S5A13RA75X

Ver.3.30 to

Ver.6.2

Note

IBM PC/ATTM Refer to OS for 3.5" 2HC

S7B13RA75X

or compatible IBM PCs

Device file Host machine Part number

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5" 2HD

S5A13DF750008

Ver.3.30 to

Ver.6.2

Note

IBM PC/AT Refer to OS for 3.5" 2HC

S7B13DF750008

or compatible IBM PCs

Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swap function, but it does not work with this

software.

Remark The operation of the assembler and device file is guaranteed only on the above host machines and OSs.

PD75P0016

Data Sheet U10328EJ3V3DS

PROM Write Tools

Hardware PG-1500 A stand-alone system can be configured of a single-chip microcomputer with on-chip PROM

when connected to an auxiliary board (companion product) and a programmer adapter

(separately sold). Alternatively, a PROM programmer can be operated on a host machine for

programming.

In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed.

PA-75P008CU This is a PROM programmer adapter for the

PD75P0016CU/GB. It can be used when

connected to a PG-1500.

PA-75P0016GB This is a PROM programmer adapter for the

PD75P0016GB-3BS-MTX. It can be used when

connected to a PG-1500.

Software PG-1500 controller Establishes serial and parallel connections between the PG-1500 and a host machine for host-

machine control of the PG-1500.

Host machine Part number

OS Supply medium (product name)

PC-9800 Series MS-DOS 3.5" 2HD

S5A13PG1500

Ver.3.30 to

Ver.6.2

Note

IBM PC/AT Refer to OS for 3.5" 2HD

S7B13PG1500

or compatible IBM PCs

Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work with

this software.

Remark Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.

PD75P0016

56 Data Sheet U10328EJ3V3DS

Debugging Tools

In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the

PD75P0016.

Various system configurations using these in-circuit emulators are listed below.

Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during

development of application systems that use 75X or 75XL Series products. For development

of the

PD750008 subseries, the IE-75000-R is used with a separately sold emulation board IE-

75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R.

These products can be applied for highly efficient debugging when connected to a host machine

and PROM programmer.

The IE-75000-R can include a connected emulation board (IE-75000-R-EM).

IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during

development of application systems that use 75X or 75XL Series products. The IE-75001-R is

used with a separately sold emulation board (IE-75300-R-EM) and emulation probe EP-

75008CU-R or EP-75008GB-R.

These products can be applied for highly efficient debugging when connected to a host machine

and PROM programmer.

IE-75300-R-EM This is an emulation board for evaluating application systems that use the

PD750008

subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator.

EP-75008CU-R This is an emulation probe for the

PD75P0016CU.

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

EP-75008GB-R This is an emulation probe for the

PD75P0016GB.

EV-9200G-44 When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

It includes a 44-pin conversion socket (EV-9200G-44) to facilitate connections with various

target systems.

Software IE control program This program can control the IE-75000-R or IE-75001-R on a host machine when connected to

the IE-75000-R or IE-75001-R via an RS-232-C or Centronics I/F.

Host machine Part number

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5" 2HD

S5A13IE75X

Ver.3.30 to

Ver.6.2

Note 2

IBM PC/AT Refer to OS for 3.5" 2HC

S7B13IE75X

or compatible IBM PCs

Notes 1. This is a service part provided for maintenance purpose only.

2. Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work

with this software.

Remarks 1. Operation of the IE control program is guaranteed only on the above host machine and OSs.

2. The

PD75000 subseries consists of the

PD750004, 750006, 750008 and 75P00016.

PD75P0016

Data Sheet U10328EJ3V3DS

OS for IBM PCs

The following operating systems for the IBM PC are supported.

OS Version

PC DOSTM Ver.3.1 to Ver.6.3

J6.1/VNote to J6.3/VNote

MS-DOS Ver.5.0 to Ver.6.22

5.0/VNote to J6.2/VNote

IBM DOSTM J5.02/VNote

Note Supports English version only.

Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function.

PD75P0016

58 Data Sheet U10328EJ3V3DS

Hardware

Software

APPENDIX C. RELATED DOCUMENTS

Some of the following related documents are preliminary. This document, however, is not indicated as

preliminary.

Device Related Documents

Document name Document No.

Japanese English

PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) U10738J U10738E

Data Sheet

PD75P0016 Data Sheet U10328J This document

PD750008 User’s Manual U10740J U10740E

PD750008, 750108 Instruction List U11456J –

75XL Series Selection Guide U10453J U10453E

Development Tool Related Documents

Document name Document No.

Japanese English

IE-75000 R/IE-75001-R User’s Manual EEU-846 EEU-1416

IE-75300-R-EM User’s Manual U11354J U11354E

EP-750008CU-R User’s Manual EEU-699 EEU-1317

EP-750008GB-R User’s Manual EEU-698 EEU-1305

PG-1500 User’s Manual U11940J U11940E

RA75X Assembler Package Operation U12622J U12622E

User’s Manual Language U12385J U12385E

PG-1500 Controller User’s Manual PC-9800 Series EEU-704 EEU-1291

(MS-DOS) Base

IBM PC Series EEU-5008 U10540E

(PC DOS) Base