CLC5903
CLC5903 Dual Digital Tuner/AGC
Literature Number: SNWS005D
©2004 National Semiconductor Corporation DS200286 www.national.com
Revision 1.6
CLC5903 Dual Digital Tuner / AGC
June 20 04
National Semiconductor
CLC5903
Dual Di gital Tuner / AGC
0
0
General Overview
The CLC5903 Dual Digital Tuner / AGC IC is a two channel
digital downconverter (DDC) with integrated automatic gain
control (AGC). The CLC5903 is a key component in the
Enhanced Diversity Receiver Chipset (EDRCS) which
includes one CLC5903 Dual Digital Tuner / AGC, two
CLC5957 12-bit analog-to-digital converters (ADCs), and two
CLC5526 digitally controlled variable gain amplifiers
(DVGAs). This system allows direct IF sampling of signals up
to 300MHz for enhanced receiver performance and reduced
system costs.
The CL C590 3 is an en hance d rep lacem ent for the CLC5 902
in the Diversity Receiver Chipset (DRCS). The main
improvements relative t o the CLC5902 are a 50% increase in
maximum sample rate from 52MHz to 78MHz, a 62%
reduction in power consumption from 760mW to 290mW,
and the added flexibility to independently program filter
coefficients in the two channels. A block diagram for a
DRCS-based narrowband communications system is shown
in Figure 1.
The C LC5903 offers high dynamic rang e digital tuning and
filtering based on hard-wired digital signal processing (DSP)
technology. Each channel has independent tuning, phase
offset, filter coefficients, and gain settings. Channel filtering
is perform ed by a ser ie s of thr ee f ilters. The f irst is a 4-stage
Cascaded Integrator Comb (CIC) filter with a programmable
decimation ratio from 8 to 2048. Next there are two
symmetric FIR filters, a 21-tap and a 63-tap, both with
independent programmable coefficients. The first FIR filter
decimates the data by 2, the second FIR decimates by either
2 or 4. Channel filter bandwidth at 52MSPS ranges from
±650kHz down to ±1.3kHz. At 78MSPS, the maximum
bandwidth increas es t o ±975kHz.
The CLC5903’s AGC controller monitors the ADC output and
controls the ADC input signal level by adjusting the DVGA
setting. AGC threshold, deadband+hysteresis, and the loop
time constant are user defined. Total dynamic range of
greater than 120 dB full-scale signal to n oise in a 200kHz
bandwidth can be achieved with the Diversity Receiver
Chipset.
Figu re 1. Diversity Receiver Ch i pset Block Diagram
DVGA
IF A SerialOutA/B
SerialOutB
SCK
SFS
RDY
LC
DVGA
IF B LC ParallelOutput[15..0]
ParallelOutputEnable
ParallelSelect[2..0]
CLC5526 CLC5957 CLC5903
CLK
12
8
12
ADC
ADC SCK_IN
Dual Digital
Tuner/AGC
DAV
DAV
Features
78MSPS Operation
Low Power, 145mW/channel, 52 MHz, Dec=192
Two Independent C ha nnels with 14-b i t inpu t s
Serial D aisy-chain Mo de for quad re cei vers
Greater th an 1 00 dB image rej ect i on
Greater th an 1 00 dB spuri ous free dynam i c ran ge
0.02 Hz tuning resolution
User Programmable AGC with enhanced Power Detector
Channel Filters include a Fourth Order CIC followed by
21-tap and 63-tap Symmetric FIRs
FIR filte rs proces s 21-bi t Data with 16- bit Pro grammable
Coefficients
Two in dep enden t FIR c oeffici ent me mories wh ich ca n be
routed to either or both channels.
Flexible output for mats inc lude 12-bit Floa ting Point or 8,
16, 24, and 32 bit Fixed Point
Serial and Parallel output ports
JTAG Bound ary Sc an
8-bit Microprocessor Interface
128 pin PQFP and 128 pin FBG A packages
100% Sof tware compatible with the CL C 5902
Pin compatible wi th the CLC5902 ex c ept for VDD voltage
Applications
Cellular Basestations
Satellite Receivers
Wirele ss Local Loop Re ceivers
Digital Communicatio ns
N
www.national.com 2
CLC5903
Functional Description
The CLC5903 block diagram is shown in Figure 2. The
CLC5903 contains two identical digital down-conversion
(DDC) circuits. Each DDC accepts an independently clocked
14-bit sample at up to 78MSPS, down converts from a
selected carrier frequency to baseband, decimates the signal
rate by a programmable factor ranging from 32 to 16384, pro-
vides ch annel filteri ng, and output s quadrature symbols.
A crossba r switch enables either o f the two i nputs or a test
register t o be routed to either DDC ch annel. Flexible channel
filter ing i s pr ovide d by the two pro gramma ble dec imating FIR
filters. The final filter outputs can be converted to a 12-bit
floating point format or standard two’s complement format.
The output data is av ailable at both serial and parallel ports.
The CLC5903 maintains over 100 dB of spurious free
dynamic range and over 100 dB of out-of-band rejection.
This allows considerable latitude in channel filter partitioning
between th e analog and digit al dom ains.
The frequencies, phase offsets, and phase dither of the two
sine/cosine numerically controlled oscillators (NCOs) can be
independently specified. Two sets of coefficient memories
and a crossbar switch allow shared or independent filter
coefficients and bandwidth for each channel. Both channels
share th e sa me decimat io n ratio and inp ut / out put for m ats.
Each channel has its own AGC circuit for use with narrow-
band radio cha nnels w here most of the channe l filteri ng pre-
cedes the ADC. The AGC closes the loop around the
CLC552 6 DVGA, compress ing the dy namic range of the sig-
nal into the AD C. AGC ga in compensation in the CLC5903
removes the DVGA gain steps at the output. The time align-
ment of this gain compensation circuit can be adjusted to
support AD Cs w ith d ifferent lat enci es. The AGC can be c on-
figured to operate continuously or set to a fixed gain step.
The two AGC circuits operate independently but share the
same programmed parameters and control signals.
The chip receives configuration and control information over
a microprocessor-compatible bus consisting of an 8-bit data
I/O port, an 8-bit address por t, a chip enable strobe, a read
strobe, an d a wr ite strobe. The c hi p’s control registers (8 bits
each) are memory mapped into the 8-bit address space of
the con tr ol port. Page select bits allow access to the overlaid
A and B set of FIR coef f ici ent s.
JTAG bound ary scan an d on -chip di agnos tic circu its are pr o-
vided to simplify system debug and test.
The CLC5903 supports 3.3V I/O even though the core logic
voltage is 1.8V. The CLC5903 outputs swing to the 3.3V rail
so they can be directly connected to 5V TTL inputs if desired.
Figure 2. CLC5903 Dual Digital Tuner / AGC Block Diagram with Control Register Associations
AIN
BIN MUX
MUX
Input Source Output Controls
Output Formatter
Floating Point:
32-bit Truncated or
24-bit Rounded or
16-bit Rounded or
8-bit Truncated
Two’s Complement:
4-bit Exponent and
8-bit Mantissa
or
AOUT/BOUT
BOUT
SCK
SFS
RDY
POUT[15..0]
PSEL[2..0]
POUT_EN
A_SOURCE
B_SOURCE RATE
SOUT_EN
SCK_POL
SFS_POL
RDY_POL
MUX_MODE
PACKED
FORMAT
DEBUG_EN
DEBUG_TAP
CKA CLK
GEN
TEST_REG Channel B Controls
GAIN_B FREQ_B
PHASE_B
AGC_IC_B AGC_RB_B
DITH_B
Common C han nel Cont rols
DEC_BY_4
SCALE
EXP_INH
AGC_HOLD_IC
AGC_LOOP_GAIN
AGC_TABLE F1B_COEFF
F2B_COEFF
AGAIN[2..0]
ASTROBE
BGAIN[2..0]
BSTROBE
Microprocessor
Interface
RD
WR
CE
A[7:0]
D[7:0]
SI
MR Sync
Logic
14
14
DEC
A
B
Channel A
Tuning,
Channel Filters, and
AGC (see Figure 16)
Channel B
Tuning,
Channel Filters, and
AGC (see Figure 16) (see Figure 29)
SCK_IN
SFS_MODE
SDC_EN
AGC_COMB_ORD
EXT_DELAY
COEF_SEL_F1B
COEF_SEL_F2B
Channel A Controls
GAIN_A FREQ_A
PHASE_A
AGC_IC_A AGC_RB_A
DITH_A COEF_SEL_F1A
COEF_SEL_F2A
F1A_COEFF
F2A_COEFF
PAGE_SEL_F1
PAGE_SEL_F2
CKB
3 www.national.com
CLC5903
Absolute Maximum Ratings
NOTE: Absolute maximum ratings are limiting values, to be
applied individually, and beyond which the serviceability of the
circuit may be impa ired. Functional operability under any of
these c onditions is no t necessar ily implied . Exposure to max i-
mum ratings for extended periods may affect device reliability.
Operating Ratings
Package Thermal Resistance
Reliability Information
Ordering Information
CLC5903 Electrical Characteristics (Note 1)
Positive IO Supply Volta ge (VDDIO)-0.3V to 4.2V
Positive CoreSupply Voltage (VDD)-0.3V to 2.4V
Voltage on Any Input or Output Pin -0.3V to VDDIO+0.5V
Input Current at Any Pin ±25mA
Package Input Current ±50mA
P ackage Dissipation at TA=25°C 1W
ESD Susceptibility
Human Body Model
Machine Model 2000V
200V
Soldering Temperature, Infrared, 10
seconds 300°C
Storage Temperature -65°C to 150°C
Positive IO Supply Voltage (VDDIO)3.3V ±10%
Positive Core Supply Volt age (VDD)1.8V ±10%
Operating Temperature Range -40°C to +85°C
Package θja θjc
128 pin PQFP 39°C/W 20°C/W
128 pin FBGA 30°C/W N/A
Transistor Count 1.4 million
Order Code Temperature
Range Description
CLC5903VLA -40°C to
+85°C 128-pin PQFP (indus-
trial temperature range)
CLC5903SM -40°C to
+85°C 128-pin FBGA (indus-
trial temperature range)
DC Characteristics
(FS= 78MHz, CIC D ecimation=48, F2 Deci m at i on=2; unless sp eci f i ed)
Symbol Parameter Min Typ Max Units
VIL Voltage input low -0.5 0.7 V
VIH Voltage input high 2.3 VDDIO+0.5 V
IOZ Input current 20 uA
VOL Voltage output low (IOL = 4mA/16mA, see Note 2) 0.4 V
VOH Voltage output high (IOH = -4mA/-16mA, see Note 2) 2.4 V
CIN Input capacitance 5.0 pF
AC Characteristics
(FS= 78MHz, CIC D ecimation=48, F2 Deci m at i on=2; unless sp eci f i ed)
Symbol Param eter ( C L=50pF) Min Typ Max Units
FCK Clock (CKA|B) Frequency (Figure 7) 78 MHz
SFDR Spurious Free Dynamic Range -100 dBFS
SNR Signal to Noise Ratio -127 dBFS
Tuning Resolution 0.02 Hz
Phase Resolution 0.005 °
tMRA MR Active Time (Figure 5) 4 CK periods
tMRIC MR Inactive to first Control Port Access (Figure 5) 10 CK periods
www.national.com 4
CLC5903
tMRSU MR Setup Time to CKA|B (Figure 5) 6 ns
tMRH MR Hold Time to CKA|B (Figure 5) 2 ns
tSISU SI Setup Time to CKA|B (Figure 6) 6 ns
tSIH SI Hold Time from CKA|B (Figure 6) 2 ns
tSIW SI Pulse Width (Figure 6) 4 CK periods
tCKDC CKA|B duty cycle (Figure 7) 40 60 %
tRF CKA|B rise and fall times (VIL to VIH) (Figure 7) 2ns
tSU Input setup before CKA|B goes high (A|BIN) (Figure 7) 3 ns
tHD Input hold time after CKA|B goes high (A|BIN) (Figure 7) 1 ns
tCKL Mini mum time l ow for CK = CKA | CKB (Figure 8) 3.1 ns
tSTIW A|BSTROBE Inactive Pulse Width (Figure 9) 2 CK period
tGSTB A|BGAIN setup before A|BSTROBE (Figure 9) 6 ns
tSFSV SCK to SFS Valid (Note 3) (Figure 10) -1 5 ns
tOV SCK to A|BOUT Valid (Note 4) (Figure 10) -1 5 ns
tRDYW RDY Pulse Width (Figure 10) 2 CK periods
tRDYV SCK to RDY valid (Figure 10) -1 5 ns
tOENV POUT_EN Acti ve to POUT[15..0] Valid (Figure 11) 12 ns
tOENT POUT_EN Inactive to POUT[15..0] Tri-State (Figure 11) 10 ns
tSELV PSEL[2..0] to POUT[15..0] Valid (Figure 12) 13 ns
tPOV RDY to POUT[15..0] New Value Valid (Note 5) (Figure 13) 7 ns
tJPCO Propagation Delay TCK to TDO (Figure 14) 25 ns
tJSCO Propagation Delay TCK to Data Out (Figure 14) 35 ns
tJPDZ Disable Time TCK to TDO (Figure 14) 25 ns
tJSDZ Disable Time TCK to Data Out (Figure 14) 35 ns
tJPEN Enable Time TCK to TDO (Figure 14) 0 25 ns
tJSEN Enable Time TCK to Data Out (Figure 14) 0 35 ns
tJSSU S e tu p Ti me Dat a to TCK (Figure 14) 10 ns
tJPSU Setup Time TDI, TMS to TCK (Figure 14) 10 ns
tJSH Hold Time Data to TCK (Figure 14) 45 ns
tJPH Hold Time TCK to TDI, TMS (Figure 14) 45 ns
tJCH TCK Pulse Width High (Figure 14) 50 ns
tJCL TCK Pulse Width Low (Figure 14) 40 ns
JTAGFMAX TCK Maximum Frequency (Figure 14) 10 MHz
tCSU Control Setup before the controlling signal goes low (Figure 15) 5 ns
tCHD Control hold after the controlling signal goes high (Figure 15) 5 ns
AC Characteristics (Continued)
(FS= 78MHz, CIC D ecimation=48, F2 Deci m at i on=2; unless sp eci f i ed)
Symbol Param eter ( C L=50pF) Min Typ Max Units
5 www.national.com
CLC5903
Note 1: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 2: All output pins provide 16mA output drive except TDO (pin 116) which provides 4mA output drive.
Note 3: tSFSV refers to the rising edge of SCK when SCK_P OL=0 and the falling edge when SCK_POL=1.
Note 4: tOV refers to the rising edge of SCK when SCK_POL=0 and the falling edge when SCK_POL=1.
Note 5: tRDYV refers to the rising edge of RDY when RDY_POL=0 and the falling edge when RDY_POL=1.
CLC5903SM Pinout
tCSPW Controlling strobe pulse width (Write) (Figure 15) 30 ns
tCDLY Control output delay controlling signal low to D (Read) (Figure 15) 30 ns
tCZ Control tri-state delay after controlling signal high (Figure 15) 20 ns
IDD Dynamic Supply Current (FCK =78MHz, N=48, SCK=39MHz) 120 200 mA
IDDIO Dynamic Supply Curr ent (FCK =78MHz, N=48, SCK=39MHz) 65 100 mA
AC Characteristics (Continued)
(FS= 78MHz, CIC D ecimation=48, F2 Deci m at i on=2; unless sp eci f i ed)
Symbol Param eter ( C L=50pF) Min Typ Max Units
Figure 3. CLC5903SM FBGA Pinout
A12
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
B12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
C12
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
D12
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
E12
E1 E2 E3 E4 E9 E10 E11
F12
F1 F2 F3 F4 F9 F10 F11
G12
G1 G2 G3 G4 G9 G10 G11
H12
H1 H2 H3 H4 H9 H10 H11
J12
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11
K12
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11
L12
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
M12
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11
AIN12
AIN10
AIN7
AIN5
AIN2
VSS
VDD
BIN10
BIN7
BIN4
BIN1
NC
VDDIO
VSSIO
AIN11
AIN8
AIN1
CKA
BIN13
BIN11
BIN8
BIN2
VSS
VDDIO
AGAIN1
NC
NC
AIN13
AIN6
AIN3
BIN12
BIN9
BIN6
BIN0
NC
BGAIN0
SCAN_EN
TRST
ASTROB
AGAIN2
AIN9
AIN4
AIN0
BIN5
BIN3
CKB
BGAIN1
MR
TCK
TMS
VSS
AGAIN0
BGAIN2
BSTROB
NC
A[7]
VDD
TDO
TDI
POUT_SEL2
SI
VSSIO
A[6]
VDD
POUT_SEL1
POUT_SEL0
POUT0
POUT1
NC
A[4]
A[5]
VSS
VSSIO
POUT_EN
POUT2
VSS
CE
A[1]
A[3]
A[2]
VDDIO
POUT4
NC
POUT7
POUT9
SFS
RDY
D[2]
D[7]
RD
A[0]
WR
POUT3
NC
VSSIO
VDDIO
VSSIO
POUT14
BOUT
D[0]
VSSIO
NC
D[6]
VSSIO
NC
SCK_IN
POUT6
POUT11
POUT13
VDD
VSSIO
SCK
D[1]
D[4]
NC
VDDIO
NC
POUT5
POUT8
POUT10
POUT12
POUT15
AOUT
VDDIO
VSS
VDD
D[3]
D[5]
Top View
www.national.com 6
CLC5903
CLC5903VLA Pinout
Pin Descriptions
Signal PQFP Pin FBGA Pin Description
MR 45 M4 MASTER RESET, Active low
Resets all registers within the chip. ASTROBE and BSTROBE are asserted during
MR.
AIN[13:0],
BIN[13:0]
4:10,12:18,
22:28,
30:36
D3,A1,C2,
B1,E4,D2,
C1,E3,D1,
F4,F3,E1,
E2,G4;
G2,G3,H2,
H1,H3,J2,
J1,J3,H4,
K1,J4,K2,
L1,K3
INPUT DATA, Active high
2’s complement input data. AIN[13] and BIN[13] are the MSBs. The data is cloc ked
into the chip on the rising edge of the corresponding clock (CKA, CKB). The
CLC595X connects directly to these input pins with no additional logic. Tie unused
input bits low.
17
16
14
11
9
8
6
4
2
1
15
13
12
10
7
5
3
20
19
18
24
22
21 VDD
BIN[12]
25
23
(MSB) BIN[13]
BIN[11]
BIN[10]
NC
VSSIO
AIN[11]
AIN[9]
AIN[8]
VDDIO
AIN[4]
AIN[2]
AIN[1]
NC
(MSB) AIN[13]
AIN[12]
AIN[10]
AIN[7]
AIN[6]
AIN[5]
AIN[3]
VSS
CKA
AIN[0]
36
34
33
31
29
27
26
38
37
35
32
30
28
BIN[9]
BIN[7]
BIN[5]
BIN[3]
BIN[2]
BIN[0]
BIN[8]
VSSIO
BIN[6]
BIN[4]
BIN[1]
NC
CKB
86
87
89
92
94
95
97
99
101
102
88
90
91
93
96
98
100
83
84
85
79
81
82
AOUT
SCK
78
80
SFS
VDDIO
BOUT
NC
NC
POUT[5]
POUT[7]
POUT[8]
VDDIO
VSSIO
POUT[13]
POUT[14]
NC
SCK_IN
VSSIO
POUT[6]
POUT[9]
POUT[10]
POUT[11]
POUT[12]
POUT[15]
VSSIO
VDD
67
69
70
72
74
76
77
65
66
68
71
73
75
RDY
D[0]
D[2]
D[4]
D[5]
NC
VSS
VDD
D[1]
D[3]
VSSIO
NC
NC
124
125
127
126
128
121
122
123
117
119
120 VSS
TMS
116
118
TCK
TDI
TDO
AGAIN[2]
AGAIN[0]
ASTROBE
VDDIO
AGAIN[1]
SCAN_EN
TRST
NC
105
107
108
110
112
114
115
103
104
106
109
111
113
VDD
POUT_SEL[1]
VSSIO
POUT[1]
VDDIO
POUT[3]
POUT_SEL[0]
POUT_SEL[2]
POUT_EN
POUT[0]
POUT[2]
POUT[4]
VSS
60
61
63
62
64
57
58
59
53
55
56
A[1]
A[3]
52
54
A[2]
A[4]
A[5]
D[6]
VSSIO
CE
VDDIO
D[7]
WR
A[0]
RD
41
43
44
46
48
50
51
39
40
42
45
47
49
VSS
VDD
SI
NC
BSTROBE
BGAIN[1]
A[6]
A[7]
VSSIO
MR
BGAIN[0]
BGAIN[2]
VDDIO
CLC5903VLA
Dual Digital Tuner / AGC
(Top View)
Figure 4. CLC5903VLA PQFP Pinout
7 www.national.com
CLC5903
AOUT
BOUT 82
78 G12
G10
SERIAL OUTP UT DATA, Ac tive high
The 2’s complement serial output data is transmitted on these pins, MSB first. The
output bits change on the rising edge of SCK (f alling edge if SCK_POL=1) and should
be captured on the falling edge of SCK (rising if SCK_POL=1). These pins are
tri-stated at power up and are enabled by the SOUT_EN control register bit. See Fig-
ure 10 and Figure 30 timing diagrams. In Debug Mode AOUT=DEBUG[1],
BOUT=DEBUG[0].
AGAIN[2:0],
BGAIN[2:0] 125:127
40:42 D4,A3,D5
J5,L4,M3 OUTPUT DATA TO DVGA, Active high
3 bit bus that sets the gain of the DVGA determined by the AGC circuit.
ASTROBE,
BSTROBE 124
43 C4
K5 DVGA STROBE, Active low
Strobes the data into the DVGA. See Figure 9 and Figure 35 timing diagrams.
SCK 80 H11
SERIAL D ATA CLOCK, Active high or low
The serial data is clocked out of the chip by this clock. The active edge of the clock is
user programmable . This pin is tri-stated at power up and is enab led by the SOUT_EN
control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode out-
puts an appropriate clock for the debug data. If RATE=0 the input CK duty cycle will
be reflected to SCK.
SCK_IN 99 B11 SERIAL DATA CLOCK INPUT, Active high or low
Data bits from a serial daisy-chain slave are clocked into a serial daisy-chain master
on the f alling edge of SCK_IN (rising if SCK_POL=1 on the sla ve). Tie low if not used.
SFS 81 F9
SERIAL FRAM E STRO BE, Active high or low
The serial word strobe. This strobe delineates the words within the serial output
streams. This strobe is a pulse at the beginning of each serial word (PACKED=0) or
each serial word I/Q pair (PACKED=1). The polarity of this signal is user programma-
ble. This pin is tri-stated at power up and is enabled b y the SOUT_EN control register
bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode SFS=DEBUG[2].
POUT[15:0]
84,86:88,
90,91,
93:97,104:
106,
108,109
F12,F10,
E11,E12,
D11,D12,
E9,C12,D9,
C11,B12,
B9,A10,C8,
D7,C7
PARALLEL OUTPUT DATA, Active high
The output data is transmitted on these pins in parallel format. The POUT_SEL[2..0]
pins select one of eight 16-bit output words. The POUT_EN pin enables these out-
puts. POUT[15] is the MSB. In Debug Mode POUT[15..0]=DEBUG[19..4].
POUT_SEL[2:0] 112:114 D6,A7,B7
PARALLEL OUTPUT DATA SELECT, Active high
The 16-bit output word is selected with these 3 pins according to Tabl e 2. Not used in
Debug Mode. F or a serial daisy-chain master, POUT_SEL[2:0] become inputs from
the slave: POUT_SEL[2]=SFSSLAVE, POUT_SEL[1]=BOUTSLAVE, and
POUT_SEL[0]=AOUTSLAVE. Tie low if not used.
POUT_EN 111 B8 PARALLEL OUTPUT ENABLE. Active low
This pin enables the chip to output the selected output word on the POUT[15:0] pins.
Not used in Deb ug Mode. Tie high if not used.
RDY 77 G9
READY FLAG, Active high or low
The chip asser ts this signal to identify the beginning of an output sample period
(OSP). The polarity of this signal is user programmable. This signal is typically used
as an interrupt to a DSP chip, but can also be used as a start pulse to dedicated cir-
cuitry. This pin is active regardless of the state of SOUT_EN. In Debug Mode
RDY=DEBUG[3].
CKA,
CKB 20,
38 F2
K4
INPU T C L OCK. Active high
The clock inputs to the chip. The corresponding AIN and BIN signals are clocked into
the chip on the rising edge of this signal. CKA and CKB are OR’ d together on chip to
create the CK signal. SI is clock ed into the chip on the rising edge of CK. Tie low if not
used.
SI 46 J6
SYNC IN. Active low
The sync input to the chip. The decimation counters, dither, and NCO phase can be
synchronized by SI. This sync is clocked into the chip on the rising edge of CK (CK =
CKA + CKB). Tie this pin high if external sync is not required. All sample data is
flushed by SI. To properly initializ e the D V GA ASTROBE and BSTROBE are asserted
during SI.
Pin Descriptions (Continued)
Signal PQFP Pin FBGA Pin Description
www.national.com 8
CLC5903
D[7:0] 62,63,
69:73,75
J9,L10,
M12,K11,
L12,H9,
J11,H10
DATA BUS. Active high
This is the 8 bit control data I/O bus. Control register data is loaded into the chip or
read from the chip through these pins. The chip will only drive output data on these
pins when CE is low, RD is low, and WR is high.
A[7:0] 48,50,
52:57
M5,L6,L7,
K7,L8,M8,
K8,L9
ADDRESS BUS. Active high
These pins are used to address the control registers within the chip. Each of the con-
trol registers within the chip are assigned a unique address in a flat address space. A
control register can be written to or read from by setting A[7:0] to the register’s
address.
RD 59 K9 READ ENABLE. Active low
This pin enables the chip to output the contents of the selected register on the D[7:0]
pins when CE is also low.
WR 58 M9 WRITE ENABLE. Active low
This pin enables the chip to write the value on the D[7:0] pins into the selected regis-
ter when CE is also low. This pin can also function as RD/WR if RD is held low.
CE 60 J8
CHIP ENA BLE. Active low
This control strobe enables the read or write operation. The contents of the register
selected by A[7:0] will be output on D[7:0] when RD is low and CE is low. If WR is lo w
and CE is low, then the selected register will be loaded with the contents of D[7:0].
TDO 116 B6 TEST DATA OUT. Active high
TDI 117 C6 TEST DATA IN. Active high with pull-up
TMS 118 B5 TEST MODE SELECT. Active high with pull-up
TCK 1 19 A5 T EST CL O CK. Active high. Tie low if JTAG is not used.
TRST 121 B4 TEST R ES ET. Active low with pull-up
Asynchronous reset for TAP controller. Tie low or to MR if JTAG is not used.
SCAN_EN 122 A4 SCAN ENABLE. Active low with pull-up
Enables access to internal scan registers. Tie high. Used for manufacturing test only!
VSS 19,51,76,
103,120 C5,D8,F1,
J12,L2,M7 Core Ground. Quantity 5 in PQFP (6 in FBGA).
VDD 21,49,74,
85,115 A6,F11,G1,
K12,M6 Core Power, 1.8V. Quantity 5.
VSSIO 3,29,47,61,
68,83,89,
98,110
A8,B2,C10,
E10,G11,
J10,K6,M10 I/O Ground. Quantity 9 (8 in FBGA).
VDDIO 11,39,64,
79,92,107,
128
A2,A9,D10,
H12,M2,
M11 I/O Power, 3.3V. Quantity 7 (6 in F B GA).
NC
1,2,37,44,
65,66,67,
100,101,
102,123
A11,A12,
B3,B10,C3,
C9,J7,K10,
L11,L5,L3,
M1
No Connect. These pins should be left floating. Quantity 11 (12 in FBGA).
Pin Descriptions (Continued)
Signal PQFP Pin FBGA Pin Description
9 www.national.com
CLC5903
Timing Diagrams
Figure 5. CLC 59 03 Master Reset Timing
CK tMRH
tMRA
tMRSU
tMRIC
MR
RD
or WR
Figure 6. CLC5903 Synchronization Input (SI) Timing
CK
tSIW
tSISU
tSIH
SI
Figure 7. CLC5903 ADC Input and Clock Timing
CKA|B
A|BIN
tSU
tHD
tCKDC
tRF
VIH
VIL
tCKDC
1/FCK
Note: AIN relative to CKA, BIN relative to CKB
Figure 8. CLC5903 CKA vs. CKB Timing
CKB
tCKL
CKA
CK
Note: CK = CKA | CKB
Figur e 9. CL C5903 DVGA Inter fa ce Timing
tGSTB
tSTIW
A|BSTROBE
A|BGAIN[2..0]
www.national.com 10
CLC5903
tSFSV
SFS
SFS
tRDYW
Figure 10. CL C 5903 Serial Port Timing
tSFSV
tOV tOV
SFS_POL=0
SFS_POL=1
msb msb-1 msb-2 msb-3lsb or undef
I Output WordPrevious Q Output Word
RDY
RDY
RDY_POL=0
RDY_POL=1
SCK
SCK_POL=0
A|BOUT
SCK=CK/2
SCK
SCK_POL=1
tRDYV
tOENV
POUT[15..0]
POUT_EN
Figure 11. CLC5903 Parallel Output Enable Timing
tOENT
Figure 12. CLC5903 Parallel Output Select Timing
tSELV
POUT[15..0]
POUT_SEL[2..0]
tSELV
n
output (n)
n+1
output (n+1)
n+2
output (n+2)
Figure 13. CLC5903 Parallel Output Data Ready Timing
tPOV
POUT[15..0] new output
old output
RDY
RDY
RDY_POL=0
RDY_POL=1
Timing Diagrams (Continued)
11 www.national.com
CLC5903
Figure 14. CLC5903 JTAG Port Ti mi ng
TCK
TDO
tJPCO
tJPEN
tJPDZ
TCK
D
tJSCO
tJSEN
tJSDZ
TCK
TDI, TDS
tJPSU
tJCL
tJPH
tJCH
TCK
D
tJSSU tJSH
CE
WR
RD
A[7:0] tCDLY
tCSU
tCZ
READ CYCLE; NORMAL MODE
CE
WR
RD
D[7:0]
A[7:0]
tCSPW
tCSU
tCHD
WRITE CYCLE; NORMAL MODE
WR
CE
D[7:0]
A[7:0] tCDLY
tCSU
tCZ
tCHD
tCHD
CE
WR
D[7:0]
A[7:0]
tCSPW
tCSU
tCHD
READ CYCLE; RD HELD LOW
WRITE CYCLE; RD HELD LOW
D[7:0]
Figure 15. CLC5903 Control I/O Timing
www.national.com 12
CLC5903
Detailed Description
Control Interface
The CLC5903 is configured by wr iting control information
into 148 cont rol registers within the chip. The contents of
these c ontrol regis ters and how to use them are des cribed
under Control Register Addresses and Defaults on pa ge 21.
The registers are written to or read from using the D[7:0],
A[7:0], CE, RD and WR pins (see Table for pin des crip-
tions). This interface is designed to allow the CLC5903 to
appear to an external processor as a memory mapped
peripheral. See Figu re 15 for details.
The cont rol inte rface is asynch ronous with res pect to the
system clo ck, CK (CK = CKA + CKB). This allows the regis-
ters to be written or read at any time. In some cases this
might cause an invalid operation since the interface is not
internally synchronized. In order to assure correct operation,
SI must be ass erted after the co nt ro l registers are w r i t ten.
The D[7:0], A[7:0], WR, RD and CE pins should not be
driven above the positive supply voltage.
Master Reset
A master re set pin, MR, is provided to initialize the CLC5903
to a known condition and should be strobed after power up.
This signal will clear all sample data and all user pro-
grammed data (filter coefficients and AGC settings). All out-
puts will be disabled (tr i-stated). ASTROBE and BSTROBE
will be asser ted to initialize the DVGA values. Control Regis-
ter Address es and Defaults on page 21 describes the control
register default values.
Synchroniz ing Multiple CLC5903 Chips
A system containing two or more CLC5903 chips will need to
be synchronized if coherent operation is desired. To synchro-
nize multiple CLC5903 chip s, connect a ll of the sy nc input
pins together so they can be driven by a common sync
strobe. Synchronization occurs on the rising edge of CKA|B
when SI goes back high. Whe n SI is asser ted all sample
data will be flushed immed iately, the numer ically controlled
oscillator (NC O) phase offset will be initialized, the NCO
dither generators will be reset, a nd the CIC decim ation ratio
will be initialized. Only the configuration data loaded into the
micropr ocessor inte rface rem ain s unaf fected.
SI may be held low as long as desired after a minimum of 4
CK periods.
Input Source
The input crossbar switch allows either AIN, BIN, or a test
register to be routed to the chan nel A or c hannel B AGC/
DDC. The AGC outputs, AGAIN and BGAIN, are not
s witched. If AIN and BIN are ex ch ang ed th e A G C l oo p wi l l be
open and t he AGCs will not fun ction proper ly. AIN and BIN
should meet the timing requirements shown in Figure 7.
Selecting the test register as the input source allows the
A GC or DDC operation to be verified with a k nown input. See
the test an d di agnostics sec t io n for further dis cussion.
Down Converters
A detailed block diagram of each DDC channel is shown in
Figure 1 6. E ach down c onverte r uses a comp lex NCO an d
mixer to quadrature downconver t a signal to baseband. The
“FLOAT TO FIXED CONVERTER” treats the 15-bit mixer out-
put as a m antissa and the AGC output, EXP, as a 3-bit expo-
nent. It perfor ms a bit shift on the data bas ed on th e value of
EXP. This bit shifting is used to expand the compressed
dynamic range resulting from the DVGA operation. The
DVGA gain is adjusted in 6dB steps which are equivalent to
each dig ital bit shi f t.
Digitally compensating for the DVGA gain steps in the
CLC5903 causes the DDC output to be linear with respect to
the DVGA input. The AGC operat ion wil l be c omplete ly t rans-
par ent at th e CLC590 3 output .
The exponent (EXP) can be forced to its maximum value by
setting the EXP_ INH bit. If is the DDC in put, the sig-
nal after the “FLOAT TO FIXED CONVERTER” is
(1)
for the I component. Changing the ‘cos’ to ‘sin’ in this equa-
tion will provid e th e Q com ponent.
The “FLOAT TO FIXED CONVERTER” circuit expands the
dynamic range compression performed by the DVGA. Sig-
nals from this point onward extend across the full dynamic
range of the signals applied to the DVGA input. This allows
the AGC to operate continuously through a burst without pro-
ducing art ifacts in the signal due to the settling response of
the decim ation f ilters aft er a 6dB DVGA gain ad justm ent. For
example, if the DVGA input signal were to increase causing
the ADC output level to cross the AGC threshold level, the
gain of the DVGA would change by -6dB. The 6dB step is
allowed to propagate through the ADC an d mixers and is
compensated out just before the filtering. The accuracy of
NCO
SCALE
DEC
CIC FILTER
FREQ_A
PHASE_A
SHIFT UP
F1_COEF
F1 FILTER
F2_COEF
F2 FILTER
DECIMATE BY
8 TO 2K
DECIMATE BY 2
DECIMATE BY
SHIFT UP
Data @ FCK
2 OR 4 DEC_BY_4
CONVERTER
TO FIXED
FLOAT
EXPONENT
EXP
EXP_INH
14
3
22
22
21
21
EXP
TO
OUTPUT
CIRCUIT
GAIN_A
17 17
SAT & ROUND
SAT
21
21
SAT & ROUND
ROUND
15
15
Figure 16. CLC5903 Down Convert er, Channel A (Ch annel B is identical)
SIN COS
I
Q
(from AGC)
x3n()
xin n()
MUXA
= FS (FSAMPLE)
Data @ FCK/N Data @ FCK/N*2 Data @ FCK/N*2*F2_DEC
= OFS (Output FSAMPLE)
N = DEC + 1
xin n()
x3n() xin n() ωn()cos•2EXP
•=
Detailed Description (Continued)
13 www.national.com
CLC5903
the compensation is dependent on timing and the accuracy
of the DVGA gain step. The CLC5903 allows the timing of the
gain compensation to be adjusted in the EXT_DELAY regis-
ter. This operating mode requires 21 bits (14-bit ADC output
+ 7-bit shift) to represent the full linear dynamic range of the
signal. The output word must be set to either 24-bit or 32-bit
to take advantage of the entire dynam ic range available. The
CLC5903 can also be configured to output a floating point
f ormat with up to 138dB of numerical resolution using only 12
output bits.
The “SHIFT UP” circuit will be discussed in the Four Stage
CIC filter section on page 14.
A 4-stage cascaded-integrator-comb (CIC) filter and a
two-stage deci mate by 4 or 8 finite i mpulse r esponse ( FIR)
filter are used t o lowpass filte r and isolat e the des ired sig nal.
The CIC filter reduc es the samp le rate by a programma ble
f actor ranging from 8 to 2048 (decimation ratio). The CIC out-
puts are followed by a gain stage and then followed by a
two-stage decimate by 4 or 8 filter. The gain circuit allows the
user to boost the gain of wea k si gnals by up to 42 dB in 6 d B
steps. It also rounds the signal to 21 bits and saturates at
plus or minu s ful l s cal e.
The first stage of t he two stage filter is a 2 1-tap, symmet ric
decimate by 2 FIR filter (F1) with programmable 16 bit tap
weights. The co efficien ts of the first 11 taps are downloaded
to the chip as 16 bit words. Since the filter is a symmetric
configuration only the first 11 coefficients must be loaded.
The F1 section on page 15 provides a generic set of coeffi-
cients that compensate f or the rolloff of the CIC filter and pro-
vide a passband flat to 0.01dB with 70 dB of out of band
rejection. A second coeffic ient set is pr ovid ed t hat has a nar-
rower output passband and greater out-of-band rejection.
The seco nd set of coef ficients is ideal for system s such as
GSM where far-image rejection is more important than adja-
cent channel rejection.
The second stage is a 63 tap decimate by 2 or 4 programma-
ble FIR filter (F2) also with 16 bit tap weights. Filter coeffi-
cients for a flat r espon se fr om -0. 4FS to +0.4FS of the outp ut
sample rate with 80dB of out of band rejection are provided
in the F2 sect ion. A seco nd set of F2 coef ficient s is also pr o-
vided to enhan ce perfor mance for GSM systems. The user
can also design and download their own final filter to custom-
ize the channel’ s spectral response. Typical uses of program-
mable filter F2 includ e matche d (root -raised cosine) fi lterin g,
or filtering to generate oversampled outputs with greater out
of band rejection. The 63 tap symmetr ical filter is down-
loaded into the ch ip as 32 word s, 16 bits each. Saturatio n to
plus or minus full scale is performed at the output of F1 and
F2 to clip the signal rather than allow it to roll over.
The CLC5903 provides two sets of coefficient memory for
both F1 and F2. These coefficient memories can be indepen-
dently routed to channel A, channel B, or both channel A and
B with a crossbar switch. The coefficients can be s witched on
the fly but some time will be re quir ed before valid output dat a
is available.
The Numerically Controlled Oscillator
The tun ing freque ncy of eac h down c onver ter is s pec ified a s
a 32 bit word (.02Hz resolution at CK=52MHz) and the phase
offset is specified as a 16 bit word (.005°). These two param-
eters are ap plied to the Numer ically Controlled Oscillator
(NCO) circuit to generate sine and cosine signals used by
the digital mixer. The NCO s can be syn chron ized w ith NCO s
on other chips via the sync pin SI. This allows multiple down
conver ter outputs to be coherently combined, each w ith a
unique p hase and ampli t ude.
The tuning f requency is set by loading the FREQ register
according to the for mula FREQ = 232F/FCK, where F is the
desired tuning f requency and FCK is the chip’s clock rate.
FREQ is a 2’s complement word. The range for F is from
-FCK/2 to +FCK(1-2-31)/2.
In some cases the samp lin g proce ss caus es th e order of the
I and Q components to be re versed. Should this occur simply
invert the pol arity of the tu ni ng f re quency F.
(a) Before Phase Dithering (b) After Phase Dithering
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
-160
-140
-120
-100
-80
-60
-40
-20
0
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
-160
-140
-120
-100
-80
-60
-40
-20
0
Frequency Normalized to FSFrequency Normalized to FS
Magnitude (dB)
Magnitude (dB)
Figure 17. Examp le of NCO s purs due to pha se tru ncation
Complex NCO Output Complex NCO Output
Detailed Description (Continued)
www.national.com 14
CLC5903
The 2’s complement format represents full-scale negative as
10000000 and full-scale positive as 01111111 for an 8-bit
example.
The 16 bit phase offse t is set by loading the PH ASE register
according to the formula PHASE = 216P/2π, where P is the
desired p has e in radians ran ging betwee n 0 and 2π. PHASE
is an unsigned 16-bit number. P ranges from 0 to 2π(1-2-16).
Phase dithering can be enabled to reduce the spurious sig-
nals created by the NCO due to phase truncation. This trun-
cation i s unavoidable since the freque ncy reso lution is m uch
finer than the phase resolution. With dither enabled, spurs
due to phase truncation are below -100 dBc for all frequen-
cies an d pha se offset s. Each NCO ha s its own di ther s ource
and the init ial stat e of one is m axi mally o ffse t wi th res pect to
the other so that they are effectively uncorrelated. The phase
dither sources are on by default. They are indepe ndently
cont rolled by th e DITH _A and D ITH_B b its. The am plitude
resolution of the ROM creates a worst-case spur amplitude
of -101dBc render in g am plitude dither unnecessary.
The spectrum plots in Figure 17 show the effectiveness of
phase di ther i n red ucin g NC O sp urs d ue to pha se tr un cation
for a worst-case example (just below FS/8). With dither off,
the spur is at -86.4dBFS. With dither on, the spur is below
-125dBFS, disappearing into the noise floor. This spur is
spread into the noise floor which results in an SNR of
-83.6dB FS. The chann el filter’s processing ga in will fur ther
improve the SNR.
Figure 18 s hows the spu r levels as the tuning frequency is
scanned over a narrow por tion of the f requency range. The
spurs ar e again a resul t of phase qua ntization but their loca-
tions move about as the frequency scan progresses. As
before, the peak spur level drops when dithering is enabled.
When dither is en abled and the f undamental frequency is
exactly at FS/8, the worst-case spur due to amplitude quanti-
zation can be observed at -101dBc in Fig ure 19.
Four Stage CIC Filter
The mixer outputs are decimated by a factor of N in a four
stage CIC filter. N is programmable to any integer betwee n 8
and 2048. Decimation is programmed in the DEC register
where DEC = N - 1. The programmable decimation allows
the chip’s usable output bandwidth to range from about
2.6kHz to 1.3MHz when the input data rate (which is equal to
the chip’s clock rate, FCK) is 52 MHz. F o r the maximum sam-
ple rate of 78MHz, the CLC5903’s output bandwidth will
range fro m about 4.7 6kHz to 1.9 5MHz. A block diagram of
the CIC filter is shown in Figure 20.
The CIC filter is primarily used to decimate the high-rate
incoming data while providing a rough lowpass characteris-
tic. The lowpass filter will have a sin(x)/x response (similar to
the AGC’s CIC shown in Figure 36 on page 24) where the
fir s t null is at F S/N.
The CIC filter has a gain equal to N 4 (filter decimation^4)
which must be compensated for in the “SHIFT U P” circuit
shown in Figure 20 as we ll as Figure 16. This circuit has a
gain equal to 2(SCALE-44), where SCALE ranges from 0 to 40.
This circuit divides the input signal by 244 providing maxi-
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
-160
-140
-120
-100
-80
-60
-40
-20
0
Frequency Normalized to FS
Magnitu de (dB )
Figure 18. NCO Spurs due to Phase Qua nt izat io n
Complex NCO Output
Phase Dither Disabled
NCO frequency swept
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
-160
-140
-120
-100
-80
-60
-40
-20
0
Frequency Normalized to FS
Magnitude (dB)
Figure 19. Worst Case Amplitude Spur, NCO at FS/8
Complex NCO Output
Phase Dither Enabled
DATA
IN DATA
OUT
DECIMATE
BY FACTOR
OF N
SCALE
SHIFT UP
22
Figure 20. Four-stage decimate by N CIC filter
66
Data @ FCK
= FS (FSAMPLE)Data @ FCK/N
N = DEC + 1
22-bit input to SHIFT_UP is aligned
at the bottom of the 66-bit path when SCALE=0.
Detailed Description (Continued)
15 www.national.com
CLC5903
mum head room th roug h the CI C filter. For optimal no ise per-
form ance the SCALE value is set to increase this level until
the CIC filter is just below the point of distort ion. A value is
normally calculated and loaded for SCALE such that
. The actual gain of the CIC
filter wi ll only be uni ty for power-of-two decim ation value s. In
other cases the gain will be somewhat less than unity.
Channel Gain
The gain of each cha nnel can be boosted up to 42 dB by
shifting th e output of the CIC filte r up by 0 to 7 bits pr ior to
rounding i t to 2 1 bi t s. For channel A , the gain of this stage is:
, where GAIN_A ranges from 0 to 7. Over-
flow due to the GAIN circuit is saturated (clipped) at plus or
minus full scale. Each channel can be given its own GAIN
setting.
First Programmable FIR Filter (F1)
The CIC/GAIN outputs are followed by two stages of filtering.
The first stag e is a 21 tap decim ate- by-2 symme tri c FIR filter
with programmable coefficients. Typically, this filter compen-
sates for a sligh t d ro op in duced by the CIC filter while remo v -
ing undesired alias images above Nyquist. In addition, it
often provides stopband assistance to F2 when deep stop
bands ar e re quir ed. T he filte r coe fficien ts a re 16 -bit 2 ’s com-
plement numbe rs. Unity gain will be achieved through th e fil-
ter if the sum of the 21 coeffi cients is equal to 216. If the sum
is not 216, then F1 will introduce a gain equal to (sum of coef-
ficients)/216. The 21 coeffici ents are i dent ified as coe fficien ts
where is the cent er tap. The
coefficients are symmetric, so only the first 11 are loaded
into the c hip.
Two exampl e sets of coe fficient s are provided here. The first
set of coefficients, referred to as the standard set (STD),
compen sa tes for the droop of th e CIC filter providin g a pass-
band which is flat (0.01 dB ripple) over 95% of the final out-
put band w idt h w i th 70dB of out- of -b and rejection ( see Figure
21). The filter has a gain of 0.999 and is symmetric with the
followin g 11 u nique taps (1| 21, 2|20, ..., 10|1 2, 11):
29, -85, -308, -56, 1068, 1405, -2056, -6009,
1303, 21121, 32703
The second set of coefficients (GSM set) are intended for
applications that need deeper stop bands or need oversam-
pled outputs. These requirements are common in cellular
systems where out of band rejection requirements can
exceed 100dB (se e Fi gure 22). They are usef ul for wideband
radio architectures where the channelization is done after the
ADC. These filter coefficients introduce a gain of 0.984 and
are: -49, -340, -1008, -1617, -1269, 425, 3027, 6030,
9115, 11620, 12606
Second Programmable FIR Filter (F2)
The second stage decimate by two or four filter also uses
externally downloaded filter co efficients. F2 deter mines the
final channel filter response. The filter coefficients are 16-bit
2’s complement numbers. Unity gain will be achiev ed through
the filter if the sum of the 63 coefficients is equal to 216. If the
sum is not 216, then the F2 will introduce a gain equal to
(sum of coefficient s) /2 16.
The 63 coefficients are identified as
where is the center tap. The coefficients are sym-
metric, so only the firs t 32 are lo ade d i nt o th e chip.
An exam ple filter (STD F2 coefficients, see Figure 23) with
80dB out-of-band rejection, gain of 1.00, and 0.03 dB peak to
peak passband ripple is created by this set of 32 unique
coefficients:
-14, -20, 19, 73, 43, -70, -82, 84, 171, -49, -269,
-34, 374, 192, -449,
-430, 460,751, -357, -1144, 81, 1581, 443, -2026,
-1337, 2437, 2886,
-2770, -6127, 2987, 20544, 29647
A second set of F2 coefficients (GSM set, see Figure 24)
suitable for meeting the stri ngent wideband GSM require-
ments w ith a gain of 0.999 are :
-536, -986, 42, 962, 869, 225, 141, 93, -280,
-708, -774, -579, -384,
-79, 536, 1056, 1152, 1067, 789, 32, -935, -1668,
-2104, -2137, -1444,
71, 2130, 4450, 6884, 9053, 10413, 10832
The filter coefficients of both filters can be used to tailor the
spectral response to the user’s needs. For example, the first
can be loaded with the standard set to provide a flat
GAINSHIFTUP GAINCIC
⋅1≤
GAIN 2GAIN_A
=
h1n() n,0…20,,=h110()
Figure 21. F1 STD fr equency respons e
0 0.1 0.2 0.3 0.4 0.5
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency Response of F1 Using STD Set
Magnitude (dB)
Frequency Normalized To Filter Input Sample Rate
Figure 22. F1 G SM fr equency response
0 0.1 0.2 0.3 0.4 0.5
−120
−100
−80
−60
−40
−20
0
Frequency Response of F1 Using GSM Set
Magnitude (dB)
Frequency Normalized To Filter Input Sample Rate
h2n() n0…62,,=,
h231()
Detailed Description (Continued)
www.national.com 16
CLC5903
respon se thr ough to the seco nd filter. The latter ca n then be
programmed as a Nyquist (typically a root-raised-cosine) fil-
ter for matched filtering of digi ta l dat a.
The complete channel filter response for standard coeffi-
cients is shown in Figure 25. Passband flatness is shown in
Figure 26. The complete filter response for GSM coefficients
is shown in Figure 2 7. GSM Passband flatness is shown in
Figure 28.
The mask shown in Figu re 27 i s der ived from the ET SI GS M
5.05 specifications for a normal Basestation Transceiver
(BTS). For interferers, 9dB was added to the carrier to inter-
ference (C/I) ratios. For blockers, 9dB was added to the dif-
ference between the blocker level and 3dB above the
reference sensitivity level.
Channel Bandwidth vs. Sample Rate
When the CLC5903 is used for GSM syst ems, a bandwidth
of about 200kHz is desired. With a sample rate of 52MHz,
the total deci mation of 192 provides the de sired 27 0.833kHz
output sample rate. This output sample rate i n combination
with the FIR filter coefficients create the desired channel
bandwidth. If the sample rate is increased to 65MHz, the
decima tion mu st also be increas ed to 65M Hz/2 70.83 3kH z or
240. This new decimation rate will maintain the same output
bandwidth. At 78MHz, the decimation must increase again to
78MHz/270.833kHz or 288. The output bandwidth may only
be changed in relation to the output sample rate by creating
a new set of FIR filter coefficients. As the filter bandwidth
Figure 23. F2 STD fr equency respons e
0 0.1 0.2 0.3 0.4 0.5
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency Response of F2 Using STD Set
Magnitude (dB)
Frequency Normalized To Filter Input Sample Rate
Figure 24. F2 G SM fr equency response
00.1 0.2 0.3 0.4 0.5
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5Frequency Response of F2 Using GSM Set
Magnitude (dB)
Frequency Normalized To Filter Input Sample Rate
Figur e 25. C I C, F1 , & F2 ST D frequency response
0500 1000 1500 2000 2500 3000
−150
−100
−50
0
Combined Frequency Response of CIC/F1/F2 Using STD Set
Magnitude (dB)
Frequency (KHz)
FCK = 52MH z
Decimation = 192
OFS = 270.83kHz
Figure 26. CIC, F1, & F2 STD Passband Flatness
0 50 100 150 200 250
−0.1
−0.08
−0.06
−0.04
−0.02
0
0.02
0.04
0.06
0.08
0.1 Combined Frequency Response of CIC/F1/F2 Using STD Set
Magnitude (dB)
Frequency (KHz)
Figure 27. CIC , F1, & F2 GS M frequency respons e
0 500 1000 1500 2000 2500 3000
−100
−80
−60
−40
−20
0
Combined Frequency Response of CIC/F1/F2 Using GSM Set
Magnitude (dB)
Frequency (KHz)
FCK = 52MH z
Decimation = 192
OFS = 270.83kHz
Detailed Description (Continued)
17 www.national.com
CLC5903
decreases relative to the output sample rate, the CIC droop
compensation perf ormed by F1 may no longer be required.
Overall Channel Gain
The overall gain of the chip is a function of the amount of
decimation (N), the settings of the “SHIFT UP” circuit
(SCALE), the GAIN setting, the sum of the F1 coefficients,
and the sum of the F2 coefficient s. The overall gain is shown
below in Equation 2.
(2)
Where:
(3)
and:
(4)
It is assume d that the DDC out put word s are tre ated as frac-
tional 2’s complement words. The numerators of and
equal the sums of the impulse respons e coeff icients of
F1 and F2 , respectively. For the STD and GS M sets,
and are nearly equal to unity. Observ e that the
term in (2) is cancelled by the DVGA operation so that the
entire gain of the DRCS is independent of the DVGA setting
when EXP_INH=0. The appearing in (2) is the result of the
6dB conversion loss in the mixer. For full-scale square wave
inputs th e shoul d be set to 1 to prevent signal distort io n.
Data Latency and Group Delay
The C LC5903 latency ca lculation assumes t hat the FIR filter
latency will be equal to the time required for data to propa-
gate thr ough on e half o f the taps. Th e CIC filte r provides 4N
equivalent taps where N is the CIC decimation ratio. F1 and
F2 provide 21 and 63 taps respectively. When these filters
are reflecte d back to the input rate, the effective taps are
increased by decimation. This results in a total of 298N taps
when the F2 decimation is 2 and 550N t aps when the F2
decimat i on i s 4.
The latency is then 149N CK per iods when the F2 decima-
tion is 2 and 275 N C K periods w hen the F2 decim at i on is 4.
The CLC5903 filters are linear phase filters so the group
delay remains constant.
Output Modes
After processing by the DDC, the data is then formatted for
output.
All output data is two’s complement. The serial outputs
power up in a tri-state condition and must be enabled
when the chip is configured. Parallel outputs are
enabled by the P O U T_EN pin.
Output format s incl ude t ru ncat ion to 8 or 3 2 b its, roundi ng t o
16 or 24 bits, and a 12- bit floating point forma t (4-bit expo-
nent, 8-bit mantissa, 138dB numeric range). This function is
perfor med in the OUTPUT CIRCUIT shown in Figure 29.
The chan nel outpu ts are acces sible thr ough ser ial output
pins and a 16-bit parallel output port . The RDY pin is pro-
vided to notify the user that a new output sample period
(OSP) h as be gun . OSP r efers to the interval betwe en ou tput
samples at the de cimated output rate. For example, if the
input rate (an d c lock rate) is 52 MHz an d the overall decima-
tion factor is 192 (N=48, F2 decimation=2) the OSP will be
3.69 microsecon ds which corresponds to an output sam ple
Figure 28. CIC, F1, & F2 GSM Passband Flatness
020 40 60 80 100
−2
−1.5
−1
−0.5
0
0.5
1Combined Frequency Response of CIC/F1/F2 Using GSM Set
Magnitude (dB)
Frequency (KHz)
GDDC 1
2
---DEC 1+()
4
2SCALE 44–AGAIN 1EXP_INH–()⋅–[]
2GAIN
GF1GF2
⋅
⋅
⋅⋅
=
GF1
h1i()
i1=
21
∑
216
-----------------------
=
GF2
h2i()
i1=
63
∑
216
-----------------------
=
GF1
GF2GF1
GF2AGAIN
1
2
---
1
2
---
DIVIDE
BY
BOUT
AOUT
16
RATE
POUT_SEL[2..0]
POUT[15..0]
CH BCH A
POUT_EN
CK SCK
3
RDY
MUX
NUMBER FORMAT
CONTROL
FORMAT
POLARITY INVERT
MUX_MODE
PACKED
RDY_POL, SCK_POL, SFS_POL
Figure 29. CLC5903 output circuit
SFS
SCK_IN
SERIALIZER AND
TDM FORMATTER
SFS_MODE
Output Modes (Continued)
www.national.com 18
CLC5903
rate of 270.833kHz. An OSP starts when a sample is ready
and stops w hen the next one is ready.
Serial Outputs
The C LC 5903 p rovid es a se rial clock (SCK), a frame s trobe
(SFS) and two data lines ( AOUT and BOUT) to output ser ial
data. The MUX_MODE control register specifies whether the
two channel outputs are transm itted on two separate se rial
pins, or multiplexed onto one pin in a time division multi-
plexed (TDM) format. Separate output pins are not provided
for the I and Q halves of complex data. The I and Q outputs
are always multiplexed onto the same serial pin. The I-com-
ponent is output first, followed by the Q-component. By set-
ting the PACKED mode bit to ‘1’ a complex pair may be
treated as a single double-wide word. The RDY signal is
used to iden tify the first word of a com plex pair of the TDM
formatted output when the SFS_MODE bit is set to ‘0’. Set-
ting SFS_MODE to ‘1’ causes the CLC5903 to output a sin-
gle SFS pulse for each ou tput per iod . This SFS pulse will be
coincident with RDY and only a single SCK pe ri od wide. The
TDM modes are summarized in Table 1.
The serial outputs use the format shown in Figure 30. Figure
30(a) shows the standard output mode (the PACKED mode
bit is low). The chi p clocks the frame an d data out of the chip
on th e ris in g edge of SCK (or falling edge if the SCK_POL bit
in the input control register is set high). Data should be cap-
tured on t he falling edg e of SCK (rising if SCK_POL=1). The
SFS_MODE MUX_MODE SERIAL OUTPUTS
AOUT BOUT
00OUTAOUTB
1OUTA, OUTBLOW
10OUTAOUTB
1OUTA, OUTBLOW
Table 1. TDM Mod es
SCK
SFS
AOUT I15 I14 I1 I0 Q15 Q14
(a) UNPACKED MODE, FRAME SYNC AT THE START OF EACH WORD
SCK
SFS
AOUT I15 I14 I1 I0 Q15 Q14
(b) PACKED MODE, ONE FRAME SYNC AT THE START OF EACH DOUBLE-WORD TRANSFER
clock stops and data is zero after transfers are complete
RDY
(c) ONE OR TWO CHANNEL MUX AND SFS MODES (PACKED MODE IS ON)
SFS
A|BOUT
AOUT
MUX_MODE=0, SFS_MODE=0|1
MUX_MODE=1, SFS_MODE=0
Output Sample Period (OSP)
Q1 Q0
Q1 Q0
IA QA
SFS
IA QA IB QB IA QA IB QB
IA QA
SCK
SFS
AOUT mI7 eI3 eI0 eQ3
(d) FLOATING POINT FORMAT
eQ0 mQ0
mI0 mQ7
leading edge of RDY aligns with leading edge of SFS
Figure 30. Serial output formats. Refer to Figure 10 for detailed timing information
RDY is 2 CK periods wide
mI6 eI2
clock stops and data is zero after transfers are complete
clock stops and data is zero after transfers are complete
SFS
AOUT MUX_MODE=1, SFS_MODE=1
IA QA IB QB IA QA IB QB
Output Modes (Continued)
19 www.national.com
CLC5903
chip sends the I data first by setting SFS high (or low if
SFS_POL in the input con trol register is se t high) for one
clock cycle, and then transmitting the data, MSB first, on as
many SCK cycles as are necessary. Without a pause, the Q
data is transferred next as shown in Figure 30(a). If the
PACKED control bit is high, then the I and Q components are
sent as a double length word with only one SFS strobe as
shown in Figure 30(b). If both channels ar e multiplexed out
the same serial pin, then the subsequent I/Q channel words
will be transmitte d immediately following the first I/Q pair as
shown in Figure 30(c). Figure 30(c) also shows how
SFS_MODE=1 allows the SFS signal to be used to identify
the I and Q channe ls in the TDM serial transmission. The
serial out put rate is programm ed by the R ATE register to CK
divided by 1, 2, 4, 8, 1 6, or 32. The serial interface will n ot
work properly if the programmed rate of SCK is insufficient t o
clock out all the bits in one OSP.
Serial Port Daisy-Chain Mode
Two CLC 5903s can be co nnected in ser ies so that a single
DSP serial port can receive four DDC output channels. This
mode is enabled by setting the SDC_EN bit to ‘1’ on the
serial daisy-chan (SDC) master. The SDC master is the
CLC5903 which is connected to the DSP while the SDC
slave’s ser ial output drives the master. The SDC master’s
RATE register must be set so that its SCK rate is twice that o f
the SDC s lave, the S DC m aste r mu st h ave MU X_M OD E=1 ,
the SDC slave must have MUX_MO DE=0 and PACKED=1,
and both chips must come out of a MR or SI event within four
CK periods of each other. In this configuration, the master’s
serial output data is shifted out to the DSP then the slave’s
serial data is shifted out. All the serial output data will be
muxed onto the maste r’s AOUT pin as shown in Figure 31.
Serial Port Output Number Form ats
Several numer ic forma ts are selectable using the FORMAT
control register. The I/Q samples can be rounded to 16 or 24
bits, or truncated to 8 bits. The packed mode works as
described abov e f or these fixed point f ormats. A floating point
format with 138dB of dynamic range in 12 bits is also pro-
vided. The m antissa (m) is 8 bits and the exponent (e ) is 4
bits. The MSB of each segment is transmitted first. When this
mode is selected, the I/Q samples are packed regardless of
the state of MUX_MODE , and the data is sent as mI/eI/eQ/
mQ which allows the two exponents to form an 8-bit word.
This is shown in Figure 30(d). For all formats, once the
defined l ength of the word is com plete, SCK stops toggling.
P a ra lle l Out puts
Output data from the channels can also be taken from a
16-bit parallel port. A 3-bit word applied to the
POUT_SEL[2:0] pins determines which 16-bit segment is
multiplexed to the parallel port. Table 2 defines this mapping.
To allow for bussing of multiple chips, the parallel port i s
tri-s tated unles s POUT_EN is low. The RDY signal indicates
the start of an OSP and that new data is ready at the parallel
output. The user has one OSP to cycle through whichever
register s ar e need ed . The RATE regist er mu st be set so that
each OSP is at least 5 SCK periods.
P a ra lle l Port Output Numeric Formats
The I/Q sample s can be round ed to 16 or 24 bits or the full
32 bit word can be read. By setting the word size to 32 bits it
is possible to read out the top 1 6 bits and only obser ve the
top 8 bits if desired. Additionally, the output samples can be
formatted as floating point numbers with an 8-bit mantissa
and a 4 bit exponent. For the fixed-point formats, the valid
bits are justified into the MSBs of the registers of Table 2 and
all other bits are set to zero. For the floating point format, the
valid bits are placed in the upp er 16 bits of the appropr iate
channe l register us ing the form at 0000/e I/mI for th e I sam-
ples.
AGC
The CLC5903 AGC processor monitors the output level of
the ADC and servos it to the desired setpoint. The ADC input
is controlled by the DVGA to maintain the proper setpoint
12
4
12
ADCs and
DVGAs
Figure 31. Serial Dai sy- C hain Mode
AOUT
SCK
SFS
RDY
ParallelOutput[15..0]
ParallelOutputEnable
ParallelSelect[2..0]
12
4
12
Slave
ADCs and
DVGAs
CLC5903 Master
CLC5903
SCK_IN
AOUT
BOUT
SFS
SCK
POUT_SEL[0]
POUT_SEL[1]
POUT_SEL[2] To DSP
SDC_EN=1
SCKMASTER=2*SCKSLAVE
SDC_EN=0
MUX_MODE=0
PACKED=1 MUX_MODE=0
POUT_SEL No rma l Register
Contents Floating Point
Register Contents
0 IA upper 16 bits 0000/eI A/mI A
1 IA lower 16 bits 0x0000
2 QA upper 16 bits 0000/ eQA/ mQ A
3 QA lower 16 bits 0x0000
4 IB upper 16 bits 0000/eI B/mI B
5 IB lower 16 bits 0x0000
6 QB upper 16 bits 0000/ eQB/ mQ B
7 QB lower 16 bits 0x0000
Table 2. Register Selection for Parallel Output
AGC (Continued)
www.national.com 20
CLC5903
level. DVGA ope ration res ults in a comp ressio n of th e signal
through t he AD C. The DVGA sign al c ompres sion is reversed
in the CLC5 903 to provide > 120 dB of linear dyn amic range.
This is illustrated in Figure 32.
In order to use the AGC, the DRCS Control Panel software
may be used to calculate the programmable parameters. To
generate these parameters, only the desired setpoint, dead-
band+hysteresis, and loop time con stant ne ed to be sup-
plied. All subsequent calculations are performed by the
software. Complete details of the AGC operation are pro-
vided in an appendix but are no t required readi ng.
AGC setpoint and deadband+hysteresis are illustrated in Fig-
ure 33. The loop time constant is a measure of how fast the
loop will track a changing signal. Values down to approxi-
mately 1.0 microsecond will b e stable with the second order
LC noise filter. Since the DVGA operates with 6dB steps the
deadband should always be greater than 6dB to prevent
oscillation. An increased deadband value will reduce the
amount of AGC operation. A decreased deadband value will
increase the amount of AGC operation but will hold the ADC
output closer to the setpoint. The threshold should be set so
that transi ents do n ot cause sustained overrange at t he ADC
inputs. The threshold setting can also be used to set the
ADC inpu t near its optimal p erfor m ance level.
The AGC will free r un when AGC_HOLD_IC is set to ‘0’. It
may be set to a fixed gain by setting AGC_HOLD_IC to ‘1’
after programming the desired gain in the AGC_IC_A and
AGC_IC_B regi ster s. Allowing t he AGC to fre e r un should b e
appropriate for most applications.
Programming the AGC_COMB_ORD register allows the
AGC power detector bandwidth to be reduced if desired. This
will tend to i mprove the power detector’s ability to reject the
signal carrier frequency and reduce overall AGC activity. Fig-
ure 36 on page 24 shows the power detector response.
Power Management
The CLC5903 can be placed in a low power (static) state by
stopping the input clock. To prevent this from placing the
CLC5903 into unexpected states, the SI pin of the CLC59 03
should be asserted p rior to disabling th e i nput clock an d held
asserted unt il the in put clock ha s retu rn ed to a s table cond i-
tion.
Test and Diagnostics
The CLC5903 supports IEEE 1149.1 compliant JTAG Bound-
ar y Scan for the I/O's. The following pins are used:
TRST (test reset)
TMS (test mode select)
TDI (test data in)
TDO (test data out)
TCK (test clock)
The following JTAG instruction s ar e supported :
The JTAG Boundary Scan can be used to verify printed cir-
cuit board continuity at th e system level.
The user is able to program a value into TES T_REG and
substitute this for the norm al channel inputs from the AIN/
BIN pins by sele cting it w ith the crossb ar. With the N CO fre-
quency set to zero this allows the DDCs and the output inter-
face o f the c hip to be ver ified . Als o, the AGC loo p ca n be
opened by setting AGC_HOLD_IC high and setting the gain
of the DVGA by programming the appropriate value into the
AGC_IC_A/B re gi st er.
Real-time a ccess to the following sign als is p rovided by c on-
figur in g t he control inter face debug regi st er:
• NCO sine and cosine outputs
• data after round following mixers
• data before F1 and F2
• data after the CIC filter within the AGC
The acce ss points are multiplexed to a 20-b it parallel output
port which is created from signal pins POUT[15:0], AOUT,
BOUT, SFS, and RDY according to th e t able below:
Figure 32. Output Gain Sca lin g vs. Input Sig nal
Input Power
ADC Output
ADC Full Scale
AGC Threshold
Deadband+Hysteresis
Output Pow er
DDC Output
Diversity Receiver
AGC Operates
Over This Range
Chipset Full Scale
Figure 33. AGC Setup.
DVGA Input Power
DVGA Ou tp ut Power
Deadband
Hysteresis=Deadband-6dB
Reference
6dB
6dB
Setpoint
Instruction Description
BYPASS Connects TDI directly to TDO
EXTEST Drives the ‘extest’ TAP controller output
IDCODE Connects the 32-bit ID register to TDO
SAMPLE/PRELOAD Drives the ‘samp_load’ TAP controller
output
HIGHZ Tri-states the outputs
Normal Mode Pin Debug Mode Pin
POUT[15:0] DEBUG[19..4]
RDY DEBUG[3]
SFS DEBUG[2]
AOUT DEBUG[1]
BOUT DEBUG[0]
Test and Diagnostics (Continued)
21 www.national.com
CLC5903
SCK will be se t to t he pro per s trobe ra te for eac h debug t ap
point. POUT_EN and PSEL[2..0] have no effect in Debug
Mode. The outputs are turned on when the Debug Mode bit
is set. Norma l serial output s ar e also disabled.
Control Registers
The chip is configured and controlled through the use of 8-bit
control registers. These registers are accessed for reading or
writing using the control bus pins (CE, RD, WR, A[7:0], and
D[7:0]) de scribe d in th e C ontrol Inter face section.
The two sets of FI R co effic ients ar e overla id at the sam e
memory address. Use the PA GE_SEL registers to access
the second set of coefficients.
The register names and descriptions are listed below under
Control Register Addresses and Defaults on page 21. A
quick reference table is provided in the Condensed CLC5903
Address Map on page 22.
Control Register Addresses and Defaults
Register Name Width T ype DefaultaAddr Bit Description
DEC 11b R/W 7 0(LSBs)
1(MSBs) 7:0
2:0 CIC decimation control. N=DEC+1. Valid range is from 7 to 2047. Format is an unsigned
integer. This affects both channels.
DEC_BY_4 1b R/W 0 1 4 Controls the decimation factor in F2. 0=Decimate by 2. 1=Decimate by 4. This affects both
channels.
SCALE 6b R/W 0 2 5:0 CIC SCALE parameter. Format is an unsigned integer representing the number of left bit
shifts to perform on the data prior to the CIC filter. Valid range is from 0 to 40. This affects
both channels.
GAIN_A 3b R/W 0 3 2:0 Value of left bit shift prior to F1 for channel A.
GAIN_B 3b R/W 0 4 2:0 Value of left bit shift prior to F1 for channel B.
RATE 1B R/W 1 5 7:0 Determines r ate of seria l output cloc k. The output rate is FCK /(RATE+1). Unsigned integer
values of 0, 1, 3, 7, 15, and 31 are allowed.
SOUT_EN 1b R/W 0 6 0 E nables the serial output pins AOUT, BOUT, SCK, and SFS. 0=Tristate. 1=Enabled.
SCK_POL 1b R/W 0 6 1 Determines polarity of the SCK output. 0=AOUT, BOUT, and SFS change on the rising
edge of SCK (capture on falling edge). 1=They change on the falling edge of SCK.
SFS_POL 1b R/W 0 6 2 Determines polarity of the SFS output. 0=Active High. 1=Active Low.
RDY_POL 1b R/W 0 6 3 Determines polarity of the RDY output. 0=Active High. 1=Active Low.
MUX_MODE 1b R/W 0 6 4 Determines the mode of the serial outputs. 0=Each channel is output on its respective pin,
1=Both channels are multiplexed and output on AOUT. See also Table 1.
PACKED 1b R/W 0 6 5 Controls when SFS goes active. 0=SFS pulses prior to the start of the I and the Q words.
1=SFS pulses only once prior to the start of each I/Q sample pa ir (i.e . the pair is tre ated a s
a double-sized word) The I word precedes the Q word. See Figure 30.
FORMAT 2b R/W 0 6 7:6 Determines ou tput n um ber format. 0=Truncate serial ou tput to 8 bits . Par all el outp ut is trun-
cated to 32 bits. 1=Round both serial and parallel to 16 bits. All other bits are set to 0.
2=Round both serial and parallel to 24 bits. All other bits are set to 0. 3=Output floating
point. 8-bit mantissa, 4-bit exponent. All other bits are set to 0.
FREQ_A 4B R/W 0 7-10 7:0 Frequ ency w ord for chann el A . Format is a 32-bit, 2’s comp lemen t n umber spre ad a cross 4
registers. The LSBs are in the lower registers. The NCO frequency F is F/FCK=FREQ_A/
232.
PHASE_A 2B R/W 0 11-12 7:0 Phase word f or cha nnel A. F ormat is a 16-bit, un signed magn itude n umber spread acr oss 2
registers . Th e LS Bs ar e in the lo wer registers. The NCO phase PHI is PHI=2 *pi*P HASE_ A/
2^16.
FREQ_B 4B R/W 0 13-16 7:0 Frequ ency word for channe l B . Format is a 32-b it , 2’s complement num ber spre ad across 4
registers. The LSBs are in the lower registers. The NCO frequency F is F/FCK=FREQ_B/
232.
PHASE_B 2B R/W 0 17-18 7:0 Phase word f or chan nel B . F ormat is a 16-bit, unsigned mag nitude number spread acr oss 2
registers . Th e LS Bs ar e in the lo wer registers. The NCO phase PHI is PHI=2 *pi*P HASE_ B/
2^16.
A_SOURCE 2 R/W 0 19 1:0 0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel
input source.
B_SOURCE 2 R/W 1 19 3:2 0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel
input source.
EXP_INH 1b R/W 0 20 0 0=Allow exponent to pass into FLOAT TO FIXED converter. 1=Force exponent in DDC
channel to a 7 (maximum digital gain). This affects both channels.
Reserved 1b R/W 1 20 1 AGC_FORCE on the CLC5902. Do not use.
Reserved 1b R/W 0 20 2 AGC_RESET_EN on the CLC5902. Do not use.
AGC_HOLD_IC 1b R/W 0 20 3 0=Normal closed-loop operation. 1=Hold integrator at initial condition. This affects both
channels.
AGC_LOOP_GAIN 2b R/W 0 20 4:5: Bit shift value for AGC loop. Valid range is from 0 to 3. This affects both channels.
Reserved 2B R/W 0 21-22 7:0 AGC_COUNT on the CLC5902. Do not use.
AGC_IC _A 1B R/W 0 23 7:0 A GC fixed g ain f or channe l A. F ormat is an 8-bit , unsigned m agnitude n umber. The channel
A DVGA gain will be set to the inverted three MSBs.
www.national.com 22
CLC5903
AGC_IC _B 1B R/W 0 24 7:0 A GC fix ed ga in f or ch annel B . F ormat is an 8- bit, unsigned magnit ude num ber . The cha nnel
B DVGA gain will be set to the inverted three MSBs.
AGC_R B_A 1B R 0 25 7:0 AGC integr ator read back va lue for chann el A. Format is an 8-bit, un signed m agnitude num-
ber. The user can read the magnitude MSBs of the channel A integrator from this register.
AGC_R B_B 1B R 0 26 7:0 AGC integr ator read bac k value f or channel B . Format is an 8-bit, un signed m agnitu de nu m-
ber. The user can read the magnitude MSBs of the channel B integrator from this register.
TEST_REG 14b R/W 0 27(LSBs)
28(MSBs) 7:0
5:0 Test input source. Instead of processing values from the A|BIN pins, the value from this
location is used instead. Format is 14-bit 2s complement number spread across 2 regis-
ters.
Reserved 1B - - 29 7:0 For future use.
Reserved 1B - - 30 7:0 For future use.
DEBUG_EN 1b R/W 0 31 0 0=Normal. 1=Enables access to the internal probe points.
DEBUG_TAP 5b R/W 0 31 5:1 Selects internal node tap for debug.
0 selects F1 output for BI, 20 bits
1 selects F1 output for BQ, 20 bits
2 selects F1 output for AQ, 20 bits
3 selects F1 output for AI, 20 bits
4 selects F1 input for BI, 20 bits
5 selects F1 input for BQ, 20 bits
6 selects F1 input for AI, 20 bits
7 selects F1 input for AQ, 20 bits
8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0.
9 selects NCO A, sine output, 17 bits, 3 LSBs are 0.
10 selects NCO B, cosine output, 17 bits, 3 LSBs are 0.
11 selects NCO B, sine output, 17 bits, 3 LSBs are 0.
12 selects NCO AI, rounded output, 15 bits, 5 LSBs are 0.
13 selects NCO AQ, rounded output, 15 bits, 5 LSBs are 0.
14 selects NCO BI, rounded output, 15 bits, 5 LSBs are 0.
15 selects NCO BQ, rounded output, 15 bits, 5 LSBs are 0.
16-31 selects AGC CIC fil te r ou tput. 9 MSB s from ch A , n e xt 9 bits f rom ch B, 2 LSBs ar e 0.
DITH_A 1b R/W 1 31 6 0=Disable NCO dither source for channel A. 1=Enable.
DITH_B 1b R/W 1 31 7 0=Disable NCO dither source for channel B. 1=Enable.
AGC_TABLE 32B R/W 0 128-159 7:0 RAM space that defines key AGC loop parameters. Format is 32 separate 8-bit, 2’s com-
plement numbers. This is common to both channels.
F1_COEFF 22B R/W 0 160-181 7:0 Coefficients for F1. Format is 11 separate 16-bit, 2’s complement numbers, each one
spread across 2 registers. The LSBs are in the lower registers. For example, coefficient
h0[7:0] is in address 160, h0[15:8] is in address 161, h1[7:0] is in address 162, h1[15:8] is
in address 163. PAGE_SEL_F1=1 maps these addresses to coefficient memory B.
F2_COEFF 64B R/W 0 182-245 7:0 Coefficients for F2. Format is 32 separate 16-bit, 2’s complement numbers, each one
spread across 2 registers. The LSBs are in the lower registers. For example, coefficient
h0[7:0] is in address 182, h0[15:8] is in address 183, h1[7:0] is in address 184, h1[15:8] is
in address 185. PAGE_SEL_F2=1 maps these addresses to coefficient memory B.
COEF_SEL_F1A 1b R/W 0 246 0 Channel A F1 coefficient select register. 0=memory A, 1=memory B.
COEF_SEL_F1B 1b R/W 0 246 1 Channel B F1 coefficient select register. 0=memory A, 1=memory B.
PAGE_SEL_F1 1b R/W 0 246 2 F1 coefficient page select register. 0=memory A, 1=memory B.
COEF_SEL_F2A 1b R/W 0 247 0 Channel A F2 coefficient select register. 0=memory A, 1=memory B.
COEF_SEL_F2B 1b R/W 0 247 1 Channel B F2 coefficient select register. 0=memory A, 1=memory B.
PAGE_SEL_F2 1b R/W 0 247 2 F2 coefficient page select register. 0=memory A, 1=memory B.
SFS_MODE 1b R/W 0 248 0 0=SFS asserted at the start of each output word when PACKED=1 or each I/Q pair when
PACKED=0, 1=SFS asserted at the start of each output sample period.
SDC_EN 1b R/W 0 248 1 0=normal serial mode, 1=serial daisy-chain master mode.
AGC_COMB_ORD 2b R/W 0 249 1:0 Enable reduced bandwidth AGC power detector. 0=2nd-order decimate-by-eight CIC,
1=1-tap comb added to CIC, 2=4-tap comb added to CIC.
EXT_DELAY 5b R/W 0 249 6:2 Number of CK period delays in excess of 4 needed to align the DVGA gain step with the
digital gain compensation step. Use the default of zero for the CLC5957 ADC.
a. These are the default values set by a master reset (MR). Sync in (SI) will not affect any of these values.
Condensed CLC5903 Address Map
Register Name Addr Addr
Hex Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DEC 0 0x00 Dec7 Dec6 Dec5 Dec4 Dec3 Dec2 Dec1 Dec0
Control Register Addresses and Defaults (Continued )
Register Name Width T ype DefaultaAddr Bit Description
23 www.national.com
CLC5903
DEC_BY_4 1 0x01 DecBy4 Dec10 Dec9 Dec8
SCALE 2 0x02 Sc5 Sc4 Sc3 Sc2 Sc1 Sc0
GAIN_A 3 0x03 GA2 GA1 GA0
GAIN_B 4 0x04 GB2 GB1 GB0
RATE 5 0x05 Rate7 Rate6 Rate5 Rate4 Rate3 Rate2 Rate1 Rate0
SERIAL_CTRL 6 0x06 FMT1 FMT0 Packed MuxMode RDY_POL SFS_POL SCK_POL SOUT_EN
FREQ_A 7 0x07 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0
8 0x08 FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8
9 0x09 FA23 FA22 FA21 FA20 FA19 FA18 FA17 FA16
10 0x0A FA31 FA30 FA29 FA28 FA27 FA26 FA25 FA24
PHASE_A 11 0x0B PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
12 0x0C PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8
FREQ_B 13 0x0D FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0
14 0x0E FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8
15 0x0F FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16
16 0x10 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24
PHASE_B 17 0x11 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
18 0x12 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8
SOURCE 19 0x13 BS1 BS0 AS1 AS0
AGC_CTRL 20 0x14 AgcLG1 AgcLG0 AgcHldIC Reserved Reserved ExpInh
AGC_COUNT 21 0x15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
22 0x16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
AGC_IC_A 23 0x17 AgcIcA7 AgcIcA6 AgcIcA5 AgcIcA4 AgcIcA3 AgcIcA2 AgcIcA1 AgcIcA0
AGC_IC_B 24 0x18 AgcIcB7 AgcIcB6 AgcIcB5 AgcIcB4 AgcIcB3 AgcIcB2 AgcIcB1 AgcIcB0
AGC_RB_A 25 0x19 AgcRbA7 AgcRbA6 AgcRbA5 AgcRbA4 AgcRbA3 AgcRbA2 AgcRbA1 AgcRbA0
AGC_RB_A 26 0x1A AgcRbB7 AgcRbB6 AgcRbB5 AgcRbB4 AgcRbB3 AgcRbB2 AgcRbB1 AgcRbB0
TEST_REG 27 0x1B Test7 Test6 Test5 Test4 Test3 Test2 Test1 Test0
28 0x1C Test13 Test12 Test11 Test10 Test9 Test8
DEBUG 31 0x1F DITH_B DITH_A TapSel4 TapSel3 TapSel2 TapSel1 TapSel0 DebugEnable
AGC_TABLE 128 0x80 The AGC Table loads from the low address to the high address in this order:
159 0x9F “1st location, 2nd location…”
F1_COEFF 160 0xA0
181 0xB5 The FIR Coefficients load from the low address to the high address in this order:
F2_COEFF 182 0xB6 “1st location low byte, 1st location high byte, 2nd location…”
245 0xF5 The Page Select bits determine which set of coefficient memory is written.
F1_CTRL 246 0xF6 PgSelF1 CfSelF1B CfSelF1A
F2_CTRL 247 0xF7 PgSelF2 CfSelF2B CfSelF2A
SERIAL_CTRL2 248 0xF8 SdcEn SfsMode
AGC_CTRL2 249 0xF9 ExtDelay4 ExtDelay3 ExtDelay2 ExtDelay1 ExtDelay0 CombOrd1 CombOrd0
Condensed CLC5903 Address Map (Continued)
Register Name Addr Addr
Hex Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
www.national.com 24
CLC5903
AGC Theory of Operation
A block diagram of the AGC is shown in Figure 34. The
DVGA interface comprises four pins f or each of the channels.
The first three pins of this interface are a 3-bit binary word
that cont rols the DVGA gain in 6dB steps (AGAIN). Th e fin al
pin is ASTROBE which allows the AGAIN bits to be latched
into the DVGA’s register. A key feature of the ASTROBE,
illustrated Figure 35, is that it toggles only if the data on
AGAIN has changed from the previous cyc le. Not shown is
that ASTROBE and BSTROBE are independent. For exam-
ple, ASTROBE only toggles when AGAIN ha s changed.
BSTROBE will not toggle b ecause AGAIN has changed.
This is done to minimize unnecessary digital noise on the
sensitive analog path through the DVGA. ASTROBE and
BSTROBE are asserted du ri ng MR an d SI to properly initial-
ize the DVGAs.
The absolute value circuit and the 2-stage, decimate-by-8
CIC filter comprise the power detection part of the AGC. The
power detector bandwidth is set by the CIC filter to FCK/8.
The abso lute value circuit doubles the effective input fre-
quency. This has the effect of reducing the power detector
bandwidth from FCK/8 to FCK/16.
For a full-scale sinusoidal input, the absolute value circuit
output is a dc value of . Becau se the absolu te
value circuit also generates undesired even har monic ter m s,
the CIC filter (response shown in Figure 36), is required to,
remove thes e har monics. The firs t respons e null occ urs at
FCK/8, where FCK is the clock frequency, and the resp onse
magnitude is at least 25dB below the dc value from FCK/10 to
9FCK/10. Beca use the 2 nd harmonic from the absolute value
circuit is about 10dB below the dc this means that the ripple
in the de tect ed level is about 0.7 dB or less for input frequ en-
cies between FCK/20 to 19FCK/20. Setting the
AGC_COMB_ORD register to either 1 or 2 will narrow the
power detector ’s bandwidth as sh own in Fi gu re 36.
The “FIXED TO FLOAT CONVERTER” takes the fixed point
9-bit output from the CIC filter and conver ts it to a “floating
point” numb er. This conversion is done so that t he 32 values
in the RAM can be uni formly assig ned (dB scale) to detect ed
power levels (54 dB range ). This provides a resolution of
1.7dB b et ween detected power levels. The truth ta ble for this
converter is given in Table 3. The uppe r three bits of the out-
put rep resent t he exponent (e) and the lower 2 ar e the man-
tissa (m). The exponent is deter mined by the position of the
AGC_LOOP_GAIN
SHIFT DOWN
VALUE
ABSOLUTE
10
CONVERTER
TO FLOAT
FIXED
2 STAGE
32X8
SHIFT DOWN
16 5
MUX
812
12
AGC_HOLD_IC
-REF
LOG
FUNCTION PROGRAMMED
INTO RAM
AGC_IC_A
3
AIN[13:4]
9
DECIMATE BY 8
CIC FILTER
RAM
AGC_TABLE
AGAIN
Fig ure 34. CL C5903 AGC circuit, C hanne l A
EXP
(from MUXA) 9
POST CIC
COMB FILTER
POUT
Figure 35. Timing diagram for AGC/DVGA interface, Channel A. Refer to Figure 9 for detailed timing information.
ASTROBE
AGAIN[2:0]
CK
CK/8
ASTROBE does not pulse because AGAIN[2:0] does not change
511 2 π⁄()⋅
Figure 36. Power detector filter response, 52M H z
0 5 10 15 20 25 30 35 40 45 50
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
Frequency/MHz
Magnitude/dB
AGC Power Detection Filter: Amplitude Response
CIC
CIC + 1−tap Comb
CIC + 4−tap Comb
AGC_COMB_ORD=2
AGC_COMB_ORD=0
AGC_COMB_ORD=1
AGC Theory of Operation (Continued)
25 www.national.com
CLC5903
leading ‘1’ out of the CIC filter. An output of ‘001 XX’ corre-
sponds to a leading ‘1’ in bit 2 (LSB is bit 0). The exponent
increases by one each time the leading ‘1’ advances in bit
position. The mantissa bits are the two bits that follow the
leading ‘1’. If we define E as the decimal value of the expo-
nent bits and M as the decimal value of the mantissa bits, the
output of the CIC filter, POUT, corresponding to a given
“FIXED TO FLOAT CONVERTER” output is,
(5)
The max() and min() operators account for row 1 of Table 3
which is a special case because M=POUT. Equation 5 associ-
ates eac h address of the RAM with a CIC filte r ou tp ut .
As shown in Figure 34, the 32X8 RAM look-up table imple-
ments the funct ions of log conver ter, reference subtraction,
error amplifier, and deadband. The user must build each of
these functions by constructing a set of 8-bit, 2’s complement
numbers to be loaded into the RAM. Each of these functions
and how to construct them are discussed in the following
paragraphs.
A log conversion is done in order to keep the loop gain inde-
penden t of op erating point. To s ee why this is benef icial, the
control gain of the DVGA computed without log conv ersion is,
(6)
where G is t he decimal equivalent of GAIN and Go acc oun ts
for the DVGA gain in excess o f unit y. This equat ion ass umes
that the DVGA gain control polarity is positive as is the case
for the CLC5526. The gain around the entire loop must be
negative. Observe in Equation 6 that the control gain is
dependent on operating poin t G. If we instead compute the
contro l ga in w ith log conversion,
(7)
which is no longer operating-point dependent. The log func-
tion is constructed by computing the CIC filter output associ-
ated with e ach addre ss (Eq uation 5) and conver ting thes e to
dB. Full scale (dc sig na l) is .
The reference subtraction is construc ted by subtracting the
desired loo p ser vo point (in dB) from the t able values com-
puted in t he previous para graph. For exampl e, if it is desired
that the DVGA servo the ADC input level (sinusoidal signal)
to -6dBFS, the number to subtract from t he data is
. (8)
The table data will then cross through zero at the address
corresponding to this reference level. A deadband wider than
6dB shou ld then be constructed symmetrically about this
point. This prevents the loop from hunting due to the 6dB
gain steps of the DVGA. Any deadband in excess of 6dB
appears as hysteresis in the servo point of the loop as illus-
trated in Figure 33. The deadband is constructed by loading
zeros into those add resses on either side of the one which
corres ponds to the reference level.
The last function of the RAM table is that of error amplifica-
tion. All the operations preceding this one gave a table slope
. This must now be adjusted in order to control the
time con st ant of th e lo op given by,
(9)
The ter m GL i n th is equation is the loop gain,
(10)
The desig n equation s are obtain ed by solving Equa tion 9 for
GL and Equat ion 10 for . AGC_LOOP_G AIN is a con-
trol re gist er value t hat det er mine s the nu mber of bit s to s hift
the output of the RAM down by. This allows some of the loop
gain to be mov ed out of the RAM so that the full output range
of the table is utilized but not exceeded. The valid range for
AGC_LOOP_GAIN is from 0 to 3 which corresponds to a 1 to
4 bit shift left.
An example set of numbers to implement a loop having a ref-
erence of 6dB below full scale, a deadband of 8dB, and a
loop gain of 0. 10 8 is :
-102 -102 -88 -80 -75 -70 -66
-63 -61 -56 -53 -50
-47 -42 -39 -36 -33 -29 -25
-22 -19 -15 -11 0
0 0 0 0 0 13 17 20
These values are shown plotted in Figure 37 with respect to
the table addresses in (a), and the CIC filter output POUT in
(b). For a 52MHz clock rate and AGC_LOOP_GAIN=2, these
values result in a loop time constant of .
The err or sign al from t he loop g ain “S HIFT D OWN” circuit is
gated into the loop integrator . The gate is controlled by a tim-
ing and control circuit discussed in the next paragraph. A
MUX within the integrator feedback allows the integrator to
be initialized to the value loaded into AGC_IC_A (channel B
can be set independently). The co nditions under which it is
initialized are configured in the registers associated with the
timing and control circuit. The top eight bits of the integrator
output can also be read back over the microprocessor inter-
face from the AGC_RB_A (or AGC_RB_B) register. The top
3 bits below the sign beco me AGAIN and are o utput alon g
with ASTROBE signal on the DVGA interface pin s. The valid
range of AGAIN is from 0 t o 7 which corresponds to a valid
range of 0 to 210-1 for the 11-bit, 2’s complement integrator
output from which AGAIN is derived. This is illustrated in Fig-
INPUT OUTPUT
(eeemm)
0-3 000XX
4-7 001XX
8-15 010XX
16-31 011XX
32-63 100XX
64-127 101XX
128-255 110XX
256-511 111XX
Table 3. Fixed to Float Conv er ter Trut h Table
POUT 4min E 1,()⋅M+[]
2max E 1,()1–()
E1.≥,
⋅=
KDVGA
′G∂∂vi2GG
o
–()
⋅(),=
vi2()2GG
o
–()
,⋅ln⋅–=
KDVGA G∂∂20 vi2GG
o
–()
⋅()log⋅[],=
6.02,–=
20 511()54dB=log
20 511
2
----------2
π
---⋅
44dB=log
SRAM 1=
τ8
FCK
-----------1
GL
------- 1
2
---+
.=
GL6.02 SRAM 2AGC_LOOP_GAIN 8–()
.⋅⋅–=
SRAM
1.5µs
AGC Theory of Operation (Continued)
www.national.com 26
CLC5903
ure 38. T he integrator saturates at these l imits to prevent
overshoots as the integrator attempts to enter the valid
range. The AGAIN value is inver ted (EXP) and used to
adjust th e gain of the incom ing signa l to provide a lin ear ou t-
put dynamic range. The relationship between the DVGA ana-
log gain (AGAIN) a nd the “ FIXED TO FLOAT CONVE RTER”
digital gain (EXP) is sh own in Ta ble 4. T he DVGA’s compre s-
sion of th e i nc oming sign al in th e analog do m ai n v s. the sub-
sequent expansion in the di gital domai n is shown in Figure
32.
The AGC may be forced to free run by setting
AGC_HOLD_IC low. Writing an initial condition to
A GC_I C_A|B and then setting AGC_HOLD_IC high will force
the AGC to a f i xed gain. The three M SBs of the valu e w ritten
to AGC_IC_A|B ar e i nver ted and output t o drive the DVGA.
Allowing the AGC to free run should be appropriate for most
applications. If the INH_EXP bit is not set, the DVGA gain
word (EXP) is routed to the “FLOAT TO FIXED CON-
VERTER” in the DDCs prior to the programmable decimation
filter. The EXP signals are delayed to account for the propa-
gation del ay of the DVGA interface and the CLC5957 ADC.
010 20 30 40 50 60
-120
-100
-80
-60
-40
-20
0
20
0 5 10 15 20 25 30
-120
-100
-80
-60
-40
-20
0
20
ADDRESS
AGC RAM CONTENTS
POUT (dB )
AGC RAM CONTENTS
(a) (b)
Figure 37. Exam ple of programm ed RAM cont ents
AGAINa
a. AGAIN sets the DVGA or analog gain value.
EXPb
b. EXP sets the “FIXED TO FLOAT CONVERT ER” or digital gain value.
Inputc
c. 22-bit input to SHIFT-UP block in Figure 16 horizontally, linearized SHIFT-UP value vertically.
2120191817161514...876543210
000 = -12dB111 = +0dB-12dB 1413121110987...10LLLLLLL
001 = -6dB 110 = -6dB-12dB 14141312111098...210LLLLLL
010 = +0dB101 = -12dB-12dB 141414131211109...3210LLLLL
011 = +6dB100 = -18dB-12dB 1414141413121110...43210LLLL
100 = +12dB011 = -24dB-12dB 1414141414131211...543210LLL
101 = +18dB010 = -30dB-12dB 1414141414141312...6543210LL
110 = +24dB001 = -36dB-12dB 1414141414141413...76543210L
111 = +30dB000 = -42dB-12dB 1414141414141414...876543210
Table 4. 15- bi t Mixe r O ut put Alignment into the 22-bit SHIFT-U P B ased On EXP.d
d. The numbers in the center of the table represent the mixer output bits. ‘L’ represents a logic low.
01x272x273x274x275x276x277x278x27
Integrator Output
0
1
2
3
4
5
6
7
AGAIN
The min integrator
output must be
limited to 0 so that
the sign of AGAIN
is positive
For this range to be
the same size as all
others, the max
integrator output must
be limited to 8x27-1=210-1
Figure 38. AGC integrator output limits
27 www.national.com
CLC5903
Evaluation Hardware
Evalu ation boards are a v ailab l e to f acilit ate designs based on
the CLC 5903:
CLC-EDRCS-PCASM
The Enhanced Diversity Receiver Chipset evaluation board
providing a complete narrowband receiver from IF to digital
symbols.
CLC-CAPT-PCASM
A simple method for captur ing output data from CLC ADCs
and the CLC 5903.
SOFTWARE
Control panel software for the CLC 5903 suppor ts compl ete
device configuration on both evaluati on boards.
Capture software manages the capture of data and its stor-
age in a file on a PC.
Matlab script files support data analysis: FFT, DNL, and INL
plotting.
This software and additional application information is avail-
able on the CLC Evaluation Kit CD ROM.
www.national.com 28
CLC5903
Physical Dimensions inches (millimeters) unless otherwise noted.
Figur e 39. C LC5903SM FBG A Package Dimensions
CLC5903SM
National does not assume any responsibility for use of any circu itry described, no circuit pate nt licenses are imp lied and Nationa l reserves the right at any time w ithou t notice
to change said circuitry and specifications.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPO NENTS IN LIFE SUPPORT
DEVICES OR SYST EMS WITHOU T THE EXP RESS WRITT EN APPROVAL OF TH E PRESID ENT AND G EN-
ERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant
into the body, or (b) suppor t or sustain life, and
whose failure to perform when properly used in ac-
cordance with instructions for use provided in the
labeling, can be reasona bly expected to result in a
signific ant injury to the user.
2. A critical c om pon ent is any com po nent of a li fe su p-
por t device or system whose failure to perfor m can
be reasonably expected to caus e the failure of the
life suppor t device or system, or to affect its safety
or effectiveness.
N
National Semiconductor
Corporation National Semiconductor
Europe
Nat ional Semiconductor
Asia Pacif ic Cus tomer
Response Group
National Semiconductor
Japan Ltd.
Americas
Tel: 1-800-272-9959
F ax: 1-80 0-737-7018
Email: support@nsc.com
www.national.com
Fax: +49 (0) 180-530 85 86
E-mail: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Francais Tel: +33 (0) 1 41 91 8790
Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
CLC5903 Dual Digital Tuner / AGC
Physical Dimensions inches (millimeters) unless otherwise noted
DETAIL A
Dimension are in millimeters
CLC5903VLA
Figure 40. CLC5903VLA PQFP Package Dimensions
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Security www.ti.com/security
Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright ©2011, Texas Instruments Incorporated
