ICSVF2509YGLF-T - Integrated Device Technology

Integrated

Circuit

Systems, Inc.

General Description Features

ICSVF2509B

1036C— 07/13/05

Block Diagram

3.3V Phase-Lock Loop Clock Driver

Pin Configuration

The ICSVF2509B is a high performance, low skew, low

jitter clock driver. It uses a phase lock loop (PLL) technology

to align, in both phase and frequency, the CLKIN signal

with the CLKOUT signal. It is specifically designed for use

with synchronous SDRAMs. The ICSVF2509B operates

at 3.3V VCC and drives up to nine clock loads.

One bank of five outputs and one bank of four outputs

provide nine low-skew, low-jitter copies of CLKIN. Output

signal duty cycles are adjusted to 50 percent, independent

of the duty cycle at CLKIN. Each bank of outputs can be

enabled or disabled separately via control (OEA and OEB)

inputs. When the OE inputs are high, the outputs align in

phase and frequency with CLKIN; when the OE inputs are

low, the outputs are disabled to the logic low state.

The ICSVF2509B does not require external RC filter

components. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost. The

buffer mode shuts off the PLL and connects the input

directly to the output buffer. This buffer mode, the

ICSVF2509B can be use as low skew fanout clock buffer

device. The ICSVF2509B comes in 24 pin 173mil Thin

Shrink Small-Outline package (TSSOP) package.

•Meets or exceeds PC133 registered DIMM

specification1.1

•Spread Spectrum Clock Compatible

•Distributes one clock input to one bank of ten outputs

•Operating frequency 20MHz to 200MHz

•External feedback input (FBIN) terminal is used to

synchrionize the outputs to the clock input

•No external RC network required

•Operates at 3.3V Vcc

•Plastic 24-pin 173mil TSSOP package

24 Pin TSSOP

4.40 mm. Body, 0.65 mm. pitch

FBIN

CLKIN

AVCC

OEA

OEB

PLL

CLKA0

FBOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB0

CLKB1

CLKB2

CLKB3

AGND

VCC

CLKA0

CLKA1

CLKA2

GND

CLKA3

CLKA4

VCC

OEA

FBOUT

CLKIN

VCC

CLKB

CLKB1

GND

CLKB

VCC

OEB

FBIN

AVCC

ICSVF2509B

1036C—07/13/05

Pin Descriptions

Functionality

PIN NUMBER PIN NAME TYPE DESCRIPTION

1 AGND PWR Analog Ground

2, 10, 15 VCC PWR Power Supply (3.3V)

3 CLKA0 OUT Buffered clock output, Bank A

4 CLKA1 OUT Buffered clock output, Bank A

5 CLKA2 OUT Buffered clock output, Bank A

6, 7, 18, 19 GND PWR Ground

8 CLKA3 OUT Buffered clock output, Bank A

9 CLKA4 OUT Buffered clock output, Bank A

11 OEA1IN

Output enable (has internal pull_up). When high, normal

operation. When low bank A clock outputs are disabled to a

ic low state.

12 FBOUT OUT Feedback output

13 FBIN IN Feedback input

14 OEB1IN

Output enable (has internal pull_up). When high, normal

operation. When low bank B clock outputs are disabled to a

logic low state.

16 CLKB3 OUT Buffered clock output. Bank B

17 CLKB2 OUT Buffered clock output. Bank B

20 CLKB1 OUT Buffered clock output. Bank B

21 CLKB0 OUT Buffered clock output. Bank B

22 VCC PWR Power Supply (3.3V) digital supply.

23 AVCC IN Analog power supply (3.3V). When input is ground PLL is off

and b

passed.

24 CLKIN IN Clock input

OEA OEB AVCC CLKA

(

0:4

)

CLKB

(

0:3

)

FBOUT Source

003.3300DrivenPLLN

0 1 3.33 0 Driven Driven PLL N

1 0 3.33 Driven 0 Driven PLL N

1 1 3.33 Driven Driven Driven PLL N

00000DrivenCLKINY

0100DrivenDrivenCLKINY

100Driven0DrivenCLKINY

110

Driven Driven Driven CLKIN Y

Test mode:

When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers

Buffer Mode

INPUTS OUTPUTS PLL

Shutdown

Note:

1. Weak pull-ups on these inputs

ICSVF2509B

1036C—07/13/05

Absolute Maximum Ratings

Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . AVCC < (Vcc + 0.7 V)

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . 4.3 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to Vcc + 0.5 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics - OUTPUT

TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF; RL = 500 Ohms (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH IOH = -8 mA 2.4 2.9 V

Output Low Voltage VOL IOL = 8 mA 0.25 0.4 V

VOH = 2.4 V 27

VOH = 2.0 V 39

VOL = 0.8 V 26

VOL = 0.55 V 19

Rise Time1TrVOL = 0.8 V, VOH = 2.0 V 0.5 1.1 2.1 ns

Fall Time1TfVOH = 2.0 V, VOL = 0.8 V 0.5 1.1 2.7 ns

Duty Cycle1DtVT = 1.5 V;CL=30 pF 48 50 52 %

Cycle to Cycle jitter1TCY

- TCY

at 66-100 MHz ; loaded outputs 75 ps

Absolute Jitter1TJABS 10000 cycles; CL = 30 pF 100 ps

Skew1Tsk VT = 1.5 V (Window) Output to Output 100 ps

Phase error1T

eVT = Vdd/2; CLKIN-FBIN -75 75 ps

Delay Input-Output1DR1 VT = 1.5 V; PLL_EN = 0 3.3 3.7 ns

1 Guaranteed by design, not 100% tested in production.

Output High Current

Output Low Current

IOH

IOL

ICSVF2509B

1036C—07/13/05

Electrical Characteristics - Input & Supply

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage VIH 2V

DD + 0.3 V

Input Low Voltage VIL VSS - 0.3 0.8 V

Input High Current IIH VIN = VDD 0.1 100 uA

Input Low Current IIL VIN = 0 V; 19 50 uA

Operating current IDD1CL = 0 pF; FIN @ 66MHz 170 mA

Input Capacitance CIN1Logic Inputs 4 pF

1Guaranteed by design, not 100% tested in production.

Symbol Parameter Test Conditions Min. Max. Unit

FOP Operating frequency 20 200 MHz

FCLK

Input clock

frequency 25 200 MHz

Input clock

frequency duty

cycle

40 60 %

Stabilization time After power up 15 µs

Timing requirements over recommended ranges of supply

voltage and operating free-air temperature

Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal.

In order for

hase lock to be obtained

a fixed-fre

uenc

fixed-

hase reference si

nal must be

resent at CLK.

Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not applicable.

ICSVF2509B

1036C—07/13/05

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit for Outputs

Notes:

1. CL includes probe and jig capacitance.

2. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 133 MHz, ZO = 5 0 Ω, T

r ≤ 1. 2 n s, Tf≤ 1. 2 n s.

3. The outputs are measured one at a time with one transition per measurement.

30 pF 500 Ω

From Output

Under Test

Figure 2. Voltage Waveforms

Propagation Delay Times

Figure 3. Phase Error and Skew Calculations

ICSVF2509B

1036C—07/13/05

General Layout Precautions:

An ICS2509C is used as an example. It is similar to the

ICSVF2509. The same rules and methods apply.

1) Use copper flooded ground on the top signal layer

under the clock buffer The area under U1 in figure 1

on the right is an example. Every ground pin goes to a

ground via. The vias are not visible in figure 1.

2) Use power vias for power and ground. Vias 20 mil or

larger in diameter have lower high frequency

impedance. Vias for signals may be minimum drill

size.

3) Make all power and ground traces are as wide as the

via pad for lower inductance.

4) VAA for pin 23 has a low pass RC filter to decouple

the digital and analog supplies. C9-12 may be replaced

with a single low ESR (0.8 ohm or less) device with

the same total capacitance. R2 may be replaced with a

ferrite bead. The bead should have a DC resistance of

at least 0.5 ohms. 1 ohm is better. It should have an

impedance of at least 300 ohms at 100MHz. 600 ohms

at 100MHz is better.

5) Notice that ground vias are never shared.

6) All VCC pins have a decoupling capacitor. Power is

always routed from the plane connection via to the

capacitor pad to the VCC pin on the clock buffer.

7) Component R1 is located at the clock source.

8) Component C1, if used, has the effect of adding delay.

9) Component C7 , if used, has the effect of subtracting

delay. Delaying the FBIn clock will cause the output

clocks to be earlier. A more effective method is to use

the propagation time of a trace between FBOut and

FBIn.

Component Values:

C1,C7= As necessary for delay

adjust

C[6:2]=.01uF

C8,C13=0.1uF

C[12:9]=4.7Uf

R1=10 ohm. Locate at driver

R2=10 ohm.

Figure 1.

ICSVF2509B

1036C—07/13/05

Ordering Information

ICSVF2509yGLN-T

Designation for tape and reel packaging

RoHS Compliant (Optional)

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 to 7 digit numbers)

Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y G - PPP LN - T

4.40 mm. Body, 0.65 mm. pitch TSSOP

(173 mil) (0.0256 Inch)

INDEX

AREA

INDEX

AREA

1 2

E1 E

SEATING

PLANE

SEATING

PLANE

-C-

- C -

aaa

MIN MAX MIN MAX

A -- 1.20 -- .047

A1 0.05 0.15 .002 .006

A2 0.80 1.05 .032 .041

b 0.19 0.30 .007 .012

c 0.09 0.20 .0035 .008

E1 4.30 4.50 .169 .177

L 0.45 0.75 .018 .030

α0° 8° 0° 8°

aaa -- 0.10 -- .004

ARIATIONS

MIN MAX MIN MAX

24 7.70 7.90 .303 .311

10-0035

SYMBOL In Millimeter s In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

SEE VARIAT IO NS SEE VARIATIONS

6.40 BASIC 0.252 BASIC

0.65 BASIC 0.0256 BASIC

SEE VARIAT IO NS SEE VARIATIONS

ND mm. D (i nch)

Reference Doc.: JEDEC Publication 95, MO-153