K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
1
Document Title
512Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
0.1
0.11
1.0
Remark
Advance
Preliminary
Final
History
Initial Draft
Revisied
- Speed bin change
KM68U4000C : 85/100ns → 70/85/100ns
- DC Characteristics change
ICC : 5mA at read/write → 4mA at read
ICC1 : 3mA → 4mA
ICC2 : 35mA → 30mA
ISB : 0.5mA → 0.3mA
ISB1 : 10µA → 15µA for commercial parts
- Add 32-TSOP1-0820
Errata correct
- 32-TSOP1-0813 products: T → TG
Finalize
Draft Data
January 13, 1998
June 12, 1998
November 7, 1998
January 15, 1999
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
2
512K×8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The K6T4008V1C and K6T4008U1C families are fabricated by
SAMSUNG′s advanced CMOS process technology. The fami-
lies support various operating temperature range and have var-
ious package type for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
FEATURES
• Process Technology: TFT
• Organization: 512K×8
• Power Supply Voltage
K6T4008V1C Family: 3.0~3.6V
K6T4008U1C Family: 2.7~3.3V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 32-SOP-525, 32-TSOP2-400F/R
32-TSOP1-0820F, 32-TSOP1-0813.4F
PIN DESCRIPTION
Name Function Name Function
A0~A18 Address Inputs Vcc Power
WE Write Enable Input Vss Ground
CS Chip Select Input I/O1~I/O8Data Inputs/Outputs
OE Output Enable Input
PRODUCT FAMILY
1. The paramerter is measured with 30pF test load.
Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type
Standby
(ISB1, Max) Operating
(ICC2, Max)
K6T4008V1C-B Commercial(0~70°C) 3.0~3.6V 701)/85ns 15µA
30mA
32-SOP
32-TSOP2-F/R
32-TSOP1-F
32-sTSOP1-F
K6T4008U1C-B 2.7~3.3V 701)/85/100ns
K6T4008V1C-F Industrial(-40~85°C) 3.0~3.6V 701)/85ns 20µA
K6T4008U1C-F 2.7~3.3V 701)/85/100ns
FUNCTIONAL BLOCK DIAGRAM
32-SOP
(Forward)
32-TSOP2
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP2
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Reverse)
A18
A17 A17
A18
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
A15
Precharge circuit.
Memory array
1024 rows
512×8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A2 A3 A8 A9 A10 A13A11
A0
A1
A4
A5
A6
A7
A14
CS
WE
I/O1Data
cont
Data
cont
OE
I/O8
A12
A16
A18
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-TSOP1
(Forward)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A17
Control
logic
32-STSOP1
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
3
PRODUCT LIST
Commercial Temp Products(0~70°C) Industrial Temp Products(-40~85°C)
Part Name Function Part Name Function
K6T4008V1C-GB70
K6T4008V1C-GB85
K6T4008V1C-VB70
K6T4008V1C-VB85
K6T4008V1C-MB70
K6T4008V1C-MB85
K6T4008V1C-TB70
K6T4008V1C-TB85
K6T4008V1C-YB70
K6T4008V1C-YB85
K6T4008U1C-GB70
K6T4008U1C-GB85
K6T4008U1C-GB10
K6T4008U1C-VB70
K6T4008U1C-VB85
K6T4008U1C-VB10
K6T4008U1C-MB70
K6T4008U1C-MB85
K6T4008U1C-MB10
K6T4008U1C-TB70
K6T4008U1C-TB85
K6T4008U1C-TB10
K6T4008U1C-YB70
K6T4008U1C-YB85
K6T4008U1C-YB10
32-SOP, 70ns, 3.3V, LL
32-SOP, 85ns, 3.3V, LL
32-TSOP2-F, 70ns, 3.3V, LL
32-TSOP2-F, 85ns, 3.3V, LL
32-TSOP2-R, 70ns, 3.3V, LL
32-TSOP2-R, 85ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL
32-SOP, 70ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP2-F, 70ns, 3.0V, LL
32-TSOP2-F, 85ns, 3.0V, LL
32-TSOP2-F, 100ns, 3.0V, LL
32-TSOP2-R, 70ns, 3.0V, LL
32-TSOP2-R, 85ns, 3.0V, LL
32-TSOP2-R, 100ns, 3.0V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL
K6T4008V1C-GF70
K6T4008V1C-GF85
K6T4008V1C-VF70
K6T4008V1C-VF85
K6T4008V1C-MF70
K6T4008V1C-MF85
K6T4008V1C-TF70
K6T4008V1C-TF85
K6T4008V1C-YF70
K6T4008V1C-YF85
K6T4008U1C-GF70
K6T4008U1C-GF85
K6T4008U1C-GF10
K6T4008U1C-VF70
K6T4008U1C-VF85
K6T4008U1C-VF10
K6T4008U1C-MF70
K6T4008U1C-MF85
K6T4008U1C-MF10
K6T4008U1C-TF70
K6T4008U1C-TF85
K6T4008U1C-TF10
K6T4008U1C-YF70
K6T4008U1C-YF85
K6T4008U1C-YF10
32-SOP, 70ns, 3.3V, LL
32-SOP, 85ns, 3.3V, LL
32-TSOP2-F, 70ns, 3.3V, LL
32-TSOP2-F, 85ns, 3.3V, LL
32-TSOP2-R, 70ns, 3.3V, LL
32-TSOP2-R, 85ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL
32-SOP, 70ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP2-F, 70ns, 3.0V, LL
32-TSOP2-F, 85ns, 3.0V, LL
32-TSOP2-F, 100ns, 3.0V, LL
32-TSOP2-R, 70ns, 3.0V, LL
32-TSOP2-R, 85ns, 3.0V, LL
32-TSOP2-R, 100ns, 3.0V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL
FUNCTIONAL DESCRIPTION
1. X means don′t care (Must be in low or high state)
CS OE WE I/O Mode Power
HX1) X1) High-Z Deselected Standby
LH H High-Z Output Disabled Active
L L HDout Read Active
LX1) LDin Write Active
ABSOLUTE MAXIMUM RATINGS1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V-
Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V-
Power Dissipation PD1.0 W-
Storage temperature TSTG -65 to 150 °C-
Operating Temperature TA0 to 70 °CK6T4008V1C-L, K6T4008U1C-L
-40 to 85 °CK6T4008V1C-P, K6T4008U1C-P
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
4
RECOMMENDED DC OPERATING CONDITIONS1)
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+2.0V in case of pulse width ≤ 30ns
3. Undershoot : -2.0V in case of pulse width ≤ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item Symbol Product Min Typ Max Unit
Supply voltage Vcc K6T4008V1C Family
K6T4008U1C Family 3.0
2.7 3.3
3.0 3.6
3.3 V
Ground Vss All Family 0 0 0 V
Input high voltage VIH K6T4008V1C, K6T4008U1C Family 2.2 -Vcc+0.32) V
Input low voltage VIL K6T4008V1C, K6T4008U1C Family -0.33) -0.6 V
CAPACITANCE1) (f=1MHz, TA=25°C)
1. Capacitance is sampled, not 100% tested
Item Symbol Test Condition Min Max Unit
Input capacitance CIN VIN=0V -8pF
Input/Output capacitance CIO VIO=0V -10 pF
DC AND OPERATING CHARACTERISTICS
1. Industrial product = 20µA
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIN=Vss to Vcc -1 -1µA
Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 -1µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 4mA
Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V,VIN≤0.2V or VIN≥Vcc-0.2V - - 4mA
ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 30 mA
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.2 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs = VIL or VIH - - 0.3 mA
Standby Current (CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - - 151) µA
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
5
AC CHARACTERISTICS (K6T4008V1C Family: Vcc=3.0~3.6V, K6T4008U1C Family: Vcc=2.7~3.3V
Commercial product:: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Parameter List Symbol
Speed Bins
Units
70ns 85ns 100ns
Min Max Min Max Min Max
Read
Read cycle time tRC 70 -85 -100 -ns
Address access time tAA -70 -85 -100 ns
Chip select to output tCO -70 -85 -100 ns
Output enable to valid output tOE -35 -40 -50 ns
Chip select to low-Z output tLZ 10 -10 -10 -ns
Output enable to low-Z output tOLZ 5-5-5-ns
Chip disable to high-Z output tHZ 025 025 030 ns
Output disable to high-Z output tOHZ 025 025 030 ns
Output hold from address change tOH 10 -10 -15 -ns
Write
Write cycle time tWC 70 -85 -100 -ns
Chip select to end of write tCW 60 -70 -80 -ns
Address set-up time tAS 0-0-0-ns
Address valid to end of write tAW 60 -70 -80 -ns
Write pulse width tWP 55 -55 -70 -ns
Write recovery time tWR 0-0-0-ns
Write to output high-Z tWHZ 025 025 030 ns
Data to write time overlap tDW 30 -35 -40 -ns
Data hold from write time tDH 0-0-0-ns
End write to output low-Z tOW 5-5-5-ns
CL1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL1)=30pF+1TTL
1. 70ns product
DATA RETENTION CHARACTERISTICS
1. Industrial product = 20µA
Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CS≥Vcc-0.2V 2.0 -3.6 V
Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V -0.5 151) µA
Data retention set-up time tSDR See data retention waveform 0- - ms
Recovery time tRDR 5- -
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
6
Address
Data Out Previous Data Valid Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
CS
Address
OE
Data out
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
tOH
tAA
tOLZ
tLZ tOHZ
tHZ
tRC
tOE
tCO1
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
7
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS
tCW(2) tWR(4)
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
CS
tWC
tWR(4)
tAS(3)
tWP(1)
tDW tDH
tOW
tWHZ
Data Undefined
Data Valid
WE
Data in
Data out
tDW tDH
Data Valid
WE
Data in
Data out High-Z High-Z
tWC
tAW
tAS(3)
tCW(2)
tWP(1)
tAW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC
3.0/2.7V
2.2V
VDR
CS
GND
Data Retention Mode
CS≥VCC - 0.2V
tSDR tRDR
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
8
PACKAGE DIMENSIONS Units: millimeters(inches)
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
20.47±0.20
0.806±0.008
MAX
20.87
0.822 MAX
2.74±0.20
0.108±0.008
3.00
0.118
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#1
0.71
( )
0.028
13.34
0.525
11.43±0.20
0.450±0.008
0.80±0.20
0.031±0.008
+0.10
0.20 -0.05
+0.004
0.008
-0.002
14.12±0.30
0.556±0.012
#17
#16
1.27
0.050
+0.100
0.41 -0.050
+0.004
0.016 -0.002
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
9
PACKAGE DIMENSIONS
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
1.00±0.10
0.039±0.004
MAX
8.40
0.331
1.10 MAX
0.004 MAX
#1
0.50
( )
0.020
11.80±0.10
0.465±0.004
0.45 ~0.75
0.018 ~0.030
13.40±0.10
0.528±0.008
+0.10
0.15 -0.05
+0.004
0.006
-0.002
0~8°
+0.10
0.20 -0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8.00
0.315
TYP
0.25
0.010
#16
#32
#17
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
#32
1.00±0.10
0.039±0.004
MAX
8.40
0.331
0.10 MAX
0.004MAX
#1
0.50
( )
0.020
18.40±0.10
0.724±0.004
0.45 ~0.75
0.018 ~0.030
20.00±0.20
0.787±0.008
#17
+0.10
0.15 -0.05
+0.004
0.006
-0.002
0~8°
+0.10
0.20 -0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8.00
0.315
TYP
0.25
0.010
#16
Units: millimeters(inches)
K6T4008V1C, K6T4008U1C Family CMOS SRAM
Revision 1.0
January 1999
10
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8°
#32
20.95±0.10
0.825±0.004
MAX
21.35
0.841
MAX
1.00±0.10
0.039±0.004
1.20
0.047
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#1
0.95
( )
0.037
10.16
0.400
+0.10
0.15 -0.05
+0.004
0.006 -0.002
11.76±0.20
0.463±0.008
#17
#16 0.50
( )
0.020
0.45~0.75
0.018 ~ 0.030
0.25
( )
0.010
1.27
0.050
0.40±0.10
0.016±0.004
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) 0~8°
#32
#1
10.16
0.400
+0.10
0.15 -0.05
+0.004
0.006 -0.002
11.76±0.20
0.463±0.008
#17
#16
0.50
( )
0.020
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
20.95±0.10
0.825±0.004
MAX
21.35
0.841
MAX
1.00±0.10
0.039±0.004
1.20
0.047
MIN
0.002
0.05
0.004 MAX
0.10 MAX
0.95
( )
0.037 1.27
0.050
0.40±0.10
0.016±0.004
Units: millimeters(inches)
