ICS8752CYLFT - Integrated Device Technology

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

BLOCK DIAGRAM PIN ASSIGNMENT

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

GND

QB1

QB0

VDDO

QA3

QA2

GND

DIV_SELB0

DIV_SELB1

DIV_SELA0

DIV_SELA1

MR/nOE

CLK0

GND

FB_IN

VDDO

QA1

QA0

GND

CLK1

VDD

VDDA

CLK_SEL

VDDO

QB2

QB3

GND

PLL_SEL

VDD

ICS8752

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y package

Top View

÷2

÷4

÷6

÷8

÷12

PLL

PHASE

DETECTOR

PLL_SEL

FB_IN

CLK0

CLK1

CLK_SEL

DIV_SELA1

DIV_SELA0

DIV_SELB1

DIV_SELB0

MR/nOE

QA0

QA1

QA2

QA3

QB0

QB1

QB2

QB3

VCO

GENERAL DESCRIPTION

The ICS8752 is a low voltage, low skew LVCMOS clock

generator. With output frequencies up to 240MHz, the

ICS8752 is targeted for high performance clock applcations.

Along with a fully integrated PLL, the ICS8752 contains

frequency configurable outputs and an external feedback

input for regenerating clocks with “zero delay”.

Dual clock inputs, CLK0 and CLK1, support redundant clock

applications. The CLK_SEL input determines which refer-

ence clock is used. The output divider values of Bank A and

B are controlled by the DIV_SELA0:1, and DIV_SELB0:1,

respectively.

For test and system debug purposes, the PLL_SEL input

allows the PLL to be bypassed. When HIGH, the MR/nOE

input resets the internal dividers and forces the outputs to

the high impedance state.

The low impedance LVCMOS outputs of the ICS8752 are

designed to drive terminated transmission lines. The

effective fanout of each output can be doubled by

utilizing the ability of each output to drive two series

terminated transmission lines.

FEATURES

•Fully integrated PLL

•Eight LVCMOS outputs, 7Ω typical output impedance

•Selectable LVCMOS CLK0 or CLK1 inputs for

redundant clock applications

•Input/Output frequency range: 18.33MHz to 240MHz

at VCC = 3.3V ± 5%

•VCO range: 220MHz to 480MHz

•External feedback for “zero delay” clock regeneration

•Cycle-to-cycle jitter: 75ps (maximum),

(all outputs are the same frequency)

•Output skew: 100ps (maximum)

•Bank skew: 55ps (maximum)

•Full 3.3V or 2.5V supply voltage

•0°C to 70°C ambient operating temperature

•Available in both standard and lead-free RoHS-compliant

packages

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15kΩ

ecnaticapaCnoitapissiDrewoP

)tuptuorep( V

ADD

ODD

V564.3=32Fp

TUO

ecnadepmItuptuO 7 Ω

rebmuNemaNepyTnoitpircseD

2,1 ,0BLES_VID

1BLES_VID tupnInwodlluP .3elbaTnidebircsedsaBknaBrofseulavredividtuptuosenimreteD

.slevelecafretniLTTVL/SOMCVL

4,3 ,0ALES_VID

1ALES_VID tupnInwodlluP .3elbaTnidebircsedsaAknaBro

fseulavredividtuptuosenimreteD

.slevelecafretniLTTVL/SOMCVL

5EOn/RMtupnInwodlluP

erastuptuoehtdnatesererasr

edividlanretnieht,HGIHcigolnehW

stuptuoehtdnadelbasidsiteserretsameht,WOLcigolnehW.delbasid

.slevelecaf

retniLTTVL/SOMCVL.delbaneera

60KLCtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolC

,71,31,7

92,82,42 DNGre

woP.dnuorgylppusrewoP

8NI_BFtupnInwodlluP ."yaledorez"htiwskcolcgnitarenegrofrotcetedesahpottupnikcabdeeF

levelecafretniLTTVL/SOMCVL

9LES_KLCtupnInwodlluP

rotcetedesahpsa1KLCro0KLCneewtebstceleS.tupnitceleskcolC

1KLCstceles,HGIHnehW.0KLCstceles,WOLnehW.ecnerefer

.slevelecafretniLTTVL/SOMCVL

01V

ADD

rewoP.nipylppusgolanA

23,11V

rewoP.snipylppuseroC

211KLCtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolC

,51,41

91,81

,1AQ,0AQ

3AQ,2AQ tu

ptuO 7.stuptuokcolcAknaB Ω.ecnadepmituptuolacipyt

.slevelecafretniLTTVL/SOMCVL

,02,61

52,12 V

ODD

rewoP.snipylppustuptuO

,32,22

72,62

,1BQ,0BQ

3BQ,2BQ tuptuO 7.stuptuokcolcBknaB Ω.ecnadepmituptuolacipyt

.slev

elecafretniLTTVL/SOMCVL

03cndesunU.tcennocoN

13LES_LLPtupnIpulluP

.sredividehtottupniehtsa1KLCro0KLCdnaLLPehtn

eewtebstceleS

.1KLCro0KLCstcelesWOLnehW.LLPstcelesHGIHnehW

.slevelecafretniLTTVL/SOMCVL

:ETON

pulluP

dna

nwodlluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 3. CONTROL INPUT FUNCTION TABLE

TABLE 4A. QA OUTPUT FREQUENCY W/FB_IN = QB

stupnIstuptuO

NI_BF _VID

1BLES

_VID

0BLES

tuptuOBQ

edoMrediviD

)2ETON(

)zHM(1KLC,0KLC

)1ETON( _VID

1ALES

_VID

0ALES

uptuOAQ

edoMrediviD

reilpitluMAQ

)2ETON(

muminiMmumixaM

BQ00 ÷455021

00 ÷22

01 ÷41

10 ÷6766.0

11 ÷85.0

BQ01 ÷666.6308

00 ÷23

01 ÷45.1

10 ÷61

11 ÷857.0

BQ10 ÷85.7206

00 ÷24

01 ÷42

10 ÷633.1

11 ÷81

BQ11 ÷21 33.8104

01 ÷26

01 ÷43

10 ÷62

11 ÷85.1

.zHM084otzHM022siegnarycneuqerfOCV

:1ETON

;reilpitlumehtsemitycneuqerfxKLCotlauqeycneuqerftuptuoAQ:2ETON

.xKLCotlauqeycneuqerftuptuoBQ

stupnIstuptuO

EOn/RMLES_LLPLES_KLC _VID

1ALES

_VID

0ALES

_VID

1BLES

_VID

0BLES xAQxBQ

1X X X X X X Z-iHZ-iH

01X 0 0 0 0 2/OCVf4/OCVf

01X 0 1 0 1 4/OCVf6/OCVf

01X 1 0 1 0 6

/OCVf8/OCVf

01X 1 1 1 1 8/OCVf21/OCVf

00 0 0 0 0 0 2/0KLCf4/0KLCf

00 0 0 1 0 1 4/0KLCf6/0KLCf

00 0 1 0 1 0 6/0KLCf8/0KLCf

00 0 1 1 1 1 8/0KLCf21/0KLCf

00 1 0 0 0 0 2/1KLCf4/1KLCf

00 1 0 1 0 1 4/1KLCf6/1KLCf

00 1 1 0 1 0 6/1KLCf8/1KLCf

00 1 1 1 1 1 8/1KLCf21/1KLCf

.delbasiderastupuolla,HGIHsiEOn/RMnehW.WOLsiEOn/RM,noitarepolamronroF:ETON

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 4B. QB OUTPUT FREQUENCY W/FB_IN = QA

stupnIstuptuO

NI_BF _VID

1ALES

_VID

0ALES

AQtuptuO

edoMrediviD

)2ETON(

)zHM(1KLC,0KLC

)1ETON( _VID

1BLES

_VID

0BLES

ptuOBQ

edoMrediviD

reilpitluMBQ

)2ETON(

muminiMmumixaM

AQ00 ÷2011042

)3ETON(

00 ÷45.0

01 ÷6333.0

10 ÷852.0

11 ÷21 761.0

AQ01 ÷4550

00 ÷41

01 ÷6766.0

10 ÷85.0

11 ÷21 333.0

AQ10 ÷666.6308

00 ÷45.1

01 ÷61

10 ÷857.0

11 ÷21 5.0

AQ11 ÷85.7206

01 ÷42

01 ÷6333.1

10 ÷81

11 ÷21 766.0

.zHM

084otzHM022siegnarycneuqerfOCV:1ETON

;reilpitlumehtsemitycneuqerfxKLCotlauqeycneuqerftuptuoBQ:2ETON

.xK

LCotlauqeycneuqerftuptuoAQ

VrofdilavzHM042foycneuqerfmumixaM:3ETON

.ylno%5±V3.3=

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5V

Outputs, VO

-0.5V to VDDO + 0.5V

Package Thermal Impedance, θ

JA 47.9°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ADD

egatloVylppuSgolanA 531.33.3564.3V

ODD

egatloVylppuStuptuO 531.33.3564.3V

tnerruCylppuSrewoP 501Am

ADD

tnerruCylppuSgolanA 51Am

ODD

tnerruCylppuStuptuO 02Am

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 573.25.2526.2V

ADD

egatloVylppuSgolanA 573.25.2526.2V

ODD

egatloVylppuStuptuO 573.25.2526.2V

tnerruCylppuSrewoP 001Am

ADD

tnerruCylppuSgolanA 51Am

ODD

tnerruCylppuStuptuO 02Am

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 6A. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

FER

ycneuqerFecnerefeRtupnI

ybdetimilsiycneuqerfecnerefertupnI:ETON

.egnarkcolOCVehtdnanoitcelesredivideht

2042zHM

TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C

TABLE 6B. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

FER

ycneuqerFecnerefeRtupnI

ybdetimilsiycneuqerfecnerefertupnI:ETON

.egnarkcolOCVehtdnanoitcelesredivideht

2021zHM

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI V

V3.3=2V

3.0+V

V5.2=7.1V

3.0+V

egatloVwoLtupnI V

V3.3=3.0-8.0V

V5.2=3.0-7.0V

tupnI

tnerruChgiH

,0xLES_VID

,0KLC,1xLES_VID

,LES_KLC,NI_BF,1KLC

EOn/RM

V564.3=

V526.2ro 051Aµ

LES_LLP V

V564.3=

V526.2ro 5Aµ

tupnI

tnerruCwoL

,0xLES_VID

,0KLC,1xLES_VID

,LES_KLC,NI_BF,1KLC

EOn/RM

=,V526.2roV564.3

V0= 5-Aµ

LES_LLP V

=,V526.2roV564.3

V0= 051-Aµ

1ETON;egatloVhgiHtuptuO V

ODD

V564.3=6.2V

ODD

V526.2=8.1V

1ETON;egatloVwoLtuptuO 5.0V

05htiwdetanimretstuptuO:1ETON ΩVot

ODD

,noitcesnoitamrofnItnemerusaeMretemaraPeeS.2/

.smargaid"tiucriCtseTdaoLtuptuO"

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

)edoMLLP(ycneuqerFtuptuO

÷2011042zHM

÷455021zHM

÷676.6308zHM

÷85.7206zHM

1÷ 233.8104zHM

OCV

egnaRkcoLOCVLLP 022084zHM

)Ø(t1ETON;tesffOesahPcitatS ,zHM004=OCVf

8÷kcabdeeF 03-07071sp

)b(ks4,2ETON;wekSknaB egdegnisirnoderusaeM

Vta

ODD

2/ 55sp

)o(ks4,3ETON;wekStuptuO egdegnisirnoderusaeM

Vta

ODD

2/ 001sp

)cc(tij elcyC-ot-elcyC

4ETON;rettiJ

seicneuqerFtnereffiD

sknaBtnereffiDno 004sp

tastuptuOllA

ycneuqerFemaS 57sp

emiTkcoLLLP 1Sm

emiTllaF/esiRtuptuO%08ot%02004059sp

cdoelcyCytuDtuptuO 740535%

ftaderusaemsretemarapllA

XAM

.esiwrehtodetonsselnu

,langistupnikcabdeefegarevaehtdnakcolctupniehtneewtebecnereffidemitehtsadenifeD:

1ETON

.elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLPehtnehw

.snoitidnocdaollauqehtiwdnasegatlovylppu

semasehttastuptuofoknabanihtiwwekssadenifeD:2ETON

.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastu

ptuoneewtebwekssadenifeD:3ETON

VtaderusaeM

ODD

.2/

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

)edoMLLP(ycneuqerFtuptuO

÷2011042zHM

÷455021zHM

÷676.6308zHM

÷85.7206zHM

1÷ 233.8104zHM

OCV

egnaRkcoLOCVLLP 022084zHM

)Ø(t1ETON;tesffOesahPcitatS zHM004=OCVf

8÷kcabdeeF 09-05091sp

)b(ks4,2ETON;wekSknaB egdegnisirnoderusaeM

Vta

ODD

2/ 55sp

)o(ks4,3ETON;wekStuptuO egdegnisirnoderusaeM

Vta

ODD

2/ 09sp

)cc(tij elcyC-ot-elcyC

4ETON;rettiJ

seicneuqerFtnereffiD

sknaBtnereffiDno 004sp

tastuptuOllA

ycneuqerFemaS 57sp

emiTkcoLLLP 1Sm

emiTllaF/esiRtuptuO%08ot%02004059sp

cdoelcyCytuDtuptuO 540555%

ftaderusaemsretemarapllA

XAM

.esiwrehtodetonsselnu

,langistupnikcabdeefegarevaehtdnakcolctupniehtneewtebecnereffidemitehtsadenifeD:1ETON

.elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLPehtnehw

.snoitidnocdaollauqehtiwdnasegatlovylppu

semasehttastuptuofoknabanihtiwwekssadenifeD:2ETON

.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON

VtaderusaeM

ODD

.2/

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

3.3V OUTPUT LOAD AC TEST CIRCUIT

(Where X denotes outputs in the same Bank) 2.5V OUTPUT LOAD AC TEST CIRCUIT

BANK SKEW

OUTPUT SKEW

OUTPUT DUTY CYLCLE/PULSE WIDTH/PERIOD

CYCLE-TO-CYCLE JITTER

jit(cc) =

cycle n –

cycle n+1

1000 Cycles

STATIC PHASE OFFSET

OUTPUT RISE/FALL TIME

PARAMETER MEASUREMENT INFORMATION

SCOPE

LVCMOS

1.65V±5%

-1.65V±5%

tsk(o)

DDO

QA0:QA3,

QB0:QB3

➤

DDO

cycle n

cycle n+1

tsk(b)

DDO

➤

t(Ø)

CLK0,

CLK1

FB_IN

QX0:QX3

tPERIOD

tPW

tPERIOD

odc =

DDO

x 100%

tPW

Clock

Outputs

20%

80% 80%

20%

tRtF

QA0:QA3,

QB0:QB3

VDD,

VDDA,VDDO

GND

SCOPE

LVCMOS

1.25V±5%

-1.25V±5%

VDD,

VDDA,VDDO

GND

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS8752 is: 1546

TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

INPUTS:

CLK INPUT:

For applications not requiring the use of a clock input, it can

be left floating. Though not required, but for additional

protection, a 1kΩ resistor can be tied from the CLK input to

ground.

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVCMOS OUTPUT:

All unused LVCMOS output can be left floating. We

recommend that there is no trace attached.

APPLICATION INFORMATION

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 8. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-026

NOITAIRAVCEDEJ

SRETEMILLIMNISNOISNEMIDLLA

LOBMYS

ABB

MUMINIMLANIMONMUMIXAM

N23

A----06.1

1A 50.0--51.0

2A 53.104.154.1

b03.073.054.0

c90.0--02.0

DCISAB00.9

1D CISAB00.7

2D .feR06.5

ECISAB00.9

1E CISAB00.7

2E .feR06.5

eCISAB08.0

L54.006.057.

θθ

θθ 0

-- 7

ccc ----01.0

PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TABLE 9. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of

any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial

applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves

the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

YC2578YC2578SCIPFQLdaeL23yartC°07otC°0

TYC2578YC2578S

CIPFQLdaeL23leer&epat0001C°07otC°0

FLYC2578FLYC2578SCIPFQL"eerF-daeL"daeL23yartC°07otC°0

TFLYC2578FLYC2578SCIPFQ

L"eerF-daeL"daeL23leer&epat0001C°07otC°0

.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntrapehtotxi

ffus"FL"nahtiwderedroeratahtstraP:ETON

8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

TEEHSYROTSIHNOISIVER

veRelbaTegaPegnahCfonoitpircseDetaD

A1T2 .noitpircsedEOn/RMdesiveR.elbaTsnoitpircseDniP 20/

91/8

B2T

nopuelbaliavaerutarepmetlairtsudnI",tellubeteled-noitceSserutaeF

.tellubeerF-daeLdeddA".ts

euqer

Cdegnahc-elbatscitsiretcarahCniP

.lacipytFp4ot.xamFp4

.etondnarebmuntrapeerF-daeLdedda-elbaTnoitamrofnIgniredrO

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8752CY www.idt.com REV. C JULY 2, 2010

ICS8752

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