High Voltage, Low Noise, Low Distortion, Unity-Gain Stable, High Speed Op Amp ADA4898-1 FEATURES CONNECTION DIAGRAM NC 1 8 PD -IN 2 7 +VS +IN 3 6 OUT -VS 4 5 NC NC = NO CONNECT 07037-001 ADA4898-1 Ultralow noise 0.9 nV/Hz 2.4 pA/Hz 1.2 nV/Hz @ 10 Hz Ultralow distortion: -93 dBc at 500 kHz Wide supply voltage range: 5 V to 16 V High speed -3 dB bandwidth: 65 MHz (G = +1) Slew rate: 55 V/s Unity gain stable Low input offset voltage: 150 V maximum Low input offset voltage drift: 1 V/C Low input bias current: -0.1 A Low input bias current drift: 2 nA/C Supply current: 8 mA Power-down feature Figure 1. Single 8-Lead ADA4898-1 SOIC_N_EP (RD-8-1) APPLICATIONS Instrumentation Active filters DAC buffers SAR ADC drivers Optoelectronics GENERAL DESCRIPTION VOLTAGE 1 0.1 1 10 100 1 1k 10k 0.1 100k FREQUENCY (Hz) CURRENT NOISE (pA/Hz) The ADA4898-1 is available in an 8-lead SOIC package that features an exposed metal paddle to improve power dissipation and heat transfer to the negative supply plane. This EPAD offers a significant thermal relief over traditional plastic packages. The ADA4898-1 is rated to work over the extended industrial temperature range of -40C to +105C. CURRENT 07037-002 With the wide supply voltage range, low offset voltage, and wide bandwidth, the ADA4898-1 is extremely versatile, and it features a cancellation circuit that reduces input bias current. 10 10 VOLTAGE NOISE (nV/Hz) The ADA4898-1 is an ultralow noise and distortion, unity gain stable, voltage feedback op amp that is ideal for use in 16-bit and 18-bit systems with power supplies from 5 V to 16 V. The ADA4898-1 features a linear, low noise input stage and internal compensation that achieves high slew rates and low noise. Figure 2. Input Voltage Noise and Current Noise vs. Frequency Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008-2009 Analog Devices, Inc. All rights reserved. ADA4898-1 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 PD (Power-Down) Pin .............................................................. 14 Connection Diagram ....................................................................... 1 Current Noise Measurement .................................................... 14 General Description ......................................................................... 1 0.1 Hz to 10 Hz Noise ................................................................ 15 Revision History ............................................................................... 2 Applications Information .............................................................. 16 Specifications..................................................................................... 3 Higher Feedback Resistor Gain Operation ............................. 16 15 V Supply ................................................................................. 3 Recommended Values for Various Gains................................ 16 5 V Supply ................................................................................... 4 Noise ............................................................................................ 17 Absolute Maximum Ratings............................................................ 5 Circuit Considerations .............................................................. 17 Thermal Resistance ...................................................................... 5 PCB Layout ................................................................................. 17 Maximum Power Dissipation ..................................................... 5 Power Supply Bypassing ............................................................ 17 ESD Caution .................................................................................. 5 Grounding ................................................................................... 17 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 18 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 18 Test Circuits ..................................................................................... 13 REVISION HISTORY 6/09--Rev. A to Rev. B Changes to General Description Section ...................................... 1 Changes to Specifications Section .................................................. 3 Changes to Figure 29 and Figure 31 ............................................. 11 Added Figure 32.............................................................................. 12 Added Figure 41.............................................................................. 13 Changes to PD (Power-Down) Pin Section ................................ 14 Added Table 6.................................................................................. 14 Changes to Figure 45 ...................................................................... 15 8/08--Rev. 0 to Rev. A Changes to General Description Section ...................................... 1 Changes to Table 5 ............................................................................ 6 Changes to Figure 17 ........................................................................ 9 Changes to Figure 28 ...................................................................... 10 Changes to Figure 29 and Figure 32 ............................................. 11 Added 0.1 Hz to 10 Hz Noise Section .......................................... 14 Added Figure 42 and Figure 43; Renumbered Sequentially ..... 14 Changes to Grounding Section ..................................................... 16 Updated Outline Dimensions ....................................................... 17 5/08--Revision 0: Initial Release Rev. B | Page 2 of 20 ADA4898-1 SPECIFICATIONS 15 V SUPPLY TA = 25C, G = +1, RF = 0 , RG open, RL = 1 k to GND (for G > 1, RF = 100 ), unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion SFDR Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Offset Current Input Bias Current Drift Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio PD (POWER-DOWN) PIN PD Input Voltages Input Leakage Current OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current (RMS) Short-Circuit Current Off Isolation POWER SUPPLY Operating Range Quiescent Current Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Conditions Min Typ Max Unit VOUT = 100 mV p-p VOUT = 2 V p-p G = +2, VOUT = 2 V p-p VOUT = 5 V step VOUT = 5 V step 65 14 3.3 55 85 MHz MHz MHz V/s ns f = 100 kHz, VOUT = 2 V p-p f = 500 kHz, VOUT = 2 V p-p f = 1 MHz, VOUT = 2 V p-p f = 100 kHz f = 100 kHz RF = 1 k -116 -93 -79 0.9 2.4 dBc dBc dBc nV/Hz pA/Hz VOUT = 5 V Differential mode Common mode Differential mode Common mode See Figure 41 VCM = 2 V p-p 99 20 1 -0.1 0.03 2 103 -103 5 30 3.2 2.5 11 -126 k M pF pF V dB -14 -13 -0.1 -0.2 V V A A -11.7 to +12.1 -12.8 to +12.7 40 150 80 V V mA mA dB Chip powered down Chip enabled PD = +VS PD = -VS RL // (RF + RG) = 500 , see Figure 41 RL // (RF + RG) = 1 k, see Figure 41 f = 100 kHz, SFDR = -70 dBc, RL = 150 Sinking/sourcing f = 1 MHz, PD = -VS -11.4 to +11.8 -12.7 to +12.5 4.5 PD = +VS PD = -VS +VS = 15 V to 17 V, -VS = -15 V +VS = 15 V, -VS = -15 V to -17 V Rev. B | Page 3 of 20 -98 -100 8.1 0.1 -107 -114 120 -0.4 0.3 16.5 8.7 0.3 V V/C A A nA/C dB V mA mA dB dB ADA4898-1 5 V SUPPLY TA = 25C, G = +1, RF = 0 , RG open, RL = 1 k to GND (for G > 1, RF = 100 ), unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion SFDR Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Offset Current Input Bias Current Drift Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio PD (POWER-DOWN) PIN PD Input Voltages Input Leakage Current OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current (RMS) Short-Circuit Current Off Isolation POWER SUPPLY Operating Range Quiescent Current Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Conditions Min Typ Max Unit VOUT = 100 mV p-p VOUT = 2 V p-p G = +2, VOUT = 2 V p-p VOUT = 2 V step VOUT = 2 V step 57 12 3 50 90 MHz MHz MHz V/s ns f = 500 kHz, VOUT = 2 V p-p f = 1 MHz, VOUT = 2 V p-p f = 100 kHz f = 100 kHz -95 -78 0.9 2.4 dBc dBc nV/Hz pA/Hz VOUT = 1 V 90 30 1 -0.1 0.01 2 94 -102 5 30 3.2 2.5 -3 to +2.5 -120 k M pF pF V dB -4 -3 0.1 -2 V V A A 3.2 3.4 8 150 80 V V mA mA dB Differential mode Common mode Differential mode Common mode See Figure 41 VCM = 1 V p-p Chip powered down Chip enabled PD = +VS PD = -VS RL // (RF + RG) = 500 , see Figure 41 RL // (RF + RG) = 1 k, see Figure 41 f = 100 kHz, SFDR = -70 dBc, RL = 150 Sinking/sourcing f = 1 MHz, PD = -VS 3.1 3.3 4.5 PD = +VS PD = -VS +VS = 5 V to 7 V, -VS = -5 V +VS = 5 V, -VS = -5 V to -7 V Rev. B | Page 4 of 20 -95 -97 7.7 0.1 -100 -104 150 -0.5 0.3 16.5 8.4 0.2 V V/C A A nA/C dB V mA mA dB dB ADA4898-1 ABSOLUTE MAXIMUM RATINGS Table 3. Rating 36 V See Figure 3 1.5 V 11.4 V -65C to +150C -40C to +105C 300C 150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, JA is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad on the PCB surface that is thermally connected to a copper plane, with zero airflow. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane to achieve the specified JA. Figure 3 shows the maximum power dissipation in the package for the ADA4898-1 vs. the ambient temperature for the 8-lead SOIC_N_EP on a JEDEC standard 4-layer board, with its underside paddle soldered to a pad that is thermally connected to a PCB plane. JA values are approximations. 4.5 4.0 Table 4. Package Type 8-Lead SOIC_N_EP on 4-Layer Board (Single) JA 47 JC 29 Unit C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the ADA4898-1 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4898-1. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices, potentially causing failure. 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 AMBIENT TEMPERATURE (C) Figure 3. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. B | Page 5 of 20 07037-003 MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage Power Dissipation Differential Mode Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the output load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. For each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. ADA4898-1 8 PD -IN 2 NC 1 ADA4898-1 7 TOP VIEW (Not to Scale) +VS +IN 3 6 OUT 5 NC -VS 4 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD (EP) CAN BE CONNECTED TO -VS OR LEFT FLOATING. 07037-046 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Single 8-Lead SOIC_N_EP Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic NC -IN +IN -VS NC OUT +VS Description No Connect. Inverting Input. Noninverting Input. Negative Supply. No Connect. Output. Positive Supply. 8 EP PD -VS Power Down. Exposed Pad. Can be connected to negative supply (-VS) or can be left floating. Rev. B | Page 6 of 20 ADA4898-1 TYPICAL PERFORMANCE CHARACTERISTICS 1 2 0 -1 -2 G = +2 RF = 100 -3 -4 -5 G = +5 RF = 100 -6 -7 -8 -9 -10 RL = 1k VOUT = 100mV p-p VS = 15V -11 1 10 100 FREQUENCY (MHz) -5 -6 -7 G = +5 RF = 100 -8 -9 -10 RL = 1k VOUT = 2V p-p VS = 15V 1 10 100 1 0 RL = 1k 0 CLOSED-LOOP GAIN (dB) -1 -2 RL = 100 -3 -4 RL = 200 -5 -6 -7 -8 -9 -10 10 100 FREQUENCY (MHz) TA = +105C 1 -5 -6 -7 -8 -9 CLOSED-LOOP GAIN (dB) TA = +25C TA = 0C -5 TA = -40C -6 -7 -8 G = +1 RL = 1k VOUT = 100mV p-p VS = 15V -11 1 TA = +85C -2 TA = +25C -3 -4 -5 TA = 0C -6 -7 TA = -40C -8 -9 G = +1 RL = 1k VOUT = 2V p-p VS = 15V -10 -11 10 FREQUENCY (MHz) 100 -12 07037-006 -10 100 TA = +105C 1 0 -4 10 2 TA = +85C -1 -3 1 Figure 9. Large Signal Frequency Response for Various Loads 0 -9 G = +1 VOUT = 2V p-p VS = 15V FREQUENCY (MHz) -1 -2 RL = 200 RL = 100 -4 -12 Figure 6. Small Signal Frequency Response for Various Loads 2 -3 -11 07037-005 1 -2 -10 G = +1 VOUT = 100mV p-p VS = 15V -11 RL = 1k -1 07037-008 1 CLOSED-LOOP GAIN (dB) -4 Figure 8. Large Signal Frequency Response for Various Gains 2 -12 G = +2 RF = 100 -3 FREQUENCY (MHz) 3 CLOSED-LOOP GAIN (dB) -2 -12 Figure 5. Small Signal Frequency Response for Various Gains -12 G = +1 RF = 100 0 -1 Figure 7. Small Signal Frequency Response for Various Temperatures 1 10 FREQUENCY (MHz) 100 07037-009 -12 G = +1 RF = 0 1 -11 07037-004 NORMALIZED CLOSED-LOOP GAIN (dB) 3 G = +1 RF = 0 07037-007 G = +1 RF = 100 2 NORMALIZED CLOSED-LOOP GAIN (dB) 3 Figure 10. Large Signal Frequency Response for Various Temperatures Rev. B | Page 7 of 20 ADA4898-1 2 2 1 1 0 0 VS = 15V -2 -3 -4 VS = 5V -5 -6 -7 -8 -9 -10 1 10 100 -7 -8 -9 1 10 100 Figure 14. Large Signal Frequency Response for Various Supply Voltages 1.0 CL = 5pF 2 0.9 1 0.8 0 0.7 -2 NORMALIZED GAIN (dB) CL = 0pF -3 -4 CL = 33pF -5 -6 -7 -8 CL = 15pF G = +1 RL = 1k VOUT = 100mV p-p VS = 15V -11 0.5 0.4 0.3 0.2 VOUT = 0.1V p-p 0.1 0 -0.1 VOUT = 2V p-p -0.2 -0.3 G = +2 RL = 1k VS = 15V -0.4 1 10 100 FREQUENCY (MHz) -0.5 100k 07037-011 -10 0.6 1M 10M FREQUENCY (Hz) Figure 12. Small Signal Frequency Response for Various Capacitive Loads 07037-014 -1 -9 Figure 15. 0.1 dB Flatness for Various Output Voltages 10 INPUT CURRENT NOISE (pA/ Hz) 100 1 1 10 100 1k 10k FREQUENCY (Hz) 100k 07037-012 VOLTAGE NOISE (nV/Hz) G = +1 RL = 1k VOUT = 2V p-p FREQUENCY (MHz) 3 CLOSED-LOOP GAIN (dB) -6 -12 Figure 11. Small Signal Frequency Response for Various Supply Voltages 0.1 VS = 5V -5 -11 FREQUENCY (MHz) -12 -4 Figure 13. Voltage Noise vs. Frequency 10 1 1 10 100 1k 10k FREQUENCY (Hz) Figure 16. Input Current Noise vs. Frequency Rev. B | Page 8 of 20 100k 07037-035 -12 VS = 15V -3 -10 G = +1 RL = 1k VOUT = 100mV p-p -11 -2 07037-013 CLOSED-LOOP GAIN (dB) -1 07037-010 CLOSED-LOOP GAIN (dB) -1 ADA4898-1 -70 VOUT = 5V VS = 15V -110 60 -120 50 -130 40 -140 GAIN 30 -150 20 -160 10 -170 0 -180 -10 -190 -20 100k 1M 10M 100M -105 -200 1G DISTORTION (dBc) -100 70 FREQUENCY (Hz) -110 HD2 -115 -120 -125 HD3 -130 -135 0 G = +2, HD3, RF = 250 -20 3 4 5 6 G = +1 VS = 5V VOUT = 2V p-p RL = 100, HD3 -40 DISTORTION (dBc) G = +2, HD2, RF = 250 -60 -80 G = +1, HD3 -100 G = +1, HD2 RL = 100, HD2 -60 -80 RL = 1k, HD3 -100 RL = 1k, HD2 -120 1M 10M FREQUENCY (Hz) -140 100k 07037-017 -140 100k Figure 18. Harmonic Distortion vs. Frequency and Gain 0 G = +1 VS = 15V VOUT = 2V p-p 10M Figure 21. Harmonic Distortion vs. Frequency and Loads 0.14 RL = 100, HD3 VOUT = 100mV p-p G = +1 0.12 R = 1k L VS = 15V 0.10 OUTPUT VOLTAGE (V) -40 -60 1M FREQUENCY (Hz) 07037-020 -120 RL = 100, HD2 -80 -100 RL = 1k, HD3 0.08 CL = 15pF CL = 0pF 0.06 0.04 0.02 CL = 5pF 0 -120 RL = 1k, HD2 -0.02 1M FREQUENCY (Hz) Figure 19. Harmonic Distortion vs. Frequency and Loads 10M 07037-018 -140 100k -0.04 CL = 33pF TIME (20ns/DIV) 07037-021 DISTORTION (dBc) -40 -20 2 Figure 20. Harmonic Distortion vs. Output Amplitude 0 RL = 1k VS = 15V -20 VOUT = 2V p-p 1 OUTPUT VOLTAGE (V p-p) Figure 17. Open-Loop Gain and Phase vs. Frequency DISTORTION (dBc) OPEN-LOOP GAIN (dB) -90 PHASE 80 f = 100kHz G = +1 RL = 1k VS = 15V -100 OPEN-LOOP PHASE (Degrees) 90 -95 -80 07037-016 100 07073-019 110 Figure 22. Small Signal Transient Response for Various Capacitive Loads Rev. B | Page 9 of 20 ADA4898-1 2.5 0.14 VOUT = 100mV p-p RL=1k 0.12 V = 15V S G = +1 2.0 VOUT = 2V p-p G = +1 RL= 1k 0.08 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.10 G = +2 0.06 0.04 0.02 1.5 VS = 5V 1.0 0.5 0 VS = 15V 0 -0.5 TIME (100ns/DIV) Figure 23. Small Signal Transient Response for Various Gains 2.5 VOUT = 2V p-p G = +1 RL = 100 1.5 2.0 VS = 5V 1.0 0.5 -0.5 VOUT = 2V p-p RL = 1k VS = 15V 1.5 G = +2 1.0 0.5 G = +1 VS = 15V 0 0 07037-023 OUTPUT VOLTAGE (V) 2.0 Figure 26. Large Signal Transient Response for Various Supply Voltages, RL = 1 k OUTPUT VOLTAGE (V) 2.5 07037-025 TIME (20ns/DIV) TIME (100ns/DIV) -0.5 Figure 24. Large Signal Transient Response for Various Supply Voltages, RL = 100 07037-024 -0.04 07037-022 -0.02 TIME (100ns/DIV) Figure 27. Large Signal Transient Response for Various Gains 10k 1k t = 85ns 0.1 0 -0.1 -0.2 VOUT = 2V p-p, PD LOW 100 VOUT = 2V p-p, PD HIGH 10 VOUT = 0.1V p-p, PD HIGH 1 G = +1 RF = 0 RL = 0 VS = 15V -0.3 -0.4 -0.5 TIME (10ns/DIV) 0.1 100k 07037-026 SETTLING TIME (%) 0.2 INPUT 1M 10M FREQUENCY (Hz) Figure 25. Settling Time Figure 28. Output Impedance vs. Frequency Rev. B | Page 10 of 20 100M 07037-028 0.4 0.3 VOUT = 0.1V p-p, PD LOW G = +1 RL = 1k VOUT = 5V p-p VS = 15V OUTPUT OUTPUT IMPEDANCE () 0.5 ADA4898-1 0 0 VCM = 1V p-p -20 -20 -40 VCM = 100mV p-p -60 PSRR (dB) CMRR (dB) -40 -80 -60 -80 +PSRR G = +1 RF = 0 RL = 1k VS = 15V 10k 100k 1M 10M FREQUENCY (Hz) 10k 100k 1M 5 15 OUTPUT VOLTAGE SWING (V), VS = 15V VOUT = 0.1V p-p -55 VOUT = 2V p-p -65 10M FREQUENCY (Hz) 100M 07037-031 G = +1 RL = 1k VS = 15V 1M 10M Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency -45 PD ISOLATION (dB) 1k FREQUENCY (Hz) Figure 29. Common-Mode Rejection Ratio (CMRR) vs. Frequency -75 100k -PSRR -120 100 POSITIVE SWING, VS = +15V 12 NEGATIVE SWING, 4 VS = -5V NEGATIVE SWING, VS =-15V 3 9 POSITIVE SWING, VS = +5V 6 2 3 1 0 50 100 1000 0 4000 LOAD RESISTANCE () Figure 32 Output Swing vs. Load, G = +2, Load = RL // (RF + RG) Figure 30. PD Isolation vs. Frequency Rev. B | Page 11 of 20 OUTPUT VOLTAGE SWING (V), VS = 5V 1k 07037-100 -140 100 G = +1 RF = 0 RL = 1k VS = 15V VOUT = 2V p-p -100 07037-029 -120 07037-030 -100 ADA4898-1 1000 N = 6180 MEAN: -0.13 SD: 0.02 VS = 15V 1000 800 COUNT 600 400 400 200 200 -0.20 -0.15 -0.10 -0.05 0 INPUT BIAS CURRENT (A) 0 07037-032 0 -0.25 N = 6180 MEAN: 27 SD: 20 VS = 15V 600 400 0 30 60 90 INPUT OFFSET VOLTAGE (V) 120 07037-033 200 -30 -60 -30 0 30 60 Figure 35. Input Offset Voltage Distribution, VS = 5 V 1000 0 -60 -90 INPUT OFFSET VOLTAGE (V) Figure 33. Input Bias Current Distribution COUNT 600 Figure 34. Input Offset Voltage Distribution, VS = 15 V Rev. B | Page 12 of 20 90 07037-034 COUNT 800 800 N = 6180 MEAN: -2.8 SD: 20 VS = 5V ADA4898-1 TEST CIRCUITS +VS 10F +VS + 10F + 0.1F RG 0.1F RF 0.1F 0.1F VOUT IN 49.9 VOUT IN RL CL 49.9 10F -VS 0.1F 07037-055 07037-052 0.1F + + 10F RL -VS Figure 36. Typical Noninverting Load Configuration Figure 39. Typical Capacitive Load Configuration +VS +VS AC 10F 49.9 + 0.1F VOUT VOUT RL RL 49.9 AC 07037-053 0.1F -VS -VS Figure 37. Positive Power Supply Rejection Figure 40. Negative Power Supply Rejection +VS RIN = 20 10F + +VS IN-AMP 1k 0.1F VOUT RL VOUT +IB RL 1k VCONTROL 0.1F -VS 07037-054 + 10F Figure 38. Common-Mode Rejection 1k -VS 20 Figure 41.DC Test Circuit Rev. B | Page 13 of 20 07037-139 0.1F 1k 53.6 RF = 1k -IB 1k IN 07037-056 + 10F ADA4898-1 THEORY OF OPERATION CURRENT NOISE MEASUREMENT To measure the very low (2.4 pA/Hz) input current noise of the ADA4898-1, 10 k resistors were used on both inputs of the amplifier. Figure 43 shows the noise measurement circuit used. The 10 k resistors are used on both inputs to balance the input impedance and cancel the common-mode noise. In addition, a high gain configuration is used to increase the total output noise and bring it above the noise floor of the instrument. The simplified ADA4898-1 topology, shown in Figure 42, is a single gain stage with a unity gain output buffer. It has over 100 dB of open-loop gain and maintains precision specifications, such as CMRR, PSRR, and offset, to levels that are normally associated with topologies having two or more gain stages. 10 100 10k 10k VOUT 07037-042 The ADA4898-1 is a voltage feedback op amp that combines unity gain stability with 0.9 nV/Hz input noise. It employs a highly linear input stage that can maintain greater than -90 dBc (at 2 V p-p) distortion out to 500 kHz while in a unity-gain configuration. This rare combination of low gain stability, low input-referred noise, and extremely low distortion is the result of Analog Devices, Inc., proprietary op amp architecture and high voltage bipolar processing technology. Figure 43. Current Noise Measurement Circuit BUFFER gm R1 CC RL 07037-041 The current noise density (In) is calculated by VOUT In = Figure 42. Topology PD (POWER-DOWN) PIN The PD pin saves power by decreasing the quiescent power dissipated in the device. It is very useful when power is an issue and the device does not need to be turned on at all times. The response of the device is rapid when going from power-down mode to full power operation mode. Note that PD does not put the output in a high-Z state, which means that the ADA4898-1 is not recommended for use as a multiplexer. Leaving the PD pin floating keeps the amplifier in full power operation mode. Table 6. Power-Down Voltage Control PD Pin Power-Down Mode Full Power Mode 15 V <-14 V >-13 V 10 V <-9 V >-8 V 5 V <-4 V >-3 V Rev. B | Page 14 of 20 [e 2 no - (11 x 18.4 nV/ Hz ) 2 20 k x 11 ] 1/ 2 x 2 ADA4898-1 0.5 0.1 Hz TO 10 Hz NOISE 0.4 Figure 44 shows the 0.1 Hz to 10 Hz voltage and current noise of the ADA4898-1. The peak-to-peak noise voltage is below 0.5 V. Figure 45 shows the circuit used to measure the low frequency noise. It uses a band-pass filter of approximately 0.1 Hz and 10 Hz and a high gain stage feeding into an instrumentation amplifier. OUTPUT VOLTAGE (V) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.5 0 2 4 6 8 10 12 TIME (s) 14 16 18 20 07037-047 -0.4 Figure 44. 0.1 Hz to 10 Hz Noise FARADAY CAGE +IN 50 +VS = +9V 1k 1F 1 10nF 2 +IN -IN -VR = -5V AD743 806k 806k 7805 15.8k 1F -IN +VS = +9V (BATTERY) OUT 3 10nF 4 RG RG AD620 -IN +VS +IN OUTPUT -VS 8 7 6 REF 5 +VS = +9V 10nF TEK TDS 754A SCOPE COAX IN FLOATING SHIELD 13k +VR = +5V 13 10nF -VS = -9V -VS = -9V 7905 -VR = -5V 07037-048 50 DUT ADA4898-1 R = 5.36k, GAIN APPROX. 10 MOMENTARY +VR = +5V -VS = -9V (BATTERY) Figure 45. Low Frequency Noise Circuit Rev. B | Page 15 of 20 ADA4898-1 APPLICATIONS INFORMATION HIGHER FEEDBACK RESISTOR GAIN OPERATION G = +2 RL = 1k 9 VS = 15V RF = 1k 6 RF = 100 3 RF = 1k, CF = 2.7pF 0 -3 -6 -9 -15 100k 1M 10M 100M FREQUENCY (Hz) RF Figure 47. Small Signal Frequency Response for Various Feedback Impedances Table 7 provides a useful reference for determining various gains and associated performance. RF is set to 100 for gains greater than 1. A low feedback RF resistor value reduces peaking and minimizes the contribution to the overall noise performance of the amplifier. 10F + +VS 0.1F 0.1F VOUT RL VIN 0.1F -VS 07037-043 10F + RT Figure 46. Noninverting Gain Schematic Table 7. Various Gains and Associated Recommended Resistor Values (Conditions: VS = 5 V, TA = 25C, RL = 1 k, RT = 49.9 ) Gain +1 +2 +5 RF () 0 100 100 07037-044 -12 RECOMMENDED VALUES FOR VARIOUS GAINS CF RF 12 CLOSED-LOOP GAIN (dB) The ADA4898-1 schematic for the noninverting gain configuration is nearly a textbook example (see Figure 46). The only exception is the feedback capacitor in parallel with the feedback resistor, RF, but this capacitor is recommended only when using a large RF value (>300 ). Figure 47 shows the difference between using a 100 resistor and a 1 k resistor. Due to the input capacitance in the ADA4898-1 when using a higher feedback resistor, more peaking appears in the closed-loop gain. Using the lower feedback resistor resolves this issue; however, when running at higher supplies (15 V) with an RF of 100 , the system draws extra current into the feedback network. To avoid this problem, a higher feedback resistor can be used with a feedback capacitor in parallel. Figure 47 also shows the effect of placing a feedback capacitor in parallel with a larger RF. In this gain-of-2 configuration, RF = RG = 1 k and CF = 2.7 pF. When using CF, the peaking drops from 6 dB to less than 2 dB. RG () N/A 100 24.9 -3 dB SS BW (MHz), VOUT = 100 mV p-p 65 30 9 Slew Rate (V/s), VOUT = 2 V Step 55 50 45 Rev. B | Page 16 of 20 ADA4898-1 Voltage Noise (nV/Hz), RTO 0.9 1.8 4.5 Total System Noise (nV/Hz), RTO 1.29 3.16 7.07 ADA4898-1 NOISE CIRCUIT CONSIDERATIONS To analyze the noise performance of an amplifier circuit, identify the noise sources, and then determine if each source has a significant contribution to the overall noise performance of the amplifier. To simplify the noise calculations, noise spectral densities were used rather than actual voltages to leave bandwidth out of the expressions. Noise spectral density, which is generally expressed in nV/Hz, is equivalent to the noise in a 1 Hz bandwidth. Careful and deliberate attention to detail when laying out the ADA4898-1 board yields optimal performance. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier. The noise model shown in Figure 48 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally specified referred to input (RTI), but it is often simpler to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise. VN, R2 R2 GAIN FROM = A TO OUTPUT 4kTR2 A VN, R1 4kTR1 VN, R3 R1 NOISE GAIN = NG = 1 + R2 R1 IN- VN VOUT R3 IN+ GAIN FROM = - R2 B TO OUTPUT R1 4kTR3 VN2 + 4kTR3 + 4kTR1 RTI NOISE = R2 R1 + R2 + IN+2R32 + IN-2 R1 x R2 R1 + R2 2 2 + 4kTR2 R1 R1 + R2 RTO NOISE = NG x RTI NOISE 2 07037-045 B Figure 48. Op Amp Noise Analysis Model PCB LAYOUT Because the ADA4898-1 bandwidth extends up to 65 MHz, it is essential that RF board layout techniques be employed. All ground and power planes under the pins of the ADA4898-1 should be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. A single mounting pad on a SOIC footprint can add as much as 0.2 pF of capacitance to ground if the ground plane is not cleared from under the mounting pads. POWER SUPPLY BYPASSING Power supply bypassing for the ADA4898-1 has been optimized for frequency response and distortion performance. Figure 46 shows the recommended values and location of the bypass capacitors. Power supply bypassing is critical for stability, frequency response, distortion, and PSR performance. The 0.1 F capacitors shown in Figure 46 should be as close to the supply pins of the ADA4898-1 as possible. The 10 F electrolytic capacitors should be adjacent to but not necessarily close to the 0.1 F capacitors. The capacitor between the two supplies helps improve PSR and distortion performance. In some cases, additional paralleled capacitors can help improve frequency and transient response. GROUNDING Ground and power planes should be used where possible. Ground and power planes reduce the resistance and inductance of the power planes and ground returns. The returns for the input and output terminations, bypass capacitors, and RG should all be kept as close to the ADA4898-1 as possible. The output load ground and the bypass capacitor grounds should be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, and overshoot and to improve distortion performance. All resistors have a Johnson noise that is calculated by (4kBTR) where: k is Boltzmann's constant (1.38 x 10-23 J/K). B is the bandwidth in Hertz. T is the absolute temperature in Kelvin. R is the resistance in ohms. A simple relationship that is easy to remember is that a 50 resistor generates a Johnson noise of 1 nV/Hz at 25C. In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors is shown in Table 7. The ADA4898-1 package features an exposed paddle. For optimum electrical and thermal performance, solder this paddle to negative supply plane. For more information on high speed circuit design, see A Practical Guide to High-Speed Printed-Circuit-Board Layout, Analog Dialogue: PCB Layout at www.analog.com. Rev. B | Page 17 of 20 ADA4898-1 OUTLINE DIMENSIONS 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 8 5 TOP VIEW 1 4 2.29 (0.090) 2.29 (0.090) 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) BOTTOM VIEW 1.27 (0.05) BSC (PINS UP) 1.75 (0.069) 1.35 (0.053) 1.65 (0.065) 1.25 (0.049) 0.10 (0.004) MAX COPLANARITY 0.10 SEATING PLANE 0.51 (0.020) 0.31 (0.012) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.50 (0.020) 0.25 (0.010) 0.25 (0.0098) 0.17 (0.0067) 8 0 45 1.27 (0.050) 0.40 (0.016) 072808-A COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 49. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] (RD-8-1) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADA4898-1YRDZ 1 ADA4898-1YRDZ-R71 ADA4898-1YRDZ-RL1 1 Temperature Range -40C to +105C -40C to +105C -40C to +105C Package Description 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP Z = RoHS Compliant Part. Rev. B | Page 18 of 20 Package Option RD-8-1 RD-8-1 RD-8-1 Ordering Quantity 1 1,000 2,500 ADA4898-1 NOTES Rev. B | Page 19 of 20 ADA4898-1 NOTES (c)2008-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07037-0-6/09(B) Rev. B | Page 20 of 20