NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 1
Feb. 2012 © NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Feature
Table 1: CAS Latency Frequency
Speed Bins
-BE*
DDR3/L-1066
CL7
-CF/CFI*
DDR3/L-1333
CL8
-DH/DHI*
DDR3/L-1600
CL10
-EJ*
DDR3-1866
CL12
-FK*
DDR3-2133
CL13
Units
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tCK(Avg.)
Clock
Frequency
300 533 300 667 300 800 300 933 300 1066 MHz
tRCD13.125 - 12 - 12.5 - 12.84 - 12.155 - ns
tRP13.125 - 12 - 12.5 - 12.84 - 12.155 - ns
tRC50.625 - 48 - 47.5 - 46.84 - 45.155
- ns
tRAS37.5 70K 36 70K 35 70K 34 70K 33 70K ns
tCK(Avg.)@CL53 3.3 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns
tCK(Avg.)@CL6 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns
tCK(Avg.)@CL7 1.875 2.5 1.875 2.5 1.875 2.5 1.875 2.5 1.875 2.5 ns
tCK(Avg.)@CL8 1.875 2.5 1.5 2.5 1.5 2.5 1.875 2.5 1.875 2.5 ns
tCK(Avg.)@CL9 - - 1.5 1.875 1.5 1.875 1.5 1.875 1.5 1.875
ns
tCK(Avg.)@CL10 - - 1.5 1.875 1.25 1.875 1.5 1.875 1.25 1.875
ns
tCK(Avg.)@CL11- - - - 1.25 1.5 1.25 1.5
1.25 1.5 ns
tCK(Avg.)@CL12- - - - - - 1.07 1.25
1.07 1.25 ns
tCK(Avg.)@CL13 - - - - - - 1.07 1.25
0.938 1.25 ns
tCK(Avg.)@CL14 0.938 1.07
ns
*The timing specification of high speed bin is backward compatible with low speed bin
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 2
Feb. 2012 © NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
z 1.35V -0.067/+0.1V &1.5V ± 0.075V (JEDEC
Standard Power Supply)
z 8 Internal memory banks (BA0- BA2)
z Differential clock input (CK, CK)
z Programmable CAS Latency: 5, 6, 7, 8, 9,
10, 11, 12, 13, (14)
z POSTED CAS ADDITIVE Programmable Additive
Latency: 0, CL-1, CL-2
z Programmable Sequential / Interleave Burst Type
z Programmable Burst Length: 4, 8
z 8n-bit prefetch architecture
z Output Driver Impedance Control
z Differential bidirectional data strobe
z Write Leveling
z OCD Calibration
z Dynamic ODT (Rtt_Nom & Rtt_WR)
z Auto Self-Refresh
z Self-Refresh Temperature
z RoHS Compliance
z Lead-Free and Halogen-Free
z Packages:
78-Ball BGA for x8 components
96-Ball BGA for x16 components
z Operation Temperture
Commerical grade (0 TC 95 ) ℃≦ ≦ ℃
- BE, CF, DH, EJ, FK
Industial grade (-40 TC 95 ) ℃≦ ≦ ℃
- CFI, DHI
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 3
Feb. 2012 © NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Description
The 1Gb Double-Data-Rate-3 (DDR3/L) B-die DRAMs is double data rate architecture to achieve high-speed operation. It
is internally configured as an eight bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices. These synchronous devices
achieve high speed double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3/L DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks
(CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.5V ± 0.075V &1.35V -0.067/+0.1V power supply and are available in BGA packages.
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 4
Feb. 2012 © NANYA TECHNOLOGY CORP.
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Fig. 1:Pin Configuration – 78 balls BGA Package (x8)
< TOP View>
See the balls through the package
A
B
C
D
E
F
G
x8
1
VSS
VSSQ
VDD
VSSQ
DQ2
DQ6
VDDQ
VSS
CS
2
NC
DQ0
DQS
DQS
DQ4
RAS
CAS
3 7 8 9
BA0
VDD
NC
VSS
VSSQ
DQ3
VSS
DQ5
VSS
VDD
NU/TDQS
DM/TDQS
DQ1
DQ7
CK
CK
VDDQ
H
J
K
L
VSS
VDDQ
VREFDQ
A3
A5VSS
VDD
WE
BA2
A0
A2 A1
A12/BC
NC
A10/AP
VDD
A4
BA1
VERFCA
ZQ
VDDQ
VSSQ
VSSQ
VDD
ODT
VSS
NC
M
N
VDD A7
RESET
A9
A13
VDDA6
A8
A11
NCVSS VSS
NC
NC
VDD
VSS
VSS
CKE
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 5
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Fig. 2: Pin Configuration – 96 balls BGA Package (X16)
< TOP View>
See the balls through the package
A
B
C
D
E
F
G
x16
1
VDDQ
VSSQ
DQU5
VDD
DQU3
VDDQ
VSSQ
DQL2
VDDQ
2
DQU7
VSS
DQU1
DMU
DQL0
DQSL
3 7 8 9
VSS
VSS
VDDQ
VDDQ
DQU6
DQU2
VSSQ
VSSQ
DQL3
VSS
DQU4
DQSU
DML
DQL1
VDD
VDDQ
H
J
K
L
VSSQ
VDDQ
VSS
VDD
NC
DQL6
DQL4
A10/AP
CK
DQL7
DQU0
ZQ
VDD
VSS
DQL5
VSSQ
VDDQ
VDD
CKE
VSSQ
NC
VSSQ
M
N
VSS BA0
A3
BA2
A0
VSSVREFCA
BA1
NC
A12/VDD VDD
VDDQ
VREFDQ
ODT
NC
NC
VSSQ
PA5VSS A2 A1 A4
R
T
VDD A7 A9
NC
VDDA6
A8
A11
NCVSS VSS
VSS
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 6
Feb. 2012 © NANYA TECHNOLOGY CORP.
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Table 2: Input / Output Functional Description
Symbol Type Function
CK, CK Input
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK.
CKE, (CKE0),
(CKE1)
Input
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE low provides Precharge
Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit and for
Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has
become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power
Down. Input buffers, excluding CKE, are disabled during Self-Refresh.
CS, (CS0), (CS1),
(CS2), (CS3)
Input
Chip Select: All commands are masked when CS is registered high. CS provides for
external rank selection on systems with multiple memory ranks. CS is considered part
of the command code.
RAS, CAS, WE Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
DM, (DMU, DML) Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write access. DM is
sampled on both edges of DQS. For x8 device, the function of DM or TDQS /TQDS is
enabled by Mode Register A11 setting in MR1
BA0 - BA2
Input
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read,
Write or Precharge command is being applied. Bank address also determines which
mode register is to be accessed during a MRS cycle.
A10 / AP Input
Auto-Precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by bank addresses.
A0 – A13 Input
Address Inputs: Provide the row address for Activate commands and the column
address for Read/Write commands to select one location out of the memory array in
the respective bank. (A10/AP and A12/BC have additional function as below.) The
address inputs also provide the op-code during Mode Register Set commands.
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 7
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Symbol Type Function
A12/BC Input
Burst Chop: A12/BC is sampled during Read and Write commands to determine if
burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
ODT, (ODT0),
(ODT1)
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal
to the DDR3/L SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS and
DM/TDQS, NU/TDQS (when TDQS is enabled via Mode Register A11=1 in MR1) signal
for x8 configurations. The ODT pin will be ignored if Mode-registers, MR1and MR2, are
programmed to disable RTT.
RESET Input
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive
when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for
DC high and 0.30V
DQ Input/output
Data Inputs/Output: Bi-directional data bus.
DQL,
DQU,
DQS,(DQS),
DQSL,(DQSL),
DQSU,(DQSU),
Input/output
Data Strobe: output with read data, input with write data. Edge aligned with read data,
centered with write data. The data strobes DQS, DQSL, DQSU are paired with
differential signals DQS, DQSL, DQSU, respectively, to provide differential pair signaling
to the system during both reads and writes. DDR3/L SDRAM supports differential data
strobe only and does not support single-ended.
TDQS, (TDQS) Output
Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When
enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination
resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via
mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS
is not used. x16 DRAMs must disable the TDQS function via mode register A11=0 in
MR1.
NC -
No Connect: No internal electrical connection is present.
VDDQ Supply
DQ Power Supply: 1.5V ± 0.075V &1.35V -0.067/+0.1V
VDD Supply
Power Supply: 1.5V ± 0.075V &1.35V -0.067/+0.1V
VSSQ Supply
DQ Ground
Vss Supply
Ground
VREFCA Supply
Reference voltage for CA
VREFDQ Supply
Reference voltage for DQ
ZQ Supply Reference pin for ZQ calibration.
Note: Input only pins (BA0-BA2, A0-A13, RAS, CAS, WE, CS, CKE, ODT, and RESET ) do not supply termination.
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 8
Feb. 2012 © NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Table 3: DDR3/L SDRAM Addressing
Configuration NT5CB128M8DN/NT5CC128M8DN NT5CB64M16DP/NT5CC64M16DP
# of Bank 8 8
Bank Address BA0 – BA2 BA0 – BA2
Auto precharge A10 / AP A10 / AP
BL switch on the fly A12 / BC A12 / BC
Row Address A0 – A13 A0 – A12
Column Address A0 – A9 A0 – A9
Page size 1KB 2KB
Note:
Page size is the number of data delivered from the array to the internal sense amplifiers when an ACTIVE command is
registered. Page size is per bank, calculated as follows:
Page size = 2 COLBITS * ORG / 8
COLBITS = the number of column address bits
ORG = the number of I/O (DQ) bits
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 9
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Table 4: Ordering Information
Organization Part Number Package
Speed
Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP
128M x 8
NT5CB128M8DN-BE
78-Ball WBGA
0.8mmx0.8mm Pitch
533 DDR3-1066 7-7-7
NT5CB128M8DN-CF 667 DDR3-1333 8-8-8
NT5CB128M8DN-DH 800 DDR3-1600 10-10-10
NT5CB128M8DN-EJ 933 DDR3-1866 12-12-12
64M x 16
NT5CB64M16DP-BE
96-Ball WBGA
0.8mmx0.8mm Pitch
533 DDR3-1066 7-7-7
NT5CB64M16DP-CF 667 DDR3-1333 8-8-8
NT5CB64M16DP-DH 800 DDR3-1600 10-10-10
NT5CB64M16DP-EJ 933 DDR3-1866 12-12-12
Industrial Temperature
Organization Part Number Package
Speed
Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP
128M x 8
NT5CB128M8DN-CFI 78-Ball WBGA
0.8mmx0.8mm Pitch
667 DDR3-1333 8-8-8
NT5CB128M8DN-DHI 800 DDR3-1600 10-10-10
64M x 16
NT5CB64M16DP-CFI 96-Ball WBGA
0.8mmx0.8mm Pitch
667 DDR3-1333 8-8-8
NT5CB64M16DP-DHI 800 DDR3-1600 10-10-10
Note: “I” meaning of the last Part Number is for Industrial Temperature.
1.35 Voltage
Organization Part Number Package
Speed
Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP
128MX8
NT5CC128M8DN-CF 78-Ball WBGA
0.8mmx0.8mm
Pitch
667 DDR3L-1333 8-8-8
NT5CC128M8DN-DH 800 DDR3L-1600 10-10-10
64MX16
NT5CC64M16DP-CF 96-Ball WBGA
0.8mmx0.8mm
Pitch
667 DDR3L-1333 8-8-8
NT5CC64M16DP-DH 800 DDR3L-1600 10-10-10
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 10
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Fig. 3: Simplified State Diagram
Table 5: State Diagram Command Definitions
Abbreviation Function Abbreviation Function
A
bbreviation Function
ACT Active Read RD, RDS4, RDS8 PED Enter Power-down
PRE Prechar
g
e Read
A
RDA, RDAS4, RDAS8 PDX Exit Power-down
PRE
A
Prechar
g
e All Write WR, WRS4, WRS8 SRE Self-Refresh entr
y
MRS Mode Re
g
ister Set Write
A
WRA, WRAS4, WRAS8 SRX Self-Refresh exit
REF Refresh RESE
T
Start RESET Procedure MPR Multi-Pur
p
ose Re
g
ister
ZQCL ZQ Calibration Lon
g
ZQCS ZQ Calibration Short - -
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 11
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Basic Functionality
The DDR3/L SDRAM D-Die is a high-speed dynamic random access memory internally configured as an eight-bank
DRAM. The DDR3/L SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch
architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write operation for the DDR3/L SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal
DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3/L SDRAM are burst oriented, start at a selected location, and continue for a burst
length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A13 select the row). The
address bit registered coincident with the Read or Write command are used to select the starting column location for the
burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the
fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3/L SDRAM must be powered up and initialized in a predefined manner. The following
sections provide detailed information covering device reset and initialization, register definition, command descriptions
and device operation.
RESET and Initialization Procedure
Power-up Initialization sequence
The Following sequence is required for POWER UP and Initialization
1. Apply power (RESET is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). RESET
needs to be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before RESET being
de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms;
and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one
side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once
power ramp is finished, AND
- Vref tracks VDDQ/2.
OR
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one
side and must be larger than or equal to VSSQ and VSS on the other side.
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
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2. After RESET is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start
internal state initialization; this will be done independently of external clocks.
3. Clock (CK, CK) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active.
Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a NOP or
Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered
“High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished,
including expiration of tDLLK and tZQinit.
4. The DDR3/L DRAM will keep its on-die termination in high impedance state as long as RESET is asserted. Further, the
DRAM keeps its on-die termination in high impedance state after RESET de-assertion until CKE is registered HIGH.
The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the
ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up
initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command
to load mode register. [tXPR=max (tXS, 5tCK)]
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1)
7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1)
8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command,
provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,
provide “High” to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3/L SDRAM is now ready for normal operation.
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 13
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Fig. 4: Reset and Initialization Sequence at Power- on Ramping (Cont’d)
Reset Procedure at Stable Power (Cont’d)
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be
maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns).
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3/L SDRAM is ready for normal operation.
Fig. 5: Reset Procedure at Power Stable Condition
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 14
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Register Definition
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the
DDR3/L SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As
the default values of the Mode Registers (MR) are not defined, contents of Mode Registers must be fully initialized and/or
re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be
altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the
user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be
redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which mean
these commands can be executed any time after power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the
minimum time required between two MRS commands shown as below.
Fig. 6: tMRD Timing
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset,
and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the
following figure.
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 15
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Fig. 7: tMOD Timing
Programming the Mode Registers (Cont’d)
The mode register contents can be changed using the same command and timing requirements during normal operation as
long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed
and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the
functionality and/or modes.
Mode Register MR0
The mode-register MR0 stores data for controlling various operating modes of DDR3/L SDRAM. It controls burst length,
read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include
various vendor specific options to make DDR3/L SDRAM useful for various applications. The mode register is written by
asserting low on CS, RAS, CAS, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the
following figure.
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Fig. 8:MR0 Definition
A0A1A2A3A4A5A6A7A8
A9
A10
A11A12A1 31
BA 2
Address Filed
BL
A0A1
8
(Fixed)
0
0
BC 4
or 8
(on the fly)
1
0
Burst Length
Read Burst
Type
A3
Nibble
Sequential
0
Interleave
1
Burst Type
MRS mode
BA 0BA1
MR 0
0
0
1
0
MRS mode
01
11
DLL Control for
Precharge PD
A12
Slow Exit (DLL off )0
Fast Exit (DLL on)
1
Precharge Power Down
*
WR(cycles)
A9A10A11
16000
5
100
Write recovery for autoprecharge **
010
110
001
101
011
111
DLL ResetA8
NO
0
YES
1
DLL Reset ModeA7
Normal0
TEST
1
Mode
* BA 2 and A13 are reserved for future use and must be set to 0 when
programming the MR .
** WR ( write recovery for autoprecharge ) min in clock cycles is calculated by
dividing tWR (ns) by tCK (ns ) and rounding up to the next integer:
Wrmin [ cycles ] = Roundup(tWR /tCK). The value in the mode register must
be programmed to be equal or larger than WRmin. The programmed WR
value is used with tRP to determine tDAL .
CAS Latency
A2A4A5
000
(5)
0
CAS Latency
01
1
1
BC 4
(Fixed)
Reserved
Reserved
A6
0
010
0100
0110
1000
1010
1100
1110
6
7
8
9
10
6
7
8
10
12
14
MR 1
MR 2
MR 3
BA 0BA
11
000
0
1
011
01 1
11 1
0
0
11
0016
15
14
13
12
1
1
1
01 1
110
11 1
Reserved
Reserved
Reserved
Reserved
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Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3
as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length,
burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4,
fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write
command via A12/BC.
Table 6: Burst Type and Burst Order
Burst
Length
Read
Write
Starting
Column
Address
(A2,A1,A0)
Burst type:
Sequential
(decimal)
A3 = 0
Burst type:
Interleaved
(decimal)
A3 = 1
Note
4
Chop
Read
0 , 0 , 0 0,1,2,3,T,T,T,T 0,1,2,3,T,T,T,T
1,2,3
0 , 0 , 1 1,2,3,0,T,T,T,T 1,0,3,2,T,T,T,T
0 , 1 , 0 2,3,0,1,T,T,T,T 2,3,0,1,T,T,T,T
0 , 1 , 1 3,0,1,2,T,T,T,T 3,2,1,0,T,T,T,T
1 , 0 , 0 4,5,6,7,T,T,T,T 4,5,6,7,T,T,T,T
1 , 0 , 1 5,6,7,4,T,T,T,T 5,4,7,6,T,T,T,T
1 , 1 , 0 6,7,4,5,T,T,T,T 6,7,4,5,T,T,T,T
1 , 1 , 1 7,4,5,6,T,T,T,T 7,6,5,4,T,T,T,T
Write 0 , V , V 0,1,2,3,X,X,X,X 0,1,2,3,X,X,X,X 1,2,4,5
1 , V , V 4,5,6,7,X,X,X,X 4,5,6,7,X,X,X,X
8 Read
0 , 0 , 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7
2
0 , 0 , 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6
0 , 1 , 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5
0 , 1 , 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4
1 , 0 , 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3
1 , 0 , 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2
1 , 1 , 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1
1 , 1 , 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0
Write V , V , V 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2,4
Note:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier
than the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of
burst length being selected on-the-fly via A12/BC, the internal write operation starts at the same point in time like a
burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be
pulled in by two clocks.
2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Do not Care.
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CAS Latency
The CAS Latency is defined by MR0 (bit A9~A11) as shown in the MR0 Definition figure. CAS Latency is the delay, in clock
cycles, between the internal Read command and the availability of the first bit of output data. DDR3/L SDRAM does not
support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL);
RL = AL + CL.
Test Mode
The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0
definition figure. Programming bit A7 to a ‘1’ places the DDR3/L SDRAM into a test mode that is only used by the DRAM
manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.
DLL Reset
The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued.
Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK must
be met before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous operations.)
Write Recovery
The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to determine
tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns) and rounding
up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be equal or larger
than tWR (min).
Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-exit’, the
DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be met
prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after entering precharge
power-down and upon exiting power-down requires tXP to be met prior to the next valid command.
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Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive
latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on CS, RAS, CAS, WE high on
BA0 and low on BA1 and BA2, while controlling the states of address pins according to the following figure.
Fig. 9: MR1 Definition
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DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to
normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0=0), the DLL is
automatically disabled when entering Self-Refresh operation and is automatically re-enable upon exit of Self-Refresh
operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or
synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock.
Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF parameters. During
tDLLK, CKE must continuously be registered high. DDR3/L SDRAM does not require DLL for any Write operation, expect
when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL Disable
operation in DLL-off Mode.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continu-
ously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register
set command during DLL-off mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9}
= {0, 0}, to disable Dynamic ODT externally.
Output Driver Impedance Control
The output driver impedance of the DDR3/L SDRAM device is selected by MR1 (bit A1 and A5) as shown in MR1 definition
figure.
ODT Rtt Values
DDR3/L SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination
value Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to enable a unique Rtt
value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3/L
SDRAM. In this operation, the DDR3/L SDRAM allows a read or write command (either with or without auto-precharge) to
be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is
issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings.
Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL
register options are shown as the following table.
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Table 7: Additive Latency (AL) Settings
A4 A3 AL
0 0 0, (AL Disable)
0 1 CL-1
1 0 CL-2
1 1 Reserved
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Write leveling
For better signal integrity, DDR3/L memory module adopted fly by topology for the commands, addresses, control signals,
and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes
flight time skew between clock and strobe at every DRAM on DIMM. It makes difficult for the Controller to maintain tDQSS,
tDSS, and tDSH specification. Therefore, the controller should support ‘write leveling’ in DDR3/L SDRAM to compensate
for skew.
Output Disable
The DDR3/L SDRAM outputs maybe enable/disabled by MR1 (bit12) as shown in MR1 definition. When this feature is
enabled (A12=1) all output pins (DQs, DQS, DQS, etc.) are disconnected from the device removing any loading of the
output drivers. This feature may be useful when measuring modules power for example. For normal operation A12 should
be set to ‘0’.
TDQS, TDQS
TDQS (Termination Data Strobe) is a feature of x8 DDR3/L SDRAM that provides additional termination resistance outputs
that may be useful in some system configurations.
When enabled via the mode register, the same termination resistance function is applied to be TDQS/TDQS pins that are
applied to the DQS/DQS pins.
In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data
strobe function of RDQS is not provided by TDQS.
The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM
function is not supported. When the TDQS function is disabled, the DM function is provided and the TDQS pin is not used.
The TDQS function is available in x8 DDR3/L SDRAM only and must be disabled via the mode register A11=0 in MR1 for
x16 configurations.
Table 8: TDQS, TDQS Function Matrix
MR1 (A11) DM / TDQS NU / TDQS
0 (TDQS Disabled) DM Hi-Z
1 (TDQS Enabled) TDQS TDQS
Note:
1. If TDQS is enabled, the DM function is disabled.
2. When not used, TDQS function can be disabled to save termination power.
3. TDQS function is only available for x8 DRAM and must be disabled for x16.
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Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency.
The Mode Register 2 is written by asserting low on CS, RAS, CAS, WE high on BA1 and low on BA0 and BA2, while
controlling the states of address pins according to the table below.
Fig. 10: MR2 Definition
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CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles,
between the internal Write command and the availability of the first bit of input data. DDR3/L DRAM does not support any
half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL);
WL=AL+CWL.
For more information on the supported CWL and AL settings based on the operating clock frequency, refer to “Standard
Speed Bins” on page116. For detailed Write operation refer to “WRITE Operation” on page41.
Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)
DDR3/L SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh
operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately.
Optional in DDR3/L SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if
DDR3/L SDRAM devices support the following options or requirements referred to in this material. For more details refer to
“Extended Temperature Usage” on page41. DDR3/L SDRAMs must support Self-Refresh operation at all supported
temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the optional
ASR function or program the SRT bit appropriately.
Dynamic ODT (Rtt_WR)
DDR3/L SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal
integrity on the data bus, it is desirable that the termination strength of the DDR3/L SDRAM can be changed without issuing
an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings.
DDR3/L SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal
integrity on the data bus, it is desirable that the termination strength of the DDR3/L SDRAM can be changed without issuing
an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling mode, only
RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT” on page69.
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Mode Register MR3
The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on CS,
RAS, CAS, WE high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table
below.
Fig. 11: MR3 Definition
A0A1A2A3A4A5A6A7A8A9A10A11A12A1 3
BA0BA
BA2
Address Filed
MRS
mode
BA 0
BA1
MR 0
00
10
MRS mode
01
11
Note:BA2 ,A3 -A 1 3 are reserved for future use and must be
set to 0 when programming the MR.
MR1
MR2
MR3
MPR
A2
Normal Operation
0
Dataflow from
MPR1
MPR
MPR Location
A0A1
00
RFU
0
MPR Location
Predefined Pattern *
2
1
10
11
RFU
1
RFU
Operation
The predefined pattern will be used for read synchronization.
When MPR control is set for normal operation (MR3 A[2] =0) then
MR3 A[1:0] will be ignored.
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Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To
enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the
MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any
subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or
RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power
down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET
function is supported during MPR enable mode.
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence.
Fig. 12: MPR Block Diagram
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1, as following
Table 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once
the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register. The resulting
operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown on
page28. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued
with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode RDA has the same functionality as a READ command
which means the auto precharge part of RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA
command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode.
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Table 9: MPR MR3 Register Definition
MR3 A[2] MR3 A[1:0] Function
MPR MPR-Loc
0b don't care (0b or 1b)
Normal operation, no MPR transaction.
All subsequent Reads will come from DRAM array.
All subsequent Write will go to DRAM array.
1b See the page28 Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
MPR Functional Description
•One bit wide logical interface via all DQ pins during READ operation.
•Register Read on x8:
•DQ[0] drives information from MPR.
•DQ[7:1] either drive the same information as DQ [0], or they drive 0b.
•Register Read on x16:
•DQL[0] and DQU[0] drive information from MPR.
•DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b.
•Addressing during for Multi Purpose Register reads for all MPR agents:
•BA [2:0]: don’t care
•A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
•A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst
Chop 4 cases, the burst order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *)
A[2]=1b, Burst order: 4,5,6,7 *)
•A[9:3]: don’t care
•A10/AP: don’t care
•A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
•A11, A13,... (if available): don’t care
•Regular interface functionality during register reads:
•Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
•Support of read burst chop (MRS and on-the-fly via A12/BC)
•All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the
DDR3/L SDRAM.
•Regular read latencies and AC timings apply.
•DLL must be locked prior to MPR Reads.
NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
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Table 10: MPR MR3 Register Definition
MR3 A[2] MR3 A[1:0] Function Burst Length Read
Address
A[2:0]
Burst Order and Data
Pattern
1b 00b Read Predefined
Pattern for System
Calibration
BL8 000b Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern
[0,1,0,1,0,1,0,1]
BC4 000b Burst order 0,1,2,3
Pre-defined Data Pattern
[0,1,0,1]
BC4 100b Burst order 4,5,6,7
Pre-defined Data Pattern
[0,1,0,1]
1b 01b RFU BL8 000b Burst order 0,1,2,3,4,5,6,7
BC4 000b Burst order 0,1,2,3
BC4 100b Burst order 4,5,6,7
1b 10b RFU BL8 000b Burst order 0,1,2,3,4,5,6,7
BC4 000b Burst order 0,1,2,3
BC4 100b Burst order 4,5,6,7
1b 11b RFU BL8 000b Burst order 0,1,2,3,4,5,6,7
BC4 000b Burst order 0,1,2,3
BC4 100b Burst order 4,5,6,7
NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
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DDR3/L SDRAM Command Description and Operation
Table 11: Command Truth Table
Function Abbreviation
CKE
CS
RAS
CAS
WE
BA0-
BA2
A13-
A15
A12-
BC
A10-
AP
A0-9,
A11
NOTES
Previous
Cycle
Current
Cycle
Mode Register Set MRS H H L L L L BA OP Code
Refresh REF H H L L L H V V V V V
Self Refresh Entry SRE H L L L L H V V V V V 7,9,12
Self Refresh Exit SRX L H
H X X X X X X X X
7,8,9,12
L H H H V V V V V
Single Bank Precharge PRE H H L L H L BA V V L V
Precharge all Banks PREA H H L L H L V V V H V
Bank Activate ACT H H L L H H BA Row Address (RA)
Write (Fixed BL8 or BC4) WR H H L H L L BA RFU V L CA
Write (BC4, on the Fly) WRS4 H H L H L L BA RFU L L CA
Write (BL8, on the Fly) WRS8 H H L H L L BA RFU H L CA
Write with Auto Precharge (Fixed BL8 or BC4) WRA H H L H L L BA RFU V H CA
Write with Auto Precharge (BC4, on the Fly) WRAS4 H H L H L L BA RFU L H CA
Write with Auto Precharge (BL8, on the Fly) WRAS8 H H L H L L BA RFU H H CA
Read (Fixed BL8 or BC4) RD H H L H L H BA RFU V L CA
Read (BC4, on the Fly RDS4 H H L H L H BA RFU L L CA
Read (BL8, on the Fly) RDS8 H H L H L H BA RFU H L CA
Read with Auto Precharge (Fixed BL8 or BC4) RDA H H L H L H BA RFU V H CA
Read with Auto Precharge (BC4, on the Fly) RDAS4 H H L H L H BA RFU L H CA
Read with Auto Precharge (BL8, on the Fly) RDAS8 H H L H L H BA RFU H H CA
No Operation NOP H H L H H H V V V V V 10
Device Deselected DES H H H X X X X X X X X 11
Power Down Entry PDE H L
L H H H V V V V V
6,12
H X X X X X X X X
Power Down Exit PDX L H
L H H H V V V V V
6,12
H X X X X X X X X
ZQ Calibration Long ZQCL H H L H H L X X X H X
ZQ Calibration Short ZQCS H H L H H L X X X L X
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DDR3/L SDRAM Command Description and Operation
Command Truth Table (Conti.)
NOTE1. All DDR3/L SDRAM commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the
clock. The MSB of BA, RA and CA are device density and configuration dependant.
NOTE2. RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH
during any function.
NOTE3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Register.
NOTE4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
NOTE5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
NOTE6. The Power-Down Mode does not perform any refresh operation.
NOTE7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self
Refresh.
NOTE8. Self Refresh Exit is asynchronous.
NOTE9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation.
NOTE10. The No Operation command should be used in cases when the DDR3/L SDRAM is in an idle or wait state. The
purpose of the No Operation command (NOP) is to prevent the DDR3/L SDRAM from registering any unwanted
commands between operations. A No Operation command will not terminate a pervious operation that is still
executing, such as a burst read or write cycle.
NOTE11. The Deselect command performs the same function as No Operation command.
NOTE12. Refer to the CKE Truth Table for more detail with CKE transition.
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Table 12: CKE Truth Table
Current State
CKE
Command (N)
RAS, CAS, WE, CS
Action (N) Notes
Previous
Cycle
(N-1)
Current
Cycle
(N)
Power-Down
L L X Maintain Power-Down
14,15
L H DESELECT or NOP Power-Down Exit 11,14
Self-Refresh
L L X Maintain Self-Refresh
15,16
L H DESELECT or NOP Self-Refresh Exit 8,12,16
Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 11,13,14
Reading H L DESELECT or NOP Power-Down Entry 11,13,14,17
Writing H L DESELECT or NOP Power-Down Entry 11,13,14,17
Precharging H L DESELECT or NOP Power-Down Entry 11,13,14,17
Refreshing H L DESELECT or NOP Precharge Power-Down Entry 11
All Banks Idle
H L DESELECT or NOP Precharge Power-Down Entry 11,13,14,18
H L REFRESH Self-Refresh
9,13,18
NOTE 1 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
NOTE 2 Current state is defined as the state of the DDR3/L SDRAM immediately prior to clock edge N.
NOTE 3 COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included
here.
NOTE 4 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
NOTE 5 The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh.
NOTE 6 CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input
level the entire time it takes to achieve the tCKEmin clocks of registrations. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + tCKEmin + tIH.
NOTE 7 DESELECT and NOP are defined in the Command Truth Table.
NOTE 8 On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read
or ODT commands may be issued only after tXSDLL is satisfied.
NOTE 9 Self-Refresh modes can only be entered from the All Banks Idle state.
NOTE 10 Must be a legal command as defined in the Command Truth Table.
NOTE 11 Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
NOTE 12 Valid commands for Self-Refresh Exit are NOP and DESELECT only.
NOTE 13 Self-Refresh cannot be entered during Read or Write operations.
NOTE 14 The Power-Down does not perform any refresh operations.
NOTE 15 “X” means “don’t care“(including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins.
NOTE 16 VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.
NOTE 17 If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered,
otherwise Active Power-Down is entered.
NOTE 18 ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all
timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh
exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
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No Operation (NOP) Command
The No operation (NOP) command is used to instruct the selected DDR3/L SDRAM to perform a NOP (CS low and RAS,
CAS, and WE high). This prevents unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
Deselect Command
The Deselect function (CS HIGH) prevents new commands from being executed by the DDR3/L SDRAM. The DDR3/L
SDRAM is effectively deselected. Operations already in progress are not affected.
DLL- Off Mode
DDR3/L DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit
set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later.
The DLL-off Mode operations listed below are an optional feature for DDR3/L. The maximum clock frequency for DLL-off
Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the
refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL)
in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data
relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command,
the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be
small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is
significantly larger than in DLL-on mode.
The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8)
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Fig. 13 DLL-off mode READ Timing Operation
Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same
way and the skew between all DQ, DQS, and DQS signals will still be tDQSQ.
CK
CK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
READ
CMD
Bank, Col b
Address
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
DQSdiff_DLL_on
DQ_DLL_on
DQSdiff_DLL_off
DQ_DLL_off
DQSdiff_DLL_off
DQ_DLL_off
RL = AL+CL = 6 (CL=6, AL=0)
RL(DLL_off) = AL+(CL-1) = 5 tDQSCKDLL_diff_min
tDQSCKDLL_diff_max
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
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DLL on/off switching procedure
DDR3/L DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit
set back to “0”.
DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh outlined in the following
procedure:
1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT,
must be in high impedance state before MRS to MR1 to disable the DLL).
2. Set MR1 Bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
5. Change frequency, in guidance with “Input Clock Frequency Change” section.
6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from
any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self
Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any
MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was
entered, ODT signal can be registered LOW or HIGH.
8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. A ZQCL command may also be issued after tXS).
9. Wait for tMOD, and then DRAM is ready for next command.
Fig. 14: DLL Switch Sequence from DLL-on to DLL-off
CK
CK
T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1
MRS2)
1)
CMD
CKE
ODT
tMOD
Tf0
tCKSRE 4) tCKSRX 5) tXS tMOD
NOP SRE3) NOP SRX 6) NOP MRS 7) NOP Valid8)
tCKESR
Valid8)
Valid 8)
Time
break Do not
Care
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting with Idle State, RTT in Hi-Z State.
2) Disable DLL by setting MR1 Bit A0 to 1.
3) Enter SR.
4) Change Frequency.
5) Clock must be stable at least tCKSRX.
6) Exit SR.
7) Update Mode registers with DLL off parameters setting.
8) Any valid command.
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DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:
1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must
be in high impedance state before Self-Refresh mode is entered).
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with “Input clock frequency change” section.
4. Wait until a stable is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from
subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when
Self Refresh mode was entered. the ODT signal must continuously be registered LOW until tDLLK timings from
subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self
Refresh mode was entered, ODT signal can be registered LOW or HIGH.
6. Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or
after tDLLK).
9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying
command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.
Fig. 15 DLL Switch Sequence from DLL-on to DLL-off
CK
CK
T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf1 Tg0
1)
CMD
CKE
ODT
Th0
tCKSRE tCKSRX 4) tXS tMRD tDLLK
NOP SRE2) SRX5) MRS 6) MRS7) MRS8) Valid
ODTLoff
+1tck 3) tMRD
Valid
tCKESR
Time
break Do not
Care
NOP
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting from Idle State.
2) Enter SR.
3) Change Frequency.
4) Clock must be stable at least tCKSRX.
5) Exit SR.
6) Set DLL-on by MR1 A0="0"
7) Start DLL Reset
8) Any valid command
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Input Clock frequency change
Once the DDR3/L SDRAM is initialized, the DDR3/L SDRAM requires the clock to be “stable” during almost all states of
normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock period is
not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specification.
The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1)
Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to change the clock
frequency.
For the first condition, once the DDR3/L SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has
been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is permissible,
provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode of the sole
purpose of changing the clock frequency. The DDR3/L SDRAM input clock frequency is allowed to change only within the
minimum and maximum operating frequency specified for the particular speed grade.
The second condition is when the DDR3/L SDRAM is in Precharge Power-Down mode (either fast exit mode or slow exit
mode). If the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was disabled in the
mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be
registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock
frequency may change. The DDR3/L SDRAM input clock frequency is allowed to change only within the minimum and
maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and
CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be provided to
the DRAM tCKSRX before precharge Power Down may be exited; after Precharge Power Down is exited and tXP has
expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to
be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock period,
ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate with new clock
frequency.
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Fig. 16: Change Frequency during Precharge Power-down
NOTES:
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down
2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements
3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register
prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in
this case.
CK
CK
T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Td1 Te0
CKE
Command
DQS,
DQS
tCH tCL
tCK
Te1
tIH tIS tIH tIS
tCKSRE
tCKE
tCKSRX
tCHb tCLb
tCKb
NOP NOP NOP NOP NOP MRS NOP Valid
DLL
Reset Valid
tIH tIS
Address
ODT
DQ
DM
High-Z
High-Z
tAOFPD/tAOF
tCPDED
tXP
tDLLK
Previous Clock Frequency New C lock Frequency
Frequency
Change
Enter Precharge
Power-D own m od e Exit Precharge
Pow er-Dow n m od e
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Write Leveling
For better signal integrity, DDR3/L memory adopted fly by topology for the commands, addresses, control signals, and
clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight
time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS,
tDSS, and tDSH specification. Therefore, the controller should support “write leveling” in DDR3/L SDRAM to compensate
the skew.
The memory controller can use the “write leveling” feature and feedback from the DDR3/L SDRAM to adjust the DQS - DQS
to CK - CK relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS - DQS to
align the rising edge of DQS - DQS with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK - CK,
sampled with the rising edge of DQS - DQS, through the DQ bus. The controller repeatedly delays DQS - DQS until a
transition from 0 to 1 is detected. The DQS - DQS delay established though this exercise would ensure tDQSS specification.
Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual
tDQSS in the application with an appropriate duty cycle and jitter on the DQS- DQS signals. Depending on the actual
tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in
“AC Timing Parameters” section in order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is
show as below figure.
Fig. 17: Write Leveling Concept
0or1 0 0
Diff _CK
Diff _DQS
Source
Diff _CK
Diff _ DQS
Destination
DQ
DQ
Push DQS to capture
0 -1 transition
0or1 1 1
DQS/DQS driven by the controller during leveling mode must be determined by the DRAM based on ranks populated.
Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM configurations x8. Therefore, a
separate feedback mechanism should be able for each byte lane. The upper data bits should provide the feedback of the
upper diff_DQS (diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower diff_DQS
(diff_LDQS) to clock relationship.
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DRAM setting for write leveling and DRAM termination unction in that mode
DRAM enters into Write leveling mode if A7 in MR1 set “High” and after finishing leveling, DRAM exits from write leveling
mode if A7 in MR1 set “Low”. Note that in write leveling mode, only DQS/DQS terminations are activated and deactivated
via ODT pin not like normal operation.
Table 13: MR setting involved in the leveling procedure
Function MR1 Enable Disable
Write leveling enable A7 1 0
Output buffer mode (Qoff) A12 0 1
Table 14: DRAM termination function in the leveling mode
ODT pin at DRAM DQS/DQS termination DQs termination
De-asserted off off
Asserted on off
Note: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed; in Write
Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2, RZQ/4, and RZQ/6 are
allowed.
Procedure Description
Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling mode, the
DQ pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands are allowed. As well
as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output of other rank
must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to
accept the ODT signal.
Controller may drive DQS low and DQS high after a delay of tWLDQSEN, at which time DRAM has applied on-die
termination on these signals. After tDQSL and tWLMRD controller provides a single DQS, DQS edge which is used by the
DRAM to sample CK – CK driven from controller. tWLMRD(max) timing is controller dependent.
DRAM samples CK - CK status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after
tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes
(DQS/DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS –
DQS delay setting and launches the next DQS/DQS pulse after some time, which is controller dependent. Once a 0 to 1
transition is detected, the controller locks DQS – DQS delay setting and write leveling is achieved for the device. The
following figure describes the timing diagram and parameters for the overall Write leveling procedure.
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Timing details of Write leveling sequence
Fig. 18: DQS - DQS is capturing CK - CK low at T1 and CK - CK high at T2
NO P NO P N OP NO P N OP N OP NO P NOP NOP
CK
CK
CMD
ODT
Di ff _ DQ S
Pr im e D Q
Late
Re m a ining
DQs
tMOD
tWLMR D tWLO
tWLS tWLH
tWLOE
tWLS tWLH
tWLO
NOPMRS
tDQSHtDQSLtDQSHtDQSL
T1 T2
Time
break Do not
Care
On e P ri me DQ :
Early
Re m a ining
DQs
tWLO
tWLO
Undefined
Dri ving Mode
tWLOEtWLO
tWLO
A ll DQ s are P rim e :
Late
Re m a ining
DQs
Early
Re m a ining
DQs
tWLMRD tWLO
tWLO
tWLOE
tWLDQSEN
NO P
Note:
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on
one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state
through out the leveling procedure.
2. MRS: Load MR1 to enter write leveling mode
3. NOP: NOP or deselect
4. diff_DQS is the differential data strobe (DQS, DQS). Timing reference points are the zero crossings. DQS
is shown with solid line, DQS is shown with dotted line.
6. DQS/DQS needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for
regular Writes; the max pulse width is system dependent.
Write Leveling Mode Exit
The following sequence describes how Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in
undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1).
2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1).
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Timing detail of Write Leveling exit
Fig. 19: Extended Temperature Usage
Nanya’s DDR3/L SDRAM supports the optional extended temperature range of 0°C to +95°C, TC. Thus, the SRT and ASR
options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double
refresh) anytime the case temperature is above +85°C (and does not exceed +95°C). The external refreshing requirement
is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either ASR or
SRT to support the extended temperature. Thus either ASR or SRT must be enabled when TC is above +85°C or self
refresh cannot be used until the case temperature is at or below +85°C.
Table 14 summarizes the two extended temperature options and Table 15 summarizes how the two extended temperature
options relate to one another.
Table 15: Mode Register Description
Field Bits Description
ASR MR2(A6)
Auto Self-Refresh (ASR)
When enabled, DDR3/L SDRAM automatically provides Self-Refresh power management
functions for all supported operating temperature values. If not enabled, the SRT bit must be
programmed to indicate TOPER during subsequent Self-Refresh operation.
0 = Manual SR Reference (SRT)
1 = ASR enable
SRT MR2(A7)
Self-Refresh Temperature (SRT) Range
If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh
operation. If ASR = 1, SRT bit must be set to 0.
0 = Normal operating temperature range
1 = Extended operating temperature range
CK
CK
T0 T1 Ta0 Tc0 Tc1 Tc2 Td1 Te1
CMD
BA
tIS
tMOD
tMRD
ODT
RTT_DQS_DQS
DQS_DQS
Result = 1
tWLO
DQ
RTT_Nom
Td0 Te0T2 Tb0
tAOFmin
tAOFmax
TransitioningTime Break Do not Care Undefined
Driving Mo de
NOP NOP NOP NOP NOP NOP NOP MRS NOP Valid NOP Valid
MR1 Valid Valid
tODTLoff
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Auto Self-Refresh mode - ASR mode
DDR3/L SDRAM provides an Auto-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit
A6=1 and MR2 bit A7=0. The DRAM will manage Self-Refresh entry in either the Normal or Extended Temperature Ranges.
In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM operating temperature
changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by DRAM, MR2 bit
A6 must set to 0. If the ASR option is not enabled (MR2 bit A6=0), the SRT bit (MR2 bit A7) must be manually programmed
with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not
automatically imply support of the Extended Temperature Range.
Self-Refresh Temperature Range - SRT
SRT applies to devices supporting Extended Temperature Range only. If ASR=0, the Self-Refresh Temperature (SRT)
Range bit must be programmed to guarantee proper self-refresh operation. If SRT=0, then the DRAM will set an
appropriate refresh rate for Self-Refresh operation in the Normal Temperature Range. If SRT=1, then the DRAM will set an
appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended Temperature
Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to IDD table for details.
Table 16:Self-Refresh mode summary
MR2
A[6]
MR2
A[7]
Self-Refresh operation
Allowed Operating
Temperature Range
for Self-Refresh mode
0 0 Self-Refresh rate appropriate for the Normal Temperature Range Normal (0 ~ 85C)
0 1
Self-Refresh appropriate for either the Normal or Extended Temperature Ranges.
The DRAM must support Extended Temperature Range. The value of the SRT bit
can effect self-refresh power consumption, please refer to the IDD table for details.
Normal and Extended
(0 ~ 95C)
1 0
ASR enabled (for devices supporting ASR and Normal Temperature Range).
Self-Refresh power consumption is temperature dependent.
Normal (0 ~ 85C)
1 0
ASR enabled (for devices supporting ASR and Extended Temperature Range).
Self-Refresh power consumption is temperature dependent.
Normal and Extended
(0 ~ 95C)
1 1 Illegal
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Table 17:MPR MR3 Register Definition
MR3 A[2] MR3 A[1:0] Function
0
don't care
(0 or 1)
Normal operation, no MPR transaction.
All subsequent Reads will come from DRAM array.
All subsequent Writes will go to DRAM array.
1
See the following
table
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
MPR Functional Description
z One bit wide logical interface via all DQ pins during READ operation.
z Register Read on x8:
z DQ [0] drives information from MPR.
z DQ [7:1] either drive the same information as DQ [0], or they drive 0.
z Addressing during for Multi Purpose Register reads for all MPR agents:
z BA [2:0]: don’t care.
z A [1:0]: A [1:0] must be equal to “00”. Data read burst order in nibble is fixed.
z A[2]: For BL=8, A[2] must be equal to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; For Burst chop 4 cases, the burst order is
switched on nibble base, A[2]=0, burst order: 0,1,2,3, A[2]=1, burst order: 4,5,6,7. *)
z A [9:3]: don’t care.
z A10/AP: don’t care.
z A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0
z A11, A13: don’t care.
z Regular interface functionality during register reads:
z Support two Burst Ordering which are switched with A2 and A[1:0]=00.
z Support of read burst chop (MRS and on-the-fly via A12/BC).
z All other address bits (remaining column addresses bits including A10, all bank address bits) will be ignored by the
DDR3/L SDRAM.
z Regular read latencies and AC timings apply.
z DLL must be locked prior to MPR READs.
Note *): Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
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MPR Register Address Definition
The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS
to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.
Table 18: MPR MR3 Register Definition
MR3 A[2] MR3 A[1:0] Function
Burst
Length
Read
Address
A[2:0]
Burst Order and Data Pattern
1 00
Read
Predefined
Pattern for
System
Calibration
BL8 000
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
BC4 000
Burst order 0,1,2,3
Pre-defined Data Pattern [0,1,0,1]
BC4 100
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
1 01 RFU
BL8 000 Burst order 0,1,2,3,4,5,6,7
BC4 000 Burst order 0,1,2,3
BC4 100 Burst order 4,5,6,7
1 10 RFU
BL8 000 Burst order 0,1,2,3,4,5,6,7
BC4 000 Burst order 0,1,2,3
BC4 100 Burst order 4,5,6,7
1 11 RFU
BL8 000 Burst order 0,1,2,3,4,5,6,7
BC4 000 Burst order 0,1,2,3
BC4 100 Burst order 4,5,6,7
Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the
BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A13 selects the row. These rows remain active
(or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before
opening a different row in the same bank.
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PRECHARGE Command
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued,
except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long
as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank
has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to
that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle bank) or if the previously open row
is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE
command issued to the bank.
READ Operation
Read Burst Operation
During a READ or WRITE command DDR3/L will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (AUTO PRECHARGE can be enabled or disabled).
A12=0, BC4 (BC4 = burst chop, tCCD=4)
A12=1, BL8
A12 will be used only for burst length control, not a column address.
Fig. 20: Read Burst Operation RL=5 (AL=0, CL=5, BL=8)
Fig. 21: READ Burst Operation RL = 9 (AL=4, CL=5, BL=8)
CK
CK
T0 T1 T3 T5 T6 T7 T9 T145
CL=5
DQS, DQS
T2 T4 T8 T10
READ NOPCMD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Bank
Col n
Address
Dout
nDout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5 Dout
n +6 Dout
n +7
DQ
RL = AL + CL
tRPRE tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9 T145
CL=5
DQS, DQS
T2 T4 T8 T10
READ NOPCMD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Bank
Col n
Address
Dout
nDout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
DQ RL = AL + CL
tRPREAL = 4
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READ Timing Definitions
Read timing is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK.
tDQSCK is the actual position of a rising strobe edge relative to CK, CK.
tQSH describes the DQS, DQS differential output high time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tQSL describes the DQS, DQS differential output low time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Fig. 22: Read Timing Definition
R ising S trobe
R egion
tD Q S K , m in tD Q S K , m a x
tD Q S K
CK
CK
DQS
DQS
tD Q S K
R ising S trobe
R egion
tQ S H tQ S L
tQ H tQ H
tD Q S Q tD Q S Q
A ssociated
DQ pins
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Read Timing; Clock to Data Strobe relationship
Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and CK.
tDQSCK is the actual position of a rising strobe edge relative to CK and CK.
tQSH describes the data strobe high pulse width.
Falling data strobe edge parameters:
tQSL describes the data strobe low pulse width.
Fig. 23: Clock to Data Strobe Relationship
NOTES: 1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe
edge can vary between tDQSCK(min) and tDQSCK(max).
2. The DQS, DQS# differential output high time is defined by tQSH and the DQS, DQS# differential output low time is defined by
tQSL.
3. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max
are not tied to tDQSCKmax (late strobe case).
4. The minimum pulse width of read preamble is defined by tRPRE(min).
5. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.
6. The minimum pulse width of read postamble is defined by tRPST(min).
7. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
CK
CK
RL Measured
to th is p o in t
DQS, DQS
Early Strobe
DQS, DQS
Late Strobe
tLZ(DQS)min
tLZ(DQS)max
tRPRE
tRPRE
tDQSCKmin
tDQSCKmax
tQSH tQSL tRPST
tRPST
tHZ(DQS)min
tHZ(DQS)max
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Read Timing; Data Strobe to Data Relationship
The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL and enabled and locked.
Rising data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
tDQSQ; both rising/falling edges of DQS, no tAC defined
Fig. 24: Data Strobe to Data Relationship
Dout
n +6 Dout
n +7
tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
DQS, DQS
T2 T4 T8
READ NOPCMD NOP NOP NOP NOP NOP NOP NOP NOP
Bank
Col n
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
DQ (Last data valid) RL = AL + CL
tRPRE
Dout
n +6 Dout
n +7
Dout
nDout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
tLZ(DQ)min
Valid data
tHZ(DQ)min
tDQSQmax
Valid data
tQH
tQH
Dout
n
tDQSQmin
DQ (First data no
longer valid)
All DQ collectively
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Fig. 25: Read to Read (CL=5, AL=0)
T11T10
NOP NOP
Dout
n +6
Dout
n +7
tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP READ NOP NOP NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
tCCD tRPRE
Dout
n
T12
NOP
T13
NOP
RL = 5
Bank
Col b
READ
Dout
b +6
Dout
b +7
Dout
b +1
Dout
b +2
Dout
b +3
Dout
b +4
Dout
b +5
Dout
b
RL = 5
DQS, DQS
DQ
READ (BL8) to READ (BL8)
NOP NOP
tRPST
NOPCMD NOP NOP READ NOP NOP NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
tCCD tRPRE
Dout
n
NOP NOP
RL = 5
Bank
Col b
READ
Dout
b +1
Dout
b +2
Dout
b +3
Dout
b
RL = 5
DQS, DQS
DQ
READ (BL4) to READ (BL4)
tRPRE
tRPST
READ
Bank
Col n
READ
Bank
Col n
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Fig. 26: READ to WRITE (CL=5, AL=0; CWL=5, AL=0)
T11T10
NOP
Dout
n +6
Dout
n +7
tWPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP WRITE
Address
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
READ to Write Command delay = RL +tCCD + 2tCK -WL
tRPRE
Dout
n
T12
NOP
T13
NOP
RL = 5
Bank
Col b
Dout
b +7
Dout
b +1
Dout
b +2
Dout
b +3
Dout
b +4
Dout
b +5
WL = 5
DQS, DQS
DQ
READ (BL8) to WRITE (BL8)
NOP
tWPST
NOPCMD NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
READ to WR I T E Command Delay = RL + tCCD/2 + 2tCK - WL tRPRE
Dout
n
NOP NOP
RL = 5
READ
Dout
b +1
Dout
b +2
Dout
b +3
WL = 5
DQS, DQS
READ (BL4) to WRITE (BL4)
tWPRE
tRPST
T14 T15
NOP NOP
tWRPRE
tRPST
Bank
Col n
READ NOP NOP NOP
NOPNOPNOP
DQ
NOP NOP
tBL = 4 clocks
tWR
tWTR
READ
Bank
Col n
WRITE
Bank
Col b
NOP
Dout
b
NOPNOPNOP NOP
Dout
b
Dout
b +6
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Fig. 27: READ to READ (CL=5, AL=0)
T11T10
NOP NOP
Dout
n +6
Dout
n +7
tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP NOP NOP NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
tCCD tRPRE
Dout
n
T12
NOP
T13
NOP
RL = 5
READ
Dout
b +1
Dout
b +2
Dout
b +3
Dout
b
RL = 5
DQS, DQS
DQ
READ (BL8) to READ (BC4)
NOP NOP
tRPST
NOPCMD NOP NOP NOP NOP NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
tCCD tRPRE
Dout
n
NOP NOP
RL = 5
READ
RL = 5
DQS, DQS
READ (BC4) to READ (BL8)
tRPRE
tRPST
DQ
READ
Bank
Col n
READ
Bank
Col n
READ
Bank
Col b
READ
Bank
Col b
Dout
b +6
Dout
b +7
Dout
b +1
Dout
b +2
Dout
b +3
Dout
b +4
Dout
b +5
Dout
b
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Fig. 28: READ to WRITE (CL=5, AL=0; CWL=5, AL=0)
T11T10
NOP NOP
Dout
n +6
Dout
n +7
tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP WRITE
Address
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
tRPRE
Dout
n
T12
NOP
T13
NOP
RL = 5
READ
Dout
b +1
Dout
b +2
Dout
b +3
WL = 5
DQS, DQS
DQ
NOP NOP
tWPST
NOPCMD NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
READ to WRITE Command delay = RL + tCCD/2 +2tCK - WL tRPRE
Dout
n
NOP NOP
RL = 5
READ
WL = 5
DQS, DQS
READ (BL4) to WRITE (BL8)
tWPRE
tRPST
DQ
READ
Bank
Col n
READ
Bank
Col n
NOP
Bank
Col b
WRITE
Bank
Col b
Dout
b +6
Dout
b +7
Dout
b +1
Dout
b +2
Dout
b +3
Dout
b +4
Dout
b +5
Dout
b
NOPNOPNOPNOP
READ (BL8) to WRITE (BC4)
NOP NOP NOPNOP
tWPST
tWPRE
Dout
b
READ to WRITE Command dela y = R L + tC CD +2tCK - WL
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Write Operation
DDR3/L Burst Operation
During a READ or WRITE command, DDR3/L will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (Auto Precharge can be enabled or disabled).
A12=0, BC4 (BC4 = Burst Chop, tCCD=4)
A12=1, BL8
A12 is used only for burst length control, not as a column address.
WRITE Timing Violations
Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the
DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to “hang up”
and errors be limited to that particular operation.
For the following, it will be assumed that there are no timing violations with regard to the Write command itself (including
ODT, etc.) and that it does satisfy all timing requirements not mentioned below.
Data Setup and Hold Violations
Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then
wrong data might be written to the memory location addressed with the offending WRITE command.
Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly
otherwise.
Strobe to Strobe and Strobe to Clock Violations
Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS,
tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might be written to
the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in
unpredictable read data, however the DRAM will work properly otherwise.
Write Timing Parameters
This drawing is for example only to enumerate the strobe edges that “belong” to a write burst. No actual timing violations
are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge -
as shown).
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Fig. 29: Write Timing Definition
Note:
1. BL=8, WL=5 (AL=0, CWL=5).
2. Din n = data in from column n.
3. NOP commands are shown for ease of illustration; other command may be valid at these times.
4. BL8 setting activated by either MR0 [A1:0=00] or MR0 [A1:0=01] and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
Tn
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP
Address
DQ
NOP
WL = AL + CWL
NOP NOP
Din
n +6 Din
n +7
Din
n +1 Din
n +2 Din
n +3 Din
n +4 Din
n +5
Din
n
tDQSS tDSH
tDQSL
tDSS
tWPST(min)
tDQSL(min)
tDSS
tDSS tDSS
tDSS
DQ
tDSH
tDQSH tDQSL
tDSS
tDQSH
tWPRE(min)
tDSS
tDSH
tDQSH
tDSH
tDSH
tDSS tDSS
tDSS
DQ Din
n +6 Din
n +7
Din
n +1 Din
n +2 Din
n +3 Din
n +4 Din
n +5
Din
n
tDSH
tDQSH tDQSH
tDSH
tDQSH
tDSHtDSH
NOP
tDQSH
tWPRE(min)
Write
Bank
Col n
tWPRE(min)
tDQSH
NOP
tDSS
tDQSL tDSS tDSS
NOP
tDSH
tDSH
Din
n +6 Din
n +7
Din
n +1 Din
n +2 Din
n +3 Din
n +4 Din
n +5
Din
n
tDQSH
tDSH
NOP
tDSS
tDSS
tDQSL(min)
tWPST(min)
tDQSL(min)
tWPST(min)
tDQSS
DQS, DQS
(tDQSS min)
DQS, DQS
(tDQSS nominal)
DQS, DQS
(tDQSS max)
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Fig. 30: WRITE to WRITE (WL=5; CWL=5, AL=0)
T11T10
NOP
Dout
n +7
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +5
tCCD tWPRE
T12
NOP
T13
NOP
WL = 5
Dout
b +6
Dout
b +7
Dout
b +1
Dout
b +2
Dout
b +3
Dout
b +5
WL = 5
DQS, DQS
DQ
WRITE (BL8) to WRITE (BL8)
NOP
tWPST
NOPCMD NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
tCCD tRPRE
NOP NOP
WL = 5
READ
Dout
b +1
Dout
b +2
Dout
b +3
WL = 5
DQS, DQS
WRITE (BC4) to WRITE (BC4)
tWPRE
tWPST
tWPST
Bank
Col n
WRITE NOP NOP NOP
NOPNOPWRITE
DQ
WRITE
Bank
Col n
WRITE
Bank
Col b
NOP
Bank
Col b
Dout
n
NOP NOP NOP NOP
Dout
n +4
Dout
n +6
Dout
b
Dout
b +4
tBL=4
tWR
tWTR
tBL=4
tWR
tWTR
Dout
n
Dout
b
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Fig. 31: WRITE to READ (RL=5, CL=5, AL=0; WL=5, CWL=5, AL=0; BL=4)
T11T10
NOP
Dout
n +7
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +5
tWPRE
T12
NOP
T13
READ
WL = 5
DQS, DQS
DQ
WRITE (BL8) to READ (BC4/BL8)
NOP
NOPCMD NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
tRPRE
Dout
n
NOP READ
WL = 5
DQS, DQS
WRITE (BC4) to READ (BC4/BL8)
tWPST
Bank
Col n
WRITE NOP NOP NOP
NOPNOPNOP
DQ
WRITE
Bank
Col n
NOP NOP
Bank
Col b
Dout
n
NOP NOP NOP NOP
Dout
n +4
Dout
n +6
tWTR
RL=5
tBL=4
tWPST
Bank
Col b
tWTR
RL=5
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Fig. 32: WRITE to WRITE (WL=5, CWL=5, AL=0)
T11T10
NOP
Dout
n +7
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +5
tCCD tWPRE
T12
NOP
T13
NOP
WL = 5
Dout
b +1
Dout
b +2
WL = 5
DQS, DQS
DQ
WRITE (BL8) to WRITE (BC4)
NOP
tWPST
NOPCMD NOP NOP NOP
Address
Dout
n +1
Dout
n +2
Dout
n +3
tCCD tRPRE
Dout
n
NOP NOP
WL = 5
READ
Dout
b +1
Dout
b +2
Dout
b +3
WL = 5
DQS, DQS
WRITE (BC4) to WRITE (BL8)
tWPRE
tWPST
tWPST
Bank
Col n
WRITE NOP NOP NOP
NOPNOPWRITE
DQ
WRITE
Bank
Col n
WRITE
Bank
Col b
NOP
Bank
Col b
Dout
n
NOP NOP NOP NOP
Dout
n +4
Dout
n +6
Dout
b
tBL=4
tWR
tWTR
tBL=4
tWR
tWTR
Dout
b +3
Dout
b +6
Dout
b +7
Dout
b +3
Dout
b +5
Dout
b +4
Dout
b
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Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3/L SDRAMs. This command is not persistent, so
it must be issued each time a refresh is required. The DDR3/L SDRAM requires Refresh cycles at an average periodic
interval of tREFI. When CS, RAS, and CAS are held Low and WE High at the rising edge of the clock, the chip enters a
Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before
the Refresh Command can be applied. The refresh addressing is generated by the internal refresh controller. This makes
the address bits “Don’t Care” during a Refresh command. An internal address counter suppliers the address during the
refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has
completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the
next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as
shown in the following figure.
In general, a Refresh command needs to be issued to the DDR3/L SDRAM regularly every tREFI interval. To allow for
improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.
A maximum of 8 Refresh commands can be postponed during operation of the DDR3/L SDRAM, meaning that at no point
in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are
postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A
maximum of 8 additional Refresh commands can be issued in advance (“pulled in”), with each one reducing the number of
regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not
further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two
surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh
commands must be executed.
Fig. 33: Self-Refresh Entry/Exit Timing
Fig. 34: Postponing Refresh Commands (Example)
CK
CK
T0 T1 Ta0 Tb0 Tb1 Tb3
Ta1 Tb2
NOPCMD NOP REF Valid
NOPREF NOP Valid ValidValid Valid REF
Tc0 Tc1
Valid
tRFC tRFC(min)
tR E F I (max, 9 x tREFI)
DRAM must be idle
DRAM must be idle
Time Break
9 x tR EFI
tR E F I
tR E F I
8 R EF-C om m and postponed
t
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Fig. 35: Pulled-in Refresh Commands (Example)
Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3/L SDRAM, even if the reset of the system is powered
down. When in the Self-Refresh mode, the DDR3/L SDRAM retains data without external clocking. The DDR3/L SDRAM
device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by
having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock.
Before issuing the Self-Refreshing-Entry command, the DDR3/L SDRAM must be idle with all bank precharge state with
tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either registering
ODT pin low “ODTL + 0.5tCK” prior to the Self-Refresh Entry command or using MRS to MR1 command. Once the
Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal
operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-Refresh and is automatically
enabled (including a DLL-RESET) upon exiting Self-Refresh.
When the DDR3/L SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and RESET, are
“don’t care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VRefCA,
and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within tCKE
period once it enters Self-Refresh mode.
The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3/L SDRAM
must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock
tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device
can exit Self-Refresh mode.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going
back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on
command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL
can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL
can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements [TBD] must be satisfied.
9 x tR E FI
tREFI
t
tREFI
8 R EF-Com mands pulled-in
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Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on
the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may be required to
compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”. To issue ZQ calibration
commands, applicable timing requirements must be satisfied.
CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry.
Upon exit from Self-Refresh, the DDR3/L SDRAM can be put back into Self-Refresh mode after waiting at least tXS period
and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each
positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL.
The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is
raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3/L SDRAM requires a minimum of one extra
refresh command before it is put back into Self-Refresh mode.
Fig. 36:Self-Refresh Entry/Exit Timing
CK, CK
T1 T2 Ta0 Tb0 Tc0 Tc1 Te0 Tf
ODTL
tCKSRE
tCKSRX
tCPDED
tRF
SRE NOP Va lid 2 )
tCKESR
tXSDLL
tXS
CMD
ODT
Note:
1. Only NOP or DES commands
2. Valid commands not requiring a locked DL L
3. Valid commands requiring a locked DLL
T0 Td0
Valid
CKE
NOP SRX NOP 1) Valid 3 )
Valid Valid
Valid
Valid
Ente r S e lf R e fre sh Exit S e lf R e fres h
Do Not
Care Time
Break
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Power-Down Modes
Power-Down Entry and Exit
Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is not
allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write
operation are in progress. CKE is allowed to go low while any of other operation such as row activation, precharge or auto
precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operation.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not
locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and
synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL
operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications.
During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in precharge
Power-Down mode; if any bank is open after in progress commands are completed, the device will be in active
Power-Down mode.
Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, CKE, and RESET. To protect
DRAM internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are needed during the
CKE switch off and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result in deactivation of
command and address receivers after tCPDED has expired.
Table 19: Power-Down Entry Definitions
Status of DRAM MRS bit A12 DLL PD Exit Relevant Parameters
Active
(A Bank or more open)
Don't Care On Fast tXP to any valid command.
Precharged
(All Banks Precharged)
0 Off Slow
tXP to any valid command. Since it is in precharge state, commands
here will be ACT, AR, MRS/EMRS, PR, or PRA.
tXPDLL to commands who need DLL to operate, such as RD, RDA,
or ODT control line.
Precharged
(All Banks Precharged)
1 On Fast tXP to any valid command.
Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during
precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, RESET high, and a stable
clock signal must be maintained at the inputs of the DDR3/L SDRAM, and ODT should be in a valid state but all other input
signals are “Don’t care” (If RESET goes low during Power-Down, the DRAM will be out of PD mode and into reset state).
CKE low must be maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.
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The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command).
CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down
exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet.
Fig. 37: Active Power-Down Entry and Exit timing diagram
Timing Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto
Precharge, Activate, Precharge, Refresh, MRS:
Fig. 38: Power-Down Entry after Read and Read with Auto Precharge
Fig. 39: Power-Down Entry after Write with Auto Precharge
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0
CK
CK
Valid NOP NOP NOP NOP NOP NOPCMD
CKE Valid Valid
tIS
tIH
tPD tIH
tIS tCKE
Address Valid Valid
tCPDED
Enter
Power-Down Exit
Power-Down
tXP
Do not
care Time
Break
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5
CK
CK
RD or
RDA NOP NOP NOP NOP NOP NOPCMD
CKE
Address Valid Valid
Power-Down
Entry Do not
care Time
Break
Ta6 Ta7 Ta8 Tb0 Tb1
NOP NOP NOP NOP NOP Valid
Valid
tIS tCPDED
DQS
RL = AL + CL
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
Din
bDin
b+1 Din
b+2 Din
b+3
tRDPDEN
BL8
BC4
tPD
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5
CK
CK
WRITE NOP NOP NOP NOP NOP NOPCMD
CKE
Address Bank,
Col n
Power-Down
Entry Do not
care Time
Break
Ta6 Ta7 Tb0 Tb1 Tb2
NOP NOP NOP NOP NOP NOP
tIS tCPDED
DQS
WL=AL+CWL
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
Din
bDin
b+1 Din
b+2 Din
b+3
tWRAPDEN
BL8
BC4
WR (1)
Tb3
NOP
Tc0
Valid
tPD
Start Internal
Precharge
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Fig. 40: Power-Down Entry after Write
Fig. 41: Precharge Power-Down (Fast Exit Mode) Entry and Exit
Fig. 42: Precharge Power-Down (Slow Exit Mode) Entry and Exit
Fig. 43: Refresh Command to Power-Down Entry
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5
CK
CK
WRITE NOP NOP NOP NOP NOP NOPCMD
CKE
Address Bank,
Col n
Power-Down
Entry Do not
care Time
Break
Ta6 Ta7 Tb0 Tb1 Tb2
NOP NOP NOP NOP NOP NOP
tIS tCPDED
DQS
WL=AL+CWL
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
Din
bDin
b+1 Din
b+2 Din
b+3
tWRPDEN
BL8
BC4
Tc0
NOP
tPDWR
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0
CK
CK
WRITE NOP NOP NOP NOP NOP NOPCMD
CKE
Do not
care Time
Break
NOP
tIS tC P D E D tIH tC K E
tIS
tX P
NOP V alid
tPD
Enter
Power-Down
Mode
Exit
Power-Down
Mode
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0
CK
CK
WRITE NOP NOP NOP NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED tIH tCKE
tIS tXP
NOP Valid
tPD
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Td0
Valid
tXPDLL
Valid
T0 T1 T2 T3 Ta0 Ta1
CK
CK
REF NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tC P D ED
Valid
tPD
Valid Valid
tREFPDEN
Address
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Fig. 44: Active Command to Power-Down Entry
Fig. 45: Precharge/Precharge all Command to Power-Down Entry
Fig. 46: MRS Command to Power-Down Entry
T0 T1 T2 T3 Ta0 Ta1
CK
CK
Active NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED
Valid
tPD
Valid Valid
tACTPDEN
Address
T0 T1 T2 T3 Ta0 Ta1
CK
CK
PRE
PREA NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED
Valid
tPD
Valid Valid
tPREPDEN
Address
T0 T1 Ta0 Ta1 Tb0 Tb1
CK
CK
NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED
Valid
t P D
Valid
tMRSPDEN
Address
MRS
Valid
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On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3/L SDRAM that allows the DRAM to turn on/off termination resistance
for each DQ, DQS, DQS, and DM for x8 configuration and TDQS, TDQS for x8 configuration, when enabled via A11=1 in
MR1) via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing
the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown as below.
Fig. 47: Functional Representation of ODT
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The
value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the Mode Register MR1
and MR2 are programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of RTT is
determined by the settings of those bits.
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)
DRAM does not use any write or read command decode information.
Table 20: Termination Truth Table
ODT pin DRAM Termination State
0 OFF
1 ON, (OFF, if disabled by MR1 {A2, A6, A9} and MR2{A9, A10} in general)
To other
circuitry
lik e
R C V, ...
VDDQ / 2
RTT
Switch DQ , DQS, DM, TDQS
ODT
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Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these
modes are:
z Any bank active with CKE high
z Refresh with CKE high
z Idle mode with CKE high
z Active power down mode (regardless of MR0 bit A12)
z Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continu-
ously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register
set command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising clock edge
and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write
latency (WL) by: ODTLonn = WL - 2; ODTLoff = WL-2.
ODT Latency and Posted ODT
In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT
signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative
to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to DDR3/L SDRAM latency
definitions.
Table 21: ODT Latency
Symbol Parameter DDR3/L-1066 DDR3/L-1333 DDR3/L-1600 DDR3-1866 DDR3-2133 Unit
ODTLon ODT turn on Latency WL - 2 = CWL + AL - 2 tCK
ODTLoff ODT turn off Latency WL - 2 = CWL + AL - 2 tCK
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Timing Parameters
In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max.
Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance
begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are
measured from ODTLon.
Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance. Maximum
RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are
measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with
ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and
ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until
ODT is registered low.
Fig. 48: Synchronous ODT Timing Example for AL=3; CWL=5; ODTLon=AL+CWL-2=6;
ODTLoff=AL+CWL-2=6
Fig. 49: Synchronous ODT example with BL=4, WL=7
ODT must be held for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8
(BL=8) after Write command (T7). ODTH is measured from ODT first registered high to ODT first registered
low, or from registration of Write command with ODT high to ODT registered low. Note that although ODTH4 is
satisfied from ODT registered at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from
the registration of the Write command at T7.
CK
CK
AL=3
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12
ODT
ODTH4, min
ODTLon = C WL + AL -2 ODTLoff = CWL + AL -2
T13 T14 T15
CWL - 2
DRAM_RTT
tAONmin
tAONmax tAONmin
tAONmax
RTT_NOM
AL=3
Transitioning Do not care
CKE
CK
CK
ODTH4
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12
ODT
ODTLon = CW L -2
T13 T14 T15
O DT L o ff = WL - 2
DRAM_RTT
tAONmin tAONmax
tAOFmax
RTT_NOM
T16 T17 T18
ODTH4min
ODTH4
O D T L o ff = CWL -2
OD TLon = CW L -2
tAOFmin
tAOFmax tAONmax
tAONmin tAOFmin
NOP NOP NOP NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Transitioning D o not care
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ODT during Reads:
As the DDR3/L SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle
before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble
as shown in the following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM
stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e. tHZ is late), then DRAM
complies with tAONmax timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read
than shown in this example.
Fig. 50: ODT must be disabled externally during Reads by driving ODT low. (Example:
CL=6; AL=CL-1=5; RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8;
ODTLoff=CWL+AL-2=8)
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination
strength of the DDR3/L SDRAM can be changed without issuing an MRS command. This requirement is supported by the
“Dynamic ODT” feature as described as follows:
Functional Description
The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’. The function is described as follows:
Two RTT values are available: RTT_Nom and RTT_WR.
z The value for RTT_Nom is preselected via bits A[9,6,2] in MR1.
z The value for RTT_WR is preselected via bits A[10,9] in MR2.
During operation without write commands, the termination is controlled as follows:
z Nominal termination strength RTT_Nom is selected.
z Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
When a Write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the
termination is controlled as follows:
z A latency ODTLcnw after the write command, termination strength RTT_WR is selected.
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12 T13 T14 T15 T16
CMD
Address
RL = AL + CL
RTT_NOMRTT
ODTLoff = CWL + AL - 2
tAOFmax
tAOFmin
ODTLon = CWL + AL - 2
RTT_NOM
tAONmax
ODT
DRAM
ODT
DQSdiff
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
DQ
Read NOP NOP NOP NOP NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
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z A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF)
after the write command, termination strength RTT_Nom is selected.
z Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
The following table shows latencies and timing parameters which are relevant for the on-die termination control in Dynamic
ODT mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2[A10,A9
= [0,0], to disable Dynamic ODT externally.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with
ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write command. ODTH4 and
ODTH8 are measured from ODT registered high to ODT registered low or from the registration of Write command until ODT
is register low.
Table 22: Latencies and timing parameters relevant for Dynamic ODT
Name and
Description
Abbr. Defined from Defined to Definition for all DDR3/L
speed pin
Unit
ODT turn-on
Latency
ODTLon registering external
ODT signal high
turning
termination on
ODTLon=WL-2 tCK
ODT turn-off
Latency
ODTLoff registering external
ODT signal low
turning
termination off
ODTLoff=WL-2 tCK
ODT Latency for
changing from
RTT_Nom to
RTT_WR
ODTLcn
w
registering external
write command
change RTT
strength from
RTT_Nom to
RTT_WR
ODTLcnw=WL-2 tCK
ODT Latency for
change from
RTT_WR to
RTT_Nom (BL=4)
ODTLcwn4 registering external
write command
change RTT
strength from
RTT_WR to
RTT_Nom
ODTLcwn4=4+ODTLoff tCK
ODT Latency for
change from
RTT_WR to
RTT_Nom (BL=8)
ODTLcwn8 registering external
write command
change RTT
strength from
RTT_WR to
RTT_Nom
ODTLc
w
n8=6+ODTLoff tCK(avg)
Minimum ODT high
time
after ODT assertion
ODTH4 registering ODT high ODT registered
low
ODTH4=4 tCK(avg)
Minimum ODT high
time
after Write (BL=4)
ODTH4 registering write with
ODT high
ODT registered
low
ODTH4=4 tCK(avg)
Minimum ODT high
time
after Write (BL=8)
ODTH8 registering write with
ODT high
ODT register low ODTH8=6 tCK(avg)
RTT change ske
w
tADC ODTLcnw
ODTLcwn
RTT valid tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
tCK(avg)
Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)
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ODT Timing Diagrams
Fig. 51: Dynamic ODT: Behavior with ODT being asserted before and after the write
Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of the Write
command. In this example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command).
Fig. 52: Dynamic ODT: Behavior without write command, AL=0, CWL=5
Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5
would also be legal.
CK
CK
T11T10T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12 T13 T14 T15 T16
CMD
ODT
RTT
DQS/DQS
DQ
ODTLon
ODTLcwn4
T17
ODTLcnw
tAONmin
tAONmax
tADCm in
tADCm ax
WL
tADCm in
tADCmax
tAOFmin
tAOFmax
Address
RTT_WR
Din
nDin
n+1 Din
n+2 Din
n+3
ODTH4 ODTLoff
NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
ODTH4
RTT_Nom
Do not
care Transitioning
RTT_Nom
tADCmax
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
CMD
ODT
RTT
DQS/DQS
DQ
ODTLon
ODTLoff
tAONmin
tAONmax
tADCmin
RTT_Nom
Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
Address
ODTH4 ODTLoff
Do not
care Transitioning
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Fig. 53: Dynamic ODT: Behavior with ODT pin being asserted together with write
command for the duration of 6 clock cycles.
Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied.
tAOFmax
tAOFmin
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
CMD
ODT
RTT
DQS/DQS
DQ
ODTH8
ODTLon
ODTLcnw
tAONmin
tAONmax
ODTLoff
WL
RTT_WR
NOP WRS8 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
Din
hDin
h+1 Din
h+2 Din
h+3 Din
h+4 Din
h+5 Din
h+6 Din
h+7
ODTLcwn8
Do not
care Transitioning
Address
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Fig. 54:Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL=0,
CWL=5.
Fig. 55: Dynamic ODT: Behavior with ODT pin being asserted together with write
command for the duration of 4 clock cycles.
CK
CK#
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
ODT
RTT
DQS/DQS
DQ
ODTLon
RTT_WR
ODTLcnw
tA O N m in tA O Fm in
tA O Fm ax
tA O N m ax
ODTLoff
WL
ODTH4
ODTLcwn4
CMD NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
Address
Din
nDin
n+1 Din
n+2 Din
n+3
Do not
care Transitioning
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
ODT
RTT
DQS/DQS
DQ
ODTLon
RTT_WR RTT_Nom
ODTLcnw
tAONmin tADCm in
tAD Cmax
tAO Fmin
tAOFm ax
tAONmax
ODTLoff
WL
ODTH4
ODTLcwn4
CMD NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
Address
Din
nDin
n+1 Din
n+2 Din
n+3
Do not
care Transitioning
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Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in
precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge power
down mode if DLL is disabled during precharge power down by MR0 bit A12.
In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the
external ODT command.
In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max.
Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high impedance state
and ODT resistance begins to turn on. Maximum RTT turn on time (tAONPD max) is the point in time when the ODT
resistance is fully on.
tAONPDmin and tAONPDmax are measured from ODT being sampled high.
Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT
resistance. Maximum ODT turn off time (tAOFPDmax) is the point in time when the on-die termination has reached high
impedance. tAOFPDmin and tAOFPDmax are measured from ODT being sample low.
Fig. 56: Asynchronous ODT Timings on DDR3/L SDRAM with fast ODT transition: AL
is ignored.
In Precharge Power Down, ODT receiver remains active; however no Read or Write command can be issued, as the
respective ADD/CMD receivers may be disabled.
CK
CK#
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
ODT
RTT
tAONPDmin
CKE
tIH
tIS
T12 T13 T14 T15
tAONPDmax tAOFPDmin
tAOFPDmax
tIH
tIS
Do not
care Transitioning
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Table 23: Asynchronous ODT Timing Parameters for all Speed Bins
Symbol Description min max Unit
tAONPD Asynchronous RTT turn-on delay (Power-Down with DLL frozen) 2 8.5 ns
tAOFPD Asynchronous RTT turn-off delay (Power-Down with DLL frozen) 2 8.5 ns
Table 24: ODT timing parameters for Power Down (with DLL frozen) entry and exit
transition period
Description min max
ODT to RTT
turn-on delay
min{ ODTLon * tCK + tAONmin; tAONPDmin }
min{ (WL - 2) * tCK + tAONmin; tAONPDmin }
max{ ODTLon * tCK + tAONmax; tAONPDmax }
max{ (WL - 2) * tCK + tAONmax; tAONPFmax }
ODT to RTT
turn-off delay
min{ ODTLoff * tCK + tAOFmin; tAOFPDmin }
min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin }
max{ ODTLoff * tCK + tAOFmax; tAOFPDmax }
max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax }
tANPD WL-1
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Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is a transition
period around power down entry, where the DDR3/L SDRAM may show either synchronous or asynchronous ODT
behavior.
The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is counted
backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the clock cycle where
CKE is first registered low. The transition period begins with the starting point of tANPD and terminates at the end point of
tCPDED(min). If there is a Refresh command in progress while CKE goes low, then the transition period ends at the later
one of tRFC(min) after the Refresh command and the end point of tCPDED(min). Please note that the actual starting point
at tANPD is excluded from the transition period, and the actual end point at tCPDED(min) and tRFC(min, respectively, are
included in the transition period.
ODT assertion during the transition period may result in an RTT changes as early as the smaller of tAONPDmin and
(ODTLon*tck+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during
the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and
as late as the larger of tAOFPDmax and (ODTLoff*tCK+tAOFmax). Note that, if AL has a large value, the range where RTT
is uncertain becomes quite large. The following figure shows the three different cases: ODT_A, synchronous behavior
before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the transition
period.
Fig. 57: Synchronous to asynchronous transition during Precharge Power Down (with
DLL frozen) entry (AL=0; CWL=5; tANPD=WL-1=4)
CK
CK
CKE
CMD
L ast sync .
ODT
tA N PD
RTT
Sync. O r
async. O D T
ODTLoff tA O Fm ax
tA O F m in
tA O FPD m in
tA O FPD m ax
ODTLoff+tAOFPDmin
ODTLoff+tAOFPDmax
RTT
tA O FPD m in
First async.
ODT
RTT
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
PD entry transition period
Do not
care Time
Break
Transitioning
tC PD E D m in
tCP DED
NOP
R T T
R T T
RTT
tAOFPDmax
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Asynchronous to Synchronous ODT Mode transition during Power-Down Exit
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a
transition period around power down exit, where either synchronous or asynchronous response to a change in ODT must
be expected from the DDR3/L SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high.
tANPD is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODT-
Lon*tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the tran-
sition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as
the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has a large value, the range where RTT is uncertain
becomes quite large. The following figure shows the three different cases: ODT_C, asynchronous response before tANPD;
ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition
period with synchronous response.
Fig. 58: Asynchronous to synchronous transition during Precharge Power Down (with
DLL frozen) exit (CL=6; AL=CL-1; CWL=5; tANPD=WL-1=9)
CK
CK
ODT_C
_sync
DRAM
_RTT_
C_sync
ODT_B
_tran
tAOFPDmax
tAOFPDmin
DRAM
_RTT_
B_tran
ODT_A
_async
DRAM_
RTT_A_
async
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Td0
Do not
care Time
Break
Transitioning
Td1
CMD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
CKE
NOP
tXPDLL
PD exit transit ion period
RTT
RTT
tAOFPDmin
ODTLoff + tAOFmax
ODTLoff + tAOFmin
tAOFPDmax
tANPD
NOP
tAOFmax
RTT
ODTLoff
tAOFmin
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Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low
periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit
may overlap. In this case, the response of the DDR3/L SDRAMs RTT to a change in ODT state at the input may be
synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period
(even if the entry ends later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the
response of the DDR3/L SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from
the state of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is
assumed that there was no Refresh command in progress when Idle state was entered.
Fig. 59: Transition period for short CKE cycles with entry and exit period overlapping
(AL=0; WL=5; tANPD=WL-1=4)
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12 T13 T14
tANPD
Do not
care Transitioning
CKE
CMD REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
PD exit transition period
tANPD tXPDLL
PD entry transition period
tRFC(min)
CKE
Short CKE high transition period tXPDLL
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ZQ Calibration Commands
ZQ Calibration Description
ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3/L SDRAM needs longer time to calibrate
output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations.
ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be
issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine
inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM IO
which gets reflected as updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the
transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing
period of tZQoper.
ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing
window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS.
No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or
tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die termination values. Once DRAM
calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-refresh
exit, DDR3/L SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible
time for ZQ Calibration command (short or long) after self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or
tZQCS between ranks.
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Fig. 60: ZQ Calibration Timing
Note:
1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.
ZQ External Resistor Value, Tolerance, and Capacitive loading
In order to use the ZQ calibration function, a 240 ohm +/- 0.1% tolerance external resistor connected between the ZQ pin
and ground. The single resistor can be used for each SDRAM or one resistor can be shared between two SDRAMs if the
ZQ calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin must be limited.
CK
CK
Tc2
T0 T1 Ta1 Ta3 Tb0 Tb1 Tc1Ta0 Ta2 Tc0
Address
CMD ZQCL NOP NOP NOP Valid Valid ZQCS NOP NOP NOP Valid
ODT
tZQCS
Valid Valid
Valid Valid Valid
A10
CKE Valid Valid Valid
Valid Valid Valid
(1)
(2)
(1)
(2)
DQ Bus Hi-Z Activities Hi-Z Activities
tZQCS
(3) (3)
Do not
care Time
Break
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Absolute Maximum Ratings
Table 25: Absolute Maximum DC Ratings
Symbol Parameter Rating Units Note
VDD Voltage on VDD pin relative to Vss -0.4 ~ 1.975 V 1,3
VDDQ Voltage on VDDQ pin relative to Vss -0.4 ~ 1.975 V 1,3
Vin, Vout Voltage on any pin relative to Vss -0.4 ~ 1.975 V 1
Tstg Storage Temperature -55 ~ 100 °C 1,2
Note:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3. VDD and VDDQ must be within 300mV of each other at all times; and Vref must be not greater than 0.6VDDQ, when
VDD and VDDQ are less than 500mV; Vref may be equal to or less than 300mV.
Table 26: Temperature Range
Symbol Condition Parameter Value Units Notes
Toper
Commercial
Normal Operating Temperature Range 0 to 85 °C 1,2
Extended Temperature Range 85 to 95 °C 1,3
Industrial Operating Temperature Range -40 to 95 °C 1.4
Note:
1. Operating Temperature Toper is the case surface temperature on the center/top side of the DRAM.
2. The Normal Temperature Range specifies the temperatures where all DRAM specification will be supported.
During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85°C and 95°C case
temperature. Full specifications are guaranteed in this range, but the following additional apply.
a) Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us. It is also
possible to specify a component with 1x refresh (tREFI to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6=0 and MR2 A7=1) or enable the
optional Auto Self-Refresh mode (MR2 A6=1 and MR2 A7=0).
4. During Industrial Temperature Operation Range, the DRAM case temperature must be maintained between
-40°C~95°C under all operating Conditions.
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AC & DC Operating Conditions
Table 27: Recommended DC Operating Conditions
Symbol Parameter Rating Unit Note
Min. Typ. Max.
VDD Supply Voltage
DDR3 1.425 1.5 1.575
V
1,2
DDR3L 1.283 1.35 1.45 3,4,5,6
VDDQ Supply Voltage for Output
DDR3 1.425 1.5 1.575
V
1,2
DDR3L 1.283 1.35 1.45 3,4,5,6
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. Maximun DC value may not be great than 1.425V.The DC value is the linear average of VDD/ VDDQ(t) over a very long period of time
(e.g., 1 sec).
4. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
5. Under these supply voltages, the device operates to this DDR3/L specification.
6. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for
DDR3L operation.
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AC & DC Input Measurement Levels
Table 28: AC and DC Logic Input Levels for Single-Ended Signals & Command and
Address
Symbol Parameter
DDR3-1066/1333/1600 DDR3-1866/2133
Unit Note
Min. Max. Min. Max.
VIH.CA(DC100) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1,5
VIL.CA(DC100) DC input logic low VSS Vref - 0.100 VSS Vref - 0.100 V 1,6
VIH.CA(AC175) AC input logic high Vref + 0.175 Note2 - - V 1,2,7
VIL.CA(AC175) AC input logic low Note2 Vref - 0.175 - - V 1,2,8
VIH.CA(AC150) AC input logic high Vref + 0.150 Note2 - - V 1,2,7
VIL.CA(AC150) AC input logic low Note2 Vref - 0.150 - - V 1,2,8
VIH.CA(AC135) AC input logic high - - Vref + 0.135 Note2 V 1,2,7
VIL.CA(AC135) AC input logic low - - Note2 Vref - 0.135 V 1,2,8
VIH.CA(AC125) AC input logic high - - Vref + 0.125 Note2 V 1,2,7
VIL.CA(AC125) AC input logic low - - Note2 Vref - 0.125 V 1,2,8
VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4
DDR3L-1066/1333/1600
VIH.CA(DC90) DC input logic high Vref + 0.09 VDD V 1
VIL.CA(DC90) DC input logic low VSS Vref - 0.09 V 1
VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 V 1,2
VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 V 1,2
VIH.CA(AC135) AC input logic high Vref + 0.135 Note2 V 1,2
VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 V 1,2
VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3,4
Note:
NOTE 1. For input only pins except RESET.Vref=VrefCA(DC)
NOTE 2. See "Overshoot and Undershoot Specifications"
NOTE 3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 0.1% VDD.
NOTE 4. For reference: approx. VDD/2 +/- 15mv, DDR3L is VDD/2 +/-13.5mv.
NOTE 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
NOTE 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
NOTE 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and
VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is referenced, VIH.CA(AC150)
value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is
referenced, and VIH.CA(AC125) value is used when Vref + 0.125V is referenced.
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NOTE 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and
VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is referenced, VIL.CA(AC150)
value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is
referenced, and VIL.CA(AC125) value is used when Vref - 0.125V is referenced.
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Table 29: AC and DC Logic Input Levels for Single-Ended Signals & DQ and DM
Symbol Parameter
DDR3/L-1066 DDR3/L-1333/1600 DDR3-1866/2133
Unit Note
Min. Max. Min. Max. Min. Max.
VIH.DQ(DC100) DC input logic high
Vref +
0.100
VDD
Vref +
0.100
VDD
Vref +
0.100
VDD V1,5
VIL.DQ(DC100) DC input logic low VSS
Vref -
0.100
VSS
Vref –
0.100
VSS
Vref -
0.100
V1,6
VIH.DQ(AC175) AC input logic high
Vref +
0.175
Note2
Vref +
0.150
Note2 - -
V 1,2,7,9
VIL.DQ(AC175) AC input logic low Note2
Vref -
0.175
Note2
Vref –
0.150
- -
V 1,2,8,9
VIH.DQ(AC150) AC input logic high
Vref +
0.150
Note2
Vref +
0.150
Note2 - -
V 1,2,7,9
VIL.DQ(AC150) AC input logic low Note2
Vref -
0.150
Note2
Vref –
0.150
- -
V 1,2,8,9
VIH.DQ(AC135) AC input logic high - - - -
Vref +
0.135
Note2 mV 1,2,7
VIL.DQ(AC135) AC input logic low - - - - Note2
Vref -
0.135
mV 1,2,8
VREFDQ(DC)
Reference Voltage for DQ,
DM inputs
0.49 *
VDD
0.51 *
VDD
0.49 *
VDD
0.51 *
VDD
0.49 *
VDD
0.51 *
VDD
V3,4
DDR3L-1066 DDR3L-1333/1600
VIH.CA(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD V 1
VIL.CA(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 V 1
VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 - - V 1,2,5
VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 - - V 1,2,5
VIH.CA(AC135) AC input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 V 1,2,5
VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1,2,5
VREFCA(DC)
Reference Voltage for
ADD, CMD inputs
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4
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Note:
NOTE 1. For input only pins except RESET.Vref=VrefCA(DC)
NOTE 2. See "Overshoot and Undershoot Specifications"
NOTE 3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 0.1% VDD.
NOTE 4. For reference: approx. VDD/2 +/- 15mv, DDR3L is VDD/2 +/-13.5mv.
NOTE 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
NOTE 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
NOTE 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and
VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is referenced, VIH.CA(AC150)
value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is
referenced, and VIH.CA(AC125) value is used when Vref + 0.125V is referenced.
NOTE 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and
VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is referenced, VIL.CA(AC150)
value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is
referenced, and VIL.CA(AC125) value is used when Vref - 0.125V is referenced.
NOTE 9. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5V, the respective levels in
JESD79-3.(VIH/L.CA(DC100),VIH/L.CA (AC175), VIH/L.CA (AC150), etc.) apply. The 1.5V levels (VIH/L.CA (DC100), VIH/L.CA (AC175),
VIH/L.CA (AC150), etc.) do not apply when the device is operated in the 1.35Voltage range.
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Vref Tolerances
The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following figure. It
shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise).
Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max
requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD.
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on Vref.
“Vref” shall be understood as Vref(DC).
The clarifies that dc-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level
and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for
Vref(DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage associated
with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD) are included in
DRAM timing and their associated de-ratings.
Fig. 61: Illustration of Vref(DC) tolerance and Vrefac-noise limits
Vref(DC) Vref(DC)max
Vref(DC)min
VDD/2
V ref ac-noise
Voltage
time
VDD
VSS
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Table 30: AC and DC Logic Input Levels for Differential Signals
Symbol Parameter DDR3/L-1066, 1333,1600 Unit Notes
Min. Max.
VIHdiff Differential input logic high +0.200 Note3 V 1
VILdiff Differential input logic low Note3 -0.200 V 1
VIHdiff(ac) Differential input high ac 2 x ( VIH(ac) – Vref ) Note3 V 2
VILdiff(ac) Differential input low ac Note3 2 x ( Vref - VIL(ac) ) V 2
Note:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL(ac)
of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also
there.
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need
to be within the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot
and undershoot.
Fig. 62: Definition of differential ac-swing and “time above ac-level”
Time
Differential Input Voltage (i.e. DQS – DQS, CK – CK)
tDVAC
tDVAC
Half cycle
VIH.Diff.AC.min
VIH.Diff. DC min
VIL.Diff.AC.max
0
VIL. Diff. DC max
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Table 31: Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns]
tDVAC [ps]
@IVIH/Ldiff(ac)I = 350mV
tDVAC [ps]
@IVIH/Ldiff(ac)I = 300mV
min max min max
> 4.0 75 - 175 -
4.0 57 - 170 -
3.0 50 - 167 -
2.0 38 - 163 -
1.8 34 - 162 -
1.6 29 - 161 -
1.4 22 - 159 -
1.2 13 - 155 -
1.0 0 - 150 -
< 1.0 0 - 150 -
1.35V
Slew Rate [V/ns]
tDVAC [ps]
@IVIH/Ldiff(ac)I = 320mV
tDVAC [ps]
@IVIH/Ldiff(ac)I = 270mV
Min. Max. Min. Max.
> 4.0 TBD - TBD-
4.0 TBD- TBD-
3.0 TBD- TBD-
2.0 TBD- TBD-
1.8 TBD- TBD-
1.6 TBD- TBD-
1.4 TBD- TBD-
1.2 TBD- TBD-
1.0 TBD- TBD-
< 1.0 TBD- TBD-
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Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply
with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH(ac) / VIL(ac)) for
ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approxi-
mately the ac-levels (VIH(ac) / VIL(ac)) for DQ signals) in every half-cycle proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH150(ac)/VIL150(ac) is used for ADD/CMD signals, then these ac-levels apply also for the singleended
signals CK and CK.
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Table 32: Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU
Symbol Parameter
DDR3/L-1066, 1333 & 1600
Unit Notes
Min Max
VSEH
Single-ended high-level for strobes (VDDQ/2) + 0.175 note3 V 1, 2
Single-ended high-level for CK, CK (VDDQ/2) + 0.175 note3 V 1, 2
VSEL
Single-ended low-level for strobes note3 (VDDQ/2) - 0.175 V 1, 2
Single-ended Low-level for CK, CK note3 (VDDQ/2) - 0.175 V 1, 2
Note:
1. For CK, CK use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) use VIH/VIL(ac)
of DQs.
2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high
or ac-low level is used for a signal group, then the reduced level applies also there.
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need
to be within the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and
undershoot.
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross
point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in the following table. The
differential input cross point voltage Vix is measured from the actual cross point of true and complete signal to the midlevel
between of VDD and VSS.
Fig. 63: Vix Definition
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Table 33: Cross point voltage for differential input signals (CK, DQS)
Symbol Parameter
DDR3/L-1066/1333/1600/1866/2133
Unit Note
Min. Max.
Vix
Differential Input Cross Point Voltage relative to VDD/2 for CK,
CK#
-150 150 mV
-175 175 mV 1
Differential Input Cross Point Voltage relative to VDD/2 for DQS,
DQS#
-150 150 mV
Note 1: Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and CK are monotonic
with a single-ended swing VSEL / VSEH of at least VDD/2 ± 250mV, and when the differential slew rate of CK - CK is
larger than 3V/ns.
Slew Rate Definition for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown below.
Table 34: Differential Input Slew Rate Definition
Description
Measured
Defined by
From To
Differential input slew rate for rising edge (CK-CK &
DQS-DQS)
VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge (CK-CK &
DQS-DQS)
VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
The differential signal (i.e., CK-CK & DQS-DQS) must be linear between these thresholds.
Fig. 64: Input Nominal Slew Rate Definition for single ended signals
Delta
TFdiff
Delta
TRdiff
VIHdiffMin
VILdiffMax
0
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AC and DC Output Measurement Levels
Table 35: Single Ended AC and DC Output Levels
Symbol Parameter Value Unit Notes
VOH(DC) DC output high measurement level (for IV curve linearity) 0.8xVDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5xVDDQ V
VOL(DC) DC output low measurement level (fro IV curve linearity) 0.2xVDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT+0.1xVDDQ V 1
VOL(AC) AC output low measurement level (for output SR) VTT-0.1xVDDQ V 1
Note:
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a
driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.
Table 36: Differential AC and DC Output Levels
Symbol Parameter DDR3/L Unit Notes
VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x VDDQ V 1
VOLdiff(AC) AC differential output low measurement level (for output SR) -0.2 x VDDQ V 1
Note:
1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver
impedance of 40 Ω and an effective test load of 25 Ω to VTT=VDDQ/2 at each of the differential outputs.
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Delta TFse
Delta TFse
VOH (AC)
VOL (AC)
VTT
Single Ended Output Voltage (i.e. DQ)
Table 37: Single Ended Output Slew Rate
Description Measured Defined by
From To
Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse
Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Fig. 65: Single Ended Output Slew Rate Definition
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Table 38: Output Slew Rate (single-ended)
Parameter Symbol
Operation
Voltage
DDR3/L-1066 DDR3/L-1333 DDR3/L-1600 DDR3-1866 DDR3-2133
Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Single-ended Output Slew
Rate
SRQse
1.35V 1.75 5 1.75 5 1.75 5 TBD TBD TBD TBD
V/ns
1.5V 2.5 5 2.5 5 TBD 5 2.5 5(1) 2.5 5(1)
Note:
SR: Slew Rate.
Q: Query Output (like in DQ, which stands for Data-in, Query -Output).
se: Single-ended signals.
For Ron = RZQ/7 setting.
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low
or low to high)
while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low
or low to high)
while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to
low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns
applies.
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Table 39: Differential Output Slew Rate
Description Measured Defined by
From To
Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTRdiff
Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Fig. 66: Differential Output Slew Rate Definition
Table 40: Differential Output Slew Rate
Parameter Symbol
Operation
Voltag
DDR3/L-1066 DDR3/L-1333 DDR3/L-1600 DDR3-1866 DDR3-2133
Unit
Min. Max. Min. Max. Mix. Max. Min. Max. Min. Max.
Single-ended Output
Slew Rate
SRQse
1.35V 3.5 12 3.5 12 3.5 12 TBD TBD TBD TBD
V/ns
1.5V 5 10 5 10 TBD 10 5 12 5 12
Note:
SR: Slew Rate.
Q: Query Output (like in DQ, which stands for Data-in, Query -Output).
diff: Differential signals.
For Ron = RZQ/7 setting.
Delta TFse
Delta TFse
VOh d iff (AC )
VO L d iff (A C )
0
Differential Output Voltage (i.e. DQS-DQS)
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Reference Load for AC Timing and Output Slew Rate
The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters
of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load
presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more
coaxial transmission lines terminated at the tester electronics.
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Overshoot and Undershoot Specifications
Table 41: AC Overshoot/Undershoot Specification for Address and Control Pins
Item DDR3/L-1066 DDR3/L-1333 DDR3/L-1600 DDR3-1866 DDR3-2133 Units
1.35V
Maximum peak amplitude allowed for
overshoot area
TBDTBDTBDTBDTBD
V
Maximum peak amplitude allowed for
undershoot area
TBDTBDTBDTBDTBD
V
Maximum overshoot area above VDD TBDTBDTBDTBDTBDV-ns
Maximum undershoot area below VSS TBDTBDTBDTBDTBDV-ns
1.5V
Maximum peak amplitude allowed for
overshoot area
0.4 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for
undershoot area
0.4 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD 0.5 0.4 0.33 0.28 0.25 V-ns
Maximum undershoot area below VSS 0.5 0.4 0.33 0.28 0.25 V-ns
(A0-A13, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
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Table 42: AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask
Item DDR3/L-1066 DDR3/L-1333 DDR3/L-1600 DDR3-1866 DDR3-2133 Units
1.35V
Maximum peak amplitude allowed for
overshoot area
TBDTBDTBDTBDTBD
V
Maximum peak amplitude allowed for
undershoot area
TBDTBDTBDTBDTBD
V
Maximum overshoot area above VDD TBDTBDTBDTBDTBDV-ns
Maximum undershoot area below VSS TBDTBDTBDTBDTBDV-ns
1.5V
Maximum peak amplitude allowed for
overshoot area
0.4 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for
undershoot area
0.4 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD 0.19 0.15 0.13 0.11 0.10 V-ns
Maximum undershoot area below VSS 0.19 0.15 0.13 0.11 0.10 V-ns
(CK, CK, DQ, DQS, DQS, DM)
Volts (V)
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34 Ohm Output Driver DC Electrical Characteristics
A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value of
the external reference resistor RZQ as follows:
RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms)
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu = [VDDQ-Vout] / l Iout l ------------------- under the condition that RONPd is turned off (1)
RONPd = Vout / I Iout I -------------------------------under the condition that RONPu is turned off (2)
Fig. 67: Output Driver: Definition of Voltages and Currents
To
other
circuitry
like
RCV, ...
RON
RON
Pu
Pd
I
Pu
I
Pd
VDDQ
VSSQ
DQ
I
Out
V
Out
Output Driver
Chip in Drive Mode
Table 43: Output Driver DC Electrical Characteristics, assuming RZQ = 240ohms; entire
operating temperature range; after proper ZQ calibration
RONNom Resistor Vout Min. Nom. Max. Unit Notes
1.35V
34 ohms
RON34Pd
VOLdc = 0.2 x VDDQ 0.6 1.0 1.15 RZQ / 7 1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 RZQ / 7 1,2,3
VOHdc = 0.8 x VDDQ 0.9 1.0 1.45 RZQ / 7 1,2,3
RON34Pu
VOLdc = 0.2 x VDDQ 0.9 1.0 1.45 RZQ / 7 1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 RZQ / 7 1,2,3
VOHdc = 0.8 x VDDQ 0.6 1.0 1.15 RZQ / 7 1,2,3
40 ohms
RON40pd
VOLdc = 0.2 × VDDQ 0.6 1.0 1.15 RZQ / 6 1,2,3
VOMdc = 0.5 × VDDQ 0.9 1.0 1.15 RZQ / 6 1,2,3
VOHdc = 0.8 × VDDQ 0.9 1.0 1.45 RZQ / 6 1,2,3
RON40pu
VOLdc = 0.2 × VDDQ 0.9 1.0 1.45 RZQ / 6 1,2,3
VOMdc = 0.5 × VDDQ 0.9 1.0 1.15 RZQ / 6 1,2,3
VOHdc = 0.8 × VDDQ 0.6 1.0 1.15 RZQ / 6 1,2,3
Mismatch between pull-up and pull-down, MMPuPd V
OMdc = 0.5 x VDDQ -10 +10 % 1,2,4
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1.5V
34 ohms
RON34Pd
VOLdc = 0.2 x VDDQ 0.6 1.0 1.1 RZQ / 7 1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 RZQ / 7 1,2,3
VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 RZQ / 7 1,2,3
RON34Pu
VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 RZQ / 7 1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 RZQ / 7 1,2,3
VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 RZQ / 7 1,2,3
40 ohms
RON40pd
VOLdc = 0.2 × VDDQ 0.6 1.0 1.1 RZQ / 6 1,2,3
VOMdc = 0.5 × VDDQ 0.9 1.0 1.1 RZQ / 6 1,2,3
VOHdc = 0.8 × VDDQ 0.9 1.0 1.4 RZQ / 6 1,2,3
RON40pu
VOLdc = 0.2 × VDDQ 0.9 1.0 1.4 RZQ / 6 1,2,3
VOMdc = 0.5 × VDDQ 0.9 1.0 1.1 RZQ / 6 1,2,3
VOHdc = 0.8 × VDDQ 0.6 1.0 1.1 RZQ / 6 1,2,3
Mismatch between pull-up and pull-down, MMPuPd V
OMdc = 0.5 x VDDQ -10 +10 % 1,2,4
Note:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration
schemes may be used to achieve the linearity spec shown above. e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ.
4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd:
Measure RONPu and RONPd, but at 0.5 x VDDQ:
MMPuPd = [RONPu - RONPd] / RONNom x 100
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Output Driver Temperature and Voltage sensitivity
If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.
Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ
Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
Table 44: Output Driver Sensitivity Definition
Items Min. Max. Unit
RONPU@VOHdc 0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl 1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl RZQ/7
RON@VOMdc 0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl 1.1 + dRONdTM*lDelta Tl - dRONdVM*lDelta Vl RZQ/7
RONPD@VOLdc 0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl 1.1 + dRONdTL*lDelta Tl - dRONdVL*lDelta Vl RZQ/7
Table 45: Output Driver Voltage and Temperature Sensitivity
Speed Bin DDR3-1066/1333 DDR3-1600
Unit
Items Min. Max Min. Max
dRONdTM 0 1.5 0 1.5
%/°C
dRONdVM 0 0.15 0 0.13 %/mV
dRONdTL 0 1.5 0 1.5
%/°C
dRONdVL 0 0.15 0 0.13 %/mV
dRONdTH 0 1.5 0 1.5
%/°C
dRONdVH 0 0.15 0 0.13 %/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
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On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register.
ODT is applied to the DQ, DM, DQS/DQS, and TDQS/TDQS (x8 devices only) pins.
A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down
resistors (RTTPu and RTTPd) are defined as follows:
RTTPu = [VDDQ - Vout] / I Iout I ------------------ under the condition that RTTPd is turned off (3)
RTTPd = Vout / I Iout I ------------------------------ under the condition that RTTPu is turned off (4)
Fig. 68: On-Die Termination: Definition of Voltages and Currents
ODT DC Electrical Characteristics
The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120,
RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification
requirements, but can be used as design guide lines:
To other
circuitry
lik e
RCV, ...
RTT
RTT
Pu
Pd
IPu
IPd
VDDQ
VSSQ
DQ
IOut
VOut
ODT
Chip in T ermination M ode
I = I - I
Out Pd Pu
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Table 46: ODT DC Electrical Characteristics, assuming RZQ = 240ohms +/- 1% entire
operating temperature range; after proper ZQ calibration
MR1 A9,A6,A2 RTT Resistor Vout Min. Nom. Max. Unit Notes
1.35V
0,1,0 120Ω
RTT120Pd240
VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ 1,2,3,4
RTT120Pu240
VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ 1,2,3,4
RTT120 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ /2 1,2,5
0, 0, 1 60Ω
RTT60Pd120
VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/2 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ/2 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/2 1,2,3,4
RTT60Pu120
VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/2 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ/2 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/2 1,2,3,4
RTT60 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/4 1,2,5
0, 1, 1 40Ω
RTT40Pd80
VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/3 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ/3 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/3 1,2,3,4
RTT40Pu80
VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/3 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ/3 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/3 1,2,3,4
RTT40 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/6 1,2,5
1, 0, 1 30Ω
RTT30Pd60
VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/4 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ/4 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/4 1,2,3,4
RTT30Pu60
VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/4 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ/4 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/4 1,2,3,4
RTT30 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/8 1,2,5
1, 0, 0 20Ω
RTT20Pd40
VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/6 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ/6 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/6 1,2,3,4
RTT20Pu40
VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/6 1,2,3,4
0.5 x VDDQ 0.9 1 1.15 RZQ/6 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/6 1,2,3,4
RTT20 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/12 1,2,5
Deviation of VM w.r.t. VDDQ/2, DVM -5 +5 % 1,2,5,6
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MR1 A9,A6,A2 RTT Resistor Vout Min. Nom. Max. Unit Notes
1.5V
0,1,0 120Ω
RTT120Pd240
VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4
RTT120Pu240
VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4
0.5 x VDDQ 0.9 1 1,1 RZQ 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4
RTT120 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ /2 1,2,5
0, 0, 1 60Ω
RTT60Pd120
VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4
RTT60Pu120
VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4
RTT60 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/4 1,2,5
0, 1, 1 40Ω
RTT40Pd80
VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4
RTT40Pu80
VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4
RTT40 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/6 1,2,5
1, 0, 1 30Ω
RTT30Pd60
VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4
RTT30Pu60
VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4
RTT30 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/8 1,2,5
1, 0, 0 20Ω
RTT20Pd40
VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4
VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4
RTT20Pu40
VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4
0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4
VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4
RTT20 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/12 1,2,5
Deviation of VM w.r.t. VDDQ/2, DVM -5 +5 % 1,2,5,6
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Note:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration may be used to
achieve the linearity spec shown above.
4. Not a specification requirement, but a design guide line.
5. Measurement definition for RTT:
Apply VIH(ac) to pin under test and measure current / (VIH(ac)), then apply VIL(ac) to pin under test and measure current
/ (VIL(ac)) respectively.
RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))]
6. Measurement definition for VM and DVM:
Measure voltage (VM) at test pin (midpoint) with no lead:
Delta VM = [2VM / VDDQ -1] x 100
ODT Temperature and Voltage sensitivity
If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.
Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ
Table 47: ODT Sensitivity Definition
Min. Max. Unit
RTT 0.9 - dRTTdT*lDelta Tl - dRTTdV*lDelta Vl 1.6 + dRTTdT*lDelta Tl + dRTTdV*lDelta Vl RZQ/2,4,6,8,12
Table 48: ODT Voltage and Temperature Sensitivity
Min. Max. Unit
dRTTdT 0 1.5 %/°C
dRTTdV 0 0.15 %/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in the following figure.
Fig. 69: ODT Timing Reference Load
Vtt =
25 Ohm
CK ,
VDDQ
DUT
Timing Reference Points
VSSQ
RTT=
DQ , DM
DQS ,
TDQS ,
VSSQ
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Table 49: ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures.
Symbol Begin Point Definition End Point Definition
tAON Rising edge of CK - CK defined by the end point of ODTLon Extrapolated point at VSSQ
tAONPD Rising edge of CK - CK with ODT being first registered high Extrapolated point at VSSQ
tAOF Rising edge of CK - CK defined by the end point of ODTLoff End point: Extrapolated point at VRTT_Nom
tAOFPD Rising edge of CK - CK with ODT being first registered low End point: Extrapolated point at VRTT_Nom
tADC
Rising edge of CK - CK defined by the end point of ODTLcnw,
ODTLcwn4, or ODTLcwn8
End point: Extrapolated point at VRTT_Wr and
VRTT_Nom respectively
Table 50: Reference Settings for ODT Timing Measurements
Measured ParameterRTT_Nom Setting RTT_Wr Setting VSW1[V] VSW2[V] Note
tAON
RZQ/4 NA 0.05 0.10
RZQ/12 NA 0.10 0.20
tAONPD
RZQ/4 NA 0.05 0.10
RZQ/12 NA 0.10 0.20
tAOF
RZQ/4 NA 0.05 0.10
RZQ/12 NA 0.10 0.20
tAOFPD
RZQ/4 NA 0.05 0.10
RZQ/12 NA 0.10 0.20
tADC RZQ/12 RZQ/2 0.20 0.30
Fig. 70: Definition of tAON
tA O N
Tsw2
Tsw1
Vsw1
Vsw2
VSSQ
VTT
DQ, DM
DQS, DQS#
TDQS, TD Q S#
End point: Extrapolated point at VSSQ
CK
CK#
Begin point: R ising edge of C K – C K#
D efined by the end point of O D TLon
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Fig. 71: Definition of tAONPD
Fig. 72: Definition of tAOF
Fig. 73: Definition of tAOFPD
tA O N P D
Tsw2
Tsw1
Vsw1
Vsw2
VSSQ
VTT
DQ, DM
DQS, DQS#
TDQ S, TDQS#
End point: Extrapolated point at VSSQ
CK
CK#
Begin point: Rising edge of CK – CK#
with O DT being first register high
tA O F
Tsw2
Tsw1
Vsw1
Vsw2
VSSQ
VTT
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point: Extrapolated point at VRTT_N om
CK
CK#
Begin point: Rising edge of CK – CK#
defined by the end point of O DTLoff
VRTT_Nom
tA O F P D
Tsw2
Tsw1
Vsw1
Vsw2
VSSQ
VTT
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point: Extrapolated point at VRTT_Nom
CK
CK#
Begin point: Rising edge of CK – CK#
with ODT being first registered low
VRTT_Nom
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Fig. 74: Definition of tADC
Table 51: Input / Output Capacitance
Symbol Parameter
DDR3/L-1066 DDR3/L-1333 DDR3/L-1600 DDR3-1866 DDR3-2133
Units Notes
Min. Max Min. Max Min. Max Min. Max. Min. Max.
CIO
Input/output capacitance (DQ, DM,
DQS, DQS, TDQS, TDQS)
1.50 3.00 1.50 2.50 1.50 2.30 1.40 2.20 1.40 2.10 pF 1,2,3
CCK Input capacitance, CK and CK 0.80 1.60 0.80 1.40 0.80 1.40 0.80 1.30 0.80 1.30 pF 2,3
CDCK Input capacitance delta, CK and CK 0.00 0.15 0.00 0.15 0.00 0.15 0.00 0.15 0.00 0.15 pF 2,3,4
CDDQS
Input/output capacitance delta, DQS
and DQS
0.00 0.20 0.00 0.15 0.00 0.15 0.00 0.15 0.00 0.15 pF 2,3,5
CI
Input capacitance, CTRL, ADD, CMD
input-only pins
0.75 1.35 0.75 1.30 0.75 1.30 0.75 1.20 0.75 1.20 pF 2,3,7,8
CDI_CTRL
Input capacitance delta, all CTRL
input-only pins
-0.50 0.30 -0.40 0.20 -0.40 0.20 -0.40 0.20 -0.40 0.20 pF 2,3,7,8
CDI_ADD_CMD
Input capacitance delta, all ADD/CMD
input-only pins
-0.50 0.50 -0.40 0.40 -0.40 0.40 -0.40 0.40 -0.40 0.40 pF 2,3,9,10
CDIO
Input/output capacitance delta, DQ,
DM, DQS, DQS, TDQS,
-0.50 0.30 -0.50 0.30 -0.50 0.30 -0.50 0.30 -0.50 0.30 pF 2,3,11
CZQ Input/output capacitance of ZQ pin - 3.00 - 3.00 - 3.00 - 3.00 - 3.00 pF 2,3,12
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.5V, VBIAS=VDD/2 and
on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
tADC
Tsw21
Tsw11
Vsw1
Vsw2
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point: Extrapolated point at VRTT_Nom
CK
CK#
Begin point: Rising edge of CK – CK#
defined by the end of ODTLcnw
VRTT_Nom
tADC
Tsw22
Tsw12
VSSQ
VTT
End point: Extrapolated point at VRTT_Wr
CK
CK#
Begin point: Rising edge of CK – CK# defined
by the end of ODTLcwn4 or ODTLcwn8
VRTT_Wr
VRTT_Nom
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4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A13, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A13, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5 pF.
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IDD Specifications and Measurement Conditions
Table 52: IDD Specifications (x8)
Symbol Parameter/Condition
Operation
Voltage
DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max.
IDD0 Operating Current 0
-> One Bank Activate-> Precharge
1.5V 50 56 53 59 58 65 66 68 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD1
Operating Current 1
-> One Bank Activate-> Read->
Precharge
1.5V 67 74 71 79 76 83 83 86 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD2P0 Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
1.5V 5 9 5 9 5 9 5 9 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD2P1 Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
1.5V 16 20 18 22 20 25 28 29 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD2Q Precharge Quiet Standby Current
1.5V 25 31 28 35 31 39 40 41 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD2N Precharge Standby Current
1.5V 26 32 30 35 33 39 42 43 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD3P Active Power-Down Current
Always Fast Exit
1.5V 16 21 19 23 21 26 28 29 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD3N Active Standby Current
1.5V 29 35 32 38 35 41 44 46 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD4R Operating Current Burst Read
1.5V 97 106 113 122 129 139 154 159 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD4W Operating Current Burst Write
1.5V 94 104 109 119 123 134 147 150 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD5B Burst Refresh Current
1.5V 47 52 50 55 53 59 64 65 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD6 Self-Refresh Current Normal
Temperature Range (0-85°C)
1.5V 3 7 3 7 3 7 3 7 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD6ET Self-Refresh Current: extended
temperature range
1.5V 4 8 4 8 4 8 4 8 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD6TC Auto Self-Refresh Current
1.5V 4 8 4 8 4 8 4 8 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
IDD7 All Bank Interleave Read Current
1.5V 169 184 203 220 209 227 364 375 TBD TBD
mA
1.35V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
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IDD Specifications and Measurement Conditions
Table 53: IDD Specifications (x16)
Symbol Parameter/Condition
Operation
Voltage
DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max.
IDD0 Operating Current 0
-> One Bank Activate-> Precharge
1.5V 63 76 66 80 73 87 79 87 TBD TBD
mA
1.35V 59 69 65 76 69 81 TBD TBD TBD TBD
IDD1
Operating Current 1
-> One Bank Activate-> Read->
Precharge
1.5V 87 106 92 112 98 119 105 120 TBD TBD
mA
1.35V 79 93 85 100 90 106 TBD TBD TBD TBD
IDD2P0 Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
1.5V 5 12 5 13 5 14 5 14 TBD TBD
mA
1.35V 3.4 8 3.4 10 3.4 12 TBD TBD TBD TBD
IDD2P1 Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
1.5V 16 21 18 23 20 26 28 31 TBD TBD
mA
1.35V 16 21 18 23 20 26 TBD TBD TBD TBD
IDD2Q Precharge Quiet Standby Current
1.5V 26 31 29 34 31 38 40 44 TBD TBD
mA
1.35V 25 31 29 34 31 38 TBD TBD TBD TBD
IDD2N Precharge Standby Current
1.5V 27 33 30 35 33 39 42 46 TBD TBD
mA
1.35V 26 33 30 35 33 39 TBD TBD TBD TBD
IDD3P Active Power-Down Current
Always Fast Exit
1.5V 17 25 20 27 22 30 29 32 TBD TBD
mA
1.35V 17 25 20 27 22 30 TBD TBD TBD TBD
IDD3N Active Standby Current
1.5V 29 38 33 41 35 45 44 48 TBD TBD
mA
1.35V 28 38 32 40 35 45 TBD TBD TBD TBD
IDD4R Operating Current Burst Read
1.5V 132 165 157 195 180 224 194 230 TBD TBD
mA
1.35V 111 133 132 158 152 182 TBD TBD TBD TBD
IDD4W Operating Current Burst Write
1.5V 130 162 152 189 174 216 206 218 TBD TBD
mA
1.35V 119 129 141 154 161 176 TBD TBD TBD TBD
IDD5B Burst Refresh Current
1.5V 48 56 51 59 54 62 66 71 TBD TBD
mA
1.35V 45 51 49 56 52 60 TBD TBD TBD TBD
IDD6 Self-Refresh Current Normal
Temperature Range (0-85°C)
1.5V 4 7 4 7 4 7 4 7 TBD TBD
mA
1.35V 2 7 2 7 2 7 TBD TBD TBD TBD
IDD6ET Self-Refresh Current: extended
temperature range
1.5V 4 8 4 8 4 8 4 8 TBD TBD
mA
1.35V 2 8 2 8 2 8 TBD TBD TBD TBD
IDD6TC Auto Self-Refresh Current
1.5V 4 8 4 8 4 8 4 8 TBD TBD
mA
1.35V 2 8 2 8 2 8 TBD TBD TBD TBD
IDD7 All Bank Interleave Read Current
1.5V 212 266 236 297 264 332 364 403 TBD TBD
mA
1.35V 191 230 222 267 248 298 TBD TBD TBD TBD
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Table 54: IDD Measurement Conditions
Symbol Parameter/Condition
IDD0
Operating Current - One bank Active - Precharge current
CKE: High; External clock: On; tCK, tRC, tRAS: see table in the next page; CS: High between ACT and PRE;
Command Inputs: SWITCHING1 (except for ACT and PRE); Row, Column Address, Data I/O: SWITCHING1
(A10 Low permanently); Bank Address: fixed (Bank 0); Output Buffer: off 2; ODT: disabled 3; Active Banks: one
(ACT-PRE loop); Idle Banks: all other; Pattern example: A0 D DD DD DD DD DD DD D P0.4
IDD1
Operating One bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, tRC, tRAS, tRCD, CL, AL: see table in the next page; CS: High between
ACT, RD, and PRE; Command Inputs: SWITCHING1 (except ACT, RD, and PRE Commands); Row, Column
Address: SWITCHING1 (A10 Low permanently); Bank Address: fixed (Bank 0); Data I/O: switching every clock
(RD Data stable during one Clock cycle); floating when no burst activity; Output Buffer: Off2; ODT: disabled 3;
Burst Length: BL85; Active Banks: one (ACT-RD-PRE loop); Idle Banks: all other; Pattern example: A0 D DD D
R0 DD DD DD DD D P04.
IDD2N
Precharge Standby Current
CKE=High; External Clock=On; tCK: see table in the next page; CS: High; Command Inputs, Row, Column,
Bank Address, Data I/O: SWITCHING1; Output Buffer: Off2; ODT: disabled 3; Active / Idle Banks: none / all.
IDD2P(0)
Precharge Powe
r
-Down Current - (Slow Exit)
CKE=Low; External Clock=On; tCK: see table in the next page; CS: Stable; Command Inputs: Stable; Row,
Column / Bank Address: Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled 3; Active / Idle Banks:
none / all. Precharge Power Down Mode: Slow Exit 6(RD and ODT must satisfy tXPDLL - AL)
IDD2P(1)
Precharge Powe
r
-Down Current - (Fast Exit)
CKE=Low; External Clock=On; tCK: see table in the next page; CS: Stable; Command Inputs, Row, Column,
Bank Address: Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled 3; Active / Idle Banks: none / all.
Precharge Power Down Mode: Fast Exit 6(any valid Command after tXP)7
IDD2Q
Precharge Quiet Standby Current
CKE=High; External Clock=On; tCK: see table in the next page; CS=High; Command Inputs, Row, Column,
Bank Address: Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled 3; Active / Idle Banks: none / all.
IDD3N
Active Standby Current
CKE=High; External Clock=On; tCK: see table in the next page; CS=High; Command Inputs, Row, Column,
Bank Address, Data I/O: SWITCHING1; Output Buffer: Off2; ODT: disabled 3; Active / Idle Banks: All / none.
IDD3P
Active Powe
r
-Down Current
CKE=Low; External Clock=On; tCK: see table in the next page; CS, Command Inputs, Row, Column, Bank
Address: Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled 3; Active / Idle Banks: All / none.
IDD4R
Operating Burst Read Current
CKE=High; External Clock=On; tCK, CL: see table in the next page; AL: 0; CS: High between valid Commands;
Command Inputs: SWITCHING1(except RD Commands); Row, Column Address: SWITCHING1(A10: Low
permanently); Bank Address: cycling10; Data I/O: Seamless Read Data Burst : Output Data switches every
clock cycle (i.e. data stable during one clock cycle); Output Buffer: Off2; ODT: disabled 3; Burst Length: BL85;
Active / Idle Banks: All / none10; Pattern: R0 D DD R1 D DD R2 D DD R3 D DD R44
IDD4W
Operating Burst Write Current
CKE=High; External Clock=On; tCK, CL: see table in the next page; AL: 0; CS: High between valid Commands;
Command Inputs: SWITCHING1(except WR Commands); Row, Column Address: SWITCHING1(A10: Low
permanently); Bank Address: cycling10; Data I/O: Seamless Write Data Burst : Input Data switches every clock
cycle (i.e. data stable during one clock cycle); DM: L permanently; Output Buffer: Off2; ODT: disabled 3; Burst
Length: BL85; Active / Idle Banks: All / none10; Pattern: W0 D DD W1 D DD W2 D DD W3 D DD W44
IDD5B
Burst Refresh Current
CKE=High; External Clock=On; tCK, tRFC: see table in the next page; CS: High between valid Commands;
Command Inputs, Row, Column, Bank Addresses, Data I/O: SWITCHING1; Output Buffer: Off2; ODT: disabled
3; Active Banks: Refresh Command every tRFC=tRFC(IDD); Idle banks: none.
IDD6
Self-Refresh Current
Tcase=0-85°C; Auto Self Refresh =Disable; Self Refresh Temperature Range=Normal9; CKE=Low; External
Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating;
Output Buffer: off 2; ODT: disabled 3; Active Banks: All (during Self-Refresh action); Idle Banks: all (between
Self-Rerefresh actions)
IDD6ET
Self-Refresh Current: extended temperature range
Tcase=0-95°C; Auto Self Refresh =Disable; Self Refresh Temperature Range=Extended9; CKE=Low; External
Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating;
Output Buffer: off 2; ODT: disabled 3; Active Banks: All (during Self-Refresh action); Idle Banks: all (between
Self-Rerefresh actions)
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IDD6TC
Auto Self-Refresh Current
Tcase=0-95°C; Auto Self Refresh =Enable8; Self Refresh Temperature Range=Normal9; CKE=Low; External
Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating;
Output Buffer: off 2; ODT: disabled 3; Active Banks: All (during Self-Refresh action); Idle Banks: all (between
Self-Rerefresh actions)
IDD7
Operating Bank Interleave Read Current
CKE=High; External Clock=On; tCK, tRC, tRAS, tRCD, tRRD, CL: see table as below; AL=tRCD.min-tCK;
CS=High between valid commands; Command Input: see table; Row, Column Address: Stable during
DESELECT; Bank Address: cycling10; Data I/O: Read Data: Output Data switches every clock cycle (i.e. data
stable during one clock cycle); Output Buffer: Off 2;ODT: disabled 3; Burst Length: BL8; Active / Idle Banks: All 10
/ none.
Note1: SWITCHING for Address and Command Input Signals as described in Definition of SWITCHING for Address and
Command Input Signals Table.
Note2: Output Buffer off: set MR1 A[12] = 1
Note3: ODT disable: set MR1 A[9,6,2]=000 and MR2 A[10,9]=00
Note4: Definition of D and D: described in Definition of SWITCHING for Address and Command Input Signals Table;
Ax/Rx/Wx: Activate/Read/Write to Bank x.
Note5: BL8 fixed by MRS: set MR0 A[1,0]=00
Note6: Precharge Power Down Mode: set MR0 A12=0/1 for Slow/Fast Exit
Note7: Because it is an exit after precharge power down, the valid commands are: ACT, REF, MRS, Enter Self-Refresh.
Note8: Auto Self-Refresh(ASR): set MR2 A6 = 0/1 to disable/enable feature
Note9: Self-Refresh Temperature Range (SRT): set MR2 A7 = 0/1 for normal/extended temperature range
Note10: Cycle banks as follows: 0,1,2,3,...,7,0,1,...
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 115
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All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
For IDD testing the following parameters are utilized.
Table 55: For testing the IDD parameters, the following timing parameters are used:
Parameter Symbol
DDR3/L-1066 DDR3/L-1333 DDR3/L-1600 DDR3-1866 DDR3-2133
Unit(-BE) (-CF/CFI) (-DH/DHI) (-EJ) (-FK)
-7-7-7 -8-8-8 -10-10-10 -11-11-11 -13-13-13
Clock Cycle Time tCKmin(IDD) 1.875 1.5 1.25 1.07 0.935
ns
CAS Latency CL(IDD) 7 8 10 11 13
nCK
Active to Read or Write delay tRCDmin(IDD) 13.125 12 12.5 11.77 12.155 ns
Active to Active / Auto-Refresh command
period
tRCmin(IDD) 50.63 48 47.5 45.77 45.155 ns
Active to Precharge Command tRASmin(IDD) 37.5 36 35 34 33
ns
Precharge Command Period tRPmin(IDD) 13.13 12 12.5 11.77 12.155 ns
Four activate window
1kB
tFAW(IDD)
37.5 30 30 27 25
ns
2kB 50 45 40 35 35
ns
Active to Active command period
1kB
tRRD(IDD)
7.5 6 6 5 5
nCK
2kB 10 7.5 7.5 6 6
nCK
Auto-Refresh to Active / Auto-Refresh
command period
tRFC(IDD) 110 110 110 110 110
ns
Table 56: Definition of SWITCHING for Address and Command Input Signals
SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as:
Address
(row, column)
If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change
then to the opposite value
(e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax…
Please see each IDDx definition for details
Bank Address
If not otherwise mentioned the bank addresses should be switched like the row/column address -
please see each IDDx for details
Command
(CS, RAS, CAS, WE)
Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
Define D = { CS, RAS, CAS, WE } := {HIGH, HIGH, HIGH, HIGH}
Define Command Background Pattern = D D D D D D D D D D D D....
If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background
Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary
command. See each IDDx definition for details.
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 116
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All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Standard Speed Bins
Table 57:DDR3/L-1066
Speed Bin DDR3/L-1066
Unit CL-nRCD-nRP 7-7-7 (-BE)
Parameter Symbol Min Max
Internal read command to first data tAA 13.125 20.000 ns
ACT to internal read or write delay time tRCD 13.125 - ns
PRE command period tRP 13.125 - ns
ACT to ACT or REF command period tRC 50.625 - ns
ACT to PRE command period tRAS 37.500 9*tREFI ns
CL=5 CWL=5 tCK(AVG) 3.000 3.300 ns
CWL=6 tCK(AVG) Reserved ns
CL=6 CWL=5 tCK(AVG) 2.500 3.300 ns
CWL=6 tCK(AVG) Reserved ns
CL=7 CWL=5 tCK(AVG) Reserved ns
CWL=6 tCK(AVG) 1.875 <2.5 ns
CL=8 CWL=5 tCK(AVG) Reserved ns
CWL=6 tCK(AVG) 1.875 <2.5 ns
Supported CL Settings 5, 6,7,8 nCK
Supported CWL Settings 5,6 nCK
Table 58:DDR3/L-1333
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 117
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Speed Bin DDR3/L-1333
Unit CL-nRCD-nRP 8-8-8 (-CF/CFI)
Parameter Symbol Min Max
Internal read command to first data tAA 12 20.000 ns
ACT to internal read or write delay time tRCD 12 - ns
PRE command period tRP 12 - ns
ACT to ACT or REF command period tRC 48 - ns
ACT to PRE command period tRAS 36.000 9*tREFI ns
CL=5
CWL=5 tCK(AVG) 2.500 3.300 ns
CWL=6 tCK(AVG) Reserved Reserved ns
CWL=7 tCK(AVG) Reserved Reserved ns
CL=6
CWL=5 tCK(AVG) 2.500 3.300 ns
CWL=6 tCK(AVG) Reserved Reserved ns
CWL=7 tCK(AVG) Reserved Reserved ns
CL=7
CWL=5 tCK(AVG) Reserved Reserved ns
CWL=6 tCK(AVG) 1.875* <2.5* ns
CWL=7 tCK(AVG) Reserved Reserved ns
CL=8
CWL=5 tCK(AVG) Reserved Reserved ns
CWL=6 tCK(AVG) 1.875 <2.5 ns
CWL=7 tCK(AVG) 1.5 <1.875 ns
CL=9
CWL=5 tCK(AVG) Reserved Reserved ns
CWL=6 tCK(AVG) Reserved Reserved ns
CWL=7 tCK(AVG) 1.500 <1.875 ns
CL=10
CWL=5 tCK(AVG) Reserved Reserved ns
CWL=6 tCK(AVG) Reserved Reserved ns
CWL=7 tCK(AVG) 1.500* <1.875* ns
Supported CL Settings 5,6,7,8,9,(10) nCK
Supported CWL Settings 5,6,7 nCK
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 118
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Table 59:DDR3/L-1600
Speed Bin DDR3/L-1600
Unit CL-nRCD-nRP 10-10-10 (-DH/DHI)
Parameter Symbol Min Max
Internal read command to first data tAA 12.500 20.000 ns
ACT to internal read or write delay time tRCD 12.500 - ns
PRE command period tRP 12.500 - ns
ACT to ACT or REF command period tRC 47.500 - ns
ACT to PRE command period tRAS 35.000 9*tREFI ns
CL=5
CWL =5 tCK(AVG) 2.500 3.300 ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=6
CWL =5 tCK(AVG) 2.500 3.300 ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=7
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) 1.875 <2.5 ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=8
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) 1.875 <2.5 ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=9
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) 1.500 <1.875 ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=10
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) 1.500 <1.875 ns
CWL =8 tCK(AVG) 1.250 <1.5 ns
CL=11
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) 1.250* <1.5* ns
Supported CL Settings 5,6,7,8,9,10,(11) nCK
Supported CWL Settings 5,6,7,8 nCK
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 119
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Table 60:DDR3-1866
Speed Bin DDR3-1866
Unit CL-nRCD-nRP 12-12-12 (-EJ)
Parameter Symbol Min Max
Internal read command to first data tAA 12.840 20.000 ns
ACT to internal read or write delay time tRCD 12.840 - ns
PRE command period tRP 12.840 - ns
ACT to ACT or REF command period tRC 46.84 - ns
ACT to PRE command period tRAS 34.000 9*tREFI ns
CL=6
CWL =5 tCK(AVG) 2.500 3.300 ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=7
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) 1.875 <2.5 ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=8
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) 1.875 <2.5 ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=9
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) 1.500 <1.875 ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=10
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) 1.500 <1.875 ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=11
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) 1.250* <1.5* ns
CL=12 CWL=5,6,7,8 tCK(AVG) Reserved Reserved ns
CWL=9 tCK(AVG) 1.07 <1.25 ns
CL=13 CWL=5,6,7,8 tCK(AVG) Reserved Rese
r
ved ns
CWL=9 tCK(AVG) 1.07 <1.25 ns
Supported CL Settings 5,6,7,8,9,10,11,12,(13) nCK
Supported CWL Settings 5,6,7,8,9 nCK
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 120
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Table 61:DDR3-2133
Speed Bin DDR3-2133
Unit CL-nRCD-nRP 13-13-13 (-FK)
Parameter Symbol Min Max
Internal read command to first data tAA 12.155 20.000 ns
ACT to internal read or write delay time tRCD 12.155 - ns
PRE command period tRP 12.155 - ns
ACT to ACT or REF command period tRC 45.155 - ns
ACT to PRE command period tRAS 33.000 9*tREFI ns
CL=5 CWL =5 tCK(AVG) 2.500 3.300 ns
CWL =6,7,8 tCK(AVG) Reserved Reserved ns
CL=6 CWL =5 tCK(AVG) 2.500 3.300 ns
CWL =6,7,8 tCK(AVG) Reserved Reserved ns
CL=7
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) 1.875 <2.5 ns
CWL =7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=8
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) 1.875 <2.5 ns
CWL =7 tCK(AVG) 1.500 <1.875 ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=9
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) 1.500 <1.875 ns
CWL =8 tCK(AVG) Reserved Reserved ns
CL=10
CWL =5 tCK(AVG) Reserved Reserved ns
CWL =6 tCK(AVG) Reserved Reserved ns
CWL =7 tCK(AVG) 1.500 <1.875 ns
CWL =8 tCK(AVG) 1.250 <1.5 ns
CL=11 CWL =5,6,7 tCK(AVG) Reserved Reserved ns
CWL =8 tCK(AVG) 1.250* <1.5* ns
CL=12 CWL=5,6,7,8 tCK(AVG) Reserved Reserved ns
CWL=9 tCK(AVG) 1.07 <1.25 ns
CL=13
CWL=5,6,7,8 tCK(AVG) Reserved Reserved ns
CWL=9 tCK(AVG) 1.07 <1.25 ns
CWL=10 tCK(AVG) 0.938 <1.07 ns
CL=14 CWL=5,6,7,8,9 tCK(AVG) Reserved Reserved ns
CWL=10 tCK(AVG) 0.938 <1.07 ns
Supported CL Settings
5,6,7,8,9,10,11,12,13, (14) nCK
Supported CWL Settings 5,6,7,8,9,10 nCK
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
REV 1.3 CONSUMER DRAM 121
Feb. 2012 © NANYA TECHNOLOGY CORP.
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Electrical Characteristics & AC Timing
Table 62: Timing Parameter by Speed Bin (DDR3/L-1066, 1333Mbps)
Parameter Symbol
DDR3/L-1066 DDR3/L-1333 Units Note
Min. Max. Min. Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode) tCK (DLL_OFF) 8 - 8 - ns
Average Clock Period tCK(avg) Refer to "Standard Speed Bins) ps
Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 tCK(avg)
Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 tCK(avg)
Absolute Clock Period tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max ps
Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - tCK(avg)
Absolute clock LOW pulse width tCL(abs) 0.43 - 0.43 - tCK(avg)
Clock Period Jitte
r
JIT(per) -90 90 -80 80 ps
Clock Period Jitter during DLL locking period JIT(per, lck) -80 80 -70 70 ps
Cycle to Cycle Period Jitte
r
tJIT(cc) 180 160 ps
Cycle to Cycle Period Jitter during DLL locking
period JIT(cc, lck) 160 140 ps
Duty Cycle Jitte
r
tJIT(duty) - - - - ps
Cumulative error across 2 cycles tERR(2per) -132 132 -118 118 ps
Cumulative error across 3 cycles tERR(3per) -157 157 -140 140 ps
Cumulative error across 4 cycles tERR(4per) -175 175 -155 155 ps
Cumulative error across 5 cycles tERR(5per) -188 188 -168 168 ps
Cumulative error across 6 cycles tERR(6per) -200 200 -177 177 ps
Cumulative error across 7 cycles tERR(7per) -209 209 -186 186 ps
Cumulative error across 8 cycles tERR(8per) -217 217 -193 193 ps
Cumulative error across 9 cycles tERR(9per) -224 224 -200 200 ps
Cumulative error across 10 cycles tERR(10per) -231 231 -205 205 ps
Cumulative error across 11 cycles tERR(11per) -237 237 -210 210 ps
Cumulative error across 12 cycles tERR(12per) -242 242 -215 215 ps
Cumulative error across n = 13, 14 . . . 49, 50
cycles tERR(nper)
tERR(nper)min = (1 + 0.68ln(n)) *
tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) *
tJIT(per)max
ps
Data Timing
DQS, DQS# to DQ skew, per group, per access tDQSQ - 150 - 125 ps
DQ output hold time from DQS, DQS# tQH 0.38 - 0.38 - tCK(avg)
DQ lo
w
-impedance time from CK, CK# tLZ(DQ) -600 300 -500 250 ps
DQ high impedance time from CK, CK# tHZ(DQ) - 300 - 250 ps
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
AC175/160
See Table.70 on page 134
ps
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
AC150/135 ps
Data hold time from DQS, DQS# referenced to
Vih(dc) / Vil(dc) levels
tDH(base)
DC100/90 ps
DQ and DM Input pulse width for each input tDIPW 490 - 400 ps
Data Strobe Timing
DQS,DQS# differential READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 tCK(avg)
DQS, DQS# differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 tCK(avg)
DQS, DQS# differential output high time tQSH 0.38 - 0.4 - tCK(avg)
DQS, DQS# differential output low time tQSL 0.38 - 0.4 - tCK(avg)
DQS, DQS# differential WRITE Preamble tWPRE 0.9 - 0.9 - tCK(avg)
DQS, DQS# differential WRITE Postamble tWPST 0.3 - 0.3 - tCK(avg)
DQS, DQS# rising edge output access time
from rising CK, CK# tDQSCK -300 300 -255 255 tCK(avg)
DQS and DQS# lo
w
-impedance time
(Referenced from RL - 1) tLZ(DQS) -600 300 -500 250 tCK(avg)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2) tHZ(DQS) - 300 - 250 tCK(avg)
DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 tCK(avg)
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
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DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 tCK(avg)
DQS, DQS# rising edge to CK, CK# rising edge tDQSS -0.25 0.25 -0.25 0.25 tCK(avg)
DQS, DQS# falling edge setup time to CK, CK#
rising edge tDSS 0.2 - 0.2 - tCK(avg)
DQS, DQS# falling edge hold time from CK,
CK# rising edge tDSH 0.2 - 0.2 - tCK(avg)
Command and Address Timing
DLL locking time tDLLK 512 - 512 - nCK
Internal READ Command to PRECHARGE
Command delay tRTP
tWTRmin.:
max(4nCK,
7.5ns)
tWTRmax.:
tRTPmin.:
max(4nCK,
7.5ns)
tRTPmax.
Delay from start of internal write
transaction to internal read command tWTR
tWTRmin.:
max(4nCK,
7.5ns)
tWTRmax.:
tRTPmin.:
max(4nCK,
7.5ns)
tRTPmax.
WRITE recovery time tWR 15 - 15 - ns
Mode Register Set command cycle time tMRD 4 - 4 - nCK
Mode Register Set command update delay tMOD tMODmin.: max(12nCK, 15ns)
tMODmax.:
ACT to internal read or write delay time tRCD
See Table.1 on page 1
PRE command period tRP
ACT to ACT or REF command period tRC
CAS# to CAS# command delay tCCD 4 - 4 - nCK
Auto precharge write recovery + precharge time tDAL(min) WR + roundup(tRP / tCK(avg)) nCK
Multi-Purpose Register Recovery Time tMPRR 1 - 1 - nCK
ACTIVE to PRECHARGE command period tRAS Standard Speed Bins
ACTIVE to ACTIVE command period for 1KB
page size tRRD tRRDmin.: max(4nCK, 6ns)
tRRDmax.:
ACTIVE to ACTIVE command period for 2KB
page size tRRD tRRDmin.: max(4nCK, 7.5ns)
tRRDmax.:
Four activate window for 1KB page size tFAW 37.5 0 30 - ns
Four activate window for 2KB page size tFAW 50 0 45 - ns
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels tIS(base) AC175/160
See Table.64 on page 131
ps
Command and Address hold time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels tIH(base) AC150/135 ps
Command and Address hold time from CK, CK#
referenced to Vih(dc) / Vil(dc) levels tIS(base) DC100/90 ps
Control and Address Input pulse width for each
input tIPW 780 - 620 - ps
Calibration Timing
Powe
r
-up and RESET calibration time tZQinit 512 - 512 - nCK
Normal operation Full calibration time tZQope
r
256 - 256 - nCK
Normal operation Short calibration time tZQCS 64 - 64 - nCK
Reset Timing
Exit Reset from CKE HIGH to a valid command tXPR
tXPRmin.: max(5nCK, tRFC(min) +
10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring a
locked DLL tXS
tXSmin.: max(5nCK, tRFC(min) +
10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a
locked DLL tXSDLL tXSDLLmin.: tDLLK(min)
tXSDLLmax.: - nCK
Minimum CKE low width for Self Refresh entry
to exit timing tCKESR tCKESRmin.: tCKE(min) + 1 nCK
tCKESRmax.: -
Valid Clock Requirement after Self Refresh
Entry (SRE)
or Power-Down Entry (PDE)
tCKSRE tCKSREmin.: max(5 nCK, 10 ns)
tCKSREmax.: -
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
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Valid Clock Requirement before Self Refresh
Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
tCKSRX tCKSRXmin.: max(5 nCK, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid
command;
Exit Precharge Power Down with DLL frozen to
commands
not requiring a locked DLL
tXP
tXPmin.:
max(3nCK, 7.5ns)
tXPmax.: -
tXPmin.:
max(3nCK,
6ns)
tXPmax.: -
Exit Precharge Power Down with DLL frozen to
commands
requiring a locked DLL
tXPDLL tXPDLLmin.: max(10nCK, 24ns)
tXPDLLmax.: -
CKE minimum pulse width tCKE
tCKEmin.:
max(3nCK ,5.625n
s)
tCKEmax.: -
tCKEmin.:
max(3nCK ,5.6
25ns)
tCKEmax.: -
Command pass disable delay tCPDED tCPDEDmin.: 1
tCPDEDmin.: - nCK
Power Down Entry to Exit Timing tPD tPDmin.: tCKE(min)
tPDmax.: 9*tREFI
Timing of ACT command to Power Down entry tACTPDEN tACTPDENmin.: 1
tACTPDENmax.: - nCK
Timing of PRE or PREA command to Power
Down entry tPRPDEN tPRPDENmin.: 1
tPRPDENmax.: - nCK
Timing of RD/RDA command to Power Down
entry tRDPDEN tRDPDENmin.: RL+4+1
tRDPDENmax.: - nCK
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF) tWRPDEN
tWRPDENmin.: WL + 4 + (tWR /
tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF) tWRAPDEN tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: - nCK
Timing of WR command to Power Down entry
(BC4MRS) tWRPDEN tWRPDENmin.: WL + 2 + (tWR /
tCK(avg))tWRPDENmax.: - nCK
Timing of WRA command to Power Down entry
(BC4MRS) tWRAPDEN tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: - nCK
Timing of REF command to Power Down entry tREFPDEN tREFPDENmin.: 1
tREFPDENmax.: - nCK
Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT turn on Latency ODTLon WL-2=CWL+AL-2 nCK
ODT turn off Latency ODTLoff WL-2=CWL+AL-2 nCK
ODT high time without write command or
with write command and BC4 ODTH4 ODTH4min.: 4;ODTH4max.: - nCK
ODT high time with Write command and BL8 ODTH8 ODTH8min.: 6;ODTH8max.: - nCK
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen) tAONPD 2 8.5 2 8.5 ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen) tAOFPD 2 8.5 2 8.5 ns
RTT turn-on tAON -300 300 -250 250 ps
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference tAOF 0.3 0.7 0.3 0.7 tCK(avg)
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 tCK(avg)
Write Leveling Timings
First DQS/DQS# rising edge after
write leveling mode is programmed tWLMRD 40 - 40 - nCK
DQS/DQS# delay after write leveling mode is
programmed tWLDQSEN 25 - 25 - nCK
Write leveling setup time from rising CK, CK#
crossing to rising DQS, DQS# crossing tWLS 245 - 195 - ps
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Write leveling hold time from rising DQS, DQS#
crossing to rising CK, CK# crossing tWLH 245 - 195 - ps
Write leveling output delay tWLO 0 9 0 9 ns
Write leveling output erro
r
tWLOE 0 2 0 2 ns
Electrical Characteristics & AC Timing
Table 63: Timing Parameter by Speed Bin (DDR3/L-1600, 1866, 2133Mbps)
Parameter Symbol
DDR3/L-1600 DDR3-1866 DDR3-2133
Units
N
o
t
e
Min. Max. Min. Max. Min.
Max.
Minimum Clock Cycle Time (DLL off
mode)
tCK
(DLL_OFF) 8 - 8 - 8 - ns
Average Clock Period tCK(avg) Refer to "Standard Speed Bins) ps
Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Absolute Clock Period tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max ps
Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - tCK(avg)
Absolute clock LOW pulse width tCL(abs) 0.43 - 0.43 - 0.43 - tCK(avg)
Clock Period Jitte
r
JIT(per) -70 70 -60 60 -50 50 ps
Clock Period Jitter during DLL locking
period JIT(per, lck) -60 60 -50 50 -40 40 ps
Cycle to Cycle Period Jitte
r
tJIT(cc) 140 120 100 ps
Cycle to Cycle Period Jitter during DLL
locking period JIT(cc, lck) 120 100 80 ps
Duty Cycle Jitte
r
tJIT(duty) - - - - - - ps
Cumulative error across 2 cycles tERR(2per) -103 103 -88 88 -74 74 ps
Cumulative error across 3 cycles tERR(3per) -122 122 -105 105 -87 87 ps
Cumulative error across 4 cycles tERR(4per) -136 136 -117 117 -97 97 ps
Cumulative error across 5 cycles tERR(5per) -147 147 -126 126 -105 105 ps
Cumulative error across 6 cycles tERR(6per) -155 155 -133 133 -111 111 ps
Cumulative error across 7 cycles tERR(7per) -163 163 -139 139 -116 116 ps
Cumulative error across 8 cycles tERR(8per) -169 169 -145 145 -121 121 ps
Cumulative error across 9 cycles tERR(9per) -175 175 -150 150 -125 125 ps
Cumulative error across 10 cycles tERR(10per) -180 180 -154 154 -128 128 ps
Cumulative error across 11 cycles tERR(11per) -184 184 -158 158 -132 132 ps
Cumulative error across 12 cycles tERR(12per) -188 188 -161 161 -134 134 ps
Cumulative error across n = 13, 14 . . . 49,
50 cycles tERR(nper) tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max ps
Data Timing
DQS, DQS# to DQ skew, per group, per
access tDQSQ - 100 - 85 - 75 ps
DQ output hold time from DQS, DQS# tQH 0.38 - 0.38 - 0.38 - tCK(avg)
DQ lo
w
-impedance time from CK, CK# tLZ(DQ) -450 225 -390 195 -360 180 ps
DQ high impedance time from CK, CK# tHZ(DQ) - 225 - 195 - 180 ps
Data setup time to DQS, DQS#
referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC175/160
See Table.70 on page 134
ps
Data setup time to DQS, DQS#
referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC150/135 ps
Data hold time from DQS, DQS#
referenced to Vih(dc) / Vil(dc) levels
tDH(base)
DC100/90 ps
DQ and DM Input pulse width for each
input tDIPW 360 - 320 - 280 - ps
Data Strobe Timing
DQS,DQS# differential READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 tCK(avg)
DQS, DQS# differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 0.3 Note 11 tCK(avg)
DQS, DQS# differential output high time tQSH 0.4 - 0.4 - 0.4 - tCK(avg)
DQS, DQS# differential output low time tQSL 0.4 - 0.4 - 0.4 - tCK(avg)
DQS, DQS# differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - tCK(avg)
DQS, DQS# differential WRITE tWPST 0.3 - 0.3 - 0.3 - tCK(avg)
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Postamble
DQS, DQS# rising edge output access
time from rising CK, CK# tDQSCK -225 225 -195 195 -180 180 tCK(avg)
DQS and DQS# lo
w
-impedance time
(Referenced from RL - 1) tLZ(DQS) -450 225 -390 195 -360 180 tCK(avg)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2) tHZ(DQS) - 225 - 195 - 180 tCK(avg)
DQS, DQS# differential input low pulse
width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg)
DQS, DQS# differential input high pulse
width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg)
DQS, DQS# rising edge to CK, CK# rising
edge tDQSS -0.27 0.27 -0.27 0.27 -0.27 0.27 tCK(avg)
DQS, DQS# falling edge setup time to
CK, CK# rising edge tDSS 0.18 - 0.18 - 0.18 - tCK(avg)
DQS, DQS# falling edge hold time from
CK, CK# rising edge tDSH 0.18 - 0.18 - 0.18 - tCK(avg)
Command and Address Timing
DLL locking time tDLLK 512 - 512 - 512 - nCK
Internal READ Command to
PRECHARGE Command delay tRTP tRTPmin.: max(4nCK, 7.5ns)
tRTPmax.: -
Delay from start of internal write
transaction to internal read command tWTR tWTRmin.: max(4nCK, 7.5ns)
tWTRmax.: -
WRITE recovery time tWR 15 - 15 - 15 - ns
Mode Register Set command cycle time tMRD 4 - 4 - 4 - nCK
Mode Register Set command update
delay tMOD tMODmin.: max(12nCK, 15ns)
tMODmax.:
ACT to internal read or write delay time tRCD
See Table.1 on page 1
PRE command period tRP
ACT to ACT or REF command period tRC
CAS# to CAS# command delay tCCD 4 - 4 - 4 - nCK
Auto precharge write recovery +
precharge time tDAL(min) WR + roundup(tRP / tCK(avg)) nCK
Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - nCK
ACTIVE to PRECHARGE command
period tRAS Standard Speed Bins
ACTIVE to ACTIVE command period for
1KB page size tRRD tRRDmin.: max(4nCK, 6ns)
tRRDmax.:
ACTIVE to ACTIVE command period for
2KB page size tRRD tRRDmin.: max(4nCK, 7.5ns)
tRRDmax.:
Four activate window for 1KB page size tFAW 30 0 27 - 25 - ns
Four activate window for 2KB page size tFAW 40 0 35 - 35 - ns
Command and Address setup time to CK,
CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base)
AC175/160
See Table.64 on page131
ps
Command and Address setup time to CK,
CK#
referenced to Vih(ac) / Vil(ac) levels
tIH(base)
AC150/135 ps
Command and Address hold time from
CK, CK#
referenced to Vih(dc) / Vil(dc) levels
tIS(base)
DC100/90 ps
Control and Address Input pulse width for
each input tIPW 560 - 535 - 470 - ps
Calibration Timing
Powe
r
-up and RESET calibration time tZQinit 512 - 512 - 512 - nCK
Normal operation Full calibration time tZQope
r
256 - 256 - 256 - nCK
Normal operation Short calibration time tZQCS 64 - 64 - 64 - nCK
Reset Timing
Exit Reset from CKE HIGH to a valid
command tXPR tXPRmin.: max(5nCK, tRFC(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not tXS tXSmin.: max(5nCK, tRFC(min) + 10ns)
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requiring a locked DLL tXSmax.: -
Exit Self Refresh to commands requiring
a locked DLL tXSDLL tXSDLLmin.: tDLLK(min)
tXSDLLmax.: - nCK
Minimum CKE low width for Self Refresh
entry to exit timing tCKESR tCKESRmin.: tCKE(min) + 1 nCK
tCKESRmax.: -
Valid Clock Requirement after Self
Refresh Entry (SRE)
or Power-Down Entry (PDE)
tCKSRE tCKSREmin.: max(5 nCK, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self
Refresh Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
tCKSRX tCKSRXmin.: max(5 nCK, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid
command;
Exit Precharge Power Down with DLL
frozen to commands
not requiring a locked DLL
tXP tXPmin.: max(3nCK, 6ns)
tXPmax.: -
Exit Precharge Power Down with DLL
frozen to commands
requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10nCK, 24ns)
tXPDLLmax.: -
CKE minimum pulse width tCKE tCKEmin.: max(3nCK ,5ns)
tCKEmax.: -
Command pass disable delay tCPDED tCPDEDmin.: 2
tCPDEDmin.: - nCK
Power Down Entry to Exit Timing tPD tPDmin.: tCKE(min)
tPDmax.: 9*tREFI
Timing of ACT command to Power Down
entry tACTPDEN tACTPDENmin.: 1, (2 for 2133)
tACTPDENmax.: - nCK
Timing of PRE or PREA command to
Power Down entry tPRPDEN tPRPDENmin.: 1 (2 for 2133)
tPRPDENmax.: - nCK
Timing of RD/RDA command to Power
Down entry tRDPDEN tRDPDENmin.: RL+4+1
tRDPDENmax.: - nCK
Timing of WR command to Power Down
entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR /
tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down
entry
(BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: - nCK
Timing of WR command to Power Down
entry (BC4MRS) tWRPDEN tWRPDENmin.: WL + 2 + (tWR /
tCK(avg))tWRPDENmax.: - nCK
Timing of WRA command to Power Down
entry
(BC4MRS)
tWRAPDEN tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: - nCK
Timing of REF command to Power Down
entry tREFPDEN tREFPDENmin.: 1 (2 for 2133)
tREFPDENmax.: - nCK
Timing of MRS command to Power Down
entry tMRSPDEN tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT turn on Latency ODTLon WL-2=CWL+AL-2 nCK
ODT turn off Latency ODTLoff WL-2=CWL+AL-2 nCK
ODT high time without write command or
with write command and BC4 ODTH4 ODTH4min.: 4
ODTH4max.: - nCK
ODT high time with Write command and
BL8 ODTH8 ODTH8min.: 6
ODTH8max.: - nCK
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen) tAONPD 2 8.5 2 8.5 2 8.5 ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen) tAOFPD 2 8.5 2 8.5 2 8.5 ns
RTT turn-on tAON -225 225 -195 195 -180 180 ps
RTT_Nom and RTT_WR turn-off time tAOF 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg)
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from ODTLoff reference
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg)
Write Leveling Timings
First DQS/DQS# rising edge after
write leveling mode is programmed tWLMRD 40 - 40 - 40 - nCK
DQS/DQS# delay after write leveling
mode is programmed tWLDQSEN 25 - 25 - 25 - nCK
Write leveling setup time from rising CK,
CK#
crossing to rising DQS, DQS# crossing
tWLS 165 - 140 - 125 - ps
Write leveling hold time from rising DQS,
DQS#
crossing to rising CK, CK# crossing
tWLH 165 - 140 - 125 - ps
Write leveling output delay tWLO 0 7.5 0 7.5 0 7.5 ns
Write leveling output erro
r
tWLOE 0 2 0 2 0 2 ns
Jitter Notes
Specific Note a
Unit “tCK(avg)” represents the actual tCK(avg) of the input clock under operation. Unit “nCK” represents one clock cycle
of the input clock, counting the actual clock edges. Ex) tMRD=4 [nCK] means; if one Mode Register Set command is
registered at Tm, anther Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) +
tERR(4per), min.
Specific Note b
These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc)
transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the
command/address. That is, these parameters should be met whether clock jitter is present or not.
Specific Note c
These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal
(CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc), as
these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or
not.
Specific Note d
These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective
data strobe signal (DQS(L/U), DQS(L/U)) crossing.
Specific Note e
For these parameters, the DDR3/L SDRAM device supports tnPARAM [nCK] = RU{tPARAM[ns] / tCK(avg)[ns]}, which is
in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP =
RU{tRP/tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3/L-1066
7-7-7, of which tRP = 13.125ns, the device will support tnRP = RU{tRP/tCK(avg)} = 7, as long as the input clock jitter
specifications are met, i.e. Precharge command at Tm and Active command at Tm+7 is valid even if (Tm+7-Tm) is less
than 13.125ns due to input clock jitter.
Specific Note f
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper), act of
the input clock, where 2 <= m <=12. (Output derating is relative to the SDRAM input clock.)
Specific Note g
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the
input clock. (Output deratings are relative to the SDRAM input clock.)
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Timing Parameter Notes
1. Actual value dependent upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register.
5. Value must be rouned-up to next higher integer value.
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT-on time tAON See “Timing Parameters”.
8. For definition of RTT-off time tAOF See “Timing Parameters”.
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles are programmed in MR0.
11. The maximum read postamble is bounded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the
right side.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this
parameter needs to be derated by TBD.
13. Value is only valid for RON34.
14. Single ended signal parameter.
15. tREFI depends on TOPER.
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew
rate. Note for DQ and DM signals, VREF(DC)=VrefDQ(DC). For input only pins except RESET,
Vref(DC)=VrefCA(DC).
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate.
Note for DQ and DM signals, VREF(DC)=VrefDQ(DC). For input only pins except RESET, Vref(DC)=VrefCA(DC).
18. Start of internal write transaction is defined as follows:
For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
19. The maximum preamble is bound by tLZ (DQS) max on the left side and tDQSCK(max) on the right side.
20. CKE is allowed to be registered low while operations such as row activation, 128recharge, autoprecharge or refresh
are in progress, but power-down IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN (min) is satisfied, there
are cases where additional time such as tXPDLL (min) is also required.
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error
within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and
Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between
ZQCS commands can be determined from these tables and other application-specific parameters.One method for
calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift
rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following
formula: ZQCorrection / [(Tsens x Tdriftrate) + (Vsens x Vdriftrate)] where Tsens = max(dRTTdT, dRONdTM) and
Vsens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if Tsens =
1.5%/C, Vsens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS
commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ~ 128ms
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
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25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following
falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising
edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of
derating to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier
reference point [(175mV – 150mV) / 1V/ns].
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Address / Command Setup, Hold, and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base)
and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + delta tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line
between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal
from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line
between shaded ‘dc to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the
nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal
from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain
above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid
input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to
complete the transition and reach VIH/IL(ac).
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Table 64: ADD/CMD Setup and Hold Base-Values for 1V/ns
Symbol Reference
DDR31066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133
Units
(-BE) (-CF/CFI) (-DH/DHI) (-EJ) (-FK)
tIS(base) AC175 VIH/L(ac) 125 65 45 - - ps
tIS(base) AC150 VIH/L(ac)275 190 170 - - ps
tIS(base) AC135 VIH/L(ac)- - - TBD TBD ps
tIS(base) AC125 VIH/L(ac)- - - TBD TBD ps
tIH(base) DC100 VIH/L(dc) 200 140 120 TBD TBD ps
1.35V
tIS(base) AC160 VIH/L(ac)140 80 60 TBD TBD ps
tIS(base) AC135 VIH/L(ac)290 205 185 TBD TBD ps
tIH(base) DC90 VIH/L(dc) 210 150 130 TBD TBD ps
Note:
1. (ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate.
2. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of
derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference
point [(175mV – 150mV) / 1V/ns].
3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for
for DDR3-1866 and 65ps for DDR3-2133 to accommodate for the lower alternate threshold of 125 mV and another 10ps to
account for earlier reference point [(135mv-125mv)/1v/ns].
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Table 65: Derating values DDR3/L-1066/1333/1600 tIS/tIH – (AC175)
Table 66: Derating values DDR3/L-1066/1333/1600 tIS/tIH – (AC150)
Table 67: Derating values DDR3-1866/2133 tIS/tIH – (AC135)
D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH
2 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100
1.559345934593467427550835891689984
1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9-2-4-2-4-2-4 6 41412222030303846
0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40
0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34
0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24
0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10
0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10
Delta tIS, Delta tIH derating in AC/DC based
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.0 V/ns1.2 V/ns
CMD/ADD Slew rate (V/n
s
4.0 V/ns 3.0 V/ns
CK, CK# Differential Slew Rate
D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH
275507550755083589166997410784115100
1.550345034503458426650745882689084
1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46
0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40
0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34
0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24
0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10
0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10
CMD/ADD Slew rate (V/n
s
4.0 V/ns 3.0 V/ns
CK, CK# Differential Slew Rate
Delta tIS, Delta tIH derating in AC/DC based
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.0 V/ns1.2 V/ns
D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH
268506850685076588466927410084108100
1.545344534453453426150695877688584
1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.92 -4 2 -4 2 -410 4 1812262034304246
0.8 3 -10 3 -10 3 -10 11 -2 19 6 27 14 35 24 43 40
0.7 6 -16 6 -16 6 -16 14 -8 22 0 30 8 38 18 46 34
0.6 9 -26 9 -26 9 -26 17 -18 25 -10 33 -2 41 8 49 24
0.5 5 -40 5 -40 5 -40 13 -32 21 -24 29 -16 37 -6 45 10
0.4 -3 -60 -3 -60 -3 -60 6 -52 14 -44 22 -36 30 -26 38 -10
Delta tIS, Delta tIH derating in AC/DC based
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.0 V/ns1.2 V/ns
CMD/ADD Slew rate (V/n
s
4.0 V/ns 3.0 V/ns
CK, CK# Differential Slew Rate
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Table 68: Derating values DDR3-1866/2133 tIS/tIH – (AC125)
Table 69: Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition
Slew Rate [V/ns]
tVAC@175mV [ps] tVAC@175mV [ps]
min max min max
>2.0 75 - 175 -
2 57 - 170 -
1.5 50 - 167 -
1 38 - 163 -
0.9 34 - 162 -
0.8 29 - 161 -
0.7 22 - 159 -
0.6 13 - 155 -
0.5 0 - 150 -
<0.5 0 - 150 -
D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH
2 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 100
1.542344234423450425850665874688284
1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.94 -4 4 -4 4 -412 4 2012282036304446
0.8 6 -10 6 -10 6 -10 14 -2 22 6 30 14 38 24 46 40
0.7 11 -16 11 -16 11 -16 19 -8 27 0 35 8 43 18 51 34
0.6 16 -26 16 -26 16 -26 24 -18 32 -10 40 -2 48 8 56 24
0.5 15 -40 15 -40 15 -40 23 -32 31 -24 39 -16 47 -6 55 10
0.4 13 -60 13 -60 13 -60 21 -52 29 -44 37 -36 45 -26 53 -10
Delta tIS, Delta tIH derating in AC/DC based
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.0 V/ns1.2 V/ns
CMD/ADD Slew rate (V/n
s
4.0 V/ns 3.0 V/ns
CK, CK# Differential Slew Rate
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Data Setup, Hold, and Slew Rate De-rating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDH(base)
and tDH(base) value to the delta tDS and delta tDH derating value respectively.
Example: tDS (total setup time) = tDS(base) + delta tDS
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the
first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line
between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal
from the ac level to dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line
between shaded ‘dc level to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the
nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal
from the dc level to Vref(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 70: Data Setup and Hold Base-Values
Unit [ps] reference DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Units
tDS(base)AC175 VIH/L(ac) 25 - - - - ps
tDS(base)AC150 VIH/L(ac)75 30 10 - - ps
tDS(base)AC135 VIH/L(ac)- - - TBD TBD ps
tDH(base)DC100 VIH/L(dc) 100 65 45 TBD TBD
ps
1.35V
tDS(base)AC160 VIH/L(ac)40 - - - - ps
tDS(base)AC135 VIH/L(ac)90 45 25 - - ps
tDH(base)DC90 VIH/L(dc) 110 75 55 TBD TBD
ps
Note: ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
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Table 71: Derating values DDR3/L-1066/1333/1600 tDS/tDH – (AC175)
Table 72: Derating values DDR3/L-1066/1333/1600 tDS/tDH – (AC150)
Table 73: Derating values DDR3-1866/2133 tDS/tDH – (AC135)
D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH
2885088508850----------
1.55934593459346742--------
1000000881616------
0.9---2-4-2-46414122220----
0.8-----6-102-210618142624--
0.7-------3-85013821182934
0.6---------1-107-21582324
0.5-----------11-16-2-6510
0.4-------------30-26-22-10
1.2 V/ns
DQ Slew rate (V/ns)
4.0 V/ns 3.0 V/ns
DQS, DQS Differential Slew Rate
Delta tDS, Delta tDH derating in AC/DC based
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.0 V/ns
D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH
2755075507550----------
1.55034503450345842--------
1000000881616------
0.9--0-40-48416122420----
0.8----0-108-216624143224--
0.7------8-816024832184034
0.6--------15-1023-23183924
0.5----------14-1622-63010
0.4------------7-2615-10
1.0 V/ns1.2 V/ns
DQ Slew rate (V/ns)
4.0 V/ns 3.0 V/ns
DQS, DQS Differential Slew Rate
Delta tDS, Delta tDH derating in AC/DC based
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns
D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH
2685068506850----------
1.54534453445345342--------
1000000881616------
0.9--2-42-410418122620----
0.8----3-1011-219627143524--
0.7------14-822030838184634
0.6--------25-1033-24184924
0.5----------29-1637-64510
0.4------------30-2638-10
DQ Slew rate (V/ns)
4.0 V/ns 3.0 V/ns
DQS, DQS Differential Slew Rate
Delta tDS, Delta tDH derating in AC/DC based
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.0 V/ns1.2 V/ns
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Table 74: Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition
Slew Rate [V/ns]
DDR3/L-1066 (AC175) DDR3/L-1333/1600 (AC150) DDR3-1866(AC135) DDR3-2133(AC135)
tVAC[ps] tVAC[ps] tVAC[ps] tVAC[ps]
Min. Max. Min. Max. Min. Max. Min. Max.
>2.0 75 - 175 - TBD - TBD -
2 57 - 170 - TBD - TBD -
1.5 50 - 167 - TBD - TBD -
1 38 - 163 - TBD - TBD -
0.9 34 - 162 - TBD - TBD -
0.8 29 - 161 - TBD - TBD -
0.7 22 - 159 - TBD - TBD -
0.6 13 - 155 - TBD - TBD -
0.5 0 - 155 - TBD - TBD -
<0.5 0 - 150 - TBD - TBD -
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Fig. 75: Package Dimensions ( x8; 78 balls; 0.8mmx0.8mm Pitch; BGA)
Min 0.25
Max 0.40
Max. 1.20
9.60
0.8
0.8
6.40
Bottom View
10.50 +/- 0.10
8.00 +/- 0.10 78 x o Max. 0.50
Min. 0.40
Min 0.1 Min 0.1
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Fig. 76 Package Dimensions (x16; 96 balls; 0.8mmx0.8mm Pitch; BGA)
Min 0.25
Max 0.40
Max. 1.20
12.00
0.8
0.8
6.40
Bottom View
13.00 +/- 0.10
9.00 +/- 0.10 96 x o Max. 0.50
Min. 0.40
Min 0.1 Min 0.1
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Table 75: Revision Log
Rev Date Modification
0.1 08/2010 Preliminary Release
0.2 09/2010 Revised Row Addressing
0.3 09/2010 Updated CAS Latency Frequency Table
0.4 11/2010 Revised x16 Pin Configuation and Separated x8/x16 Idd Specification
0.5 12/2010 Revised Programmable CAS Latency
1.0 01/2011 Added x16 Idd Specification
1.1 02/2011 Added the part numbers for I-Temp and the description of 1.35V
1.2 05/2011
Added x8 Idd specification and the description of DDR3-2133
Added the part numbers of 1.35V ordering information on page 9
Revised the typos of command, address and data timing on page 119,120, 122 and 123
Added the descriptions of Lead-Free and Halogen-Free on page 1.
Added and modified 1.35V and 1.5V IDD values.
Added the descriptions of I-temp for 1600Mbps.
Added the part numbers of I-temp for 1600Mbps and 1.35V for 1600Mbps on page 9.
1.3 2/2012
Revised the part number and the description of DDR3-1866 CL11 (EI) to CL12 (EJ)
Added the IDD values of DDR3-1866 (1.5V)
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performance of its semiconductor products and related software to the specifications applicable at the time of sale in
accordance with NTC’s standard warranty. Testing and other quality control techniques are utilized to the extent NTC
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