AVG Semiconductors Technical Data DDi 4-Bit Presettable Decade and Binary Synchronous Counters DV74LS160A, DV74LS161A DV74LS162A, DV74LS163A DV74ALS160B, DV74ALS161B DV74LS162B, DV74ALS163B These devices are high-speed four-bit synchronous count- ers which are edge-triggered, synchronously presettable, and cascadable building blocks for counting, memory addressing frequency division and other applictions. The 161 and "163 count modulo 16 (binary). The "160 and "162 count modulo 10 (BCD). A Terminal Count (TC) output is included which decodes the highest count of the respective device for convenient expandibility. The 160 and "161 have an asynchronous Master Reset (Clear) input that overrides, and is independent of the clock and all other control inputs. The 162 and 163 have a Syn- chronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge. N Suffix Plastic DIP AVG-003 Case D Suffix Plastic SOP AVG-004 Case AVG's LS operates over extended Vcc from 4.5 EOL COL LOL O9L BCD Binary to 5.5 V (Modula 10) (Modulo 16) = ~AVG's LS and ALS both have guaranteed DC Asynchronous Reset LS 1604 LS 161A and AC specification over full temperature and , Swi ching ifications for ALS at 50 pF Synchronous Reset LS 162A LS163A * Switching specitications tor ALS at 50 p AVG's ALS has the lowest speed power product ALS1628 ALS 1638 r gate typical) of all logic series po 14 99 _ _ 4 i3 Reset | | 1 ry 16| | Yec Presel Fi O1 BCD or Data 5 19 Binary Clock | 2 15 Z TC Inputs Pp aa | 2 Q2 Outputs eo [13 141] co p3 a3 _ fT Pl j4 13) | 01 p2[|s 12| | 02 Rippl ny 7 Clock 2 h 15 Coe PS Us 11] | O53 (CP) Ou Enable P | |7 10/ | Enable T rc ke PIN 16 = Ver GND | |8 9 |_| Load | PIN 8 = GND Lo a Load | PIN NAMES Enable P (CEP see MODE Load Parallel Enable (Active LOW) Input Count j Enable P (CEP) SELECT TABLE | po-p3 Parallel Inputs Enables] Enable T (CET) 1 | onnext page. CEP Count Enable Parallel Input CET Count Enable Trickle Input R Count Reset LOGIC EQUATIONS ese! Asynchronous Active low TC forl60 &162=CETQo-O1-Qe-O3 : TC for 161 & 163=CET-Oo-O1-Os-0 Synchronous Active low 7 ~ QoQ1-O2"Q3 Reset along with rising clock edge PresetsLOAD-CPT(rising clock edge) for 162 and 163 "Reset acts differently for these devices. See Pin Names. Q0-03 Parallel Outputs NOTE: . TC Terminal Count Output The 160 and 162 can be preset to any state, but will not count Clock Clock -Active high going edge beyond 9. If preset to state 10, 11, 12, 13, 14 or 15, it will re- turn to its normal sequence within two clock pulses. 1-600-AVG-SEMI 3-105 DV74LS160, 161, 162, 163 DV74ALS160, 161, 162, 163co 4 0, 161, 162, 163 ABSOLUTE MAXIMUM RATINGS Maximum ratings are those values beyond which damage to the device may occur. Symbol Parameter LS160A, 161A, 162A,] ALS160,161B, | Unit oe a 163A 1628, 1638 fF Vec | Supply Voltage oO : Vin | Input Voltage a 0.5 to +7.0 Tste_| Storage Temperature Range _ 65 to +150 GUARANTEED OPERATING CONDITIONS 7 | Symbol Parameter LS160A, 161A, 162A, ALS160, 161B, Unit : 163A 162B, 163B | a Min Max Min Max Vv Supply Vollage 4.5 5.5 4.5 5.5 V __Vin,_| High Level Input Voltage 2.0 2.0 V _Vic__| Low Level Input Voltage 0.8 08 | V lou | High Level Output Current _ -0.4 0.4 | mA! lo.__| Low Level Output Current 8.0 a _ 8.0 [mA Ta | Ambient Temperature Range 10 to +70 10 to +70 "C_| Dc ELECTRICAL CHARACTERISTICS over full operating range Symbol Parameter Conditions LSI60A, 161A, 162A, ALS160, 161B, Unit 163A _ 1628, 1638 Min Typ | Max | Min | Typ | Max Vix | Input Clamp Voltage Voc = min, -1.5 -1.5] V - ; lin = 18 mA _ a : Von | High Level Output Voltage | Voc=min, lon=-0.4mA] Voc-2/ 3.5 | | Vec-2 V oe Viec=min, lon=max Vor | Low Level Output Voltage | Voc=min; lot =4.0mA 0.25 | 0.4 0.2|04 ] V | _| Vec=min; lo. =8.0 mA 0.35 | 0.5 0.3} 0.5 | V | tin | High Level Input Current | Vec=max, ViH=2.7V A Data, CEP, CP, MR 20 20 CET, SR, LOAD 40 20 | Data, CEP, CP, MR | Vec=max, Vin=7.0V 0.4 0.1 J mA ____| GET, SR,LOAD 0.2 0.1 - lit =| Low Level Input Current Voc=max, Vin=0.4V mA Data, CEP, CP, MR -0.4 -0.1 CET, SR,LOAD _ 0.8 -0.1 log | Short Circuit Current Voec=max, Vo=2.25 V_] -20 =30 =112] mA | icc _| Supply Current Voc=max | 32 12 | 21 | mA. MODE SELECT TABLE Reset | 160,'161,'162, | Action on the Rising _ 163 Clock Edge T LOAD) CET | CEP H=High Logic Level L=Low Logic Level - X=Don't Care L x | MX | X RESET (Clear) | T= Low to High Transition H L x x LOAD (PnQn) * 162 & 163 only, 160 & 161 reset asynchronously H H H H Count (Increment) H H L X | NO CHANGE (Hold) H H x L__| NO CHANGE (Hold) | DV74LS160, 161, 162, 163 3-106 1-800-AVG-SEMI DV74ALS160, 161, 162, 163AC CHARACTERISTICS over full operating conditions EOL ZOL LOL O9L Symbol Parameter LS160A, 161A, | ALS160, 161B, | Unit 162A, 1634 163A 162B, 163B CL=15pF C= 50 pF Fis 5000 Min Max fmax | Maximum Clock Frequency 40 MHz tpLH | Propagation Delay, 24 4 15 ns tpHi Clock to Output Q o7 6 20) tPLH_ | Propagation Delay, 14 3 13 ns tpHL | Reset to Output O 28 8 24 ns tPHL | Reset to Ripple Carry Out (160-161 Only) 26 11 23 ns AC SETUP REQUIREMENTS over full operating conditions symbol Parameter LS160A, 16174, ALS160, 161B, | Unit 162A, 163A 162B, 163B Min Max Min Max tw Pulse Width, Clock 25 12.5 ns tw Pulse Width, Reset 20 15 ns (160-16710nly) ts Setup Time, 20 15 ns Data, Enable P or Enable T ts | Setup Time, SR, LOAD 25 15 ns ts Setup Time, CEP, CET, DATA 25 15 ns th Hold Time 0 0 ns trae | Recovery Time, Reset to Clock 15 10 ns | (160-161 Only) i SWITCHING WAVEFORMS ee tw te x ; se Tp | GHD Lav Qo O er TC r VALID | 3V ' LOAD OR ras 1.3 av GHD 1.3 a 7 1.34 CLOCK ___- SNE 1-800-AVG-SEMI CLOCK GHD 3-107 DV74LS160, 161, 162, 163 DV74ALS160, 161, 162, 163