Digitally Programmable Delay Units sens: pou-13256F (8-Bit) TTL Interfaced Specifications: Test Conditions: m Delay variation: Monotonic in one direction. m Programmed delay tolerance: +5% or 2 ns whichever is greater. g Inherent delay (Tpo): 15 ns on pin 6 g Input pulse-width: 2150% of Max. delay. m Input pulse spacing: typical 23 times of Max. delay. . : 18 ns on pin & Input pulse voltage: Features: m Propagation delay: TTL logic. w Input & output TTL buffered Address to output (Tsua) 12ns typ. u Measurements taken @ Enable to output (Tsue) 12 ns typ. Ta = 25C: Vcc = BV. a 8-BIT TTL programmable delay line m@ Two (2) separate outputs; inverting & non-inverting Power dissipation: .95 w max. m Supply voltage: 5 Vde + 5%. m Operating temperature: 0-70C. m Completely interfaced m Temperature coefficient: 100 PPM/"C. a Compact & low profile m DC parameters: See TTL-Fast Schottky Logic Table on Page 6. f * . J T TT j if if Y f f YY Yo Y af E12 sass 7 8 oo 9 --2 431 42] 41198]34/ 33} 30} teh v 92.40.48 q Ce Oneree rere e ik { Wot DELAY > our O75 TP | NETWORK GAD este s our T Se793 qa a | | 400.300 L J 4 48 43 42 Al 40 35 34 33 32 BO ee ee a mono ooron m 2.450 | TRUTH TABLE Address (Bit No.) 81776); 514;,3)211 Enable | Delay Out . (E,) 0o;O0O 7/0/0070] 0] 0 0 Ty OoOFOoOFO;O;oO Oyo 0 T, ofofoflojoftolilo 0 Ty incremental Delay Total Programmed ofoflolojofota]4 0 T, Part No. Per Step (ns) Dalay (ns) PDU-13256F-.5 St 3 127.5 Oo10;0 7040 1 070 0 T. ololoflololiiaia 0 T. PDU-13256F-1 12465 255 olololo 1 0 7 PDU-13256F-2 245 510 6 | 0 0 T, PDU-13256F-3 3 +10 765 Oo7;O0O;OffOu4 1 1 1 0 Ths PDU-13256F-4 4 +10 1,020 ofoyzoi4 o1rotoio 0 Tis PDU-13256F-5 5 +15 1,275 ololo i 1 1 1 { 0 Ts, PDU-13256F-6 6 15 1,530 clo 1 olololola 0 Tyo PDU-13256F-7 7 15 1,785 0]; 0 1 1 1 1 1 1 0 T55 PDU-13256F-8 8 20 2,040 PDU-13256F-9 9 +20 2,295 0 1 o;o;o;oy;ota 0 T54 PDU-13256F-10 10 +2.0 2,550 0 1 1 1 1 1 1 1 0 Tioz 1 OTfToO;oy;yoTototlo 0 Troe 1 1 1 4 1 1 1 4 0 T NOTE: 1. Forthe sake of simplicity all 256 programmable steps 256 are not shown in this truth table. 0 ) 0 o o o ) o 1 1 2. After Bit 6, the incremental delay tolerance is 5% of programmed delay. 0 = LogicO 1 = Logic1 = Don't care. Ty = Reference or inherent delay of unit. T, >T,,;, multiplier of incremental delay. 3 Mt. Prospect Avenue, Clifton. New .lersey 07013 (201) 773-2299 = FAX (201) 773-9672 BB 26443982 0003055 4OT 56