Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
4A, 26V, 380kHz, Asynchronous Step-Down Converter
Features
•Wide Input Voltage from 4.5V to 26V
•Output Current up to 4A
•Adjustable Output Voltage from 0.8V to 90%VIN
- 0.8V Reference Voltage
- ±2.5% System Accuracy
•80mΩ Integrated P-Channel Power MOSFET
•High Efficiency up to 91%
- Pulse-Skipping Mode (PSM) / PWM Mode Operation
•Current-Mode Operation
- Stable with Ceramic Output Capacitors
- Fast Transient Response
•Power-On-Reset Monitoring
•Fixed 380kHz Switching Frequency in PWM Mode
•Built-in Digital Soft-Start
•Output Current-Limit Protection with Frequency
Foldback
•70% Undervoltage Protection
•Over-Temperature Protection
•<5µA Quiescent Current during Shutdown
•Thermal-Enhanced SOP-8P Package
•Lead Free and Green Devices Available
(RoHS Compliant)
Applications
General Description
The APW7080 is a 4A, asynchronous, step-down converter
with integrated 80mΩ P-channel MOSFET. The device,
with current-mode control scheme, can convert 4.5~26V
input voltage to the output voltage adjustable from 0.8 to
90% VIN to provide excellent output voltage regulation.
The APW7080 regulates the output voltage in automatic
PSM/PWM mode operation, depending on the output
current, for high efficiency operation over light to full load
current.The APW7080 is also equipped with power-on-
reset, soft-start, and whole protections (undervoltage, over
temperature, and current-limit) into a single package. In
shutdown mode, the supply current drops below 5µA.
This device, available in an 8-pin SOP-8P package,
provides a very compact system solution with minimal
external components and good thermal conductance.
•LCD Monitor / TV
•Set-Top Box
•Portable DVD
•Wireless LAN
•ADSL, Switch HUB
•Notebook Computer
•Step-down Converters Requiring High Efficiency
and 4A Output Current
Simplified Application Circuit
Efficiency (%)
Output Current, IOUT (A)
R2
1%
LX
EN
VIN
GND
COMP
U1
APW7080
FB
UGND
VOUT
+3.3V
L1
4A
D1
VCC
C3
C2
VIN
+12
C1
10µF
C5
R4
C6
C4
22µF
R1
1%
VIN
C7
(Optional)
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 110
VOUT =5V
VOUT =3.3V
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw2
Ordering and Marking Information
Pin Configuration
GND
FB
COMP
LX
VIN
EN
UGND
VCC
9
LX
8
7
6
5
1
2
3
4
SOP-8P
Top View
The Pin 5 must be connected to the Exposed Pad
Symbol Parameter Rating Unit
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 30 V
> 100ns -2 ~ VIN+0.3
VLX LX to GND Voltage < 100ns -5 ~ VIN+6 V
VIN > 6.2V -0.3 ~ 6.5
VCC VCC Supply Voltage (VCC to GND) VIN ≤ 6.2V < VIN+0.3 V
VUGND_GND UGND to GND Voltage -0.3 ~ VIN+0.3 V
VVIN_UGND VIN to UGND Voltage -0.3 ~ 6.5V V
EN to GND Voltage -0.3 ~ 20 V
FB, COMP to GND Voltage -0.3 ~ VCC +0.3 V
Maximum Junction Temperature 150 °
C
TSTG Storage Temperature -65 ~ 150 °
C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °
C
Absolute Maximum Ratings (Note 1)
Note 1: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device.
APW7080
Handling Code
Temperature Range
Package Code
Package Code
KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 C
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device G : Halogen and Lead Free Device
°
Assembly Material
APW7080 KA : APW7080
XXXXX XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish;
which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-
020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and
halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed
1500ppm by weight).
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw3
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in Free Air (Note 2)
SOP-8P
50 oC/W
θJC Junction-to-Case Resistance in Free Air (Note 3)
SOP-8P
10 oC/W
Recommended Operating Conditions (Note 4)
Symbol Parameter Range Unit
VIN VIN Supply Voltage 4.5 ~ 26 V
VCC Supply Voltage 4.0 ~ 5.5 V
VOUT Converter Output Voltage 0.8 ~ 90% VIN V
IOUT Converter Output Current 0 ~ 4 A
VCC Input Capacitor 0.22 ~ 2.2 µF
VIN-to-UGND Input Capacitor 0.22 ~ 2.2 µF
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Thermal Characteristics
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is
soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package.
Note 4: Refer to the typical application circuits
Electrical Characteristics
APW7080
Symbol
Parameter Test Conditions Min. Typ. Max.
Unit
SUPPLY CURRENT
IVIN VIN Supply Current VFB = 0.85V, VEN=3V, LX=Open - 1.0 2.0 mA
IVIN_SD
VIN Shutdown Supply Current VEN = 0V, VIN=26V - - 5 µA
IVCC VCC Supply Current VEN = 3V, VCC = 5.0V, VFB=0.85V - 0.7 - mA
IVCC_SD
VCC Shutdown Supply Current VEN = 0V, VCC = 5.0V - - 1 µA
VCC 4.2V LINEAR REGULATOR
Output Voltage VIN = 5.2 ~ 26V, IO = 0 ~ 8mA 4.0 4.2 4.5 V
Load Regulation IO = 0 ~ 8mA -60 -40 0 mV
Current-Limit VCC > POR Threshold 8 - 30 mA
VIN-to-UGND 5.5V LINEAR REGULATOR
Output Voltage (VVIN-UGND) VIN = 6.2 ~ 26V, IO = 0 ~ 10mA 5.3 5.5 5.7 V
Load Regulation IO = 0 ~ 10mA -80 -60 0 mV
Current-Limit VIN = 6.2 ~ 26V 10 - 30 mA
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise
specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw4
Electrical Characteristics (Cont.)
APW7080
Symbol
Parameter Test Conditions Min. Typ. Max.
Unit
POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS
VCC POR Voltage Threshold VCC rising 3.7 3.9 4.1 V
VCC POR Hysteresis - 0.15 - V
EN Lockout Voltage Threshold VEN rising 2.3 2.5 2.7 V
EN Lockout Hysteresis - 0.2 - V
VIN-to-UGND Lockout Voltage
Threshold VVIN-UGND rising - 3.5 - V
VIN-to-UGND Lockout Hysteresis - 0.2 - V
REFERENCE VOLTAGE
VREF Reference Voltage - 0.8 - V
TJ = 25oC, IOUT=0A, VIN=12V -1.0 - +1.0
Output Voltage Accuracy TJ = -40 ~ 125oC, IOUT = 0 ~ 4A,
VIN = 4.5 ~ 26V -2.5 - +2.5 %
Line Regulation VIN = 4.5V to 26V, IOUT = 0A - 0.36 - %
Load Regulation IOUT = 0 ~ 4A - 0.4 - %
OSCILLATOR AND DUTY
FOSC Free Running Frequency VIN = 4.5 ~ 26V 340 380 420 kHz
Foldback Frequency VFB = 0V - 80 - kHz
Maximum Converter’s Duty Cycle - 93 - %
Minimum Pulse Width of LX VIN = 4.5 ~ 26V - 200 - ns
CURRENT-MODE PWM CONVERTER
Gm Error Amplifier Transconductance - 400 - µA/V
Error Amplifier DC Gain COMP = Open 60 80 - dB
Current-Sense Resistance - 0.12 - Ω
P-channel Power MOSFET
Resistance Between VIN and Exposed Pad,
TJ=25oC - 80 100 mΩ
PROTECTIONS
ILIM P-channel Power MOSFET
Current-limit Peak Current 5.0 6.5 8.0 A
VUV FB Under-Voltage Threshold VFB falling 66 70 74 %
FB Under-Voltage Hysteresis - 40 - mV
FB Under-Voltage Debounce - 2 - µs
TOTP Over-Temperature Trip Point - 150 - oC
Over-Temperature Hysteresis - 50 - oC
SOFT-START, ENABLE AND INPUT CURRENTS
tSS Soft-Start Interval 9 10.8 12 ms
Preceding Delay before Soft-Start 9 10.8 12 ms
EN Shutdown Voltage Threshold VEN falling, VIN = 4 ~ 26V 0.5 - - V
EN Enable Voltage Threshold VEN rising, VIN = 4 ~ 26V - - 2.1 V
EN Pin Clamped Voltage IEN=10mA 12 - 17 V
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise
specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw5
Electrical Characteristics (Cont.)
APW7080
Symbol
Parameter Test Conditions Min. Typ. Max.
Unit
SOFT-START, ENABLE, AND INPUT CURRENTS (Cont.)
P-channel Power MOSFET
Leakage Current VEN = 0V, VLX = 0V, VIN = 26V - - 4 µA
IFB FB Pin Input Current VFB = 0.8V -100 - +100
nA
IEN EN Pin Input Current VEN < 3V -500 - +500
nA
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise
specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw6
Typical Operating Characteristics
Reference Voltage, VREF (V)
Junction Temperature, TJ (oC)
Reference Voltage vs. Junction Temperature
Switching Frequency, FOSC (kHz)
Junction Temperature, TJ (oC)
Switching Frequency vs. Junction Temperature
Output Voltage, VOUT (V)
Supply Voltage, VIN (V)
Output Voltage vs. Supply Voltage
Output Voltage, VOUT (V)
Output Current, IOUT (A)
Output Voltage vs. Output Current
Current-Limit Level, ILIM (A)
Junction Temperature, TJ (oC)
Current-Limit Level (Peak Current)
vs. Junction Temperature
VIN Input Current, IVIN (mA)
VIN Supply Voltage, VIN (V)
VIN Input Current vs. Supply Voltage
340
350
360
370
380
390
400
410
420
-50 -25 025 50 75 100 125 150
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
4 6 8 10 12 14 16 18 20 22 24 26
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 4 8 12 16 20 24 28
IOUT = 1AIOUT = 1A
VFB=0.85VVFB=0.85V
0.784
0.788
0.792
0.796
0.800
0.804
0.808
0.812
0.816
-50 -25 025 50 75 100 125 150
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VIN = 12VVIN = 12V
5.0
5.5
6.0
6.5
7.0
7.5
8.0
-50 -25 0 25 50 75 100 125 150
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw7
Typical Operating Characteristics (Cont.)
Efficiency (%)
Output Current, IOUT (A)
Efficiency vs. Output Current
EN Clamp Voltage, VEN (V)
EN Input Current, IEN (µA)
EN Clamp Voltage vs. EN Input Current
0
2
4
6
8
10
12
14
16
18
110 100 1000 10000
Operating Waveforms
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
VOUT
IL1
Load Transient Response Load Transient Response
11
22
11
22
VOUT
Ch1 : VOUT, 200mV/Div, DC,
Voltage Offset = 3.3V
Ch2 : IL1, 1A/Div, DC
Time : 50µs/Div
Ch1 : VOUT, 100mV/Div, DC,
Voltage Offset = 3.3V
Ch2 : IL1, 1A/Div, DC
Time : 50µs/Div
TJ=-30oCTJ=-30oC
TJ=25oCTJ=25oC
TJ=100oCTJ=100oC
IOUT = 50mA -> 3A -> 50mA
IOUT rise/fall time=10µs
IOUT = 50mA -> 3A -> 50mA
IOUT rise/fall time=10µs
0A0A
3A3A
0.5A0.5A
IOUT = 0.5A -> 3A -> 0.5A
IOUT rise/fall time=10µs
IOUT = 0.5A -> 3A -> 0.5A
IOUT rise/fall time=10µs
3A3A
IL1
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
VIN=12v, L=10µH (DCR=50mΩ)
C1=10µF, C4=22µF
VOUT =5VVOUT
=5V
VOUT=3.3VVOUT=3.3V
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw8
Operating Waveforms (Cont.)
VOUT
IL1
Power OnPower Off
11
22
11
22 VOUT
Ch1 : VIN, 5V/Div, DC
Ch2 : VOUT, 2V/Div, DC
Ch3 : IL1, 2A/Div, DC
Time : 5ms/Div
Ch1 : VIN, 5V/Div, DC
Ch2 : VOUT, 2V/Div, DC
Ch3 : IL1, 2A/Div, DC
Time : 5ms/Div
IL1
IOUT = 3AIOUT = 3A
IOUT = 3AIOUT = 3A
VIN
VIN
33
33
VOUT
IL1
Enable Through EN PinShutdown Through EN Pin
11
22
11
22 VOUT
Ch1 : VEN, 5V/Div, DC
Ch2 : VOUT, 2V/Div, DC
Ch3 : IL1, 2A/Div, DC
Time : 5ms/Div
Ch1 : VEN, 5V/Div, DC
Ch2 : VOUT, 2V/Div, DC
Ch3 : IL1, 2A/Div, DC
Time : 5ms/Div
IL1
IOUT = 3AIOUT = 3A
IOUT = 3AIOUT = 3A
VEN
VEN
33
33
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw9
Operating Waveforms (Cont.)
Over CurrentShort Circuit
11
22
VOUT
Ch1 : VOUT, 1V/Div, DC
Ch2 : IL1, 2A/Div, DC
Time : 50µs/Div
Ch1 : VOUT, 1V/Div, DC
Ch2 : IL1, 2A/Div, DC
Time : 50ms/Div
IL1
IL1
Switching WaveformSwitching Waveform
11
22
11
22
Ch1 : VLX, 5V/Div, DC
Ch2 : IL1, 1A/Div, DC
Time : 1.25µs/Div
Ch1 : VLX, 5V/Div, DC
Ch2 : IL1, 2A/Div, DC
Time : 1.25µs/Div
IL1
VLX
VOUT is shorted to ground by a short wireVOUT is shorted to ground by a short wire
VLX
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
2
1
VOUT
IL1
IOUT = 1 -> 6A
22
11
VOUT
IL1
IOUT = 1 -> 6A
IOUT = 3AIOUT = 3A
IOUT = 3AIOUT= 0.2A
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw10
Operating Waveforms (Cont.)
VOUT
VIN
Line Transient Response
11
22
Ch1 : VOUT, 50mV/Div, DC,
Voltage Offset = 3.3V
Ch2 : VIN, 5V/Div, DC,
Voltage Offset = 12V
Time : 50µs/Div
VIN = 12V --> 24V --> 24V
VIN rise/fall time=20µs
VIN = 12V --> 24V --> 24V
VIN rise/fall time=20µs
24V24V
12V12V
Pin Description
PIN NAME FUNCTION
1 VIN Power Input. VIN supplies the power (4.5V to 26V) to the control circuitry, gate driver and step-
down
converter switch. Connecting a ceramic bypass capacitor and a suitably large capacitor between
VIN and GND eliminates switching noise and voltage ripple on the input to the IC.
2 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the
regulator, drive it low to turn it off. Pull up with 100kΩ resistor for automatic startup.
3 UGND
Gate driver power ground of the P-channel Power MOSFET. A linear regulator regulates a 5.5V
voltage between VIN and UGND to supply power to P-channel MOSFET gate driver. Connect a
ceramic capacitor (1µF typ.) between VIN and U
GND for noise decoupling and stability of the linear
regulator.
4 VCC
Bias input and 4.2V linear regulator’s output. This pin supplies the bias to some control circuits. The
4.2V linear regulator converts the voltage on VIN to 4.2V to supply the bias when no external 5V
power supply is connected with VCC. Connect a ceramic capacitor (1µF typ.) between VCC and
GND for noise decoupling and stability of the linear regulator.
5 LX Power Switching Output. Connect this pin to the underside Exposed Pad.
6 COMP Output of error amplifier. Connect a series RC network from COMP to GND to compensate the
regulation control loop. In some cases, an additional capacitor from COMP to GND is required for
noise decoupling.
7 FB Feedback Input. The IC senses feedback voltage via FB and regulate the voltage at 0.8V.
Connecting FB with a resistor-divider from the output set the output voltage in the range from 0.8V
to 90% VIN.
8 GND Power and Signal Ground.
9
(Exposed Pad)
LX Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output.
The Exposed Pad provides current with lower impedance than Pin 5. Connect the pad to output LC
filter via a top-layer thermal pad on PCBs. The PCB will be a heat sink of the IC.
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw11
Block Diagram
Typical Application Circuit
1. 4.5~26V Single Power Input Step-down Converter (with Ceramic Input/Output Capacitors)
LX
Gate
Control
VREF
0.8V
Soft-Start
and
Fault Logic
Error
Amplifier
FB
Inhibit
70%VREF UVP
GND
POR
Soft-Start
4.2V Regulator
and
Power-On-Reset
VCC
VCC
Enable
Current Sense
Amplifier
EN
COMP
Oscillator
380kHz
Slope
Compensation
Current
Compartor
0.8V
UGND
VIN
Over
Temperature
Protection
Current
Limit
VIN-to-UGND
Linear Regulator
VIN
5.5V
FB
2.5V ENOK
UG
Gate
Driver
R2
1%
LX
EN
2
VIN
1
GND
8
COMP
6
9
U1
APW7080
FB 7
UGND 3
VOUT
0.8V~90%VIN
/4A
L1
4A
D1
VCC
4
C3
1µF
C2
1µF
VIN
4.5~26V
C1
10µF
C5
R4
C6
C4
22µF
R1
1%
R5
100kΩ
VIN
C7
(Optional)
LX 5
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw12
Typical Application Circuit (Cont.)
Recommended Feedback Compensation Network Components List:
VIN
(V) VOUT
(V) L1
(µH) C4
(µF) C4 ESR
(mΩ)
R1
(kΩ) R2
(kΩ) C7
(pF) R4
(kΩ) C5
(pF) C6
(pF)
24 12 15 22 5 140 10 22 62 820 22
24 12 15 44 3 140 10 22 120
820 22
24 5 10 22 5 63 12 33 24 1500
22
24 5 10 44 3 63 12 33 51 1500
22
12 5 10 22 5 63 12 68 24 820 22
12 5 10 44 3 63 12 68 51 820 22
12 3.3 10 22 5 46.9 15 82 15 1000
22
12 3.3 10 44 3 46.9 15 82 33 1000
22
12 2 4.7 22 5 30 20 56 10 2200
22
12 2 4.7 44 3 30 20 56 20 2200
22
12 1.2 3.3 22 5 7.5 15 150
6.2 3300
22
12 1.2 3.3 44 3 7.5 15 150
12 3300
22
5 3.3 3.3 22 5 46.9 15 68 15 560 22
5 3.3 3.3 44 3 46.9 15 68 33 560 22
5 1.2 2.2 22 5 7.5 15 270
5.6 1500
22
5 1.2 2.2 44 3 7.5 15 270
12 1500
22
5 0.8 2.2 22 5 0 NC NC 2.7 2700
22
5 0.8 2.2 44 3 0 NC NC 6.2 2700
22
2. Dual Power Inputs Step-down Converter (VIN=4.5~26V)
+5V
R2
1%
LX
EN
2
VIN
1
GND
8
COMP
6
9
U1
APW7080
FB 7
UGND 3
VOUT
0.8V~90%VIN
/4A
L1
4A
D1
VCC
4
C3
1µF
C2
1µF
VIN
4.5~26V
C1
10µF
C5
R4
C6
D2
Schottky
Diode
C4
22µF
R1
1%
R5
100kΩ
VIN
C7
(Optional)
LX 5
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw13
3. 4.5~5.5V Single Power Input Step-down Converter
Typical Application Circuit (Cont.)
4. +12V Single Power Input Step-down Converter (with Electrolytic Input/Output Capacitors)
R2
1%
LX
EN
2
VIN
1
GND
8
COMP
6
9
U1
APW7080
FB 7
UGND 3
VOUT
0.8V~90%VIN
/4A
L1
4A
D1
VCC
4
C3
1µF
C2
1µF
VIN
4.5~5.5V
C1
10µF
C5
R4
C6
C4
22µF
R1
1%
C7
(Optional)
R5
100kΩ
VIN
LX 5
R2
15k
1%
LX
EN
2
VIN
1
GND
8
COMP
6
9
U1
APW7080
FB 7
UGND 3
VOUT
+3.3V/4A
L1
10uH
4A
D1
VCC
4
C3
1µF
C2
1µF
VIN
+12V
C1
2.2µF
C5
4700pF
R4
56k
C6
22pF
C4
470µF
R1
46.9k
1%
R5
100kΩ
VIN
C8
470µF
C7
33pF
LX 5
(ESR=30mΩ)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw14
Typical Application Circuit (Cont.)
5. -8V Inverting Converter with 4.5~5.5V Single Power Input
LX
EN
2
VIN
1
GND
8
COMP
6
9
U1
APW7080
UGND 3
L1
6.8µH
4A
D1
VCC
4
C3
1µF
C2
1µF
VIN
4.5~5.5V
C1
10µF
C5
560pF
R4
39kΩ
C6
22pF C4
22µF
R5
100kΩ
LX 5
R2
10kΩ
FB 7
R1
90kΩ
C7
27pF
PGND
AGND
VOUT
-8V/4A
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw15
Function Description
Main Control Loop
The APW7080 is a constant frequency current mode
switching regulator. During normal operation, the internal
P-channel power MOSFET is turned on each cycle when
the oscillator sets an internal RS latch and would be turned
off when an internal current comparator (ICMP) resets
the latch. The peak inductor current at which ICMP resets
the RS latch is controlled by the voltage on the COMP pin,
which is the output of the error amplifier (EAMP). An
external resistive divider connected between VOUT and
ground allows the EAMP to receive an output feedback
voltage VFB at FB pin. When the load current increases, it
causes a slight decrease in VFB relative to the 0.8V
reference, which in turn causes the COMP voltage to in-
crease until the average inductor current matches the
new load current.
VCC Power-On-Reset(POR) and EN Undervoltage
Lockout
The APW7080 keeps monitoring the voltage on VCC pin
to prevent wrong logic operations which may occur when
VCC voltage is not high enough for the internal control
circuitry to operate. The VCC POR has a rising threshold
of 3.9V (typical) with 0.15V of hysteresis.
An external undervoltage lockout (UVLO) is sensed and
programmed at the EN pin. The EN UVLO has a rising
threshold of 2.5V with 0.2V of hysteresis. The EN UVLO
should be programmed by connecting a resistive divider
from VIN to EN to GND.
After the VCC, EN, and VIN-to-UGND voltages exceed their
respective voltage thresholds, the IC starts a start-up
process and then ramps up the output voltage to the
setting of output voltage. Connect a RC network from EN
to GND to set a turn-on delay that can be used to sequence
the output voltages of multiple devices.
VCC 4.2V Linear Regulator
VCC is the output terminal of the internal 4.2V linear
regulator which is powered from VIN and provides power
to the APW7080. The linear regulator is designed to be
stable with a low-ESR ceramic output capacitor powers
the internal control circuitry. Bypass VCC to GND with a
ceramic capacitor of at least 0.22µF. Place the capacitor
physically close to the IC to provide good noise
decoupling. The linear regulator is not intended for
powering up any external loads. Do not connect any
external loads to VCC. The linear regulator is also
equipped with current-limit protection to protect itself dur-
ing over-load or short-circuit conditions on VCC pin.
VIN-to-UGND 5.5V Linear Regulator
The built-in 5.5V linear regulator regulates a 5.5V voltage
between VIN and UGND pins to supply bias and gate
charge for the P-channel Power MOSFET gate driver. The
linear regulator is designed to be stable with a low-ESR
ceramic output capacitor of at least 0.22µF. It is also
equipped with current-limit function to protect itself
during over-load or short-circuit conditions between VIN
and UGND.
The APW7080 shuts off the output of the converters when
the output voltage of the linear regulator is below 3.5V
(typical). The IC resumes working by initiating a new soft-
start process when the linear regulator’s output voltage
is above the undervoltage lockout voltage threshold.
Digital Soft-Start
The APW7080 has a built-in digital soft-start to control the
output voltage rise and limit the input current surge
during start-up. During soft-start, an internal ramp,
connected to the one of the positive inputs of the error
amplifier, rises up from 0V to 1V to replace the reference
voltage (0.8V) until the ramp voltage reaches the reference
voltage.
The device is designed with a preceding delay about
10.8ms (typical) before soft-start process.
Output Undervoltage Protection
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the
required regulation range. The undervoltage continually
monitors the FB voltage after soft-start is completed. If a
load step is strong enough to pull the output voltage lower
than the undervoltage threshold, the IC shuts down
converter’s output.
The undervoltage threshold is 70% of the nominal output
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw16
Function Description (Cont.)
voltage. The undervoltage comparator has a built-in 2µs
noise filter to prevent the chips from wrong UVP shut-
down caused by noise. The undervoltage protection works
in a hiccup mode without latched shutdown. The IC will
initiate a new soft-start process at the end of the
preceeding delay.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction tempera-
ture of the APW7080. When the junction temperature ex-
ceeds TJ = +150oC, a thermal sensor turns off the power
MOSFET, allowing the devices to cool. The thermal sensor
allows the converter to start a start-up process and
regulate the output voltage again after the junction
temperature is cooled by 50oC. The OTP is designed
with a 50oC hysteresis to lower the average TJ during con-
tinuous thermal overload conditions, increasing lifetime
of the IC.
Enable/Shutdown
Driving EN to ground places the APW7080 in shutdown.
When in shutdown, the internal power MOSFET turns off,
all internal circuitry shuts down and the quiescent supply
current of VIN reduces to <1µA (typical).
Current-Limit Protection
The APW7080 monitors the output current, flowing through
the P-channel power MOSFET, and limits the current peak
at current-limit level to prevent loads and the IC from
damages during overload or short-circuit conditions.
Frequency Foldback
When the output is shortened to ground, the frequency of
the oscillator will be reduced to about 80kHz. This lower
frequency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s
frequency will gradually increase to its designed rate
when the feedback voltage on FB again approaches 0.8V.
Output Undervoltage Protection (Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw17
Application Information
(V) )
R2
R1
(10.8VOUT +⋅=
Power Sequencing
The APW7080 can operate with sigle or dual power input(s).
In dual-power applications, the voltage (VCC) applied at
VCC pin must be lower than the voltage (VIN) on VIN pin.
The reason is the internal parasitic diode from VCC to VIN
will conduct due to the forward-voltage between VCC and
VIN. Therefore, VIN must be provided before VCC.
Setting Output Voltage
The regulated output voltage is determined by:
(A) D)-(1DI IOUTRMS ⋅⋅=
where D is the duty cycle of the power MOSFET.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current
rating.
VIN
VOUT
CIN
COUT
L
Q1
LX
ESR
ILIOUT
IQ1
ICOUT
D1
VIN
Figure 1 Converter Waveforms
IOUT
VLX
T=1/FOSC
IL
IQ1
ICOUT
IOUT
I
I
DT
VOUT
VOUT
Output Capacitor Selection
An output capacitor is required to filter the output and
supply the load transient current. The filtering requirements
are the function of the switching frequency and the ripple
current (∆I). The output ripple is the sum of the voltages,
having phase shift, across the ESR and the ideal output
capacitor. The peak-to-peak voltage of the ESR is calcu-
lated as the following equations:
DIN
DOUT VV VV
D++
=........... (1)
........... (2)
........... (3)
L · FD)-(1 · V
IOSC
OUT
=∆
(V) ESR · I VESR ∆=
where VD is the forward voltage drop of the diode.
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equation:
Suggested R2 is in the range from 1K to 20kΩ. For
portable applications, a 10kΩ resistor is suggested for
R2. To prevent stray pickup, locate resistors R1 and R2
close to APW7080.
Input Capacitor Selection
It is necessary to turn on the P-channel power MOSFET
(Q1) each time when using small ceramic capacitors for
high frequency decoupling and bulk capacitors to sup-
ply the surge current. Place the small ceramic capcaitors
physically close to the VIN and between VIN and the an-
ode of the Schottky diode (D1)
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than
the maximum input voltage and a voltage rating of 1.5
times is a conservative guideline. The RMS current (IRMS)
of the bulk input capacitor is calculated as the following
equation:
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw18
Application Information (Cont.)
Output Capacitor Selection (Cont.)
(V)
CF8I
VOUTOSC
COUT ⋅⋅ ∆
=∆........... (4)
For the applications using bulk capacitors, the ∆VCOUT
is much smaller than the VESR and can be ignored.
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
shown below:
(V) ESRI VOUT ⋅∆=∆........... (5)
For the applications using ceramic capacitors, the VESR is
much smaller than the ∆VCOUT and can be ignored.
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
close to ∆VCOUT .
The load transient requirements are a function of the
slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a
mix of capacitors and careful layout. High frequency
capacitors initially supply the transient and slow the
current load rate seen by the bulk capacitors. The bulk
filter capacitor values are generally determined by the ESR
(Effective Series Resistance) and voltage rating require-
ments rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the
Equivalent Series Inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness
of the capacitor to high slew-rate transient loading.
Inductor Value Calculation
The operating frequency and inductor selection are
interrelated in that higher operating frequencies permit
the use of a smaller inductor for the same amount of
inductor ripple current. However, this is at the expense of
efficiency due to an increase in MOSFET gate charge
losses. The equation (2) shows that the inductance value
has a direct effect on ripple current.
Accepting larger values of ripple current allows the use of
low inductances, but results in higher output voltage ripple
........... (6)
IN(MAX)IN V V=
Output Diode Selection
The Schottky diode carries load current during the off-time.
The average diode current is therefore dependent on the
P-channel power MOSFET duty cycle. At high input voltages
the diode conducts most of the time. As VIN approaches
VOUT the diode conducts only a small fraction of the time.
The most stressful condition for the diode is when the
output is short-circuited. Therefore, it is important to
adequately specify the diode peak current and average
power dissipation so as not to exceed the diode ratings.
Under normal load conditions, the average current
conducted by the diode is:
OUT
DIN
OUTIN
DI
V V V- V
I⋅
+
=
The APW7080 is equipped with whole protections to
reduce the power dissipation during short-circuit
condition. Therefore, the maximum power dissipation of
the diode is calculated from the maximum output current
as:
D(MAX)D DIODE(MAX) I · V P=
OUT(MAX)OUT I I=
where
where
Remember to keep lead length short and observe proper
grounding to avoid ringing and increased dissipation.
and greater core losses. A reasonable starting point for
setting ripple current is ∆I ≤ 0.4 ⋅ IOUT(MAX) . Remember, the
maximum ripple current occurs at the maximum input
voltage. The minimum inductance of the inductor is
calculated by using the following equation:
1.2
V· L · 380000 )V-(V · V
IN
OUTINOUT ≤
(H)
V· 456000 )V-(V · V
LIN
OUTINOUT
≥
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw19
Layout Consideration
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short, wide printed circuit traces. Signal and
power grounds are to be kept separate and finally
combined using ground plane construction or single
point grounding. Figure 2 illustrates the layout, with bold
lines indicating high current paths. Components along
the bold lines should be placed close together. Below is
a checklist for your layout:
1. Begin the layout by placing the power components
first. Orient the power circuitry to achieve a clean power
flow path. If possible, make all the connections on
one side of the PCB with wide, copper filled areas.
2. In Figure 2, the loops with same color bold lines
conduct high slew rate current. These interconnecting
impedances should be minimized by using wide and
short printed circuit traces.
3. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB.
Therefore, place the feedback divider and the feed-
back compensation network close to the IC to avoid
switching noise. Connect the ground of feedback
divider directly to the GND pin of the IC using a
dedicated ground trace.
4. The VCC decoupling capacitor should be right next
to the VCC and GND pins. Capacitor C2 should be
connected as close to the VIN and UGND pins as
possible.
5. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. The bulk capacitors C8 are
also placed near VIN. Use a wide power ground plane
to connect the C1, C8, C4, and Schottky diode to
provide a low impedance path between the com-
ponents for large and high slew rate current.
R2
LX
EN
2
VIN
1
GND
8
COMP
6
9
U1
APW7080
FB 7
L1
VCC
4
C3
+
VIN
-C1
C5
R4
C6
C4
R1
C7
(Optional)
Load
D1
Feedback
Divider
Compensation
Network
UGND
3
C2 LX 5
+
VOUT
-
C8
Figure 2 Current Path Diagram
Figure 3 Recommended Layout Diagram
Thermal Consideration
In Figure 4, the SOP-8P is a cost-effective package
featuring a small size, like a standard SOP-8, and a
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current
applications. The exposed pad must be soldered to the
top VLX plane. The copper of the VLX plane on the Top layer
conducts heat into the PCB and air. Please enlarge the
area of VLX plan to reduces the case-to-ambient resistance
(θCA).
Exposed
Pad
Die Top
VLX
plane
PCB
Ambient
Air
118 mil
102 mil
SOP-8P
5
6
7
8
1
2
3
4
Figure 4
SOP-8P
5
6
7
8
1
2
3
4
C1
L1
D1
C4
Load
VIN
GND
VOUT
GND
VLX
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw20
Package Information
SOP-8P
0.020
0.010
0.020
0.050
0.006
0.063
MAX.
0.40L
0
E
e
h
E1
0.25
D
c
b
0.17
0.31
0.016
1.27
0.50
1.27 BSC
0.51
0.25
0.050 BSC
0.010
0.012
0.007
MILLIMETERS
MIN.
S
Y
M
B
O
L
A1
A2
A
0.00
1.25
SOP-8P
MAX.
0.15
1.60
MIN.
0.000
0.049
INCHES
D1 2.25 0.098
2.00 0.079
E2
3.50
3.00
0.138
0.118
8o0o8o
0o
h X 45
°
D
e
E
E1
SEE VIEW
A
cb
D1
E2
THERMAL
PAD
A
0
L
VIEW A
0.25
SEATING PLANE
GAUGE PLANE
A1A2
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
4.80 5.00
5.80 6.20
3.80 4.00
0.2440.228
0.1570.150
0.1970.189
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw21
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP- 8(P)
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
(mm)
Carrier Tape & Reel Dimensions
Package Type Unit Quantity
SOP- 8P Tape & Reel 2500
Devices Per Unit
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw22
Reflow Condition (IR/Convection or VPR Reflow)
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
(TL to TP) 3°C/second max. 3°C/second max.
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
Time maintained above:
- Temperature (TL)
- Time (tL) 183°C
60-150 seconds 217°C
60-150 seconds
Peak/Classification Temperature (Tp)
See table 1 See table 2
Time within 5°C of actual
Peak Temperature (tp) 10-30 seconds 20-40 seconds
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Notes: All temperatures refer to topside of the package. Measured on the body surface.
t 25 C to Peak
tp
Ramp-up
tL
Ramp-
down
ts
Preheat
Tsmax
Tsmin
TL
TP
25
Temperature
Time
Critical Zone
TL to TP
°
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA
Reliability Test Program
Copyright ANPEC Electronics Corp.
Rev. A.6 - Jun., 2008
APW7080
www.anpec.com.tw23
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the
stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C)
at the rated MSL level.
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Classification Reflow Profiles (Cont.)
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
