256K x 4 Static RAM
CY7C106
CY7C1006
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Jul
y
9
,
1998
Features
•High speed
—tAA = 12 ns
•CMOS for optimum speed/power
•Low active power
—910 mW
•Low sta n db y pow er
—275 mW
•2.0V data ret enti on (optional)
—100 µW
•A utomatic power-down when desel ected
•TTL-compatibl e inputs and outputs
Functional Description
The CY7C106 and CY7C1006 are high-performance CMOS
stat ic RAMs organi zed as 26 2,144 wo rds b y 4 bits . Easy mem-
ory ex pansion i s p rovi ded by a n act iv e LO W chi p enabl e (CE),
an active LOW output enable (OE), and three-state drivers.
These de vi ces ha v e an autom ati c power -do wn f eat ure that re -
duces powe r consumpti on by m ore than 65% when the devic-
es are deselected.
Writing to the devices is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written int o the location speci-
fied on the address pins (A0 through A17).
Reading from the devices is accomplished by taking chip en-
able (CE) and out put enab l e (OE) LO W while f orc ing write en-
able (W E) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the four I/O pins.
The four input/output pins (I/O 0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LO W ).
The CY7C106 is av ailab le in a standard 400-mil -wide SOJ; t he
CY7C1006 is available in a standard 300-mil-wide SOJ.
LogicBlockDiagram Pin Configuration
C106–1
C106–2
512 x 512 x 4
ARRAY
A1
A0
A10
A12
A11
A13
A14
COLUMN
DECODER
ROW DECODER
SENSE AM PS
POWER
DOWN
OE
INPUTBUFFER
A15
A16
A17
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A1
A2
A3
A4
A5
A6
A7
A8
A17
VCC
A16
A15
A14
A13
I/O3
I/O2
I/O1
I/O0
A9
A0
A10
CE
OE
NC
A12
A11
WE
WE
CE
I/O0
I/O1
I/O2
I/O3
A2
A3
A4
A6
A7
A8
A9
A5
Selectio n Guide 7C106-12
7C1006-12 7C106-15
7C1006-15 7C106-20
7C1006-20 7C106-25
7C1006-25 7C106-35
Maxi m um Access Ti me (ns) 12 15 20 25 35
Maxim um Operating
Current (mA) 165 155 145 130 125
Maxim um Standby
Current (mA) 50 30 30 30 25
CY7C106
CY7C1006
2
Maximum Ratings
(Above which the usefu l l ife may be impa ired. F or user guide-
li nes, not tes ted.)
Storage Temperature ... .. ....... ....... ..............–65°C to +150°C
Ambient Temperature wit h
Power Applied.............................................–55°C to +125°C
Supply Volt age on VCC Relative to GND[1] ....–0.5V to +7.0V
DC Voltage Applied to Output s
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage [1].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......... .. .............. ............. .. .>2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Current.............. .......................................>200 mA
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 5V ± 10%
Electrical Characte ristics Over the Operating Range
Parameter De scription Test Conditi ons
7C106-12
7C1006-12 7C106-15
7C1006-15 7C106-20
7C1006-20
Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+0.3 2.2 VCC
+0.3 2.2 VCC
+0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 –1 +1 µA
IOZ Output Leakage Current GND < VI < VCC,
Output Disabled –5 +5 –5 +5 –5 +5 µA
IOS Output Short
Circ uit Current[3] VCC = Max. , V OUT = G N D –300 –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/t RC
165 155 140 mA
ISB1 Au to m a tic C E
Power-Do wn Current
—TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
50 30 30 mA
ISB2 Au to m a tic C E
Power-Do wn Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0. 3V, f=0
Com’l101010mA
L222
Notes:
1. VIL (min.) = –2.0V f or pul se durati on s of les s than 20 ns .
2. TA is the “instant on” case temperatu re.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C106
CY7C1006
3
Electrical Characte ristics Ov er the Operating Range (continued)
7C106-25
7C1006-25 7C106-35
P aram eter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0 .3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < V I < VCC –1 +1 –1 +1 µA
IOZ Ou tput Leakage Current GND < V I < VCC,
Output Disabled –5 +5 –5 +5 µA
IOS Ou tput Short
Circuit Curren t [3] VCC = Max., V OUT = G ND –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
130 125 mA
ISB1 A u tomatic CE
Power-Down Current
—TTL Input s
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
30 25 mA
ISB2 A u tomatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0. 3V,
VIN > VCC – 0.3V
or VIN < 0.3V, f=0
Com’l 10 10 mA
L22
Capacitance[4]
P arameter De scription Test Conditi ons Max . Unit
CIN: A d dr e ss es Input Capacitance TA = 25 °C, f = 1 MHz,
VCC = 5.0V 7pF
CIN: Controls 10 pF
COUT Output Capacitance 10 pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
C106–3 C106–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<3ns <3n
s
OUTPUT
R1 480ΩR1 48 0Ω
R2
255ΩR2
255Ω
167Ω
Equiv alent to: THÉ VENIN EQUIVALENT
1.73V
CY7C106
CY7C1006
4
Switching Characteristics Over the Operating Range[5]
7C106-12
7C1006-12 7C106-15
7C1006-15 7C106-20
7C1006-20 7C106-25
7C1006-25 7C106-35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 12 15 20 25 35 ns
tAA Address to Data Valid 12 1 5 20 25 35 ns
tOHA Data Hold fro m Address Change 3 3 3 3 3 ns
tACE CE LOW to Data Valid 12 15 20 25 35 ns
tDOE OE LOW to Data Valid 6 7 8 10 10 ns
tLZOE OE LOW to Low Z 0 0 0 0 0 ns
tHZOE OE HIGH to High Z[6,7] 6781010ns
tLZCE CE LOW to Low Z[7] 33333ns
tHZCE CE HIGH to High Z[6,7] 6781010ns
tPU CE LOW to Powe r- Up 0 0 0 0 0 ns
tPD CE HIGH to Power-Down 12 15 20 25 35 ns
WRITE CYCLE[8,9]
tWC Write Cycle Time 12 15 20 25 35 ns
tSCE CE LOW to Write End 1012152025ns
tAW Address Set-Up to Write End1012152025ns
tHA Addr ess Hold f rom Write End 0 0 0 0 0 ns
tSA Address Set-Up to W rite Start 0 0 0 0 0 ns
tPWE WE Pulse Width 1012152025ns
tSD Data Set-Up to Write End 7 8 10 15 20 ns
tHD Data Hold from Write End 0 0 0 0 0 ns
tLZWE WE HIGH to Low Z[7] 23333ns
tHZWE WE LOW to High Z[6,7] 6781010ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30–pF load capac itance.
6. tHZOE, tHZCE, and t HZWE are specif ied with a load capa citan ce of 5 pF a s in part (b) o f A C Test Loads . Transition i s measur ed ±500 mV fr om stea dy-state v oltag e.
7. At any given temperature and voltage condition, tHZCE is les s than tLZCE, tHZOE is less than tLZOE, and tHZWE is le ss than t LZWE for an y giv en de vice .
8. The internal write time of the memory is defined by the overlap of CE and W E LO W. CE and WE mu st be LO W to i nit iate a w rite, and t he tran sition of eith er o f these
signals can terminate the w rite. The input da ta set- up an d hold t iming should be ref e renced to the l eading ed ge of the signal that terminates the write .
9. The minimum write cycle time for Wri te Cycle No. 3 (WE controlled, O E LO W) is th e sum of tHZWE and t SD.
CY7C106
CY7C1006
5
Data Retention Characteristics Over the Operati ng Range (L Version Only)
Parameter Description Conditions[10] Min. Max. Unit
VDR VCC f or Data Retention 2.0 V
ICCDR Data Ret ention Current VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
50 µA
tCDR[4] Ch ip Dese lect to Data Ret ention Time 0ns
tR[4] Oper ati on Recovery Time tRC ns
Data Retention Waveform
4.5V4.5V
CE
VCC tCDR
VDR >2V
DATA RETENTION MODE
tR
C106–5
Switching Waveforms
Read Cycle No.1[11, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Notes:
10. No input may exceed VCC +0.5V.
11. Device is continuously selected, OE and CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE tr ansitio n LO W.
1
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
C106–6
C106–7
50%
50%
DATA VA L I D
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE tHZCE
tPD
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
CY7C106
CY7C1006
6
Write Cycle No. 1 (CE Controll ed)[14, 15]
Write Cycle No. 2 (WE Controlled, OE HIGH During Writ e)[14, 15]
Notes:
14. If CE goes HIGH simultaneousl y with WE g oing HIGH, the output rema ins in a high- impedance state.
15. Data I/O is high impedance if OE = VIH.
Switching Waveforms (contin ued)
C106A–8
tWC
DATA VA L I D
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA I/O
WE
DATA VA LID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE C106–9
ADDRESS
CE
WE
DATA I/O
OE
CY7C106
CY7C1006
7
Document #: 38-00230-C
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15]
Switching Waveforms (contin ued)
DATA VALI D
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE C106–10
ADDRESS
CE
WE
DATA I/O
Truth Table
CE OE WE Input/Output Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Nam e Package Typ e Operating
Range
12 CY7C106–12VC V28 28-Lead (400- Mil) Molded SOJ Commercial
CY7C1006–12VC V21 28-Lead (300- Mil) Molded SOJ
15 CY7C106–15VC V28 28-Lead (400- Mil) Molded SOJ Commercial
CY7C1006–15VC V21 28-Lead (300- Mil) Molded SOJ
20 CY7C106–20VC V28 28-Lead (400- Mil) Molded SOJ Commercial
CY7C1006–20VC V21 28-Lead (300- Mil) Molded SOJ
25 CY7C106–25VC V28 28-Lead (400- Mil) Molded SOJ Commercial
CY7C1006–25VC V21 28-Lead (300- Mil) Molded SOJ
35 CY7C106–35VC V28 28-Lead (400- Mil) Molded SOJ Commercial
Contact factory for “L” version availability.
CY7C106
CY7C1006
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights . Cypress Semiconductor does not authoriz e
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cy press Semiconductor against all charges.
Package Di ag r ams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
28-Lead (400-Mil) Molded SOJ V28
51-85032-A
