Data Sheet SiI3726 SATA Port Multiplier Data Sheet Document # SiI-DS-0121-C1 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Silicon Image, Inc. June, 2006 Silicon Image, Inc. reserves the right to make changes to the product(s) or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable, but Silicon Image, Inc. shall not be responsible for any errors that may appear in this document. Silicon Image, Inc. makes no commitment to update or keep current the information contained in this document. However, no responsibility is assumed for its use; or any infringement of patents or other rights of third parties, which may result from its use. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Silicon Image, Inc. products are not designed or intended for use in Life Support Systems. A Life Support System is a product or system intended to support or sustain life, which if it fails, can be reasonably expected to result in significant personal injury or death. If Buyer or any of its direct or indirect customers applies any product purchased or licensed from Silicon Image, Inc. to any such unauthorized use, Buyer shall indemnify and hold Silicon Image, Inc., its affiliates and their respective suppliers, harmless against all claims, costs, damages and expenses arising directly or indirectly, out of any such unintended or unauthorized use, even if such claims alleges that Silicon Image, Inc. or any other person or entity was negligent in designing or manufacturing the product. Specifications are subject to change without notice Copyright Notice Copyright (c) 2006 Silicon Image, Inc. All rights reserved. These materials contain proprietary and confidential information (including trade secrets, copyright and other interests) of Silicon Image, Inc. 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Further Information To request other materials, documentation, and information, contact your local Silicon Image, Inc. sales office or visit the Silicon Image, Inc. web site at www.siliconimage.com. Revision History Revision A B C Date 4/2005 6/2006 7/2006 Comment Derived from preliminary specification rev. 0.51 Updated green package, Converted to standard format Datasheet is no longer under NDA, removed confidential markings. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 2 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Table of Contents Table of Contents.......................................................................................................................................... 3 Table of Figures ............................................................................................................................................ 5 Table of Tables .............................................................................................................................................. 5 Overview ........................................................................................................................................................ 6 Description ................................................................................................................................................ 6 Features ..................................................................................................................................................... 6 Overall Features ...................................................................................................................................... 6 Robust, High Performance PHY Technology .......................................................................................... 6 Storage System Features........................................................................................................................ 6 Architecture Features .............................................................................................................................. 6 Applications ............................................................................................................................................. 7 Functional Block Diagram ........................................................................................................................... 7 SATA Ports ................................................................................................................................................. 8 LED Modes................................................................................................................................................. 8 Device/Host LED Modes ......................................................................................................................... 8 System LED Modes................................................................................................................................. 8 High Speed Serial Interface Optimization .............................................................................................. 9 PHY Configuration Settings..................................................................................................................... 9 Tx Eye Measurement .............................................................................................................................. 9 GPIO Support .......................................................................................................................................... 10 BIST Support ........................................................................................................................................... 10 Serial ATA Power Mode Request ........................................................................................................... 10 Device Enumeration Sequence ............................................................................................................. 10 Storage Enclosure Support ................................................................................................................... 11 Internal Register Space.............................................................................................................................. 12 General Status and Control (GSCR) Registers .................................................................................... 12 Port Status and Control Registers (PSCR) .............................................................................................. 17 Device Initialization .................................................................................................................................... 20 Auto-Initialization from the EEPROM.................................................................................................... 20 EEPROM Specifications........................................................................................................................ 20 EEPROM Read/Write Operations........................................................................................................... 20 System Reset........................................................................................................................................... 22 Electrical Characteristics........................................................................................................................... 23 Absolute Maximum Ratings................................................................................................................... 23 DC Specifications.................................................................................................................................... 23 SATA Interface DC Specifications ......................................................................................................... 24 CLKI SerDes Input Reference Clock Requirements ............................................................................ 25 SATA Interface Timing Specifications................................................................................................... 25 SATA Interface Transmitter Output Jitter Characteristics .................................................................. 26 Pin Descriptions ......................................................................................................................................... 27 SiI 3726 SATA Port Multiplier Pin-out.................................................................................................... 27 Package Pin Descriptions.......................................................................................................................... 37 Pin Descriptions...................................................................................................................................... 37 Package Information .................................................................................................................................. 38 Dimensions.............................................................................................................................................. 38 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 3 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Part Ordering Numbers: ........................................................................................................................ 39 References............................................................................................................................................... 40 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 4 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Table of Figures Figure 1: SiI 3726 SATA Port Multiplier Block Diagram .................................................................................. 7 Figure 2: Enclosure Management Support Overview................................................................................... 11 Figure 3: I2C Transfer Timing........................................................................................................................ 20 Figure 4: I2C Random Read and Write Timing ............................................................................................. 21 Figure 5: I2C Block Transfer.......................................................................................................................... 22 Figure 6: Power-Up Reset Circuit................................................................................................................. 22 Figure 7: Eye Diagram.................................................................................................................................. 24 Figure 8: Sil3726 Pinout Diagram................................................................................................................. 37 Figure 9: 364 Ball HSBGA Package Dimensions (in Millimeters) ................................................................ 38 Figure 10: Marking Specification - SiI3726CB.............................................................................................. 39 Figure 11: Marking Specification - SiI3726CBHU......................................................................................... 39 Table of Tables Table 1: Device or Host LED Modes and Descriptions................................................................................... 8 Table 2: System LED Modes and Descriptions .............................................................................................. 8 Table 3: PHY Configuration Settings .............................................................................................................. 9 Table 4: SError Bit Definitions....................................................................................................................... 18 Table 5: Absolute Maximum Ratings ............................................................................................................ 23 Table 6: DC Specifications............................................................................................................................ 23 Table 7: SATA Interface DC Specifications ................................................................................................... 24 Table 8: CLK1 SerDes Reference Clock Input Requirements...................................................................... 25 Table 9: SATA Interface Timing Specifications.............................................................................................. 25 Table 10: SATA Interface Transmitter Output Jitter Characteristics (1.5 G) ................................................. 26 Table 11: SATA Interface Transmitter Output Jitter Characteristics (3.0 G).................................................. 26 Table 12: SiI3726 Pin List (Sorted by Pin Name) ......................................................................................... 27 Table 13: SiI3726 Pin List (Sorted by Pin Number) ...................................................................................... 31 Table 14: Power Supply Pin List ................................................................................................................... 36 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 5 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Overview Description Silicon Images SiI 3726 SATA Port Multiplier is 1-to-5 SATA Port Multiplier designed to provide a high performance link between a single SATA host port and five SATA device ports. With its unique data aggregation capability and 3 Gbps serial link capability, the SiI 3726 SATA Port Multiplier is able to take full advantage of 3 Gbps host link bandwidth and FIS-based switching host controllers by bundling together data from device ports and sending it over the 3 Gbps host link. Additionally, the feature-rich SiI 3726 supports all the port multiplier related SATA II extensions allowing system designers to exploit the full potential of SATA in their storage solutions. The SiI 3726 SATA Port Multiplier supports host and device link rates of 1.5 Gbps and 3 Gbps with autonegotiation allowing system designers to utilize 3 Gbps host links with today's 1.5 Gbps hard drives, and to futureproof designs for the emergence of 3 Gbps SATA hard drives. Additionally, the SiI 3726 contains a SATA Enclosure Management Bridge (SEMB) to pass in-band enclosure management information between the host and an enclosure management device. Other important features include, programmable high drive capability for backplane and external applications, asynchronous notification to eliminate the need for host polling to determine if a device has been added or removed, and hot plug support. The SiI 3726 is designed for optimum power, performance and price. It is based on Silicon Images industry leading SATALink technology. It leverages much of the circuit innovation at the physical layer of Silicon Image's proprietary reduced-overhead Multi-layer Serial Link (MSLTM) architecture, which was pioneered and proven with our market-leading PanelLink(R) products. Silicon Image has shipped over 35 million units of PanelLink(R) products for host systems and displays in the PC and the CE markets, notable for their noisy operating conditions. Features Overall Features * * * * * * One-to-five native SATA Port Multiplier Full support for FIS-based switching and command-based switching SATA host controllers Advanced data aggregation architecture for ultra-fast read and write operations with FIS-based switching controllers 21mm x 21mm, 364 pin BGA package with a 20 x 20 array of balls High-speed, native SATA connections to host and device Host and device status and activity LEDs Robust, High Performance PHY Technology * * * * 1.5 Gbps and 3.0 Gbps PHY support with auto-negotiation Compliant with SATA II external PHY specifications Independently programmable PHY settings to support extended PCB trace lengths and external SATA applications Industry proven SATALink technology Storage System Features * * * * * Hot-plug and ATAPI support SATA Enclosure Management Bridge (SEMB) support with I2C interface to the external Storage Enclosure Processor (SEP) Far-end Re-timed loop-back BIST for host initiated system testing Supports host control of hard disk drive staggered spin-up Asynchronous notification support Architecture Features * * Features independent 8 kByte FIFO per device serial ATA channel for reads and writes High performance data movement between all SATA ports SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 6 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Applications * * * Expansion Storage Bricks Disk Shelves Storage Enclosures Functional Block Diagram Figure 1 shows the Block Diagram for the SiI 3726 SATA Port Multiplier. BIST and JTAG Status LED Drivers PLL SATA Host Port Buffer SATA Enclosure Management Bridge Port Multiplier Buffer SATA Device Port0 Buffer SATA Device Port1 Buffer SATA Device Port2 Buffer SATA Device Port3 Buffer SATA Device Port4 Serial EEPROM Figure 1: SiI 3726 SATA Port Multiplier Block Diagram The following sections will describe the features of the port multiplier. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 7 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. SATA Ports The host port supports the SATA-II speed of 3 Gbps and auto-negotiates to 1.5 Gbps to interface with SATA-I host controllers. The device ports operate at SATA-II speeds of 3 Gbps or auto-negotiate to 1.5 Gbps. All ports support hot plug and extended (48 bit LBA) drive capability. LED Modes Device/Host LED Modes Table 1 shows the device or host LED modes and descriptions. The mode is determined by the LED_MODE pin (pin A3). LED pins are open-drain and sink current up to 12mA in their low voltage active state (LED On), or are high impedance in their high voltage non-active state (LED Off). These signals will operate with an external pullup resistor and LED. Each activity will turn on or off LED0 for approximately 70ms. The blinking rate is approximately 400ms on and 400ms off. Table 1: Device or Host LED Modes and Descriptions LED_MODE LED1 LED0 0 (PC mode) 0 (PC mode) 0 (PC mode) 1 (Enterprise mode) 1 (Enterprise mode) Off On Blink Off On Off Off Blink Off Off Description Power on, no device attached PHY communication established, (activity = LED0 On) Error Power on, no device Error System LED Modes Table 2 shows the System LED modes and their descriptions. Table 2: System LED Modes and Descriptions Signal Description LED_S0 EEPROM load error On: Loading error Off: No loading errors System ready On: System is ready Off: System is not ready System error On: System error Off: No system errors LED_S1 LED_S2 In normal operation, if system reset is released, LED_S3 will turn-on while the firmware loads into the SiI 3726 SATA Port Multiplier (~ 1 second). When the firmware load is complete, LED_S1 will turn-on indicating the system is ready to be used. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 8 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. High Speed Serial Interface Optimization In order to accommodate different system environments, the port multiplier allows the designer to configure the device PHYs to support various cable/PCB lengths on each serial I/O independently. PHY Configuration Settings Table 3 shows the configuration settings and description for each high-speed serial port. Pre-emphasis and equalization are used to compensate the signal degradation due to increased cable lengths. Without pre-emphasis or equalization, jitter at the receiver end will increase along with the increase of the cable length, causing signal degradation and Bit Error Rate problems. The effect may depend on the system environment. Factors such as cable quality, PCB implementation, receiver load, etc. all affect the signal quality. Please consult with Silicon Image's technical support department for more information. Table 3: PHY Configuration Settings Serial Port Signal Settings and Description Host Port HIO[2:0] Device #0 Device #1 Device #2 Device #3 Device #4 DAIO[1:0] DBIO[1:0] DCIO[1:0] DDIO[1:0] DEIO[1:0] HIO[2:0] = 0b000 (Default). PC motherboard to device applications up to 1m internal cable, external desktop up to 2m external cable ((2 Meter eSATA cable) or short backplane up to 18 inch of FR4 (0.012 mil trace width with 1 oz copper) HIO[2:0] = 0b001: Tx amplitude will be 100mV lager than 000 setting HIO[2:0] = 0b010 - 0b100 (Reserved. please consult with Silicon Image technical support for this detail): external desktop up to 4m external cable or short backplane up to 30 inch of FR4 (0.012 mil trace width with 1 oz copper) 0b 010: Only pre-emphasis enabled 0b 011: Only equalization enabled 0b111: Both pre-emphasis and equalization enabled HIO[2:0] = 0b101 - 0b111 (Reserved. Contact Silicon Image Technical Support for details): external desktop longer than 4m external cable or short backplane longer than 30 inch of FR4 (0.012 mil trace width with 1 oz copper) 0b010: Only pre-emphasis enabled 0b011: Only equalization enabled 0b111: Both pre-emphasis and equalization enabled DxIO[1:0] = 0b00 (Default): PC motherboard to device applications up to 1m internal cable, external desktop up to 2m external cable (2 Meter eSATA cable) or short backplane up to 18 inch of FR4 (0.012 mil trace width with 1 oz copper) DxIO[1:0] = 0b01: Tx amplitude will be 100mV lager than 00 setting DxIO[1:0] = 0b10 (Reserved. Contact Silicon Image Technical Support): external desktop up to 4m external cable or short backplane up to 30 inch of FR4 (0.012 mil trace width with 1 oz copper). Both pre-emphasis and equalization are enabled DxIO[1:0] = 0b11 (Reserved. Contact Silicon Image Technical Support): external desktop longer than 4m external cable or short backplane longer than 30 inch of FR4 (0.012 mil trace width with 1 oz copper). Both pre-emphasis and equalization are enabled Tx Eye Measurement The SiI 3726 SATA Port Multiplier has the capability to output random (scrambled) and deterministic data patterns (primitives) to downstream devices bypassing the OOB sequence for eye measurement testing. Upon completing the device enumeration process, the port multiplier outputs COM_RESET/COMINIT periodically. This implementation maintains compatibility with the SATA compliant host/device and enables hot plug support. But this implementation also prevents evaluating the Tx eye quality by connecting it directly to the oscilloscope. By bypassing the OOB sequence after the host completes the device enumeration sequence, the Tx will output a random data pattern. The port multiplier can bypass the OOB sequence by setting pin Y12 (OOB_BP) to high. In addition to this, if CONT primitive is disabled by setting pin Y11 (CONT_DIS) to high, the Tx will output a deterministic data pattern. The output generation (1.5 G or 3.0 G) can be selected by pin W12 (TX_GEN). The random data pattern is a scrambled data pattern and useful for eye mask testing. The deterministic pattern is a repetitive pattern of primitives and is useful for jitter analysis. The primitive is normally synchronous and includes Align primitives every 256DWORDs. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 9 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. GPIO Support The 32 bits in General Status and Control Register [130] each correspond to its associated General Purpose Output pin on a write (GPO[31:0]). If the bit is set to 0, the GPO will output a high logic level. Bits [2:9] and [22:29] are not assigned to the pins and the value in the bit field does not effect the operation. The 32 bits in General Status and Control Register [130] each correspond to its associated General Purpose Input pin on a read (GPI[31:0]). If the GPI1 is high, bit 1 will be set. Some of these GPI pins are reserved for various other functions as follows. * Bit fields [12:10 / EMID [2:0] * Bit fields [9:2] / 1000_0000b * Bit fields [24:14] / DEIO[1], DDIO[0], DCIO[1:0], DBIO[1:0], DAIO[1:0] * Bits 27 and 25 / DEIO[0], DDIO[1] GPI pins have internal pull-downs, and GPO pins are initialized to drive low by the firmware. The Read/Write Port Multiplier command can be used to read or write the GSCR. Address 0x0F must be specified in PortNum field of the command FIS in order to read or write the GSCR. The details of the Read/Write Port Multiplier commands are defined in the SATA II Port Multiplier Specification. BIST Support The SiI 3726 SATA Port Multiplier supports far-end retimed loopback BIST only as a target as described by the SATA II Port Multiplier Specification. If the port multiplier receives a BIST activated FIS, it enters BIST mode and loops back the SATA interface. The port multiplier does not propagate the BIST activated FIS to the other ports. Serial ATA Power Mode Request Either the host or the devices may initiate power mode requests. If the request is initiated by the device, upon receipt of the appropriate PMREQ (PMREQ_P or PMREQ_S) request, the port multiplier sends back the PMACK primitives and disables the TxP/TxN pair for the port. If the request is initiated by the host, the port multiplier sends back the PMACK primitives and disables the TxP/TxN pair for the host port. The port multiplier issues the PMREQ to the all attached devices. Upon receipt of PMACK primitives from the physical devices, the TxP/TxN pair will be disabled. Device Enumeration Sequence The device enumeration process is defined in the SATA II Port Multiplier Specification. Upon receipt of the software reset with 0x0F as the PM port number, the SiI 3726 SATA Port Multiplier issues a Register Frame Information Structure (FIS) with the Port Multiplier Signature. Before receiving the software reset with 0x0F as the PM port number, the port multiplier delivers all Frame Information Structures to port 0 regardless of the PM port number value in the receiving FIS. After sending the software reset with 0x0F as the PM port number, the PM aware host resets each device port by programming bit 1 in the SControl register and writing 0xFFFF_FFFF in the SError register to clear the bits in the register. The host should examine the SStatus and SError registers to determine whether or not a device is connected to the device ports. If a device is attached to the port, the host should initialize the device before it using it for a read or a write operation. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 10 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Storage Enclosure Support The SiI 3726 SATA Port Multiplier is compliant with the SATA II port multiplier specification. It has a SATA Enclosure Management Bridge (SEMB) that passes in-band enclosure management data between the host controller and a companion enclosure management device through an I2C bus. SATA HBA SiI3726 SEMB I2C SEP Figure 2: Enclosure Management Support Overview The port multiplier supports the SAF-TE and SES protocols. The host issues Enclosure Management commands through the SATA interface. Enclosure Management commands use the SEP_ATTN commands in the Command register and the SEP command code in the Features register. The SEP command protocol is defined in the SAFTE or SES specification. The I2C interface is multi-master capable and can transfer data at 0 - 400 kbits/s. The SEMB I2C address is 0001xxx0, where xxx are selected using pins EM_ID[2:0]. This allows up to eight SiI 3726 SATA Port Multipliers on the same SEMB I2C bus. The SEP I2C address should be 0xC0, as defined in the SATA II specification. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 11 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Internal Register Space The SiI 3726 SATA Port Multiplier has 32-bit wide registers that control its internal operations. General Status and Control (GSCR) Registers These registers are defined in the SATA II Port Multiplier specification. The Read/Write Port Multiplier command is used to read or write the GSCR registers. Address 0x0F must be specified in the PortNum field of the command FIS in order to read or write the GSCR. The Read/Write Port Multiplier commands are defined in the SATA II Port Multiplier Specification. Bit Addr Name 31 30 29 28 0x00 GSCR[00] Product Identifier 23 22 21 20 15 14 13 7 6 5 Label R/W 27 Device ID 19 Device ID 12 11 Vendor ID 4 3 Vendor ID 26 25 24 18 17 16 10 9 8 2 1 0 Description Default This register defines the Device ID and Vendor ID associated with the SiI 3726. 31:16 Device ID R The default value of 0x3726 identifies the device as Silicon Image SiI3726. 15:0 Vendor ID R This field defaults to 0x1095 to identify the vendor as Silicon Image. Addr 0x01 GSCR[01] Bit Label Name Revision Information 31 30 29 28 0x3726 0x1095 27 26 25 24 19 18 17 16 RSVD0 23 22 15 14 7 6 21 20 RSVD0 12 11 10 9 Revision ID/Chip Revision ID 5 4 3 2 1 RSVD0 PM spec 13 R/W Description 8 0 RSVD0 Default This register defines the revision ID associated with the SiI3726. 31:16 RSVD0 R This bit field is reserved and returns a zero value. 15:8 R Revision This bit field is set to indicate the revision level of the chip design, revision ID/Chip 0x17 is defined by this specification. Revision ID 7:3 RSVD0 R This bit field is reserved and returns a zero value. 2:1 PM spec R This register defines the Port Multiplier Specification Supports. This bit field is set to 0x11 to indicate that SiI 3726 supports the Port Multiplier Specification and 1.1. 0 RSVD0 R This bit field is reserved and returns a zero value. 0x0000 0x17 0b00000 0b00 0b0 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 12 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr Name 0x02 GSCR[02] Port Information 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 RSVD0 23 22 21 20 RSVD0 15 14 13 12 RSVD0 7 6 5 4 3 RSVD0 Bit Label R/W 2 1 Number of Fan-out ports Description 0 Default This register defines port information associated with the SiI3726. 31:4 RSVD0 R This bit field is reserved and returns a zero value. 3:0 Number of Fan-out ports R This bit field is set to 0x06 to indicate that SiI3726 supports one host and five device ports. Addr Name 0x20 GSCR[32] Error Information 31 30 23 22 21 15 14 13 7 6 RSVDRW Bit Label R/W 31:06 5 RSVDRW Error Information Error Information Error Information Error Information Error Information Error Information R/W 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 29 5 Error Informat ion 28 27 RSVDRW 20 19 RSVDRW 12 11 RSVDRW 4 3 Error Error Informat Informat ion ion 0x0000 000 0x6 26 25 24 18 17 16 10 9 8 2 Error Informat ion 1 Error Informat ion 0 Error Informat ion Description Default This bit field is reserved and returns the value written to it. This bit is set to 1 when the bits in port5 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33].. This bit is set to 1 when the bits in port4 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. This bit is set to 1 when the bits in port3 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. This bit is set to 1 when the bits in port2 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. This bit is set to 1 when the bits in port1 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. This bit is set to 1 when the bits in port0 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. 0x0000 0b0 0b0 0b0 0b0 0b0 0b0 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 13 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr Name 0x21 GSCR[33] Error Information Bit Label R/W 31:0 Error Information R/W 31 30 29 23 22 21 15 14 13 7 6 5 28 27 Error Information 20 19 Error Information 12 11 Error Information 4 3 Error Information 26 25 24 18 17 16 10 9 8 2 1 0 Description Default This bit field provides the bits used for error information in the GSCR[32] Error Information register. If the bit set to 1, that bit will be used by the GSCR[32]. Addr Name 31 30 29 28 0x40 GSCR[64] Optional Features Support 23 22 21 20 0x0400 FFFF 27 26 25 24 19 18 17 16 11 10 9 8 3 Async notificati on support 2 Dynami c SSC Transmi t Enable support 1 Issuing PMREQ _P to host support 0 BIST support RSVD0 RSVD0 15 14 13 12 7 6 5 4 RSVD0 RSVD0 Bit Label R/W 31:4 RSVD0 R This bit field is reserved and returns a zero value. 3 Async notification support Dynamic SSC Transmit Enable support Issuing PMREQ_ P to host support BIST support R This bit field is set to 1 to indicate that the SiI3726 supports Asynchronous notification. R This bit field is set to 0 to indicate that the SiI3726 does not support Dynamic SSC Transmit Enable. 0b0 R This bit field is set to 0 to indicate that the SiI3726 does not support issuing PMREQ_P to host. 0b0 R This bit field is set to 1 to indicate that the SiI3726 supports BIST. 0b1 2 1 0 Description Default 0x0000 000 0b1 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 14 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr Name 0x60 GSCR[96] Optional Features Enable 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 Enable Asynchr onous notificati on 2 Enable Dynamic SSC Transmit 1 Enable issuing PMREQ _P to host 0 Enable BIST RSVD0 23 22 21 20 RSVD0 15 14 13 12 RSVD0 7 6 5 4 RSVD0 Bit Label R/W 31:4 RSVD0 R This bit field is reserved and returns a zero value. 3 Enable Asynchron ous notification Enable Dynamic SSC Transmit Enable issuing PMREQ_ P to host Enable BIST R Setting this bit enables Asynchronous notification. R The SiI3726 does not support Dynamic SSC Transmit and setting this bit does not affect the operation. 0b0 R The SiI3726 does not support issuing PMREQ_P to the host and setting this bit does not affect the operation. 0b0 R Setting this bit enables BIST. 0b1 2 1 0 Addr Name 0x03 - 0x1F GSCR[03-31], 0x22 - 0x3F GSCR[34-63], 0x41 - 0x5F GSCR[65-95], 0x61 - 0x7F GSCR[97-127] Reserved Description 31 30 29 28 Default 0x0000 000 0b0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSVD0 23 22 21 20 15 14 13 12 RSVD0 RSVD0 7 6 5 4 RSVD0 Bit Label R/W 31:0 RSVD0 R Description This bit field is reserved and returns a zero value. Default 0x0000 0000 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 15 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr Name 0x80 - 0x81 GSCR[128-129, 0x83 - 0xFF GSCR[131-255] Vendor Unique Bit Label R/W 31:0 Vendor Unique R/W Addr Name 0x82 GSCR[130] GPIO 31 30 29 23 22 21 15 14 13 7 6 5 28 27 Vendor Unique 20 19 Vendor Unique 12 11 Vendor Unique 4 3 Vendor Unique 26 25 24 18 17 16 10 9 8 2 1 0 Description Default These registers define vendor unique and may be used by the firmware. The user shall not access these registers. 31 30 29 28 23 22 21 20 0x0000 0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 GPIO GPIO 15 14 13 12 GPIO 7 6 5 4 GPIO Bit Label R/W Description Default 31:0 GPIO R/W The bit field is corresponding to the GPO pins on a write. If the bit 0 is set, the GPO 0 will output high. The bit field is corresponding to the GPI pins on a read. If the GPI 1 is high, the bit 1 will be set. GPI pins have internal pulldowns, and GPO pins will be initialized to drive low by the firmware. For details, see GPIO Support on page 10. N/A SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 16 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Port Status and Control Registers (PSCR) The registers are defined in the SATA II Extensions to Serial ATA 1.0a Specification. The Read/Write Port Multiplier command may be used to read or write the PSCR. The port number must be specified in the PortNum field of the command FIS in order to read or write the PSCR. The Read/Write Port Multiplier commands are defined in the SATA II Port Multiplier specification. Addr Name 0x00 PSCR[00] SStatus 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 RSVD0 23 22 21 20 RSVD0 15 7 14 13 RSVD0 6 5 SPD 12 IPM 4 3 2 DET Bit Label R/W 31:12 RSVD0 R This bit field is reserved and returns a zero value. Description Default 11:08 IPM R 7:4 SPD R 3:0 DET R This field identifies the current interface power management state. 0000: Device not present or communicating not established 0001: Interface in active state 0010: Interface in partial power management state 0110: Interface in slumber power management state Others: Reserved This field identifies the negotiated interface communication speed. 0000: No negotiated speed 0001: Generation 1 communication rate (1.5 Gb/s) 0010: Generation 2 communication rate (3 Gb/s) Others: Reserved This field indicates the interface device detection and PHY state. 0000: No device detected and PHY communication not established 0001: Device presence detected, but PHY communication not established 0010: Device presence detected and PHY communication established 0110: PHY in off-line mode as a result of the interface being disabled or running in a BIST loopback mode Others: Reserved, no action 0x0000 0 0x0 0x0 0x0 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 17 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr Name 0x01 PSCR[01] SError 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DIAG 23 22 21 20 15 14 13 12 DIAG ERR 7 6 5 4 ERR Bit Label R/W Description Default 31:16 DIAG R/W 0x0000 15:0 ERR R/W This field contains bits as defined in Table 4. Writing a 1 to the register bit clears the B, C, F, N, H, W, and X bits. Writing a 1 to the corresponding bits in the Port Interrupt Status register also clears the F, N, W, and X bits. The B, C, and H bits operate independently of the corresponding Error Counter registers. If the error counters are used, these bits should be ignored. This field is not implemented; all bits are always zero. 0x0000 Table 4: SError Bit Definitions Bit Definition B C D 10b to 8b decode error CRC error Disparity error F I N H R S T W Unrecognized FIS type PHY internal error PHYRDY change Handshake error Reserved Link sequence error Transport state transition error ComWake Description Latched decode error or disparity error from the Serial ATA PHY Latched CRC error from the Serial ATA PHY N/A; always 0. This error condition is combined with the decode error and reported as B errors. Latched unrecognized FIS error from the Serial ATA link N/A; always 0 Indicates a change in the status of the Serial ATA PHY Latched handshake error from the Serial ATA PHY Always 0 N/A; always 0 N/A; always 0 Latched ComWake status from the Serial ATA PHY SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 18 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr Name 0x02 PSCR[02] SControl 31 23 15 7 30 29 22 21 RSVDRW 14 13 SPM 6 5 SPD 28 27 26 25 24 RSVDRW 20 19 18 17 16 12 10 9 8 1 0 PMP 11 IPM 4 3 2 DET Bit Label R/W Description Default 31:20 19:16 RSVDRW PMP R/W R/W 0x000 0x0 15:12 SPM R/W 11:8 IPM R/W 7:4 SPD R/W 3:0 DET R/W This bit field is reserved and returns the value written to it. This field identifies the currently selected Port Multiplier port for accessing the SActive register and some bit fields of the Diagnostic registers. This field selects a power management state. A non-zero value written to this field causes initiation of the select power management state. This field self-resets to 0 as soon as action begins to initiate the power management state transition. 0000: No power management transition requested 0001: Transition to the partial power management state initiated 0010: Transition to the slumber power management state initiated 0100: Transition from a power management state initiated (ComWake asserted) Others: Reserved This field identifies the interface power management states that may be invoked via Serial ATA interface power management capabilities. 0000: No interface power management restrictions (partial and slumber modes enabled) 0001: Transitions to the partial power management state are disabled 0010: Transitions to the slumber power management state are disabled 0011: Transitions to both the partial and slumber power management states are disabled Others: Reserved This field identifies the highest allowed communication speed the interface is allowed to negotiate. 0000: No restrictions (default value) 0001: Limit to Generation 1 (1.5 Gb/s) 0010: Limit to Generation 2 (3.0 Gb/s) Others: Reserved This field controls host adapter device detection and interface initialization. 0000: No action 0001: COMRESET is periodically generated until another value is written to the field 0100: No action Others: Reserved; no action Addr Name 0x03 - 0x0F PSCR[03-15] Reserved 31 30 29 28 23 22 21 20 0x0 0x0 0x0 0x0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSVD0 RSVD0 15 14 13 12 RSVD0 7 6 5 4 RSVD0 Bit Label R/W 31:00 RSVD0 R Description This bit fields are reserved and return a zero value. Default 0x0000 0000 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 19 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Device Initialization Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM EEPROM Specifications The port multiplier requires an external 64 kByte (or two 64 kByte EEPROMs for double buffering) serial EEPROM (400 KHz) memory device. When double buffering is used (for fail over purposes) the primary EEPROM address must be set to "000" and the secondary EEPROM address must be set to "001". When powered-up, the port multiplier verifies the checksum in the primary EEPROM before loading the firmware. If the checksum does not match, the port multiplier loads the firmware from the secondary EEPROM. The firmware contained in the EEPROM is shown below: Address Contents 0x0000 - 0xFFED Code to configure the SiI 3726 0xFFEC - 0xFFF3 System Information, may contain the Serial Number, must be an ASCII string (null terminated) 0xFFF4 - 0xFFF7 Vendor ID and Chip ID 0x10953726 0xFFF8 - 0xFFFB Firmware Revision 0xFFFC - 0xFFFF Signature / CheckSum The sequence of events is as follows: 1. System power-up 2. Code transfer from the EEPROM (I2C) to the SiI 3726 SATA Port Multiplier (boot) 3. The port multiplier starts operating under software control (normal operation) EEPROM Read/Write Operations The timing diagram for read or write operations is shown in Figure 3. The high-level timing for a random read or write is shown in Figure 4. The high-level timing for a block transfer is shown in Figure 5. EPR_SC EPR_SD Start Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ack Stop Figure 3: I2C Transfer Timing S Control Byte Address Hi Address Lo S Control Byte EPR_SC EPR_SD S 1 0 1 0 0 0 0 0 A A7 A6 A5 A4 A3 A2 A1 A0 A A7 A6 A5 A4 A3 A2 A1 A0 A S 1 0 1 0 0 0 0 1 A Random Read Command EPR_SD S 1 0 1 0 0 0 0 0 A A7 A6 A5 A4 A3 A2 A1 A0 A A7 A6 A5 A4 A3 A2 A1 A0 A Random Write Command SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 20 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Figure 4: I2C Random Read and Write Timing SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 21 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. EPR_SC Data LLLL ST 1 DW (R/W) Data LHLL ND 2 3 DW(R/W) 4 DW (R/W) DW (Read) 4 DW (Write) Data LLHH A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Data LHHL Data HLLH Data LHHH A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Data HLHL Data HHLH Data HLHH A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Data HHHL D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 Data HHLL TH Data LHLH D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 Data HHLL TH Data LLHL D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 Data HLLL RD Data LLLH D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 Data HHLH Data HHHH A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 N/A P Data HHHL D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 Data HHHH A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P Figure 5: I2C Block Transfer System Reset System reset (pin A10) must be low whenever the voltage is in or out of operation range and remain for 100 ms after both 1.8V and 3.3V are stable. An example circuit is shown in Figure 6. 3.3 V VCC Reset 0.1uF GND GND System Reset 100K ST Micro STM 809SWX6F or Fairchild FM809SS3X Figure 6: Power-Up Reset Circuit SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 22 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Electrical Characteristics Specifications are for commercial temperature ranges, 0C to +70C, unless otherwise specified. Absolute Maximum Ratings Table 5 specifies the absolute maximum ratings for the device. Table 5: Absolute Maximum Ratings Symbol VDDO VDDA, VDDI VIN VCLKI_IN IOUT JA Parameter I/O supply voltage Core supply voltage Input voltage for 3.3V I/O Input voltage for CLKI DC output current Thermal resistance Rating Unit 4.0 2.15 -0.3 ~ VDDO+0.3 -0.3 ~ VDDA+0.3 16 17.6 V V V V mA C/W DC Specifications Table 6 specifies the DC specifications of the device. Table 6: DC Specifications Type Limits Symbol VDDA VDDI VDDO IDD1.8V VIH VIL IIH IIL IILOD VOH VOL IOZ Parameter Analog supply voltage Digital supply voltage I/O supply voltage 1.8V supply voltage Input high voltage Input low voltage Input high current Input low current Open drain sink current Output high voltage Output low voltage 3-State Leakage Current Condition Minimum Typical Maximum Units 1.71 1.71 3.0 1.8 1.8 3.3 8001 1.89 1.89 3.6 13002 V V V mA V V 2.0 VIN = VDD -10 VIN = VSS -10 0.8 10 10 12 2.4 0.4 A A mA V V A -10 Notes: Note 1: Attached to the 3 G host and all device ports attached to 1.5 G devices. Note 2: Attached to 3 G host and devices. Notes 1 and 2: 3.3V power consumption depends upon the LED, JTAG, I2C and enclosure management status. If all are disabled, 3.3V power consumption will be uA. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 23 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. SATA Interface DC Specifications Table 7 shows the SATA interface DC specifications. Table 7: SATA Interface DC Specifications Type Limits Symbol Parameter Condition Minimum Typical Maximum Units VDOUT_00 TX+/- Differential peak-topeak voltage swing 50 Termination PHY Configuration Setting = 000b for host port and 00b for device ports 500 550 650 mV VDIN VSQ VDOH VACCM VDIH Rx+/Rx- Differential peakto-peak input sensitivity Rx+/Rx- OOB signal detection threshold Tx+/Tx- Differential output common-mode voltage Tx AC common-mode voltage Rx+/Rx- Differential input common-mode voltage ZDIN Tx Pair differential impedance ZDOUT Rx Pair differential impedance ZSIN Tx Single-ended impedance ZSOUT Rx Single-ended impedance 240 Must be AC coupled Must be AC coupled RREF1 = 1 kOhms 1% RREF2 = 4.99 kOhms 1% RREF1 = 1 kOhms 1% RREF2 = 4.99 kOhms 1% RREF1 = 1 kOhms 1% RREF2 = 4.99 kOhms 1% RREF1 = 1 kOhms 1% RREF2 = 4.99 kOhms 1% mV 50 125 240 mV VDD-375 VDD-250 VDD-125 mV 50 mV -50 0 50 mV 85 100 115 85 100 115 40 40 Maximum Amplitude Minimum Amplitude Peak-to peak Total Jitter Figure 7: Eye Diagram SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 24 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. CLKI SerDes Input Reference Clock Requirements Table 8 shows the input reference clock requirements. Table 8: CLK1 SerDes Reference Clock Input Requirements Type Limits Symbol Parameter Condition TCLKI_FREQ Nominal frequency RREF1: 1Kohms 1% RREF2: 4.99Kohms 1% VCLKI_IH Input high voltage - VCLKI_IL Input Low Voltage CLKI frequency tolerance Rise and fall times at CLKI - CLKI duty cycle 20% - 80% TCLKI_J TCLKI_ RISE_FALL TCLKI_ RC_DUTY Minimum Typical Maximum 25 MHz 0.7 x VDDA - Units V -50 25 MHz reference, 20% - 80% 40 0.3 x VDDA V +50 ppm 4 ns 60 % SATA Interface Timing Specifications Table 9 shows the SATA interface timing specifications. Table 9: SATA Interface Timing Specifications Type Limits Symbol Parameter TTX_RISE_FALL Transmitter rise and fall time TTX_DC_FREQ Tx DC Clock frequency skew TTX_AC_RREQ Tx AC Clock frequency skew TTX_SKEW Tx Differential skew Condition 20%-80% at Gen1 20%-80% at Gen2 SerDes Ref_Clk = SSC AC Modulation Maximum Units 85 67 273 136 ps -350 +350 ppm -5000 +0 ppm 15 ps Minimum Typical SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 25 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. SATA Interface Transmitter Output Jitter Characteristics Table 10 and Table 11 show the SATA output jitter characteristics. Table 10: SATA Interface Transmitter Output Jitter Characteristics (1.5 G) Type Limits Symbol Parameter TJ5UI_1.5 G Total Jitter, DataData 5UI DJ5UI_1.5 G Deterministic Jitter, Data-Data 5UI TJ250UI_1.5 G Total Jitter, DataData 250UI DJ250UI_1.5 G Deterministic Jitter, Data-Data 250UI Condition Minimum Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Typical Maximum Units 58 ps 15 ps 55 ps 15 ps Table 11: SATA Interface Transmitter Output Jitter Characteristics (3.0 G) Type Limits Symbol Parameter TJfBAUD/ 10_3.0G Total Jitter, fC3dB=fBAUD/10 DJfBAUD/ 10_3.0G Deterministic Jitter, fC3dB=fBAUD/10 TJfBAUD/ 500_3.0G Total Jitter, fC3dB=fBAUD/50 0 DJfBAUD/ 500_3.0G Deterministic Jitter, fC3dB=fBAUD/50 0 TJfBAUD/ 1667_3.0G Total Jitter, fC3dB=fBAUD/16 67 DJfBAUD/ 1667_3.0G Deterministic Jitter, fC3dB=fBAUD/16 67 Condition Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Minimum Typical Maximum Units 63 ps 16 ps 63 ps 21 ps 86 ps 20 ps SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 26 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Pin Descriptions SiI 3726 SATA Port Multiplier Pin-out Table 12 and Table 13 list the SiI 3726 SATA Port Multiplier pin numbers, names, types, and descriptions. Table 12 is sorted by pin name, and Table 13 is sorted by pin number. Note that NC (No Connect pins) must not be connected to any circuitry on the PCB. Table 12: SiI3726 Pin List (Sorted by Pin Name) Pin Number Pin Name Type Y11 CONT_DIS Input Pull-Down (60 k) D16 DAIO0 Input Pull-Down (60 k) C15 DAIO1 Input Pull-Down (60 k) C11 DBIO0 Input Pull-Down (60 k) C10 DBIO1 Input Pull-Down (60 k) C9 DCIO0 Input Pull-Down (60 k) C8 DCIO1 Input Pull-Down (60 k) C7 DDIO0 Input Pull-Down (60 k) C6 DDIO1 Input Pull-Down (60 k) B5 DEIO0 Input Pull-Down (60 k) B6 DEIO1 Input Pull-Down (60 k) A11 EM_ID0 Input Pull-Down (60 k) B11 EM_ID1 Input Pull-Down (60 k) B10 EM_ID2 Input Pull-Down (60 k) A12 EM_SC I/O Pull-Up (70 k) 4 mA B12 EM_SD I/O Pull-Up (70 k) 4 mA Internal Resistor Description CONT disable in OOB bypass mode. Leave NC for normal operation. For details, see Tx Eye Measurement on page 9. Device0 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device0 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device1 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device1 interface optimization input bit. For details, see High Speed Serial Interface Optimization on page 9. Device2 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device2 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device3 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization. on page 9. Device3 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device4 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device4 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Enclosure management ID input bit 0. This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management ID input bit 1.This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management ID input bit 2 This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management serial clock. This pin is used to send/receive serial clock to/from Enclosure processor, and complies with I2C Bus Specification. For details, see Storage Enclosure Support on page 11. Enclosure management serial data. This pin is used to send/receive serial data to/from Enclosure processor, and complies with I2C Bus Specification. For details, see Storage Enclosure Support on page 11. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 27 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. A9 EPR_SC I/O Pull-Up (70 k) 4 mA B9 EPR_SD I/O Pull-Up (70 k) 4 mA B3 W4 Y4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 W17 Y17 GPI 31 GPO 31 GPO 30 GPO 21 GPO 20 GPO 19 GPO 18 GPO 17 GPO 16 GPO 15 GPO 14 GPO 13 GPO 12 GPO 11 GPO 10 GPO 1 GPO 0 Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Pull-Down (60 k) 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA C14 HIO0 Input Pull-Down (60 k) C13 HIO1 Input Pull-Down (60 k) C12 HIO2 Input Pull-Down (60 k) Y16 LED_A0 Output-Open Drain Pull-Up (70 k) 12 mA W16 LED_A1 Output-Open Drain Pull-Up (70 k) 12 mA Y14 LED_B0 Output-Open Drain Pull-Up (70 k) 12 mA W14 LED_B1 Output-Open Drain Pull-Up (70 k) 12 mA Y7 LED_C0 Output-Open Drain Pull-Up (70 k) 12 mA W7 LED_C1 Output-Open Drain Pull-Up (70 k) 12 mA EEPROM serial clock. This pin is used to send serial clock to EEPROM having I2C interface to download firmware from EEPROM. For details, see Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM on page 20. EEPROM serial data. This pin is used to send/receive serial data to/from EEPROM having I2C interface to download firmware from EEPROM. For details, see Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM on page 20. GPI signal bit 31 GPO signal bit 31 GPO signal bit 30 GPO signal bit 21 GPO signal bit 20 GPO signal bit 19 GPO signal bit 18 GPO signal bit 17 GPO signal bit 16 GPO signal bit 15 GPO signal bit 14 GPO signal bit 13 GPO signal bit 12 GPO signal bit 11 GPO signal bit 10 GPO signal bit 1 GPO signal bit 0 Host interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Host interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Host interface optimization input bit 2. For details, see High Speed Serial Interface Optimization on page 9. LED device port0 [0]. This pin indicates the status of device port0 together with LED_A1 pin. For details, see LED Modes on page 8. LED device port0 [1]. This pin indicates the status of device port0 together with LED_A0 pin. For details, see LED Modes on page 8. LED device port1 [0]. This pin indicates the status of device port1 together with the LED_B1 pin. For details, see LED Modes on page 8. LED device port1 [1]. This pin indicates the status of device port1 together with the LED_B0 pin. For details, see LED Modes on page 8. LED device port2 [0]. This pin indicates the status of device port2 together with the LED_C1 pin. For details, see LED Modes on page 8. LED device port2 [1]. This pin indicates the status of device port2 together with the LED_C0 pin. For details, see LED Modes on page 8. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 28 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Y6 LED_D0 Output-Open Drain Pull-Up (70 k) 12 mA W6 LED_D1 Output-Open Drain Pull-Up (70 k) 12 mA Y5 LED_E0 Output-Open Drain Pull-Up (70 k) 12 mA W5 LED_E1 Output-Open Drain Pull-Up (70 k) 12 mA Y15 LED_H0 Output-Open Drain Pull-Up (70 k) 12 mA W15 LED_H1 Output-Open Drain Pull-Up (70 k) 12 mA A3 LED_MODE Input Pull-Down (60 k) Y13 LED_S0 Output-Open Drain Pull-Up (70 k) 12 mA W13 LED_S1 Output-Open Drain Pull-Up (70 k) 12 mA Y8 LED_S2 Output-Open Drain Pull-Up (70 k) 12 mA W8 LED_S3 Output-Open Drain Pull-Up (70 k) 12 mA A13 A14 A15 A16 A17 A4 B13 B14 B15 B16 B17 B4 H18 H19 J18 K16 M1 M3 M5 N1 N2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC - - LED device port3 [0]. This pin indicates the status of device port3 together with the LED_D1 pin. For details, see LED Modes on page 8. LED device port3 [1]. This pin indicates the status of device port3 together with the LED_D0 pin. For details, see LED Modes on page 8. LED device port4 [0]. This pin indicates the status of device port4 together with the LED_E1 pin. For details, see LED Modes on page 8. LED device port4 [1]. This pin indicates the status of device port4 together with the LED_E0 pin. For details, see LED Modes on page 8. LED host port [0] This pin, together with the LED_H1 pin, indicates the status of the host port. For details, see LED Modes on page 8. LED host port [1]. This pin indicates the status of host port together with the LED_H0 pin. For details, see LED Modes on page 8. Select LED mode. For details, see LED Modes on page 8. System LED [0]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. System LED [1]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. System LED [2]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. System LED [3]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 29 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. N3 W10 W11 W9 Y10 Y9 NC NC NC NC NC NC - - Y12 OOB_BP Input Pull-Down (60 k) J20 PCLKI1 Input - H20 PCLKO1 Output - J19 RREF1 Input - M2 RREF2 Input - A10 RST_N Input-Schmitt Trigger - U19 RXNDA Input - F19 RXNDB Input - D2 RXNDC Input - H2 RXNDD Input - R2 RXNDE Input - L20 RXNH Input - U20 RXPDA Input - F20 RXPDB Input - D1 RXPDC Input - H1 RXPDD Input - R1 RXPDE Input - L19 RXPH Input - A8 B8 A7 B7 TCK TDI TDO TMS Input Input Output Input Pull-Up (70 k) Pull-Up (70 k) Pull-Up (70 k) A6 TRSTN Input Pull-Up (70 k) W12 TX_GEN - Pull-Down (60 k) R20 TXNDA Output - D20 TXNDB Output - F1 TXNDC Output - Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry OOB Bypass mode. Leave NC for normal operation. For details, see Tx Eye Measurement on page 9. Crystal oscillator Input or external clock input (25 MHz crystal) Crystal oscillator output (25 MHz crystal) External reference resistor input, 1 k 1% resistor needs to be connected. External Reference Resistor Input, 4.99 k 1% resistor needs to be connected System Reset. This pin is used to reset the SiI 3726. Serial device port0 differential receiver - input. Must be AC coupled. Serial device port1 differential receiver - input. Must be AC coupled.. Serial device port2 differential receiver - input. Must be AC coupled.. Serial device port3 differential receiver - input. Must be AC coupled.. Serial device port4 differential receiver - input. Must be AC coupled. Serial host port differential receiver - input. Must be AC coupled. Serial device port0 differential receiver + input. Must be AC coupled. Serial device port1 differential receiver + input. Must be AC coupled. Serial device port2 differential receiver + input. Must be AC coupled. Serial device port3 differential receiver + input. Must be AC coupled. Serial device port4 differential receiver + input. Must be AC coupled. Serial HOST port differential receiver + input. Must be AC coupled. JTAG clock JTAG data Input JTAG data output JTAG mode select JTAG reset. This pin must be tied to ground if the JTAG function is not used. Tx generation rate in OOB Bypass mode. Leave NC for normal operation mode. For details, see Tx Eye Measurement on page 9. Serial device port0 differential transmitter - output. Must be AC coupled. Serial device port1 differential transmitter - output. Must be AC coupled. Serial device port2 differential transmitter - output. Must be AC coupled. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 30 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. K1 TXNDD Output - U1 TXNDE Output - N19 TXNH Output - R19 TXPDA Output - D19 TXPDB Output - F2 TXPDC Output - K2 TXPDD Output - U2 TXPDE Output - N20 TXPH Output - Serial device port3 differential transmitter - output. Must be AC coupled. Serial device port4 differential transmitter - output. Must be AC coupled. Serial HOST port differential transmitter - output. Must be AC coupled. Serial device port0 differential transmitter + output. Must be AC coupled. Serial device port1 differential transmitter + output. Must be AC coupled. Serial device port2 differential transmitter + output. Must be AC coupled. Serial device port3 differential transmitter + output. Must be AC coupled. Serial device port4 differential transmitter + output. Must be AC coupled. Serial host port differential transmitter + output. Must be AC coupled. Table 13: SiI3726 Pin List (Sorted by Pin Number) Pin Number Pin Name Type A3 LED_MODE Input Pull-Down (60 k) A4 NC - - A5 GPI 26 Input Pull-Down (60 k) Internal Resistor Description Do not connect to any circuitry A6 TRSTN Input A7 TDO Output - A8 TCK Input Pull-Up (70 k) A9 EPR_SC I/O Select LED mode. For details, see LED Modes on page 8. Pull-Up (70 k) GPI signal bit 26 JTAG reset. This pin must be tied to ground if the JTAG function is not used. JTAG data output Pull-Up (70 k) 4 mA JTAG clock EEPROM serial clock. This pin is used to send serial clock to EEPROM having I2C interface to download firmware from EEPROM. For details, see Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM on page 20. A10 A11 RST_N EM_ID0 InputSchmitt Trigger System Reset. This pin is used to reset SiI 3726 - Input Pull-Down (60 k) Enclosure management ID input bit 0. This pin is used to set the identification number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management serial clock. This pin is used to send/receive serial clock to/from Enclosure processor, and complies with I2C Bus Specification. For details, see Storage Enclosure Support on page 11. A12 EM_SC I/O Pull-Up (70 k) 4 mA A13 NC - - Do not connect to any circuitry A14 NC - - Do not connect to any circuitry A15 NC - - Do not connect to any circuitry A16 NC - - Do not connect to any circuitry A17 NC - - Do not connect to any circuitry SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 31 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. A18 GPI 0 Input Pull-Down (60 k) B3 GPI 31 Input Pull-Down (60 k) B4 NC - - B5 DEIO0 Input Pull-Down (60 k) Device4 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. B6 DEIO1 Input Pull-Down (60 k) Device4 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. B7 TMS Input Pull-Up (70 k) JTAG mode select B8 TDI Input Pull-Up (70 k) JTAG data input B9 EPR_SD I/O GPI signal bit 0 GPI signal bit 31 Do not connect to any circuitry Pull-Up (70 k) 4 mA EEPROM serial data. This pin is used to send/receive serial data to/from EEPROM having I2C interface to download firmware from EEPROM. For details, see Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM on page 20. B10 B11 EM_ID2 EM_ID1 Pull-Down (60 k) Enclosure management ID input bit 2. This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Input Pull-Down (60 k) Enclosure management ID input bit 1. This pin is used to This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management serial data. This pin is used to send/receive serial data to/from Enclosure processor, and complies with I2C Bus Specification. For details, see Storage Enclosure Support on page 11. Input B12 EM_SD I/O Pull-Up (70 k) 4 mA B13 NC - - Do not connect to any circuitry B14 NC - - Do not connect to any circuitry B15 NC - - Do not connect to any circuitry B16 NC - - Do not connect to any circuitry B17 NC - - Do not connect to any circuitry B18 GPI 1 Input Pull-Down (60 k) GPI signal Bit 1 C5 GPI 28 Input Pull-Down (60 k) GPI signal Bit 28 C6 DDIO1 Input Pull-Down (60 k) Device3 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. C7 DDIO0 Input Pull-Down (60 k) Device3 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. C8 DCIO1 Input Pull-Down (60 k) Device2 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. C9 DCIO0 Input Pull-Down (60 k) Device2 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. C10 DBIO1 Input Pull-Down (60 k) Device2 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. C11 DBIO0 Input Pull-Down (60 k) Device1 interface optimization input bit. For details, see High Speed Serial Interface Optimization on page 9. C12 HIO2 Input Pull-Down (60 k) Host interface optimization input bit 2. For details, see High Speed Serial Interface Optimization on page 9. C13 HIO1 Input Pull-Down (60 k) Host interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9.. SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 32 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. C14 HIO0 Input Pull-Down (60 k) Host interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9.. C15 DAIO1 Input Pull-Down (60 k) Device0 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. C16 GPI 13 Input Pull-Down (60 k) GPI signal Bit 13 D1 RXPDC Input - Serial device port2 differential receiver + input. Must be AC coupled. D2 RXNDC Input - Serial device port2 differential receiver + input. Must be AC coupled. D5 GPI 29 Input Pull-Down (60 k) GPI signal Bit 29 D16 DAIO0 Input Pull-Down (60 k) Device0 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. D19 TXPDB Output - Serial device port1differential transmitter + output. Must be AC coupled. D20 TXNDB Output - Serial device port1 differential transmitter - output. Must be AC coupled. F1 TXNDC Output - Serial device port2 differential transmitter - output. Must be AC coupled. F2 TXPDC Output - Serial device port2 differential transmitter + output. Must be AC coupled. F19 RXNDB Input - Serial device port1 differential receiver - input. Must be AC coupled. F20 RXPDB Input - Serial device port1 differential receiver + input. Must be AC coupled. H1 RXPDD Input - Serial device port3 differential receiver + input. Must be AC coupled. H2 RXNDD Input - Serial device port3 differential receiver + input. Must be AC coupled. H18 NC - - Do not connect to any circuitry H19 NC - - Do not connect to any circuitry H20 PCLKO1 Output - Crystal oscillator output (25 MHz crystal) J18 NC - - Do not connect to any circuitry J19 RREF1 Input - External reference resistor input. 1 k 1% resistor needs to be connected. J20 PCLKI1 Input - Crystal oscillator Input or external clock input (25 MHz crystal) K1 TXNDD Output - Serial device port3 differential transmitter - output. Must be AC coupled. K2 TXPDD Output - Serial device port3 differential transmitter - output. Must be AC coupled. K16 NC - - Do not connect to any circuitry L19 RXPH Input - Serial host port differential receiver + input. Must be AC coupled. L20 RXNH Input - Serial host port differential receiver + input. Must be AC coupled. M1 NC - - Do not connect to any circuitry M2 RREF2 Input - External reference resistor input. 4.99 k 1% resistor needs to be connected M3 NC - - Do not connect to any circuitry M5 NC - - Do not connect to any circuitry N1 NC - - Do not connect to any circuitry SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 33 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. N2 NC - - N3 NC - - Do not connect to any circuitry Do not connect to any circuitry N19 TXNH Output - Serial host port differential transmitter - output. Must be AC coupled. N20 TXPH Output - Serial host port differential transmitter + output. Must be AC coupled. R1 RXPDE Input - Serial device port4 differential receiver + input. Must be AC coupled. R2 RXNDE Input - Serial device port4 differential receiver - input. Must be AC coupled. R19 TXPDA Output - Serial device port0 differential transmitter + output. Must be AC coupled. R20 TXNDA Output - Serial device port0 differential transmitter - output. Must be AC coupled. U1 TXNDE Output - Serial device port4 differential transmitter - output. Must be AC coupled. U2 TXPDE Output - Serial device port4 differential transmitter + output. Must be AC coupled. U19 RXNDA Input - Serial device port0 differential receiver - input. Must be AC coupled. U20 RXPDA Input - Serial device port0 differential receiver + input. Must be AC coupled. V5 GPO 21 Output 8 mA GPO signal bit 21 V6 GPO 20 Output 8 mA GPO signal bit 20 V7 GPO 19 Output 8 mA GPO signal bit 19 V8 GPO 18 Output 8 mA GPO signal bit 18 V9 GPO 17 Output 8 mA GPO signal bit 17 V10 GPO 16 Output 8 mA GPO signal bit 16 V11 GPO 15 Output 8 mA GPO signal bit 15 V12 GPO 14 Output 8 mA GPO signal bit 14 V13 GPO 13 Output 8 mA GPO signal bit 13 V14 GPO 12 Output 8 mA GPO signal bit 12 V15 GPO 11 Output 8 mA GPO signal bit 11 V16 GPO 10 Output 8 mA GPO signal bit 10 W4 GPO 31 Output 8 mA GPO signal bit 31 W5 LED_E1 Output-Open Drain Pull-Up (70 k) 12 mA LED device port4 [1]. This pin indicates the status of device port4 together with LED_E0 pin. For details, see LED Modes on page 8. W6 LED_D1 Output-Open Drain Pull-Up (70 k) 12 mA LED device port3 [1]. This pin indicates the status of device port3 together with LED_D0 pin. For details, see LED Modes on page 8. W7 LED_C1 Output-Open Drain Pull-Up (70 k) 12 mA LED device port2 [1]. This pin indicates the status of device port2 together with LED_C0 pin. For details, see LED Modes on page 8. W8 LED_S3 Output-Open Drain Pull-Up (70 k) 12 mA System LED [3]. This pin indicates the status of firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. W9 NC - - Do not connect to any circuitry W10 NC - - Do not connect to any circuitry SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 34 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. W11 NC - - W12 TX_GEN - Pull-Down (60 k) W13 LED_S1 Output-Open Drain Pull-Up (70 k) 12 mA System LED [1]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. W14 LED_B1 Output-Open Drain Pull-Up (70 k) 12 mA LED device port1 [1]. This pin indicates the status of device port1 together with LED_B0 pin. For details, see LED Modes on page 8. W15 LED_H1 Output-Open Drain Pull-Up (70 k) 12 mA LED host port [1]. This pin indicates the status of host port together with LED_H0 pin. For details, see LED Modes on page 8. W16 LED_A1 Output-Open Drain Pull-Up (70 k) 12 mA LED device port0 [1]. This pin indicates the status of device port0 together with LED_A0 pin. For details, see LED Modes on page 8. W17 GPO 1 Output 8 mA GPO signal bit 1 Y4 GPO 30 Output 8 mA GPO signal bit 30 Y5 LED_E0 Output-Open Drain Pull-Up (70 k) 12 mA LED device port4 [0]. This pin indicates the status of device port4 together with LED_E1 pin. For details, see LED Modes on page 8. Y6 LED_D0 Output-Open Drain Pull-Up (70 k) 12 mA LED device port3 [0]. This pin indicates the status of device port3 together with LED_D1 pin. For details, see LED Modes on page 8. Y7 LED_C0 Output-Open Drain Pull-Up (70 k) 12 mA LED device port2 [0]. This pin indicates the status of device port #2 together with LED_C1 pin. For details, see LED Modes on page 8. Y8 LED_S2 Output-Open Drain Pull-Up (70 k) 12 mA System LED [2]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. Y9 NC - - Do not connect to any circuitry Y10 NC - - Do not connect to any circuitry Y11 CONT_DIS Input Pull-Down (60 k) CONT disable in OOB bypass mode. Leave NC for normal operation. For details, see Tx Eye Measurement on page 9. Y12 OOB_BP Input Pull-Down (60 k) OOB bypass mode. Leave NC for normal operation. For details, see Tx Eye Measurement on page 9. Y13 LED_S0 Output-Open Drain Pull-Up (70 k) 12 mA System LED [0]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. Y14 LED_B0 Output-Open Drain Pull-Up (70 k) 12 mA LED device port1 [0]. This pin indicates the status of device port1 together with LED_B1 pin. For details, see LED Modes on page 8. Y15 LED_H0 Output-Open Drain Pull-Up (70 k) 12 mA LED host port [0]. This pin indicates the status of HOST port together with LED_H1 pin. For details, see LED Modes on page 8. Y16 LED_A0 Output-Open Drain Pull-Up (70 k) 12 mA LED device port0 [0]. This pin indicates the status of device port0 together with LED_A1 pin. For details, see LED Modes on page 8. Y17 GPO 0 Output 8 mA Do not connect to any circuitry Tx generation rate in OOB Bypass mode. Leave NC for normal operation mode. For details, see Tx Eye Measurement on page 9. GPO signal bit 0 Table 14: Power Supply Pin List SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 35 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Pin Number Pin Name Type A1, B2, C1, C3, D4, E1, E3, F4, G1, G3, H5 H4, J1, J3, K4, K5, L1, L3 N4, N5, P1, P3 P5, R4, T1, T3, U4, V1 V3, W2, Y1, Y3 D6, D10, D11, D15, E5, E6, E10, E11, E15, E16, F5, T5, T6, T7, T14, T15, T16, U5, U6, U7, U14, U15, U16 D7, D8, D9, D12, D13, D14, E7, E8, E9, E12, E13, E14, T8, T9, T10, T11, T12, T13, U8, U9, U10, U11, U12, U13 P16, P18, P20, R17, T18, T20, U17, V18, V20, W19, Y18, Y20 K18, K20, L17, M16, M18, M20, N17 G18, G20, H17, J16 D17, E18, E20, F17, G16 A20, B19, C18, C20 VDD RX3 VDD TX3 VDD P2 VDD RX4 VDD TX4 3V3DDO Power Power Power Power Power Power VDD (1.8V) for SATA PHY Receiver3 VDD (1.8V) for SATA PHY Transmitter3 VDD (1.8V) for SATA PHY PLL2 VDD (1.8V) for SATA PHY Receiver4 VDD (1.8V) for SATA PHY Transmitter4 VDD I/O (3.3V) Description VDDD Power VDD (1.8V) VDD RX1 Power VDD (1.8V) for SATA PHY Receiver1 VDD TX1 VDD P1 VDD RX2 VDD TX2 Power Power Power Power VDD (1.8V) for SATA PHY Transmitter1 VDD (1.8V) for SATA PHY PLL1 VDD (1.8V) for SATA PHY Receiver2 VDD (1.8V) for SATA PHY Transmitter2 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 36 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Package Pin Descriptions Pin Descriptions Figure 8 shows the Pin-Diagram for the 21 mm x 21 mm BGA with a 20 x 20 array of Balls. 1 2 VDD RX3 VSS LED NC GPI TRS MODE [26] TN TDO TCK EPR SC RST N B VSS VDD RX3 GPI NC DEIO DEIO TMS [31] 0 1 TDI EPR SD EMID EMID EM S [2] [1] D C VDD RX3 VSS DCI O1 DCI O0 DBI O1 D DC RxP DC RxN VSS E VDD RX3 VSS VDD RX3 F DC TxN DC TxP VDD RX3 A G H J K L M N 3 VDD RX3 T U V W Y VSS 5 6 GPI DDI [28] O1 7 DDI O0 8 9 10 11 12 13 14 15 16 17 18 19 20 EMID EM S NC [0] C DBI O0 HI O2 NC NC NC NC GPI [0] VSS VDD TX2 NC NC NC NC NC GPI [1] VDD TX2 VSS B HI O1 HI O0 DAI GPI O1 [13] VSS VDD TX2 VSS VDD TX2 C DB TxN D GPI [29] 3V3 DDO VDD D VDD D VDD D 3V3 DDO 3V3 DDO VDD D VDD D VDD D VSS 3V3 DDO 3V3 DDO VDD D VDD D VDD D 3V3 DDO 3V3 DDO VDD D VDD D VDD D VSS VDD RX3 3V3 DDO VSS VDD RX3 VSS VSS VSS VSS VSS VSS VSS VSS VSS DD RxP DD RxN VSS VDD TX3 VDD RX3 VSS VSS VSS VSS VSS VSS VDD TX3 VSS VDD TX3 VSS VSS VSS VSS VSS VSS VSS DD TxN DD TxP VSS VDD TX3 VDD TX3 VSS VSS VSS VSS VDD TX3 VSS VDD TX3 VSS VSS VSS VSS VSS NC PR EF2 NC VSS NC VSS VSS NC NC NC VDD P2 VDD P2 VSS VDD P2 VSS VDD P2 VSS VDD RX4 VSS DE RxP DE RxN VSS VDD RX4 VSS VDD RX4 VSS VDD RX4 VSS 3V3 DDO 3V3 DDO 3V3 DDO VDD D VDD D VDD D VDD D VDD D VDD D 3V3 DDO DE TxN DE TxP VSS VDD RX4 3V3 DDO 3V3 DDO 3V3 DDO VDD D VDD D VDD D VDD D VDD D VDD D 3V3 DDO VSS VDD TX4 P R 4 VDD RX4 VSS VDD TX4 VDD RX3 VSS 3V3 DDO DAI O0 VDD RX2 VSS DB TxP 3V3 DDO 3V3 DDO VSS VDD RX2 VSS VDD RX2 E VSS VDD RX2 VSS DB RxN DB RxP F VSS VDD RX2 VSS VDD P1 VSS VDD P1 VSS VSS VSS VDD P1 NC NC PCL KO1 VSS VSS VSS VDD P1 VSS NC PR EF1 PCL KI1 VSS VSS VSS VSS NC VSS VDD TX1 VSS VDD TX1 VSS VSS VSS VSS VSS VSS VDD TX1 VSS H RxP H RxN VSS VSS VSS VSS VSS VSS VDD TX1 VSS VDD TX1 VSS VDD TX1 VSS VSS VSS VSS VSS VSS VSS VSS VDD TX1 VSS H TxN H TxP VSS VSS VSS VSS VSS VSS VSS VDD RX1 VSS VDD RX1 VSS VDD RX1 VSS VDD RX1 VSS DA TxP DA TxN 3V3 DDO 3V3 DDO VSS VDD RX1 VSS VDD RX1 3V3 DDO 3V3 DDO VDD RX1 VSS DA RxN DA RxP VSS VDD RX1 VSS VDD RX1 W Y GPO GPO GPO GPO GPO GPO GPO GPO GPO GPO GPO GPO [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] VSS GPO LED LED LED LED NC [31] E[1] D[1] C[1] S[3] NC TX LED LED LED LED GEN S[1] B[1] H[1] A[1] GPO [1] VSS VDD RX1 VSS GPO LED LED LED LED NC [30] E[0] D[0] C[0] S[2] NC CONT OOB LED LED LED LED _DIS _BP S[0] B[0] H[0] A[0] GPO [0] VDD RX1 VSS VDD RX1 VDD TX4 VSS VDD TX4 1 2 3 4 5 6 7 A 8 9 NC G H J K L M N P R T U V 10 11 12 13 14 15 16 17 18 19 20 Figure 8: Sil3726 Pinout Diagram SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 37 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Package Information Dimensions Figure 9 shows the dimensions of the 364-Ball HSBGA package. 1.00 0.50 0.36 0.85 Figure 9: 364 Ball HSBGA Package Dimensions (in Millimeters) SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 38 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Part Ordering Numbers: * SiI3726CB (364-pin BGA, standard package) shown in Figure 10. * SiI3726CBHU (364-pin BGA, green package) shown in Figure 11. Pin 1 Designator Location Logo Trademark SiI3726CB LLLLLL.LLLL YYWW XXXXXXX SiI Part No. Lot No. (= Job No.) Date Code Trace No. Figure 10: Marking Specification - SiI3726CB Pin 1 Designator Location Logo Trademark SiI3726CBHU LLLLLL.LLLL YYWW XXXXXXX SiI Part No. Lot No. (= Job No.) Date Code Trace No. Figure 11: Marking Specification - SiI3726CBHU SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 39 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. References For more details about Serial ATA technology, refer to the following industry specifications: * Serial ATA /High Speed AT Attachment Specification, Revision 1.0a * Serial ATA II: Extensions to Serial ATA 1.0a, Revision 1.2 * Serial ATA II: Port Multiplier, Revision 1.1 and Revision 1.2 Release Candidate * Serial ATA II: Electrical Specification, Revision 1.0 * Serial ATA II: Cables and Connectors, Volumes 1 and 2 SiI-DS-0121-C1 (c) 2006 Silicon Image, Inc. 40 SiI3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Disclaimers These materials are provided on an "AS IS" basis. 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