© 2005 Fairchild Semiconductor Corporation DS005341 www.fairchildsemi.com
September 1983
Revised May 2005
MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Descript ion
The MM74HC540 and MM74HC541 3-STATE buffers uti-
lize advanced silicon-gate CMOS technology. They pos-
sess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
cir cui try, i.e. , high nois e immu nit y, an d low po wer consu mp-
tion. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC5 41 offers a pinout h aving inputs and o utputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
■Typical propagation delay: 12 ns
■3-STATE outputs for connection to system buses
■Wide power supply range: 2–6V
■Low quiescent current: 80
P
A maximum (74HC Series)
■Output current: 6 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix let t er “X” to th e ordering co de.
Connection Diagrams
Pin A ssignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC540
Top View
MM74HC541
Order Number Package Number Package Description
MM74HC540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC540N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com 2
MM74HC540 • MM74HC541
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings a re those va lues beyon d which d am-
age to the device may occur.
Note 2: Unless ot herwise sp ec ified all voltages are r ef erenced to ground.
Note 3: Power Dis sipation temp erature de rating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics (Note 4)
Note 4: For a power supply of 5V
r
10% t he wor st case ou tput vo ltages (V OH, and VOL) occur for HC a t 4.5V. Thus t he 4.5V values s hould be used w hen
designing with this sup ply. Worst case VIH and VIL occur at VCC
5.5V a nd 4.5V res pectively. (T he VIH value at 5. 5V is 3.8 5V.) Th e w orst cas e leakage cur-
rent (IIN, I CC, and IOZ) occur fo r C M OS at the hi gher voltage and so th e 6.0V valu es s hould be u s ed.
Supply Voltage (VCC)
0.5 to
7.0V
DC Input Voltage (VIN)
1.5 to VCC
1.5V
DC Output Voltage (VOUT)
0.5 to VCC
0.5V
Clamp Diode Current (ICD)
r
20 mA
DC Output Current, per pin (IOUT)
r
35 mA
DC VCC or GND Current,
per pin (ICC)
r
70 mA
Storage Temperature Range (TSTG)
65
q
C to
150
q
C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 se conds) 260
q
C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage
(VIN, VOUT)0V
CC V
Operating Temperature Range (TA)
40
85
q
C
Input Rise or Fall Times
(tr, tf) VCC
2.0V 1000 ns
VCC
4.5V 500 ns
VCC
6.0V 400 ns
Symbol Parameter Conditions VCC TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guar ant eed Lim i ts
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input V olt age 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input V olt age 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN
VIH or VIL
Output Voltage |IOUT|
d
20
P
A 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN
VIH or VIL
|IOUT|
d
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT|
d
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN
VIH or VIL
Output Voltage |IOUT|
d
20
P
A 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN
VIH or VIL
|IOUT|
d
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT|
d
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN
VCC or GND 6.0V
r
0.1
r
1.0
r
1.0
P
A
Current
IOZ Maximum 3-S TATE VIN
VIH or VIL, G
VIH 6.0V
r
0.5
r
5
r
10
P
A
Output Leakage VOUT
VCC or GND
Current
ICC Maximum Quiescent VIN
VCC or GND 6.0V 8.0 80 160
P
A
Supply Current IOUT
0
P
A
3 www.fairchildsemi.com
MM74HC540 • MM74HC541
AC Electrical Characteristics
VCC
5V, TA
25
q
C, tr
tf
6 ns
AC Electrical Characteristics
VCC
2.0V to 6.0V, CL
50 pF, tr
tf
6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynamic power consumption, PD
CPD VCC2f
ICC VCC, and the no load dy namic cu rrent consumptio n,
IS
CPD VCC f
ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL, tPLH Maximum Propagation CL
45 pF 12 18 ns
Delay (540)
tPHL, tPLH Maximum Propagation CL
45 pF 14 20 ns
Delay (541)
tPZH, tPZL Maximum Output Enable RL
1 k
:
17 28 ns
Time CL
45 pF
tPHZ, tPLZ Maximum Output Disable RL
1 k
:
15 25 ns
Time CL
5 pF
Symbol Parameter Conditions VCC TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guaranteed Limits
tPHL, tPLH Maximum Propagation CL
50 pF 2.0V 55 100 126 149 ns
Delay (540) CL
150 pF 2.0V 83 150 190 224 ns
CL
50 pF 4.5V 12 20 25 30 ns
CL
150 pF 4.5V 22 30 38 45 ns
CL
50 pF 6.0V 11 17 21 25 ns
CL
150 pF 6.0V 18 26 32 38 ns
tPHL, tPLH Maximum Propagation CL
50 pF 2.0V 58 115 145 171 ns
Delay (541) CL
150 pF 2.0V 83 165 208 246 ns
CL
50 pF 4.5V 14 23 29 34 ns
CL
150 pF 4.5V 17 33 42 49 ns
CL
50 pF 6.0V 11 20 25 29 ns
CL
150 pF 6.0V 14 28 35 42 ns
tPZH, tPZL Maximum Output Enable RL
1 k
:
Time CL
50 pF 2.0V 75 150 189 224 ns
CL
150 pF 2.0V 100 200 252 298 ns
CL
50 pF 4.5V 15 30 38 45 ns
CL
150 pF 4.5V 30 40 50 60 ns
CL
50 pF 6.0V 13 26 32 38 ns
CL
150 pF 6.0V 17 34 43 51 ns
tPHZ, tPLZ Maximum Output Disable RL
1 k
:
2.0V 75 150 189 224 ns
Time CL
50 pF 4.5V 15 30 38 45 ns
6.0V 13 26 32 38 ns
tTHL, tTLH Maximum Output Rise CL
50 pF 2.0V 25 60 75 90 ns
and Fall Time 4.5V 7 12 15 18 ns
6.0V 6 10 13 15 ns
CPD Power Dissipation G
VIH 10 pF
Capacitance (Note 5) G
VIL 50 pF
CIN Maximum Input 5 10 10 10 pF
Capacitance
COUT Maximum Output Capacitance 15 20 20 20 pF
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MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5 www.fairchildsemi.com
MM74HC540 • MM74HC541
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com 6
MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7 www.fairchildsemi.com
MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses are im plied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use provided in the l abe li ng, can be re a-
sonably expected to result in a significant injury to the
user.
2. A crit ical com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t
device or system, or to affect its safety or effectiveness.
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