BC857CWH6327 - INFINEON TECHNOLOGIES AG

 2013-2015 Microchip Technology Inc. DS40001729C-page 1

PIC16(L)F1705/9

Description

PIC16(L)F1705/9 microcontrollers combine Intelligent analog integration with low cost and extreme low-power (XLP) to

suit a variety of general purpose applications. These 14- and 20-pin devices deliver on-chip op amps, core independent

peripherals (CLC and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased design flexibility.

Core Features

• C Compiler Optimized RISC Architecture

• Only 49 Instructions

• Operating Speed:

- 0-32 MHz

- 125 ns minimum instruction cycle

• Interrupt Capability

• 16-Level Deep Hardware Stack

• Four 8-bit Timers

• One 16-bit Timer

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Low-Power Brown-Out Reset (LPBOR)

• Programmable Watchdog Timer (WDT) up to

256s

• Programmable Code Protection

Memory

• 8 Kwords Flash Program Memory

• 1024 Bytes Data SRAM Memory

• Direct, Indirect and Relative Addressing modes

• High Endurance Flash Data Memory (HEF)

- 128 bytes of nonvolatile data storage

- 100k erase/write cycles

Operating Characteristics

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1705/9)

- 2.3V to 5.5V (PIC16F1705/9)

• Temperature Range:

- Industrial: -40°C to 85°C

- Extended: -40°C to 125°C

eXtreme Low-Power (XLP) Features

• Sleep mode: 50 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Secondary Oscillator: 500 nA @ 32 kHz

• Operating Current:

- 8 uA @ 32 kHz, 1.8V, typical

- 32 uA/MHz @ 1.8V, typical

Digital Peripherals

• Configurable Logic Cell (CLC):

- Integrated combinational and sequential logic

• Complementary Output Generator (COG):

- Rising/falling edge dead-band control/

blanking

• Capture/Compare/PWM (CCP) module

• PWM: Two 10-bit Pulse-Width Modulators

• Serial Communications:

- SPI, I2C, RS-232, RS-485, LIN compatible

- Auto-Baud Detect, auto-wake-up on start

• Up to 17 I/O Pins plus One Input-Only Pin:

- Individually programmable pull-ups

- Slew rate control

- Interrupt-on-change with edge-select

• Peripheral Pin Select (PPS):

- Enables pin mapping of digital I/O

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Low-power 32 kHz secondary oscillator

driver

• Timer2/4/6: 8-Bit Timer/Counter with 8-Bit Period

Intelligent Analog Peripherals

• Operational Amplifiers:

- Two configurable rail-to-rail op amps

- Selectable internal and external channels

- 2 MHz gain bandwidth product

• High-Speed Comparators:

- Two comparators

- 50 ns response time

- Rail-to-rail inputs

• 10-Bit Analog-to-Digital Converter (ADC):

- Up to 12 external channels

- Conversion available during Sleep

- Temperature indicator

Cost-Effective 8-Bit Intelligent Analog Flash Microco ntrollers

PIC16(L)F1705/9

DS40001729C-page 2  2013-2015 Microchip Technology Inc.

Intelligent Analog Peripherals (Cont.)

• Zero-Cross Detector (ZCD):

- Detect when AC signal on pin crosses

ground

• 8-Bit Digital-to-Analog Converter (DAC):

- Output available externally

- Internal connections to comparators, op

amps, Fixed Voltage Reference (FVR) and

ADC

• Internal Voltage Reference module

Clocking Structure

• 16 MHz Internal Oscillator Block:

- ±1% at calibration

- Selectable frequency range from 0 to 32 MHz

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- Three crystal/resonator modes up to 20 MHz

- Two external clock modes up to 20 MHz

• Fail-Safe Clock Monitor

• Two-Speed Oscillator Start-up

• Oscillator Start-up Timer (OST)

Programming/Debug Features

• In-Circuit Debug Integrated On-Chip

• Emulation Header for Advanced Debug:

- Provides trace, background debug and up to

32 hardware break points

• In-Circuit Serial Programming™ (ICSP™) via Two

Pins

PIC16(L)F170x Famil y Types

Device

Data Sheet Index

Program Memory

Flash (words)

Data SRAM

(bytes)

High-Endurance

Flash (bytes)

I/O’s(2)

10-bit ADC (ch)

8-bit DAC

High-Speed/

Comparators

Op Amp

Zero C r os s

Timers

(8/16-bit)

CCP

PWM

COG

EUSART

MSSP (I2C/SPI)

CLC

PPS

Debug(1)

XLP

PIC16(L)F1703 (3) 2048 256 128 12 8 0 0 2 1 2/1 200010YI/E Y

PIC16(L)F1704 (1) 4096 512 128 12 8 1 2 2 1 4/1 221113YI/E Y

PIC16(L)F1705(2)81921024128128 1 2 2 1 4/1 221113YI/EY

PIC16(L)F1707 (3) 2048 256 128 18 12 0 0 2 1 2/1 200010YI/E Y

PIC16(L)F1708 (1) 4096 512 128 18 12 1 2 2 1 4/1 221113YI/E Y

PIC16(L)F1709(2)8192102412818121 2 2 1 4/1 221113YI/EY

Note 1: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS40001715 PIC16(L)F1704/8 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers.

2: DS40001729 PIC16(L)F1705/9 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers.

3: DS40001722 PIC16(L)F1703/7 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers

Note: For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

 2013-2015 Microchip Technology Inc. DS40001729C-page 3

PIC16(L)F1705/9

Pin Diagrams

FIGURE 1: 14-PIN PDIP, SOIC, TSSOP

FIGURE 2: 16- P IN QFN

PIC16(L)F1705

VDD

RA5

RA4

VPP/MCLR/RA3

RC5

RC4

RC3

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RC0

RC1

RC2

VSS

RC4

VSS

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RC0

VDD

RA5

RA4

RA3/MCLR/VPP

RC5

RC3

RC2

RC1

PIC16(L)F1705

PIC16(L)F1705/9

DS40001729C-page 4  2013-2015 Microchip Technology Inc.

FIGURE 3: 20-PIN PDIP, SOIC, SSOP

FIGURE 4: 20- P IN QFN

PIC16(L)F1709

VDD

RA5

RA4

VPP/MCLR/RA3

RC5

RC4

RC3

RC6

RC7

RB7

ICSPDAT/RA0

ICSPCLK/RA1

RA2

RC0

RC1

RC2

RB4

RB5

RB6

VSS

PIC16(L)F1709

RB4

RB5

RB6

RB7

RC7

VPP/MCLR/RA3

RC5

RC4

RC3

RC6

RA4

RA5

VDD

VSS

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RC0

RC1

RC2

 2013-2015 Microchip Technology Inc. DS40001729C-page 5

PIC16(L)F1705/9

Pin Allocation Tables

TABLE 1: 14/16-PIN ALLOCATION TABLE (PIC16(L)F1705)

I/O(2)

14-Pin P DIP/SOI C/TS SOP

16-Pin QFN

ADC

Reference

Comparator

Op Amp

DAC

Zero Cross

Timers

CCP

PWM

COG

MSSP

EUSART

CLC

Interrupt

Pull-up

Basic

RA0 13 12 AN0 VREF-C1IN+ —DAC1OUT1 — — — — — — — — IOC YICSPDAT

RA1 12 11 AN1 VREF+C1IN0-

C2IN0-

——————————IOC YICSPCLK

RA2 11 10 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1)

IOC

Y —

RA3 4 3 — — —— — ——— — ————IOC YMCLR

VPP

RA4 3 2 AN3 — — — — — T1G(1)

SOSCO

— — — — — — IOC YCLKOUT

OSC2

RA5 2 1 — — —— — —T1CKI(1)

SOSCI

—————

CLCIN3(1) IOC YCLKIN

OSC1

RC0 10 9AN4 —C2IN+ OPA1IN+ — — — — — — SCK(1)

SCL(3) — — IOC Y —

RC1 9 8 AN5 —C1IN1-

C2IN1-

OPA1IN- — — — — — — SDI(1)

SDA(3) —CLCIN2(1) IOC Y —

RC2 8 7 AN6 —C1IN2-

C2IN2-

OPA1OUT — — — — — — — — — IOC Y —

RC3 7 6 AN7 —C1IN3-

C2IN3-

OPA2OUT — — —CCP2(1) ——SS

(1) —CLCIN0(1) IOC Y —

RC4 6 5 — — — OPA2IN- — — — — — — — CK(1) CLCIN1(1) IOC Y —

RC5 5 4 — — —OPA2IN+ — — —CCP1(1) ———RX

(1,3) —IOC Y —

VDD 116 — — — — — — — — — — — — — — — VDD

VSS 14 13 — — — — — — — — — — — — — — — VSS

OUT(2)

— — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3) CK CLC1OUT — — —

— — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — —

— — — — — — — — — — — COGC SDO TX CLC3OUT — — —

————— — — ——— —COGDSCK—————

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F1705/9

DS40001729C-page 6  2013-2015 Microchip Technology Inc.

TABLE 2: 20-PIN ALLOCATION TABLE (PIC16(L)F1709)

I/O(2)

20-Pin PDIP/

SOIC/SSOP

20-Pin QFN

ADC

Reference

Comparator

Op Amp

DAC

Zero Cross

Timers

CCP

PWM

COG

MSSP

EUSART

CLC

Interrupt

Pull-up

Basic

RA0 19 16 AN0 VREF-C1IN+ —DAC1OUT1 — — — — — — — — IOC YICSPDAT

RA1 18 15 AN1 VREF+C1IN0-

C2IN0-

——————————IOC YICSPCLK

RA2 17 14 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1)

IOC

Y —

RA3 4 1 — — —— — ——— — ————IOC YMCLR

VPP

RA4 320 AN3 — — — — — T1G(1)

SOSCO

— — — — — — IOC YCLKOUT

OSC2

RA5 219 — — —— — —T1CKI

SOSCI

—————CLCIN3(1) IOC YCLKIN

OSC1

RB4 13 10 AN10 — — OPA1IN- — — — — — — SDI(1)

SDA(3) ——IOC Y —

RB5 12 9AN11 — — OPA1IN+ — — —— — ——RX

(1,3) —IOC Y —

RB6 11 8— — — — — — — — — — SCK(1)

SCL(3) ——IOC Y —

RB7 10 7 — — —— — ——— — ——CK

(1) —IOC Y —

RC0 16 13 AN4 —C2IN+ — — — — — — — — — — IOC Y —

RC1 15 12 AN5 —C1IN1-

C2IN1-

—————————CLCIN2(1) IOC Y —

RC2 14 11 AN6 —C1IN2-

C2IN2-

OPA1OUT — — — — — — — — — IOC Y —

RC3 7 4 AN7 —C1IN3-

C2IN3-

OPA2OUT — — —CCP2(1) ————CLCIN0(1) IOC Y —

RC4 6 3 — — — — — — — — — — — — CLCIN1(1) IOC Y —

RC5 5 2 — — —— — ——CCP1(1) —————IOC Y —

RC6 8 5 AN8 — — OPA2IN- — — — — — — SS(1) — — IOC Y —

RC7 9 6 AN9 ——OPA2IN+ — — — — — — — — — IOC Y —

VDD 118 — — — — — — — — — — — — — — — VDD

VSS 20 17 — — — — — — — — — — — — — — — VSS

OUT(2)

— — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3) CK CLC1OUT — — —

— — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — —

— — — — — — — — — — — COGC SDO TX CLC3OUT — — —

————— — — ——— —COGDSCK—————

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

 2013-2015 Microchip Technology Inc. DS40001729C-page 7

PIC16(L)F1705/9

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 17

3.0 Memory Organization ................................................................................................................................................................. 19

4.0 Device Configuration.................................................................................................................................................................. 47

5.0 Resets ........................................................................................................................................................................................ 53

6.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 61

7.0 PIC16(L)F1705/9 Interrupts........................................................................................................................................................ 79

8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 92

9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 96

10.0 Flash Program Memory Control ............................................................................................................................................... 101

11.0 I/O Ports ................................................................................................................................................................................... 118

12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 137

13.0 Interrupt-On-Change ................................................................................................................................................................ 144

14.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 151

15.0 Temperature Indicator Module ................................................................................................................................................. 154

16.0 Comparator Module.................................................................................................................................................................. 156

17.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 165

18.0 Complementary Output Generator (COG) Module................................................................................................................... 171

19.0 Configurable Logic Cell (CLC).................................................................................................................................................. 203

20.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 218

21.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 232

22.0 8-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 235

23.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 239

24.0 Timer0 Module ......................................................................................................................................................................... 243

25.0 Timer1 Module with Gate Control............................................................................................................................................. 246

26.0 Timer2/4/6 Module ................................................................................................................................................................... 257

27.0 Capture/Compare/PWM Modules ............................................................................................................................................ 262

28.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 270

29.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 323

30.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 354

31.0 Instruction Set Summary.......................................................................................................................................................... 356

32.0 Electrical Specifications............................................................................................................................................................ 370

33.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 403

34.0 Development Support............................................................................................................................................................... 425

35.0 Packaging Information.............................................................................................................................................................. 429

Appendix A: Data Sheet Revision History.......................................................................................................................................... 450

The Microchip Website ...................................................................................................................................................................... 451

Customer Change Notification Service .............................................................................................................................................. 451

Customer Support .............................................................................................................................................................................. 451

Product Identification System ............................................................................................................................................................ 452

Worldwide Sales and Service ............................................................................................................................................................ 454

PIC16(L)F1705/9

DS40001729C-page 8  2013-2015 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

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enhanced as new volumes and updates are introduced.

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Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer No tific atio n Syst em

 2013-2015 Microchip Technology Inc. DS40001729C-page 9

PIC16(L)F1705/9

1.0 DEVICE OVERVIEW

The PIC16(L)F1705/9 are described within this data

sheet. They are available in 14-pin and 20-pin DIP

packages and 16-pin and 20-pin QFN packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1705/9 devices. Table 1-2 shows the pinout

descriptions.

Reference Table 1-1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1705

PIC16(L)F1709

Analog-to-Digital Converter (ADC) ●●

Digital-to-Analog Converter (DAC) ●●

Complementary Output Generator (COG) ●●

Fixed Voltage Reference (FVR) ●●

Zero-Cross Detection (ZCD) ●●

Temperature Indicator ●●

Capture/Compare/PWM (CCP/ECCP) Modules

CCP1 ●●

CCP2 ●●

Comparators

C1 ●●

C2 ●●

Configurable Logic Cell (CLC)

CLC1 ●●

CLC2 ●●

CLC3 ●●

Enhanced Universal Synchronous/Asynchronous

Receiver/Transmitter (EUSART)

EUSART ●●

Master Synchronous Serial Ports

MSSP ●●

Op Amp

Op Amp 1 ●●

Op Amp 2 ●●

Pulse-Width Modulator (PWM)

PWM3 ●●

PWM4 ●●

Timers

Timer0 ●●

Timer1 ●●

Timer2 ●●

PIC16(L)F1705/9

DS40001729C-page 10  2013-2015 Microchip Technology Inc.

FIGURE 1-1: PIC16( L) F1705 /9 BLOCK DIAGRAM

PORTA

PORTB(1)

PORTC

Note 1: PIC16(L)F1709 only.

2: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

RAM

Timing

Generation

LFINTOSC

Oscillator

MCLR

Figure 2-1

CLKIN

CLKOUT

ADC

10-Bit FVR

Temp .

Indicator EUSART

Comparators

MSSPTimer2Timer1Timer0

DAC CCPs

PWMOp Amps

HFINTOSC/

CLCs

COG

ZCD

 2013-2015 Microchip Technology Inc. DS40001729C-page 11

PIC16(L)F1705/9

TABLE 1-2: PIC16(L)F1705 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/VREF-/C1IN+/

DAC1OUT/ICSPDAT

RA0 TTL/ST CMOS General purpose I/O.

AN0 AN — ADC Channel 0 input.

VREF- AN — ADC Negative Voltage Reference input.

C1IN+ AN — Comparator C1 positive input.

DAC1OUT — AN Digital-to-Analog Converter output.

ICSPDAT ST CMOS ICSP™ Data I/O.

RA1/AN1/VREF+/C1IN0-/C2IN0-/

ICSPCLK

RA1 TTL/ST CMOS General purpose I/O.

AN1 AN — ADC Channel 1 input.

VREF+ AN — ADC Voltage Reference input.

C1IN0- AN — Comparator C2 negative input.

C2IN0- AN — Comparator C3 negative input.

ICSPCLK ST — Serial Programming Clock.

RA2/AN2/DAC1OUT2/ZCD/

T0CKI(1)/COGIN(1)/INT(1) RA2 TTL/ST CMOS General purpose I/O.

AN2 AN — ADC Channel 2 input.

DAC1OUT2 — AN Digital-to-Analog Converter output.

ZCD — AN Zero-Cross Detection Current Source/Sink.

T0CKI TTL/ST — Timer0 clock input.

COGIN TTL/ST CMOS Complementary Output Generator input.

INT TTL/ST — External interrupt.

RA3/MCLR/VPP RA3 TTL/ST CMOS General purpose I/O.

MCLR ST — Master Clear with internal pull-up.

VPP HV — Programming voltage.

RA4/AN3/T1G(1)/SOSCO/

OSC2/CLKOUT

RA4 TTL/ST CMOS General purpose I/O.

AN3 AN — ADC Channel 3 input.

T1G TTL/ST — Timer1 gate input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

RA5/T1CKI(1)/SOSCI/

CLCIN3(1)/OSC1/CLKIN

RA5 TTL/ST CMOS General purpose I/O.

T1CKI TTL/ST — Timer1 clock input.

SOSCI XTAL XTAL Secondary Oscillator Connection.

CLCIN3 TTL/ST — Configurable Logic Cell source input.

OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKIN ST — External clock input (EC mode).

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels

I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

See Register 12-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the

PPS output selection registers. See Register 12-3.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin

selections.

PIC16(L)F1705/9

DS40001729C-page 12  2013-2015 Microchip Technology Inc.

RC0/AN4/C2IN+/OPA1IN+/

SCK(1)/SCL(3) RC0 TTL/ST CMOS General purpose I/O.

AN4 AN — ADC Channel 4 input.

C2IN+ AN — Comparator positive input.

OPA1IN+ AN — Operational Amplifier 1 non-inverting input.

SCK TTL/ST — SPI clock.

SCL I2C—I

2C clock.

RC1/AN5/C1IN1-/C2IN1-/

OPA1IN-/SDI(1)/SDA(3)/

CLCIN2(1)

RC1 TTL/ST CMOS General purpose I/O.

AN5 AN — ADC Channel 5 input.

C1IN1- AN — Comparator C1 negative input.

C2IN1- AN — Comparator C2 negative input.

OPA1IN- AN — Operational Amplifier 1 inverting input.

SDI CMOS — SPI data input.

SDA I2C—I

2C data input.

CLCIN2 TTL/ST — Configurable Logic Cell source input.

RC2/AN6/C1IN2-/C2IN2-/

OPA1OUT

RC2 TTL/ST CMOS General purpose I/O.

AN6 AN — ADC Channel 6 input.

C1IN2- AN — Comparator C1 negative input.

C2IN2- AN — Comparator C2 negative input.

OPA1OUT — AN Operational Amplifier 1 output.

RC3/AN7/C1IN3-/C2IN3-/

OPA2OUT/CCP2(1)/SS(1)/

CLCIN0(1)

RC3 TTL/ST CMOS General purpose I/O.

AN7 AN — ADC Channel 7 input.

C1IN3- AN — Comparator C1 negative input.

C2IN3- AN — Comparator C2 negative input.

OPA2OUT — AN Operational Amplifier 2 output.

CCP2 TTL/ST — Capture/Compare/PWM2.

SS TTL/ST — Slave Select input.

CLCIN0 TTL/ST — Configurable Logic Cell source input.

RC4/OPA2IN-/CK(1)/CLCIN1(1) RC4 TTL/ST CMOS General purpose I/O.

OPA2IN- AN — Operational Amplifier 2 inverting input.

CK TTL/ST — USART synchronous clock.

CLCIN1 TTLST — Configurable Logic Cell source input.

RC5/OPA2IN+/CCP1(1)/RX(1) RC5 TTL/ST CMOS General purpose I/O.

OPA2IN+ AN — Operational Amplifier 2 non-inverting input.

CCP1 TTL/ST — Capture/Compare/PWM1.

RX TTL/ST — USART asynchronous input.

TABLE 1-2: PIC16(L)F1705 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels

I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

See Register 12-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the

PPS output selection registers. See Register 12-3.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin

selections.

 2013-2015 Microchip Technology Inc. DS40001729C-page 13

PIC16(L)F1705/9

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

OUT(2) C1OUT — CMOS Comparator output.

C2OUT — CMOS Comparator output.

CCP1 — CMOS Capture/Compare/PWM1 output.

CCP2 — CMOS Capture/Compare/PWM2 output.

PWM3OUT — CMOS PWM3 output.

PWM4OUT — CMOS PWM4 output.

COGA — CMOS Complementary Output Generator Output A.

COGB — CMOS Complementary Output Generator Output B.

COGC — CMOS Complementary Output Generator Output C.

COGD — CMOS Complementary Output Generator Output D.

SDA(3) —ODI

2C data input/output.

SDO — CMOS SPI data output.

SCK — CMOS SPI clock output.

SCL(3) —ODI

2C clock output.

TX/CK — CMOS USART asynchronous TX data/synchronous

clock output.

DT — CMOS USART synchronous data output.

CLC1OUT — CMOS Configurable Logic Cell 1 source output.

CLC2OUT — CMOS Configurable Logic Cell 2 source output.

CLC3OUT — CMOS Configurable Logic Cell 3 source output.

TABLE 1-2: PIC16(L)F1705 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels

I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

See Register 12-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the

PPS output selection registers. See Register 12-3.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin

selections.

PIC16(L)F1705/9

DS40001729C-page 14  2013-2015 Microchip Technology Inc.

TABLE 1-3: PIC16(L)F1709 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/VREF-/C1IN+/

DAC1OUT/ICSPDAT

RA0 TTL/ST CMOS General purpose I/O.

AN0 AN — ADC Channel 0 input.

VREF- AN — ADC Negative Voltage Reference input.

C1IN+ AN — Comparator C1 positive input.

DAC1OUT — AN Digital-to-Analog Converter output.

ICSPDAT ST CMOS ICSP™ Data I/O.

RA1/AN1/VREF+/C1IN0-/C2IN0-/

ICSPCLK

RA1 TTL/ST CMOS General purpose I/O.

AN1 AN — ADC Channel 1 input.

VREF+ AN — ADC Voltage Reference input.

C1IN0- AN — Comparator C2 negative input.

C2IN0- AN — Comparator C3 negative input.

ICSPCLK ST — Serial Programming Clock.

RA2/AN2/DAC1OUT2/ZCD/

T0CKI(1)/COGIN(1)/INT(1) RA2 TTL/ST CMOS General purpose I/O.

AN2 AN — ADC Channel 2 input.

DAC1OUT

— AN Digital-to-Analog Converter output.

ZCD — AN Zero-Cross Detection Current Source/Sink.

T0CKI ST — Timer0 clock input.

COGIN ST CMOS Complementary Output Generator input.

INT ST — External interrupt.

RA3/MCLR/VPP RA3 TTL/ST CMOS General purpose I/O.

MCLR ST — Master Clear with internal pull-up.

VPP HV — Programming voltage.

RA4/AN3/T1G(1)/SOSCO/

OSC2/CLKOUT

RA4 TTL/ST CMOS General purpose I/O.

AN3 AN — ADC Channel 3 input.

T1G ST — Timer1 gate input.

SOSCO XTAL XTAL Secondary Oscillator Connection.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

RA5/T1CKI/SOSCI/

CLCIN3(1)/OSC1/CLKIN

RA5 TTL/ST CMOS General purpose I/O.

T1CKI ST — Timer1 clock input.

SOSCI XTAL XTAL Secondary Oscillator Connection.

CLCIN3 ST — Configurable Logic Cell source input.

OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKIN ST — External clock input (EC mode).

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain

TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels

I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL=Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the

PPS output selection registers. See Register 12-3.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin

selections.

 2013-2015 Microchip Technology Inc. DS40001729C-page 15

PIC16(L)F1705/9

RB4/AN10/OPA1IN-/SCK(1)/

SDA(3) RB4 TTL/ST CMOS General purpose I/O.

AN10 AN — ADC Channel 10 input.

OPA1IN- AN — Operational Amplifier 1 inverting input.

SCK ST CMOS SPI clock.

SDA I2CODI

2C data input/output.

RB5/AN11/OPA1IN+/RX(1) RB5 TTL/ST CMOS General purpose I/O.

AN11 AN — ADC Channel 11 input.

OPA1IN+ AN — Operational Amplifier 1 non-inverting input.

RX ST — USART asynchronous input.

RB6/SDI(1)/SCL(3) RB6 TTL/ST CMOS General purpose I/O.

SDI CMOS — SPI data input.

SCL I2CODI

2C clock.

RB7/CK(1) RB7 TTL/ST CMOS General purpose I/O.

CK ST CMOS USART synchronous clock.

RC0/AN4/C2IN+ RC0 TTL/ST CMOS General purpose I/O.

AN4 AN — ADC Channel 4 input.

C2IN+ AN — Comparator positive input.

RC1/AN5/C1IN1-/C2IN1-/

CLCIN2(1) RC1 TTL/ST CMOS General purpose I/O.

AN5 AN — ADC Channel 5 input.

C1IN1- AN — Comparator C1 negative input.

C2IN1- AN — Comparator C2 negative input.

CLCIN2 ST — Configurable Logic Cell source input.

RC2/AN6/C1IN2-/C2IN2-/

OPA1OUT

RC2 TTL/ST CMOS General purpose I/O.

AN6 AN — ADC Channel 6 input.

C1IN2- AN — Comparator C1 negative input.

C2IN2- AN — Comparator C2 negative input.

OPA1OUT — AN Operational Amplifier 1 output.

RC3/AN7/C1IN3-/C2IN3-/

OPA2OUT/CCP2(1)/CLCIN0(1) RC3 TTL/ST CMOS General purpose I/O.

AN7 AN — ADC Channel 7 input.

C1IN3- AN — Comparator C1 negative input.

C2IN3- AN — Comparator C2 negative input.

OPA2OUT — AN Operational Amplifier 2 output.

CCP2 ST CMOS Capture/Compare/PWM2.

CLCIN0 ST — Configurable Logic Cell source input.

RC4/CLCIN1(1) RC4 TTL/ST CMOS General purpose I/O.

CLCIN1 ST — Configurable Logic Cell source input.

TABLE 1-3: PIC16(L)F1709 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain

TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels

I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL=Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the

PPS output selection registers. See Register 12-3.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin

selections.

PIC16(L)F1705/9

DS40001729C-page 16  2013-2015 Microchip Technology Inc.

RC5/CCP1(1) RC5 TTL/ST CMOS General purpose I/O.

CCP1 ST CMOS Capture/Compare/PWM1.

RC6/AN8/OPA2IN-/SS(1) RC6 TTL/ST CMOS General purpose I/O.

AN8 AN — ADC Channel 8 input.

OPA2IN- AN — Operational Amplifier 2 inverting input.

SS ST — Slave Select input.

RC7/AN9/OPA2IN+ RC7 TTL/ST CMOS General purpose I/O.

AN9 AN — ADC Channel 9 input.

OPA2IN+ AN — Operational Amplifier 2 non-inverting input.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

OUT(2) C1OUT — CMOS Comparator output.

C2OUT — CMOS Comparator output.

CCP1 — CMOS Capture/Compare/PWM1 output.

CCP2 — CMOS Capture/Compare/PWM2 output.

PWM3OUT — CMOS PWM3 output.

PWM4OUT — CMOS PWM4 output.

COGA — CMOS Complementary Output Generator Output A.

COGB — CMOS Complementary Output Generator Output B.

COGC — CMOS Complementary Output Generator Output C.

COGD — CMOS Complementary Output Generator Output D.

SDA(3) —ODI

2C data input/output.

SDO — CMOS SPI data output.

SCK — CMOS SPI clock output.

SCL(3) I2CODI

2C clock output.

TX/CK — CMOS USART asynchronous TX data/synchronous

clock output.

DT — CMOS USART synchronous data output.

CLC1OUT — CMOS Configurable Logic Cell 1 source output.

CLC2OUT — CMOS Configurable Logic Cell 2 source output.

CLC3OUT — CMOS Configurable Logic Cell 3 source output.

TABLE 1-3: PIC16(L)F1709 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain

TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels

I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL=Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the

PPS output selection registers. See Register 12-3.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin

selections.

 2013-2015 Microchip Technology Inc. DS40001729C-page 17

PIC16(L)F1705/9

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

Relative Addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read

program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

VDD

Brown-out

Reset

VSS

Internal

Oscillator

Block

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

15 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

ConfigurationConfigurationConfiguration

Flash

Program

Memory

PIC16(L)F1705/9

DS40001729C-page 18  2013-2015 Microchip Technology Inc.

2.1 Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 7.5 “Automatic Context Saving”

for more information.

2.2 16-Level Stack with Overflow and

Underflow

These devices have a hardware stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Under-

flow will set the appropriate bit (STKOVF or STKUNF)

in the PCON register, and if enabled, will cause a soft-

ware Reset. See Section 3.6 “S ta ck” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.7 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 31.0 “Instruction Set Summary” for more

details.

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PIC16(L)F1705/9

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and

control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program

counter capable of addressing a 32K x 14 program

memory space. Table 3-1 shows the memory sizes

implemented for the PIC16(L)F1705/9 family. Accessing

a location above these boundaries will cause a

wrap-around within the implemented memory space.

The Reset vector is at 0000h and the interrupt vector is

at 0004h (see Figure 3-1).

3.2 High-Endurance Flash

This device has a 128-byte section of high-endurance

program Flash memory (PFM) in lieu of data EEPROM.

This area is especially well suited for nonvolatile data

storage that is expected to be updated frequently over

the life of the end product. See Section 10.2 “Flash

Program Me mor y Ove rview ” for more information on

writing data to PFM. See Section 3.2.1.2 “Indirect

Read with FSR” for more information about using the

FSR registers to read byte data stored in PFM.

Note 1: The method to access Flash memory

through the PMCON registers is described

in Section 10.0 “Flash Program Memory

Control”.

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space

(Words) Last Program Memory

Address High-Enduran ce Flas h

Memory Address Range(1)

PIC16(L)F1705/9 8,192 1FFFh 1F80h-1FFFh

Note 1: High-endurance Flash applies to the low byte of each address in the range.

PIC16(L)F1705/9

DS40001729C-page 20  2013-2015 Microchip Technology Inc.

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1705/9

3.2.1 READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in

program memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

3.2.1.1 RETLW Instruction

The RETLW instruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

EXAMPL E 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very

simple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRW instruction is not available so the older table read

method must be used.

3.2.1.2 Indirect Read with FSR

The program memory can be accessed as data by

setting bit 7 of the FSRxH register and reading the

matching INDFx register. The MOVIW instruction will

place the lower eight bits of the addressed word in the

W register. Writes to the program memory cannot be

performed via the INDF registers. Instructions that

access the program memory via the FSR require one

extra instruction cycle to complete. Example 3-2

demonstrates accessing the program memory via an

FSR.

The high directive will set bit<7> if a label points to a

location in program memory.

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh

1000h

7FFFh

Page 1

Rollover to Page 3

Interrupt, RETFIE

Page 2

Page 3

17FFh

1800h

1FFFh

2000h

constants

BRW ;Add Index in W to

;program counter to

;select data

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

 2013-2015 Microchip Technology Inc. DS40001729C-page 21

PIC16(L)F1705/9

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.3 Data Memory Organization

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.7 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper five bits

of the address define the Bank address and the lower

seven bits select the registers/RAM in that bank.

3.3.1 CORE REGISTERS

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in Ta bl e 3- 2. For detailed

information, see Tab le 3- 9.

TABLE 3-2: CORE REGISTERS

3.3.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 31.0

“Instruction Set Summary”).

constants

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

Note: The C and DC bits operate as Borrow and

Digit Borrow out bits, respectively, in

subtraction.

Addresses BANKx

x00h or x80h INDF0

x01h or x81h INDF1

x02h or x82h PCL

x03h or x83h STATUS

x04h or x84h FSR0L

x05h or x85h FSR0H

x06h or x86h FSR1L

x07h or x87h FSR1H

x08h or x88h BSR

x09h or x89h WREG

x0Ah or x8Ah PCLATH

x0Bh or x8Bh INTCON

PIC16(L)F1705/9

DS40001729C-page 22  2013-2015 Microchip Technology Inc.

3.4 R e g is t er D e finiti o n s: Status

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —TOPD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT Time-out occurred

bit 3 PD: Power-Down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand.

 2013-2015 Microchip Technology Inc. DS40001729C-page 23

PIC16(L)F1705/9

3.4.1 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch

through x1Fh/x9Fh). The registers associated with the

operation of the peripherals are described in the

appropriate peripheral chapter of this data sheet.

3.4.2 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank. The Special Function Registers occupy the 20

bytes after the core registers of every data memory

bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.4.2.1 Linear Access to GPR

The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section 3.7.2

“Linear Data Memory” for more information.

3.4.3 COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

FIGURE 3-2: BANKED MEMORY

PARTITIONING

3.4.4 DEVICE MEMORY MAPS

The memory maps for the device family are as shown

in Tables 3-3 through 3-8.

0Bh

0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

PIC16(L)F1705/9

DS40001729C-page 24  2013-2015 Microchip Technology Inc.

TABLE 3-3: PIC16(L)F1705 MEMORY MAP (BANKS 0-7)

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Unimplemented on PIC16LF1705.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Table 3-2)

080h

Core Registers

(Table 3-2)

100h

Core Registers

(Table 3-2)

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

380h

Core Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA

00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh —

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC

00Fh —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

010h —090h—110h—190h—210h—290h— 310h — 390h —

011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP

012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN

013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF

014h —094h— 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h —

015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON 295h — 315h — 395h —

016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h —

017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h IOCCP

018h T1CON 098h OSCTUNE 118h DAC1CON0 198h —218h— 298h CCPR2L 318h — 398h IOCCN

019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF

01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah —39Ah—

01Bh PR2 09Bh ADRESL 11Bh — 19Bh SP1BRGL 21Bh —29Bh—31Bh—39Bh—

01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch — 29Ch — 31Ch — 39Ch —

01Dh — 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh —

01Eh — 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh —39Eh—

01Fh — 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh —29Fh—31Fh—39Fh—

020h

General

Purpose

80 Bytes

0A0h

General

Purpose

80 Bytes

120h

General

Purpose

80 Bytes

1A0h

General

Purpose

80 Bytes

220h

General

Purpose

80 Bytes

2A0h

General

Purpose

80 Bytes

320h

General

Purpose

80 Bytes

3A0h

General

Purpose

80 Bytes

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

070h

Common RAM

70h – 7Fh

0F0h

Accesses

70h – 7Fh

170h

Accesses

70h – 7Fh

1F0h

Accesses

70h – 7Fh

270h

Accesses

70h – 7Fh

2F0h

Accesses

70h – 7Fh

370h

Accesses

70h – 7Fh

3F0h

Accesses

70h – 7Fh

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

 2013-2015 Microchip Technology Inc. DS40001729C-page 25

PIC16(L)F1705/9

TABLE 3-4: PIC16(L)F1709 MEMORY MAP (BANKS 0-7)

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Unimplemented on PIC16LF1709.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Table 3-2)

080h

Core Registers

(Table 3-2)

100h

Core Registers

(Table 3-2)

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

380h

Core Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA

00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC

00Fh —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

010h —090h—110h—190h—210h—290h— 310h — 390h —

011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP

012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN

013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF

014h —094h— 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP

015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON 295h — 315h — 395h IOCBN

016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF