DESCRIPTION
The 3803 group (Spec. H) is the 8-bit microcomputer based on the
740 family core technology.
The 3803 group (Spec. H) is designed for household products, of-
fice automation equipment, and controlling systems that require
analog signal processing, including the A-D converter and D-A
converters.
FEATURES
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time ................................ 0.24 µs
(at 16.8 MHz oscillation frequency)
●Memory size
ROM ............................................................... 16 K t o 3 2 K bytes
RAM ................................................................. 640 to 1024 bytes
●Programmable input/output ports ............................................ 56
●Software pull-up resistors .................................................Built-in
●Interrupts
21 sources, 16 vectors .................................................................
(external 8, internal 12, software 1)
●Timers........................................................................... 16-bit ✕ 1
8-bit ✕ 4
(with 8-bit prescaler)
●Watchdog timer ............................................................ 16-bit ✕ 1
●Serial I/O...................... 8-bit ✕ 2 (UART or Clock-synchronized)
8-bit ✕ 1 (Clock-synchronized)
●PWM ............................................8-bit ✕ 1 (with 8-bit prescaler)
●A-D converter ............................................. 10-bit ✕ 16 channels
(8-bit reading enabled)
●D-A converter ................................................. 8-bit ✕ 2 channels
●LED direct drive port .................................................................. 8
●Clock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode
At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V
At 12.5 MHz oscillation frequency ............................ 4.0 to 5.5 V
At 8.4 MHz oscillation frequency) ............................. 2.7 to 5.5 V
At 4.2 MHz oscillation frequency .............................. 2.2 to 5.5 V
At 2.1 MHz oscillation frequency) ............................. 2.0 to 5.5 V
In middle-speed mode
At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V
At 12.5 MHz oscillation frequency ............................ 2.7 to 5.5 V
At 8.4 MHz oscillation frequency) ............................. 2.2 to 5.5 V
At 6.3 MHz oscillation frequency) ............................. 1.8 to 5.5 V
In low-speed mode
At 32 kHz oscillation frequency................................. 1.8 to 5.5 V
●Power dissipation
In high-speed mode ................................................ 40 mW (typ.)
(at 16.8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ................................................... 45 µW (typ.)
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range....................................–20 to 85°C
●Packages
SP .................................................. 64P4B (64-pin 750 mil SDIP)
FP ....................................... 64P6N-A (64-pin 14 ✕ 14 mm QFP)
HP .....................................64P6Q-A (64-pin 10 ✕ 10 mm LQFP)
KP ..................................... 64P6U-A (64-pin 14 ✕ 14 mm LQFP)
Currently support products are listed below.
RAM size (bytes) Remarks
Package
Table 1 Support products
Product name
32768
(32638)
ROM size (bytes)
ROM size for User in ( )
M38034M4H-XXXSP
M38034M4H-XXXFP
M38034M4H-XXXHP
M38034M4H-XXXKP
M38037M6H-XXXSP
M38037M6H-XXXFP
M38037M6H-XXXHP
M38037M6H-XXXKP
M38037M8H-XXXSP
M38037M8H-XXXFP
M38037M8H-XXXHP
M38037M8H-XXXKP
1024
64P4B
64P6N-A
64P6Q-A
64P6U-A
64P4B
64P6N-A
64P6Q-A
64P6U-A
64P4B
64P6N-A
64P6Q-A
64P6U-A
Mask ROM version
16384
(16254) 640
Mask ROM version
24576
(24446) 1024
Mask ROM version
Rev.2.00 2003.05.28 page 1 of 81
3803 Group (Spec.H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0017-0200Z
Rev.2.00
2003.05.28
Rev.2.00 2003.05.28 page 2 of 81
3803 Group (Spec.H)
PIN CONFIGURATION (TOP VIEW)
Fig. 1 3803 group (Spec. H) pin configuration
Package type : 64P6N-A/64P6Q-A/64P6U-A
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
48
47
46
45
43
42
41
40
39
38
37
36
35
34
33
44
P0
0
/AN
8
P0
1
/AN
9
P0
2
/AN
10
P0
3
/AN
11
P0
4
/AN
12
P0
5
/AN
13
P0
6
/AN
14
P0
7
/AN
15
P1
0
/INT
41
P1
1
/INT
01
P1
2
P1
3
P1
6
P1
4
P1
5
P1
7
P2
7(
LED
7)
P2
0(
LED
0)
P2
1(
LED
1)
P2
2(
LED
2)
P2
3(
LED
3)
P2
4(
LED
4)
P2
5(
LED
5)
P2
6(
LED
6)
V
SS
X
OUT
X
IN
P4
2
/INT
1
RESET
CNV
SS
P4
0
/INT
40
/X
COUT
P4
1
/INT
00
/X
CIN
P3
5
/T
X
D
3
P3
4
/R
X
D
3
P3
1
/DA
2
P3
0
/DA
1
V
CC
V
REF
AV
SS
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
P6
3
/AN
3
P3
7
/S
RDY3
P3
6
/S
CLK3
P3
3
P3
2
P6
1
/AN
1
P6
0
/AN
0
P5
7
/INT
3
P5
6
/PWM
P5
5
/CNTR
1
P5
4
/CNTR
0
P5
2
/S
CLK2
P5
1
/S
OUT2
P5
0
/S
IN2
P4
6
/S
CLK1
P4
5
/T
X
D
1
P4
4
/R
X
D
1
P4
3
/INT
2
P6
2
/AN
2
P4
7
/S
RDY1
/CNTR
2
P5
3
/S
RDY2
M38037M6H-XXXFP/HP/KP
M38037M8H-XXXFP/HP/KP
M38034M4H-XXXFP/HP/KP
32
30
29
28
25
23
20
19
18
17
27
22
21
31
26
24
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
5
RAM size (bytes) Remarks
Package
Table 2 List of package (Spec. H)
Product name ROM size (bytes)
ROM size for User in ( )
M38034M4H-XXXFP
M38037M6H-XXXFP
M38037M8H-XXXFP
M38034M4H-XXXHP
M38037M6H-XXXHP
M38037M8H-XXXHP
M38034M4H-XXXKP
M38037M6H-XXXKP
M38037M8H-XXXKP
Mask ROM version
16384 (16254)
24576 (24446)
32768 (32638)
16384 (16254)
24576 (24446)
32768 (32638)
16384 (16254)
24576 (24446)
32768 (32638)
640
1024
1024
640
1024
1024
640
1024
1024
Mask ROM version
Mask ROM version
64P6N-A
64P6Q-A
64P6U-A
Rev.2.00 2003.05.28 page 3 of 81
3803 Group (Spec.H)
PIN CONFIGURATION (TOP VIEW)
Fig. 2 3803 group (Spec. H) pin configuration
Package type : 64P4B
VCC
VREF
AVSS
P67/AN7
P66/AN6
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/INT3
P56/PWM
P55/CNTR1
P54/CNTR0
P52/SCLK2
P51/SOUT2
P50/SIN2
P46/SCLK1
P45/TXD1
P44/RXD1
P43/INT2
P42/INT1
CNVSS
P40/INT40/XCOUT
XIN
XOUT
VSS
RESET
P30/DA1
P31/DA2
P34/RXD3
P35/TXD3
P00/AN8
P20(LED0)
P53/SRDY2
P65/AN5
P41/INT00/XCIN
P01/AN9
P02/AN10
P03/AN11
P04/AN12
P05/AN13
P06/AN14
P07/AN15
P10/INT41
P11/INT01
P12
P13
P14
P15
P16
P17
P21(LED1)
P22(LED2)
P23(LED3)
P24(LED4)
P25(LED5)
P26(LED6)
P27(LED7)
P32
P33
P36/SCLK3
P37/SRDY3
P47/SRDY1/CNTR2
M38034M6H-XXXSP
M38037M6H-XXXSP
M38037M8H-XXXSP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63
62
61
60
59
58
57
56
64
RAM size (bytes) RemarksPackage
Table 3 List of package (Spec. H)
Product name ROM size (bytes)
ROM size for User in ( )
M38034M4H-XXXSP
M38037M6H-XXXSP
M38037M8H-XXXSP Mask ROM version
16384 (16254)
24576 (24446)
32768 (32638)
640
1024
1024
64P4B
Rev.2.00 2003.05.28 page 4 of 81
3803 Group (Spec.H)
FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B)
Fig. 3 Functional block diagram
FUNCTIONAL BLOCK
I
N
T
4
0
I
N
T
0
0
I
N
T
2
X
I
N
O
U
T
X
R
A
M
R
O
M
X
Y
S
P
C
H
P
C
L
P
S
S
S
V
3
2
R
E
S
E
T
2
7
C
C
V
1
2
6
C
N
V
S
S
C
N
T
R
0
P
0
(
8
)
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
P
1
(
8
)
4
1
4
3
4
5
4
7
4
2
4
4
4
6
4
8
3
3
3
5
3
7
3
9
3
4
3
6
3
8
4
0
P
3
(
8
)
5
7
5
9
6
1
6
3
5
8
6
0
6
2
6
4
P
4
(
8
)
2
0
2
2
2
4
2
8
2
1
2
3
2
5
2
9
4
6
8
1
0
5
7
9
1
1
2
3
I
/
O
p
o
r
t
P
4
I
/
O
p
o
r
t
P
0
I
/
O
p
o
r
t
P
1
I
/
O
p
o
r
t
P
2
(
L
E
D
d
r
i
v
e
)
I
/
O
p
o
r
t
P
3
I
/
O
p
o
r
t
P
6
C
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o
c
k
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a
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C
l
o
c
k
i
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p
u
t
P
r
e
s
c
a
l
e
r
1
2
(
8
)
D
a
t
a
b
u
s
C
N
T
R
1
T
i
m
e
r
Z
(
1
6
)
A
-
D
c
o
n
v
e
r
t
e
r
(
1
0
)
V
R
E
F
A
V
S
S
I
N
T
3
1
2
1
4
1
6
1
8
1
3
1
5
1
7
1
9
P
W
M
(
8
)
P
5
(
8
)
D
-
A
c
o
n
v
e
r
t
e
r
1
(
8
)
X
C
I
N
C
O
U
T
X
3
0
3
1
2
8
2
9
C
N
T
R
2
S
I
/
O
3
(
8
)
I
N
T
0
1
I
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T
4
1
I
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1
C
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-
c
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-
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m
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r
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(
8
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P
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c
a
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(
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P
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a
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(
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r
2
(
8
)
Rev.2.00 2003.05.28 page 5 of 81
3803 Group (Spec.H)
PIN DESCRIPTION
Functions
NamePin
•Apply voltage of 1.8 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reference voltage input pin for A-D and D-A converters.
•Analog power source input pin for A-D and D-A converters.
•Connect to VSS.
•Reset input pin for active “L”.
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
•P20–P27 are enabled to output large current for LED drive.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•P30, P31, P34–P37 are CMOS 3-state output structure.
•P32, P33 are N-channel open-drain output structure.
•Pull-up control of P30, P31, P34–P37 is enabled in a bit
unit.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
Power source
CNVSS input
Reference voltage
Analog power source
Reset input
Table 4 Pin description
Function except a port function
•A-D converter input pin
•Interrupt input pin
•D-A converter input pin
•Serial I/O3 function pin
I/O port P4 •Interrupt input pin
•Sub-clock generating I/O pin
(resonator connected)
•Interrupt input pin
VCC, VSS
CNVSS
VREF
AVSS
RESET
XIN Clock input
Clock output
XOUT
P00/AN8–
P07/AN15 I/O port P0
P10/INT01
P11/INT41 I/O port P1
P12–P17
P20–P27I/O port P2
P3
0
/DA
1
P3
1
/DA
2
I/O port P3
P32, P33
P34/RxD3
P35/TxD3
P36/SCLK3
P37/SRDY3
P40/INT40/
XCOUT
P41/INT00/
XCIN
P42/INT1
P43/INT2
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
•Serial I/O1 function pin
•Serial I/O1, timer Z function pin
I/O port P5
I/O port P6
•Serial I/O2 function pin
•Timer X function pin
•Timer Y function pin
•PWM output pin
•Interrupt input pin
•A-D converter input pin
P44/RxD1
P45/TxD1
P46/SCLK1
P47/SRDY1
/CNTR2
P50/SIN2
P51/SOUT2
P52/SCLK2
P53/SRDY2
P54/CNTR0
P55/CNTR1
P56/PWM
P57/INT3
P60/AN0–
P67/AN7
Rev.2.00 2003.05.28 page 6 of 81
3803 Group (Spec.H)
PART NUMBERING
Fig. 4 Part numbering
M3803 7 M 8 H – XXX SP
Product name
Package type
SP : 64P4B
FP : 64P6N-A
HP : 64P6Q-A
KP : 64P6U-A
ROM number
ROM size
1
2
3
4
5
6
7
8
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they
cannot be used as a user’s ROM area.
However, they can be programmed or erased in the flash memory version,
so that the users can use them.
Memory type
M: Mask ROM version
F : Flash memory version
RAM size
0
1
2
3
4
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
– : standard
Omitted in the flash memory version.
H– : Minner spec. change product
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
9
A
B
C
D
E
F
5
6
7
8
9
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
Rev.2.00 2003.05.28 page 7 of 81
3803 Group (Spec.H)
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 3803 group (Spec. H) as follows.
Memory Type
Support for mask ROM version.
Memory Size
Mask ROM size ................................................. 1 6 K t o 3 2 K bytes
RAM size ............................................................640 to 1024 bytes
Packages
64P4B ......................................... 64-pin shrink plastic-molded DIP
64P6N-A ....................................0.8 mm-pitch plastic molded QFP
64P6Q-A ..................................0.5 mm-pitch plastic molded LQFP
64P6U-A ..................................0.8 mm-pitch plastic molded LQFP
Fig. 5 Memory expansion plan
Memory Expansion Plan
48K
32K
28K
24K
20K
16K
12K
8K
384 512 640 768 896 1024
60K
1152 1280 1408 1536
ROM
exteranal
2048 3072 4032
ROM size (bytes)
RAM size (bytes)
M38037M6H
M38037M8H
M38034M4H
Note 1: Products under development or planning: the development schedule and specification may be revised
without notice. The development of planning products may be stopped.
Note 2: See the 3803/3804 group data sheet about 3803 group products other than 3803 group (spec. H) because
there are electrical characteristics differences and so on.
As of Mar. 2003
: Under development : Mass production
M38039MF
M38039FF
M38039FFH
M38039MC
Rev.2.00 2003.05.28 page 8 of 81
3803 Group (Spec.H)
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3803 group (Spec. H) uses the standard 740 Family instruc-
tion set. Refer to the table of 740 Family addressing modes and
machine instructions or the 740 Family Software Manual for de-
tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
Fig.6 740 Family CPU register structure
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 10.
Store registers other than those described in Figure 10 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
A Accumulator
b7
b7
b7
b7 b0
b7b15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PC
L
Program counterPC
H
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Rev.2.00 2003.05.28 page 9 of 81
3803 Group (Spec.H)
Table 5 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 7 Register push and pop at interrupt generation and subroutine call
N
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e:
C
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M
(
S
)(
P
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(
S
)
(
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Rev.2.00 2003.05.28 page 10 of 81
3803 Group (Spec.H)
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can execute decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 6 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
Rev.2.00 2003.05.28 page 11 of 81
3803 Group (Spec.H)
Fig.8 Structure of CPU mode register
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
CPUM : address
003B
16
)
b
7b0
Fix this bit to “1”.
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Rev.2.00 2003.05.28 page 12 of 81
3803 Group (Spec.H)
MISRG
(1) Bit 0 of address 001016: Oscillation stabilizing time set af-
ter STP instruction released bit
When the MCU stops the clock oscillation by the STP instruction
and the STP instruction has been released by an external interrupt
source, usually, the fixed values of Timer 1 and Prescaler 12
(Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded
in order for the oscillation to stabilize. The user can inhibit the au-
tomatic setting by setting “1” to bit 0 of MISRG (address 001016).
However, by setting this bit to “1”, the previous values, set just be-
fore the STP instruction was executed, will remain in Timer 1 and
Prescaler 12. Therefore, you will need to set an appropriate value
to each register, in accordance with the oscillation stabilizing time,
before executing the STP instruction.
Figure 9 shows the structure of MISRG.
(2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Auto-
matic Switch Function
In order to switch the clock mode of an MCU which has a sub-
clock, the following procedure is necessary:
set CPU mode register (003B16) --> start main clock oscillation -->
wait for oscillation stabilization --> switch to middle-speed mode
(or high-speed mode).
However, the 3803 group (Spec. H) has the built-in function which
automatically switches from low to middle-speed mode by pro-
gram.
●Middle-speed mode automatic switch by program
The middle-speed mode can also be automatically switched by
program while operating in low-speed mode. By setting the
middle-speed automatic switch start bit (bit 3) of MISRG (address
001016) to “1” in the condition that the middle-speed mode auto-
matic switch set bit is “1” while operating in low-speed mode, the
MCU will automatically switch to middle-speed mode. In this case,
the oscillation stabilizing time of the main clock can be selected by
the middle-speed automatic switch wait time set bit (bit 2) of
MISRG (address 001016).
Fig. 9 Structure of MISRG
MISRG
(MISRG : address 0010
16
)
b7 b0
Note: When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (3B16) change.
Not used (return “0” when read)
(Do not write “1” to this bit)
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start (Note)
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enabled (Note)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “01
16
” to Timer 1, “FF
16
” to
Prescaler 12
1: Automatically set disabled
Rev.2.00 2003.05.28 page 13 of 81
3803 Group (Spec.H)
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
Fig. 10 Memory map diagram
010016
000016
004016
FF0016
FFDC16
FFFE16
FFFF16
192
256
384
512
640
768
896
1024
1536
2048
XXXX16
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
YYYY16
ZZZZ16
RAM
ROM
0FF016
0FFF16
SFR area
Not used
Interrupt vector area
ROM area Reserved ROM area
(128 bytes)
Zero page
Special page
RAM area
RAM size
(bytes) Address
XXXX16
ROM size
(bytes) Address
YYYY16
Reserved ROM area
Address
ZZZZ16
SFR area
Not used
Rev.2.00 2003.05.28 page 14 of 81
3803 Group (Spec.H)
Fig. 11 Memory map of special function register (SFR)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16 Serial I/O2 register (SIO2)
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
MISRG
Transmit/Receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator (BRG1)
Serial I/O2 control register (SIO2CON)
Interrupt control register 2 (ICON2)
A-D conversion register 1 (AD1)
Prescaler Y (PREY)
Timer Y (TY)
AD/DA control register (ADCON)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Prescaler 12 (PRE12)
Timer 2 (T2)
Prescaler X (PREX)
Timer X (TX)
Timer 1 (T1)
Timer XY mode register (TM)
A-D conversion register 2 (AD2)
Interrupt source selection register (INTSEL)
Watchdog timer control register (WDTCON)
0FF016
0FF116
Port P0 pull-up control register (PULL0)
Timer Z low-order (TZL)
Timer Z high-order (TZH)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
Timer Z mode register (TZM)
PWM register (PWM)
Baud rate generator 3 (BRG3)
Transmit/Receive buffer register 3 (TB3/RB3)
Serial I/O3 status register (SIO3STS)
Serial I/O3 control register (SIO3CON)
UART3 control register (UART3CON)
Port P1 pull-up control register (PULL1)
0FF216
0FF316
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
0FF416 Port P4 pull-up control register (PULL4)
0FF516
0FF616
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
✽ Reserved area: Do not write any data to these addresses,
because these areas are reserved.
Rev.2.00 2003.05.28 page 15 of 81
3803 Group (Spec.H)
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
P00/AN8–P07/AN15
P10/INT41
P11/INT01
P12–P17
P20/LED0–
P27/LED7
P30/DA1
P31/DA2
P32
P33
P34/RxD3
P35/TxD3
P36/SCLK3
P37/SRDY3
P40/INT00/XCIN
P41/INT40/XCOUT
P42/INT1
P43/INT2
P44/RxD1
P45/TxD1
P46/SCLK1
P47/SRDY1/CNTR2
Pin Name I/O Structure
CMOS compatible input level
CMOS 3-state output
Non-Port Function Ref.No.
Table 7 I/O port function Related SFRs
Port P0
Port P1
Port P3
(1)
(2)
Port P2
A-D converter input
External interrupt input
D-A converter output
AD/DA control register
Interrupt edge selection
register
AD/DA control register
(3)
(4)
(5)
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
N-channel open-drain output
CMOS compatible input level
CMOS 3-state output
Port P4
Serial I/O3 function I/O Serial I/O3 control
register
UART3 control register
(6)
(7)
(8)
(9)
External interrupt input
Sub-clock generating
circuit
External interrupt input
Serial I/O1 function I/O
Interrupt edge selection
register
CPU mode register
Interrupt edge selection
register
Serial I/O1 control
register
UART1 control register
(10)
(11)
(2)
(6)
(7)
(8)
(12)
Serial I/O1 function I/O
Timer Z function I/O Serial I/O1 control
register
Timer Z mode register
Serial I/O2 control
register
Serial I/O2 function I/OPort P5
Port P6
(13)
(14)
(15)
(16)
(17)
(18)
(2)
(1)
Timer X, Y function I/O
PWM output
External interrupt input
A-D converter input
Timer XY mode register
PWM control register
Interrupt edge selection
register
AD/DA control register
Notes 1:Refer to the applicable sections how to use double-function ports as function I/O ports.
2:Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
P50/SIN2
P51/SOUT2
P52/SCLK2
P53/SRDY2
P54/CNTR0
P55/CNTR1
P56/PWM
P57/INT3
P60/AN0–P67/AN7
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
Rev.2.00 2003.05.28 page 16 of 81
3803 Group (Spec.H)
Fig. 12 Port block diagram (1)
(
6
)
P
o
r
t
s
P
34,
P
44
Serial I/O input
(1) Ports P0, P6
A
-
D
c
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v
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b
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t(2) Ports P10, P11, P42, P43, P57
Interrupt input
(3) Ports P12 to P17, P2 (4) Ports P30, P31
D
A
1
o
u
t
p
u
t
e
n
a
b
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e
(
P
3
0
)
D
A
2
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(
P
3
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(
8
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s
P
36,
P
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7
)
P
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s
P
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P
45
(
5
)
P
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P
32,
P
33
D
a
t
a
b
u
s
Direction
register
P
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h
P
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D
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b
u
sD
a
t
a
b
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s
Direction
register
P
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h
P
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l
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u
p
c
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t
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b
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D
-
A
c
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Data bus
D
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g
i
s
t
e
r
Port latc h
Pull-up control bit
Serial I/O enable bit
Receive enable bit
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
P
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
tP
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
tS
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
Data bus
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Port latc h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
S
e
r
i
a
l
I
/
O
e
x
t
e
r
n
a
l
c
l
o
c
k
i
n
p
u
t
S
e
r
i
a
l
I
/
O
c
l
o
c
k
o
u
t
p
u
t
S
e
r
i
a
l
I
/
O
o
u
t
p
u
t
Rev.2.00 2003.05.28 page 17 of 81
3803 Group (Spec.H)
Fig. 13 Port block diagram (2)
(10) Port P40
(11) Port P41
(13) Port P50
Port X
C switch bit
INT40 interrupt input
Port P41
Serial I/O2 input
(12) Port P47
(9) Port P37
S
RDY3 output enable bit
(14) Port P51
INT
00 interrupt input
Serial I/O3 enable bit
Serial I/O3 mode
selection bit
Data bus
Direction
register
Port latch
Pull-up control bit
Serial I/O3 ready output
Pull-up control bit
Data bus
Direction
register
Port latch
Port XC switch bit
Oscillator
CNTR2 interrupt input
SRDY1 output enable bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Data bus
Serial I/O1 ready output
Timer output
Data bus
Direction
register
Port latch
Pull-up control bit
Sub-clock generating circuit input
Port XC switch bit
Pull-up control bit
Data bus
Direction
register
Port latch
Pull-up control bit
Data bus
Direction
register
Port latch
Serial I/O2 output
Serial I/O2 transmit completion signal
Serial I/O2 port selection bit
P-channel output
disable bit
Bit 2
Timer Z operating
mode bits
Bit 1
Bit 0
Port latch
Direction
register
Pull-up control bit
Rev.2.00 2003.05.28 page 18 of 81
3803 Group (Spec.H)
Fig. 14 Port block diagram (3)
(
1
6
)
P
o
r
t
P
5
3
(
1
5
)
P
o
r
t
P
5
2
(
1
7
)
P
o
r
t
s
P
5
4
,
P
5
5
(
1
8
)
P
o
r
t
P
5
6
PWM outp ut
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Port latc h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
S
e
r
i
a
l
I
/
O
2
e
x
t
e
r
n
a
l
c
l
o
c
k
i
n
p
u
t
S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
o
u
t
p
u
t
S
R
D
Y
2
e
n
a
b
l
e
b
i
t
Serial I/O2 ready output
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
Data bus
Direction
register
Port latc h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
C
N
T
R
i
n
t
e
r
r
u
p
t
i
n
p
u
t
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Timer output
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Port latc h
P
W
M
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
Pull-up control bit
P
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
Rev.2.00 2003.05.28 page 19 of 81
3803 Group (Spec.H)
Fig. 15 Structure of port pull-up control register (1)
Port P0 pull-up control register
b
7b
0
P
00
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
01
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
02
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
03
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
04
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
05
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
06
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
07
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
b
7b
0P
o
r
t
P
1
p
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P
10
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
11
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
12
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
13
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
14
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
15
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
16
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
17
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
(PULL1: address 0FF116)
(
P
U
L
L
0
:
a
d
d
r
e
s
s
0
F
F
01
6)
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
Rev.2.00 2003.05.28 page 20 of 81
3803 Group (Spec.H)
Fig. 16 Structure of port pull-up control register (2)
Port P2 pull-up control register
b
7b
0
P
2
0
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
2
1
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
2
2
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
2
3
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
2
4
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
2
5
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
2
6
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
2
7
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
b7 b0 P
o
r
t
P
3
p
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P3
0
pull-up control bit
0: No pull-up
1: Pull-up
P3
1
pull-up control bit
0: No pull-up
1: Pull-up
Not used
(return “0” when read)
P3
4
pull-up control bit
0: No pull-up
1: Pull-up
P3
5
pull-up control bit
0: No pull-up
1: Pull-up
P3
6
pull-up control bit
0: No pull-up
1: Pull-up
P3
7
pull-up control bit
0: No pull-up
1: Pull-up
(PULL3: address 0FF3
16
)
(
P
U
L
L
2
:
a
d
d
r
e
s
s
0
F
F
2
1
6
)
N
o
t
e:
P
u
l
l
-
u
p
c
o
n
t
r
o
l
i
s
v
a
l
i
d
w
h
e
n
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
b
i
t
o
f
t
h
e
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
i
s
“
0
”
(
i
n
p
u
t
)
.
W
h
e
n
t
h
a
t
b
i
t
i
s
“
1
”
(
o
u
t
p
u
t
)
,
p
u
l
l
-
u
p
c
a
n
n
o
t
b
e
s
e
t
t
o
t
h
e
p
o
r
t
o
f
w
h
i
c
h
p
u
l
l
-
u
p
i
s
s
e
l
e
c
t
e
d
.
N
o
t
e:
P
u
l
l
-
u
p
c
o
n
t
r
o
l
i
s
v
a
l
i
d
w
h
e
n
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
b
i
t
o
f
t
h
e
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
i
s
“
0
”
(
i
n
p
u
t
)
.
W
h
e
n
t
h
a
t
b
i
t
i
s
“
1
”
(
o
u
t
p
u
t
)
,
p
u
l
l
-
u
p
c
a
n
n
o
t
b
e
s
e
t
t
o
t
h
e
p
o
r
t
o
f
w
h
i
c
h
p
u
l
l
-
u
p
i
s
s
e
l
e
c
t
e
d
.
Rev.2.00 2003.05.28 page 21 of 81
3803 Group (Spec.H)
Fig. 17 Structure of port pull-up control register (3)
Port P4 pull-up control register
b
7b
0
P40 pull-up control bit
0: No pull-up
1: Pull-up
P41 pull-up control bit
0: No pull-up
1: Pull-up
P42 pull-up control bit
0: No pull-up
1: Pull-up
P43 pull-up control bit
0: No pull-up
1: Pull-up
P44 pull-up control bit
0: No pull-up
1: Pull-up
P45 pull-up control bit
0: No pull-up
1: Pull-up
P46 pull-up control bit
0: No pull-up
1: Pull-up
P47 pull-up control bit
0: No pull-up
1: Pull-up
b
7b
0P
o
r
t
P
5
p
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P50 pull-up control bit
0: No pull-up
1: Pull-up
P51 pull-up control bit
0: No pull-up
1: Pull-up
P52 pull-up control bit
0: No pull-up
1: Pull-up
P53 pull-up control bit
0: No pull-up
1: Pull-up
P54 pull-up control bit
0: No pull-up
1: Pull-up
P55 pull-up control bit
0: No pull-up
1: Pull-up
P56 pull-up control bit
0: No pull-up
1: Pull-up
P57 pull-up control bit
0: No pull-up
1: Pull-up
(PULL5: address 0FF516)
(
P
U
L
L
4
:
a
d
d
r
e
s
s
0
F
F
41
6)
N
o
t
e:
P
u
l
l
-
u
p
c
o
n
t
r
o
l
i
s
v
a
l
i
d
w
h
e
n
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
b
i
t
o
f
t
h
e
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
i
s
“
0
”
(
i
n
p
u
t
)
.
W
h
e
n
t
h
a
t
b
i
t
i
s
“
1
”
(
o
u
t
p
u
t
)
,
p
u
l
l
-
u
p
c
a
n
n
o
t
b
e
s
e
t
t
o
t
h
e
p
o
r
t
o
f
w
h
i
c
h
p
u
l
l
-
u
p
i
s
s
e
l
e
c
t
e
d
.
N
o
t
e:
P
u
l
l
-
u
p
c
o
n
t
r
o
l
i
s
v
a
l
i
d
w
h
e
n
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
b
i
t
o
f
t
h
e
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
i
s
“
0
”
(
i
n
p
u
t
)
.
W
h
e
n
t
h
a
t
b
i
t
i
s
“
1
”
(
o
u
t
p
u
t
)
,
p
u
l
l
-
u
p
c
a
n
n
o
t
b
e
s
e
t
t
o
t
h
e
p
o
r
t
o
f
w
h
i
c
h
p
u
l
l
-
u
p
i
s
s
e
l
e
c
t
e
d
.
Rev.2.00 2003.05.28 page 22 of 81
3803 Group (Spec.H)
Fig. 18 Structure of port pull-up control register (4)
P
o
r
t
P
6
p
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
b
7b0
P
6
0
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
6
1
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
6
2
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
6
3
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
6
4
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
6
5
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
6
6
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
P
6
7
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
0
:
N
o
p
u
l
l
-
u
p
1
:
P
u
l
l
-
u
p
(
P
U
L
L
6
:
a
d
d
r
e
s
s
0
F
F
6
1
6
)
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
Rev.2.00 2003.05.28 page 23 of 81
3803 Group (Spec.H)
INTERRUPTS
The 3803 group (Spaec. H)’s interrupts are a type of vector and
occur by 16 sources among 21 sources: eight external, twelve in-
ternal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The reset and the BRK instruction cannot be disabled with any
flag or bit. The I (interrupt disable) flag disables all interrupts ex-
cept the reset and the BRK instruction interrupt.
When several interrupt requests occur at the same time, the inter-
rupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Which of each combination of the following interrupt sources can
be selected by the interrupt source selection register (address
003916).
1. INT 0 or Timer Z
2. CNTR1 or Serial I/O3 reception
3. Serial I/O2 or Timer Z
7. INT4 or CNTR2
8. A-D converter or serial I/O3 transmission
External Interrupt Pin Selection
The occurrence sources of the external interrupt INT0 and INT4
can be selected from either input from INT00 and INT40 pin, or in-
put from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit
of interrupt edge selection register (bit 6 of address 003A16).
■ Notes
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 003A16)
Timer XY mode register (address 002316)
Timer Z mode register (address 002A16)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection register
(address 003916)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit or the interrupt source select bit
to “1”.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
④Set the corresponding interrupt enable bit to “1” (enabled).
Rev.2.00 2003.05.28 page 24 of 81
3803 Group (Spec.H)
Interrupt Request
Generating Conditions Remarks
Interrupt Source Low
FFFC16
FFFA16
High
FFFD16
FFFB16
Priority
1
2
Table 8 Interrupt vector addresses and priority
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Vector Addresses (Note 1)
Reset (Note 2)
INT0
Timer Z
INT1
Serial I/O1
reception
Serial I/O1
transmission
At reset
At detection of either rising or
falling edge of INT0 input
At timer Z underflow
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of serial I/O3 data
reception
At completion of serial I/O2 data
transmission or reception
At timer Z underflow
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At detection of either rising or
falling edge of CNTR2 input
At completion of A-D conversion
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
3
4
5
6
7
8
9
10
Timer X
T imer Y
Timer 1
Timer 2
CNTR0
CNTR1
Serial I/O3
reception
Serial I/O2
Timer Z
INT2
INT3
INT4
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O3 is selected
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O3 is selected
Non-maskable software interrupt
11 FFE916 FFE816
12
CNTR2
A-D converter
Serial I/O3
transmission
BRK instruction
14
15
13
16
17
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Rev.2.00 2003.05.28 page 25 of 81
3803 Group (Spec.H)
Fig. 19 Interrupt control
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
(
I
)
Interrupt reques
t
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
BRK instruction
R
e
s
e
t
Rev.2.00 2003.05.28 page 26 of 81
3803 Group (Spec.H)
Fig. 20 Structure of interrupt-related registers
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
INT
0
active edge selection bit
INT
1
active edge selection bit
Not used (returns “0” when read)
INT
2
active edge selection bit
INT
3
active edge selection bit
INT
4
active edge selection bit
INT
0
, INT
4
interrupt switch bit
0 : INT
00
, INT
40
interrupt
1 : INT
01
, INT
41
interrupt
Not used (returns “0” when read)
(
I
N
T
E
D
G
E
:
a
d
d
r
e
s
s
0
0
3
A
1
6
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
I
N
T
0
/
T
i
m
e
r
Z
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
1
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
1
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
0 : No interrupt request issued
1 : Interrupt request issued
(
I
R
E
Q
1
:
a
d
d
r
e
s
s
0
0
3
C
1
6
)
(ICON1 : address 003E
16
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
CNTR
0
interrupt request bit
CNTR
1
/Serial I/O3 receive interrupt
request bit
Serial I/O2/Timer Z interrupt request bit
INT
2
interrupt request bit
INT
3
interrupt request bit
INT
4
/CNTR
2
interrupt request bit
AD converter/Serial I/O3 transmit
interrupt request bit
Not used (returns “0” when read)
(
I
R
E
Q
2
:
a
d
d
r
e
s
s
0
0
3
D
1
6
)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F
16
)
0
:
F
a
l
l
i
n
g
e
d
g
e
a
c
t
i
v
e
1
:
R
i
s
i
n
g
e
d
g
e
a
c
t
i
v
e
0
:
F
a
l
l
i
n
g
e
d
g
e
a
c
t
i
v
e
1
:
R
i
s
i
n
g
e
d
g
e
a
c
t
i
v
e
CNTR
0
interrupt enable bit
CNTR
1
/Serial I/O3 receive interrupt
enable bit
Serial I/O2/Timer Z interrupt enable bit
INT
2
interrupt enable bit
INT
3
interrupt enable bit
INT
4
/CNTR
2
interrupt enable bit
AD converter/Serial I/O3 transmit
interrupt enable bit
Not used (returns “0” when read)
I
N
T
0
/
T
i
m
e
r
Z
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
1
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
1
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
b
7
I
N
T
0
/
T
i
m
e
r
Z
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
N
T
0
i
n
t
e
r
r
u
p
t
1
:
T
i
m
e
r
Z
i
n
t
e
r
r
u
p
t
S
e
r
i
a
l
I
/
O
2
/
T
i
m
e
r
Z
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
1
:
T
i
m
e
r
Z
i
n
t
e
r
r
u
p
t
N
o
t
u
s
e
d
(D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
.
)
I
N
T
4
/
C
N
T
R
2
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
N
T
4
i
n
t
e
r
r
u
p
t
1
:
C
N
T
R
2
i
n
t
e
r
r
u
p
t
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
.
)
C
N
T
R
1
/
S
e
r
i
a
l
I
/
O
3
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
C
N
T
R
1
i
n
t
e
r
r
u
p
t
1
:
S
e
r
i
a
l
I
/
O
3
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
A
D
c
o
n
v
e
r
t
e
r
/
S
e
r
i
a
l
I
/
O
3
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
A
-
D c
o
n
v
e
r
t
e
r
i
n
t
e
r
r
u
p
t
1
:
S
e
r
i
a
l
I
/
O
3
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
Interrupt source selection register
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
s
i
m
u
l
t
a
n
e
o
u
s
l
y
.
)
(INTSEL: address 0039
16
)
b0
b
7
b
0
b
7
b
0
b7 b0
b7 b0
b7 b0
Rev.2.00 2003.05.28 page 27 of 81
3803 Group (Spec.H)
TIMERS
●8-bit Timers
The 3803 group (Spec. H) has four 8-bit timers: timer 1, timer 2,
timer X, and timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt re-
quest bit corresponding to that timer is set to “1”.
●Timer divider
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B16). When these bits are “00” (high-speed mode) or “01”
(middle-speed mode), XIN is selected. When these bits are“10”
(low-speed mode), XCIN is selected.
●Prescaler 12
The prescaler 12 counts the output of the timer divider. The count
source is selected by the timer 12, X count source selection
register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512,
1/1024 of f(XIN) or f(XCIN).
Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and pe-
riodically set the interrupt request bit.
●Prescaler X and prescaler Y
The prescaler X and prescaler Y count the output of the timer
divider or f(XCIN). The count source is selected by the timer 12, X
count source selection register (address 000E16) and the timer Y,
Z count source selection register (address 000F16) among 1/2,
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN)
or f(XCIN); and f(XCIN).
Timer X and Timer Y
The timer X and timer Y can each select one of four operating
modes by setting the timer XY mode register (address 002316).
(1) Timer mode
●Mode selection
This mode can be selected by setting “00” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
●Explanation of operation
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316).
When the timer reaches “0016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
(2) Pulse output mode
●Mode selection
This mode can be selected by setting “01” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
●Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR0/CNTR1 pin. Regardless of the timer counting or not
the output of CNTR0/CNTR1 pin is initialized to the level of speci-
fied by their active edge switch bits when writing to the timer.
When the CNTR0 active edge switch bit (bit 2) and the CNTR1 ac-
tive edge switch bit (bit 6) of the timer XY mode register (address
002316) is “0”, the output starts with “H” level. When it is “1”, the
output starts with “L” level.
Switching the CNTR0 or CNTR1 active edge switch bit will reverse
the output level of the corresponding CNTR0 or CNTR1 pin.
■Precautions
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to output in this mode.
Rev.2.00 2003.05.28 page 28 of 81
3803 Group (Spec.H)
(3) Event counter mode
●Mode selection
This mode can be selected by setting “10” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
●Explanation of operation
The operation is the same as the timer mode’s except that the
timer counts signals input from the CNTR0 or CNTR1 pin. The
valid edge for the count operation depends on the CNTR0 active
edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6)
of the timer XY mode register (address 002316). When it is “0”, the
rising edge is valid. When it is “1”, the falling edge is valid.
■Precautions
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to input in this mode.
(4) Pulse width measurement mode
●Mode selection
This mode can be selected by setting “11” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
●Explanation of operation
When the CNTR0 active edge switch bit (bit 2) or the CNTR1 ac-
tive edge switch bit (bit 6) of the timer XY mode register (address
002316) is “1”, the timer counts during the term of one falling edge
of CNTR0/CNTR1 pin input until the next rising edge of input (“L”
term). When it is “0”, the timer counts during the term of one rising
edge input until the next falling edge input (“H” term).
■Precautions
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to input in this mode.
The count operation can be stopped by setting “1” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316). The interrupt request bit
is set to “1” each time the timer underflows.
•Precautions when switching count source
When switching the count source by the timer 12, X and Y count
source selection bits, the value of timer count is altered in incon-
siderable amount owing to generating of thin pulses on the count
input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
Rev.2.00 2003.05.28 page 29 of 81
3803 Group (Spec.H)
Fig. 21 Block diagram of timer X, timer Y, timer 1, and timer 2
Q
Q
“1”
“0”
P
5
4
/
C
N
T
R
0
Q
Q
P
5
5
/
C
N
T
R
1
“0
”
“
1
”
R
R
T
T
f(XCIN)
f
(
XC
I
N)
C
l
o
c
k
f
o
r
t
i
m
e
r
1
2
XI
N
XC
I
N
(
1
/
2
,
1
/
4
,
1
/
8
,
1
/
1
6
,
1
/
3
2
,
1
/
6
4
,
1
/
1
2
8
,
1
/
2
5
6
,
1
/
5
1
2
,
1
/
1
0
2
4
)
D
i
v
i
d
e
r
C
l
o
c
k
f
o
r
t
i
m
e
r
Y
C
l
o
c
k
f
o
r
t
i
m
e
r
X
Count sour c e
selection bit
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
Port P5
4
direction register
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Port P5
4
latch
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
T
o
g
g
l
e
f
l
i
p
-
f
l
o
p
P
u
l
s
e
w
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t
h
m
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a
s
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r
e
m
e
n
t
m
o
d
eT
i
m
e
r
m
o
d
e
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Timer X count stop bit
P
r
e
s
c
a
l
e
r
X
(
8
)
Prescaler X latch (8)
D
a
t
a
b
u
s
Timer X latch (8)
T
i
m
e
r
X
(
8
)T
o
t
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
o
C
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T
R
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
X
l
a
t
c
h
w
r
i
t
e
p
u
l
s
e
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Clock for timer Y
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
Pulse width
measurement
mode T
i
m
e
r
m
o
d
e
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Timer Y count stop bit
Event
counter
mode
“0
”
“1”
CNTR
1
active edge
switch bit
Prescaler Y (8)
P
r
e
s
c
a
l
e
r
Y
l
a
t
c
h
(
8
)
D
a
t
a
b
u
s
Timer Y latch (8)
T
i
m
e
r
Y
(
8
)T
o
t
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
o
C
N
T
R
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
Port P5
5
direction register
Pulse out put mode
Port P5
5
latch
“1”
“0”
CNTR
1
active
edge swi tch bit T
o
g
g
l
e
f
l
i
p
-
f
l
o
p
Timer Y lat c h wr ite pulse
Pulse out put mode
T
i
m
e
r
2
l
a
t
c
h
(
8
)
Timer 2 (8) T
o
t
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
o
t
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
Clock for timer 12 P
r
e
s
c
a
l
e
r
1
2
(
8
)
P
r
e
s
c
a
l
e
r
1
2
l
a
t
c
h
(
8
)
Data bus
T
i
m
e
r
1
l
a
t
c
h
(
8
)
Timer 1 (8)
“
0
0
”
“
0
1
”
“
1
0
”
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
Rev.2.00 2003.05.28 page 30 of 81
3803 Group (Spec.H)
Fig. 22 Structure of timer XY mode register
T
i
m
e
r
X
Y
m
o
d
e
r
e
g
i
s
t
e
r
(
T
M
:
a
d
d
r
e
s
s
0
0
2
3
1
6
)
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
b
1b
0
00
:
T
i
m
e
r
m
o
d
e
01
:
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
10
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
11
:
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
I
n
t
e
r
r
u
p
t
a
t
f
a
l
l
i
n
g
e
d
g
e
C
o
u
n
t
a
t
r
i
s
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
1
:
I
n
t
e
r
r
u
p
t
a
t
r
i
s
i
n
g
e
d
g
e
C
o
u
n
t
a
t
f
a
l
l
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
T
i
m
e
r
X
c
o
u
n
t
s
t
o
p
b
i
t
0
:
C
o
u
n
t
s
t
a
r
t
1
:
C
o
u
n
t
s
t
o
p
T
i
m
e
r
Y
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
b
5b
4
00
:
T
i
m
e
r
m
o
d
e
01
:
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
10
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
11
:
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
I
n
t
e
r
r
u
p
t
a
t
f
a
l
l
i
n
g
e
d
g
e
C
o
u
n
t
a
t
r
i
s
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
1
:
I
n
t
e
r
r
u
p
t
a
t
r
i
s
i
n
g
e
d
g
e
C
o
u
n
t
a
t
f
a
l
l
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
T
i
m
e
r
Y
c
o
u
n
t
s
t
o
p
b
i
t
0
:
C
o
u
n
t
s
t
a
r
t
1
:
C
o
u
n
t
s
t
o
p
b
7b
0
Rev.2.00 2003.05.28 page 31 of 81
3803 Group (Spec.H)
Fig. 23 Structure of timer 12, X and timer Y, Z count source selection registers
Timer 12 count source selection bits
b3b2b1b0
0000: f(X
IN)/2 or f(XCIN)/2
0001: f(X
IN)/4 or f(XCIN)/4
0010: f(X
IN)/8 or f(XCIN)/8
0011: f(X
IN)/16 or f(XCIN)/16
0100: f(X
IN)/32 or f(XCIN)/32
0101: f(X
IN)/64 or f(XCIN)/64
0110: f(X
IN)/128 or f(XCIN)/128
0111: f(X
IN)/256 or f(XCIN)/256
1000: f(X
IN)/512 or f(XCIN)/512
1001: f
(
XIN
)
/1024 or f
(
XCIN
)
/1024
Timer 12, X count source selection regist er
(T12XCSS : address 000E16)
b
7b
0
Timer X count source selection bits
b7b6b5b4
0000: f(X
IN)/2 or f(XCIN)/2 1011 :
0001: f(X
IN)/4 or f(XCIN)/4 1100 :
0010: f(X
IN)/8 or f(XCIN)/8 1101 : Not used
0011: f(X
IN)/16 or f(XCIN)/16 1110 :
0100: f(X
IN)/32 or f(XCIN)/32 1111 :
0101: f(X
IN)/64 or f(XCIN)/64
0110: f(X
IN)/128 or f(XCIN)/128
0111: f(X
IN)/256 or f(XCIN)/256
1000: f(X
IN)/512 or f(XCIN)/512
1001: f(X
IN)/1024 or f(XCIN)/1024
1010: f
(
XCIN
)
Timer Y, Z count source selection register
(TYZCSS : address 000F16)
Timer Y count source selection bits
b3b2b1b0
0000: f(X
IN)/2 or f(XCIN)/2
0001: f(X
IN)/4 or f(XCIN)/4
0010: f(X
IN)/8 or f(XCIN)/8
0011: f(X
IN)/16 or f(XCIN)/16
0100: f(X
IN)/32 or f(XCIN)/32
0101: f(X
IN)/64 or f(XCIN)/64
0110: f(X
IN)/128 or f(XCIN)/128
0111: f(X
IN)/256 or f(XCIN)/256
1000: f(X
IN)/512 or f(XCIN)/512
1001: f(X
IN)/1024 or f(XCIN)/1024
1010: f
(
XCIN
)
b
7b0
Timer Z count source selection bits
b7b6b5b4
0000: f(X
IN)/2 or f(XCIN)/2 1011 :
0001: f(X
IN)/4 or f(XCIN)/4 1100 :
0010: f(X
IN)/8 or f(XCIN)/8 1101 : Not used
0011: f(X
IN)/16 or f(XCIN)/16 1110 :
0100: f(X
IN)/32 or f(XCIN)/32 1111 :
0101: f(X
IN)/64 or f(XCIN)/64
0110: f(X
IN)/128 or f(XCIN)/128
0111: f(X
IN)/256 or f(XCIN)/256
1000: f(X
IN)/512 or f(XCIN)/512
1001: f(X
IN)/1024 or f(XCIN)/1024
1010: f
(
XCIN
)
1
0
1
1
:
1
1
0
0
:
1
1
0
1
:
1
1
1
0
:
1
1
1
1
:
N
o
t
u
s
e
d
1
0
1
0
:
1
0
1
1
:
1
1
0
0
:
1
1
0
1
:
1
1
1
0
:
1
1
1
1
:
N
o
t
u
s
e
d
Rev.2.00 2003.05.28 page 32 of 81
3803 Group (Spec.H)
●16-bit Timer
The timer Z is a 16-bit timer. When the timer reaches “000016”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When the timer underflows, the interrupt request bit corresponding
to the timer Z is set to “1”.
When reading/writing to the timer Z, perform reading/writing to
both the high-order byte and the low-order byte. When reading the
timer Z, read from the high-order byte first, followed by the low-or-
der byte. Do not perform the writing to the timer Z between read
operation of the high-order byte and read operation of the low-or-
der byte. When writing to the timer Z, write to the low-order byte
first, followed by the high-order byte. Do not perform the reading
to the timer Z between write operation of the low-order byte and
write operation of the high-order byte.
The timer Z can select the count source by the timer Z count
source selection bits of timer Y, Z count source selection register
(bits 7 to 4 at address 000F16).
Timer Z can select one of seven operating modes by setting the
timer Z mode register (address 002A16).
(1) Timer mode
●Mode selection
This mode can be selected by setting “000” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
When an underflow occurs, the INT0/timer Z interrupt request bit
(bit 0) of the interrupt request register 1 (address 003C16) is set to
“1”.
●Explanation of operation
During timer stop, usually write data to a latch and a timer at the
same time to set the timer value.
The timer count operation is started by setting “0” to the timer Z
count stop bit (bit 6) of the timer Z mode register (address
002A16).
When the timer reaches “000016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
When writing data to the timer during operation, the data is written
only into the latch. Then the new latch value is reloaded into the
timer at the next underflow.
(2) Event counter mode
●Mode selection
This mode can be selected by setting “000” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “1” to the timer/event
counter mode switch bit (bit 7) of the timer Z mode register (ad-
dress 002A16).
The valid edge for the count operation depends on the CNTR2 ac-
tive edge switch bit (bit 5) of the timer Z mode register (address
002A16). When it is “0”, the rising edge is valid. When it is “1”, the
falling edge is valid.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s.
Set the double-function port of CNTR2 pin and port P47 to input in
this mode.
Figure 26 shows the timing chart of the timer/event counter mode.
(3) Pulse output mode
●Mode selection
This mode can be selected by setting “001” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of
the timer Z mode register (address 002A16) is “0”, the output starts
with “H” level. When it is “1”, the output starts with “L” level.
■Precautions
Set the double-function port of CNTR2 pin and port P47 to output
in this mode.
The output from CNTR2 pin is initialized to the level depending on
CNTR2 active edge switch bit by writing to the timer.
When the value of the CNTR2 active edge switch bit is changed,
the output level of CNTR2 pin is inverted.
Figure 27 shows the timing chart of the pulse output mode.
Rev.2.00 2003.05.28 page 33 of 81
3803 Group (Spec.H)
(4) Pulse period measurement mode
●Mode selection
This mode can be selected by setting “010” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse period measurement is completed, the INT4/
CNTR2 interrupt request bit (bit 5) of the interrupt request register
2 (address 003D16) is set to “1”.
●Explanation of operation
The cycle of the pulse which is input from the CNTR2 pin is mea-
sured. When the CNTR2 active edge switch bit (bit 5) of the timer
Z mode register (address 002A16) is “0”, the timer counts during
the term from one falling edge of CNTR2 pin input to the next fall-
ing edge. When it is “1”, the timer counts during the term from one
rising edge input to the next rising edge input.
When the valid edge of measurement completion/start is detected,
the 1’s complement of the timer value is written to the timer latch
and “FFFF16” is set to the timer.
Furthermore when the timer underflows, the timer Z interrupt re-
quest occurs and “FFFF16” is set to the timer. When reading the
timer Z, the value of the timer latch (measured value) is read. The
measured value is retained until the next measurement comple-
tion.
■Precautions
Set the double-function port of CNTR2 pin and port P47 to input in
this mode.
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse pe-
riod).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during mea-
surement.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Conse-
quently, the timer value at start of pulse period measurement
depends on the timer value just before measurement start.
Figure 28 shows the timing chart of the pulse period measurement
mode.
(5) Pulse width measurement mode
●Mode selection
This mode can be selected by setting “011” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse widths measurement is completed, the INT4/
CNTR2 interrupt request bit (bit 5) of the interrupt request register
2 (address 003D16) is set to “1”.
●Explanation of operation
The pulse width which is input from the CNTR2 pin is measured.
When the CNTR2 active edge switch bit (bit 5) of the timer Z mode
register (address 002A16) is “0”, the timer counts during the term
from one rising edge input to the next falling edge input (“H” term).
When it is “1”, the timer counts during the term from one falling
edge of CNTR2 pin input to the next rising edge of input (“L” term).
When the valid edge of measurement completion is detected, the
1’s complement of the timer value is written to the timer latch and
“FFFF16” is set to the timer.
When the timer Z underflows, the timer Z interrupt occurs and
“FFFF16” is set to the timer Z. When reading the timer Z, the value
of the timer latch (measured value) is read. The measured value is
retained until the next measurement completion.
■Precautions
Set the double-function port of CNTR2 pin and port P47 to input in
this mode.
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse
widths).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during mea-
surement.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Conse-
quently, the timer value at start of pulse width measurement
depends on the timer value just before measurement start.
Figure 29 shows the timing chart of the pulse width measurement
mode.
Rev.2.00 2003.05.28 page 34 of 81
3803 Group (Spec.H)
(6) Programmable waveform generating mode
●Mode selection
This mode can be selected by setting “100” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z mode register (address 002A16) from the CNTR2 pin each
time the timer underflows.
Changing the value of the output level latch and the timer latch af-
ter an underflow makes it possible to output an optional waveform
from the CNTR2 pin.
■Precautions
Set the double-function port of CNTR2 pin and port P47 to output
in this mode.
Figure 30 shows the timing chart of the programmable waveform
generating mode.
(7) Programmable one-shot generating mode
●Mode selection
This mode can be selected by setting “101” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the
INT1 active edge selection bit (bit 1) of the interrupt edge selection
register (address 003A16). When it is “0”, the falling edge active is
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT1 pin is detected, the INT1 interrupt
request bit (bit 1) of the interrupt request register 1 (address
003C16) is set to “1”.
●Explanation of operation
•“H” one-shot pulse; Bit 5 of timer Z mode register = “0”
The output level of the CNTR2 pin is initialized to “L” at mode se-
lection. When trigger generation (input signal to INT1 pin) is
detected, “H” is output from the CNTR2 pin. When an underflow
occurs, “L” is output. The “H” one-shot pulse width is set by the
setting value to the timer Z register low-order and high-order.
When trigger generating is detected during timer count stop, al-
though “H” is output from the CNTR2 pin, “H” output state contin-
ues because an underflow does not occur.
•“L” one-shot pulse; Bit 5 of timer Z mode register = “1”
The output level of the CNTR2 pin is initialized to “H” at mode se-
lection. When trigger generation (input signal to INT1 pin) is
detected, “L” is output from the CNTR2 pin. When an underflow
occurs, “H” is output. The “L” one-shot pulse width is set by the
setting value to the timer Z low-order and high-order. When trigger
generating is detected during timer count stop, although “L” is out-
put from the CNTR2 pin, “L” output state continues because an
underflow does not occur.
■Precautions
Set the double-function port of CNTR2 pin and port P47 to output,
and of INT1 pin and port P42 to input in this mode.
This mode cannot be used in low-speed mode.
If the value of the CNTR2 active edge switch bit is changed during
one-shot generating enabled or generating one-shot pulse, then
the output level from CNTR2 pin changes.
Figure 31 shows the timing chart of the programmable one-shot
generating mode.
■Notes regarding all modes
●Timer Z write control
Which write control can be selected by the timer Z write control bit
(bit 3) of the timer Z mode register (address 002A16), writing data
to both the latch and the timer at the same time or writing data
only to the latch.
When the operation “writing data only to the latch” is selected, the
value is set to the timer latch by writing data to the address of
timer Z and the timer is updated at next underflow. After reset re-
lease, the operation “writing data to both the latch and the timer at
the same time” is selected, and the value is set to both the latch
and the timer at the same time by writing data to the address of
timer Z.
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
●Timer Z read control
A read-out of timer value is impossible in pulse period measure-
ment mode and pulse width measurement mode. In the other
modes, a read-out of timer value is possible regardless of count
operating or stopped.
However, a read-out of timer latch value is impossible.
●Switch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2 ac-
tive edge switch bit and the INT1 active edge selection bit.
●Switch of count source
When switching the count source by the timer Z count source se-
lection bits, the value of timer count is altered in inconsiderable
amount owing to generating of thin pulses on the count input sig-
nals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
●Usage of CNTR2 pin as normal I/O port
To use the CNTR2 pin as normal I/O port P47, set timer Z operat-
ing mode bits (b2, b1, b0) of timer Z mode register (address
002A16) to “000”.
Rev.2.00 2003.05.28 page 35 of 81
3803 Group (Spec.H)
Fig. 24 Block diagram of timer Z
“1”
“0”
P4
2
/INT
1
P4
7
/CNTR
2
“0”
“1”
“001”
“100”
“101”
f(X
CIN
)
X
IN
X
CIN
Output level latch
Programmable one-shot
generating mode
Programmable one-shot
generating circuit
CNTR
2
active edge
switch bit Programmable one-shot
generating mode
Data bus
To timer Z interrupt
request bit
To CNTR
2
interrupt
request bit
To INT
1
interrupt
request bit
Programmable waveform
generating mode
Pulse output mode
CNTR
2
active edge
switch bit
Pulse output mode
Timer Z low-order latch
Timer Z low-order Timer Z high-order latch
Timer Z high-order
Timer Z operating
mode bits
Port P4
7
direction register
Port P4
7
latch
Pulse period measurement mode
Pulse width measurement mode
Edge detection circuit
Timer Z count stop bit
Count source
selection bit
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Divider
Clock for timer Z
CNTR
2
active edge
switch bit
DQ
T
TQ
Q
S
“1”
“0”
“0”
“1”
Timer/Event
counter mode
switch bit
Rev.2.00 2003.05.28 page 36 of 81
3803 Group (Spec.H)
Fig. 25 Structure of timer Z mode register
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Rev.2.00 2003.05.28 page 37 of 81
3803 Group (Spec.H)
Fig. 26 Timing chart of timer/event counter mode
Fig. 27 Timing chart of pulse output mode
F
F
F
F1
6
0
0
0
01
6
T
L
TR TR TR
TL : Value set to timer latch
TR : Timer interrupt request
F
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e
)
TR T
RT
RTR
W
a
v
e
f
o
r
m
o
u
t
p
u
t
f
r
o
m
C
N
T
R2
p
i
nCNTR
2
CNTR
2
Rev.2.00 2003.05.28 page 38 of 81
3803 Group (Spec.H)
Fig. 28 Timing chart of pulse period measurement mode (Measuring term between two rising edges)
Fig. 29 Timing chart of pulse width measurement mode (Measuring “L” term)
F
F
F
F
1
6
0
0
0
0
1
6
T
3
T
RTR
T
2
T
1
C
N
T
R
2
C
N
T
R
2
C
N
T
R
2
CNTR
2
F
F
F
F
1
6
+
T
1T
2T
3FFFF
16
S
i
g
n
a
l
in
p
u
t
f
r
o
m
C
N
T
R
2
p
i
n
C
N
T
R
2
o
f
r
i
s
i
n
g
e
d
g
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a
c
t
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T
R
:
T
i
m
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r
i
n
t
e
r
r
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p
t
r
e
q
u
e
s
t
C
N
T
R
2
:
C
N
T
R
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
F
F
F
F1
6
0
0
0
01
6
T3
T
R
T
2
T1
C
N
T
R
2
C
N
T
R
2
C
N
T
R
2
F
F
F
F1
6 +
T
2T1
T3
CNTR
2
interrupt of rising edge active; Measurement of “L” width
TR : Timer interrupt request
CNTR
2
: CNTR
2
interrupt request
Signal input from
CNTR2 pin
Rev.2.00 2003.05.28 page 39 of 81
3803 Group (Spec.H)
Fig. 30 Timing chart of programmable waveform generating mode
Fig. 31 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating)
F
F
F
F1
6
0
0
0
01
6
T3
T
2
T
1
T2
T
3
L
LT1
TR TR TR TR
CNTR2C
N
T
R2
S
i
g
n
a
l
o
u
t
p
u
t
f
r
o
m
C
N
T
R2
p
i
n
L : Timer initial value
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Falling edge active)
F
F
F
F1
6
L
L
T
RT
RT
R
LL
CNTR
2
CNTR
2
S
i
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n
a
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o
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t
p
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t
f
r
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m
C
N
T
R2
p
i
n
L : One-shot pulse width
TR : Timer interrupt request
CNTR
2
: CNTR
2
interrupt request
(CNTR
2
active edge switch bit = “0”; Falling edge active)
Signal input from
INT1 pin
Rev.2.00 2003.05.28 page 40 of 81
3803 Group (Spec.H)
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Fig. 32 Block diagram of clock synchronous serial I/O1
Fig. 33 Operation of clock synchronous serial I/O1
1/4
1
/
4
F/F
P
46/
SC
L
K
1
Serial I/O1 status register
Serial I/O1 control register
P47/SRDY1
P44/RXD1
P45/TXD1
Recei v e buffer regi s ter 1
Address 001816
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
1
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator 1
Address 001C16
B
R
G
c
o
u
n
t
s
o
u
r
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s
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l
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c
t
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b
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t
Clock control circuit
F
a
l
l
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g
-
e
d
g
e
d
e
t
e
c
t
o
r
Transmit buffer register 1
Data bus Address 001816
Shift cloc
k
Transmit shift completion f lag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
D
a
t
a
b
u
s
A
d
d
r
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6
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g
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r
1
f(XIN)
(f(XCIN) in low-speed mode)
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
R
B
F
=
1
T
S
C
=
1
T
B
E
=
0T
B
E
=
1
T
S
C
=
0
T
r
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1
Rev.2.00 2003.05.28 page 41 of 81
3803 Group (Spec.H)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 34 Block diagram of UART serial I/O1
Fig. 35 Operation of UART serial I/O1
f(XIN)
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register 1
Address 001816
Receive shift register 1
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+
1) Address 001C16
ST/SP/PA generator
Transmit buffer register 1
Data bus
Transmit shift register 1
Address
0018
16
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address
0019
16
ST detector
SP detector UART1 control register
Address 001B
16
Character length selection bit
Address 001A16
BRG count source selection bit
Transmit interrupt source selection
bit
Serial I/O1 synchronous clock selection bit
Clock control circuit
Character length selection bit
7
bits
8
bits
Serial I/O1 control register
P46/SCLK1
Serial I/O1 status register
P44/RXD1
P45/TXD1
(f(XCIN) in low-speed mode)
TSC=0
TBE=1
RBF=0
T
B
E
=
0T
B
E
=
0
R
B
F
=
1R
B
F
=
1
STD
0
D
1
S
P
D
0
D
1
S
TS
P
T
B
E
=
1T
S
C
=
1
S
T
D
0
D
1
S
P
D
0
D
1
S
T
S
P
T
r
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m
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r
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l
Generated at 2nd bit in 2-st op-bit mode
1
s
t
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r
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d
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]
]
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Rev.2.00 2003.05.28 page 42 of 81
3803 Group (Spec.H)
[Serial I/O1 Control Register (SIO1CON)]
001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART1 Control Register (UART1CON)]
001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer, and one bit (bit 4) which is al-
ways valid and sets the output structure of the P45/TXD1 pin.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer Register 1/Receive Buffer
Register 1 (TB1/RB1)] 001816
The transmit buffer register 1 and the receive buffer register 1 are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Baud Rate Generator 1 (BRG1)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
Rev.2.00 2003.05.28 page 43 of 81
3803 Group (Spec.H)
Fig. 36 Structure of serial I/O1 control registers
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O1 status register
Serial I/O1 control register
b0 b0
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P47 pin operates as normal I/O pin
1: P47 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P44 to P47 operate as normal I/O pins)
1: Serial I/O1 enabled
(pins P44 to P47 operate as serial I/O pins)
b7 UART1 control register
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD1 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
b0
(SIO1STS : address 001916) (SIO1CON : address 001A16)
(UART1CON : address 001B16)
Rev.2.00 2003.05.28 page 44 of 81
3803 Group (Spec.H)
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
● Note
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O1 enable
bit to “0”.
● Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD1 pin and an operation failure occurs.
2.2 Stop of receive operation
● Note
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
● Note 1 (only transmission operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O1 enable
bit to “0”.
● Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD1 pin and an operation failure occurs.
● Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
■ Notes concerning serial I/O1
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
● Note
Clear the serial I/O1 enable bit and the transmit enable bit to “0”
(serial I/O and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD1 pin and an operation failure occurs.
1.2 Stop of receive operation
● Note
Clear the receive enable bit to “0” (receive disabled), or clear the
serial I/O1 enable bit to “0” (serial I/O disabled).
1.3 Stop of transmit/receive operation
● Note
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception can-
not be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and re-
ception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clear-
ing the serial I/O1 enable bit to “0” (serial I/O disabled) (refer to
1.1).
Rev.2.00 2003.05.28 page 45 of 81
3803 Group (Spec.H)
3. SRDY1 output of reception side
● Note
When signals are output from the SRDY1 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY1 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
4. Setting serial I/O1 control register again
● Note
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0.”
5. Data transmission control with referring to transmit shift
register completion flag
● Note
After the transmit data is written to the transmit buffer register, the
transmit shift register completion flag changes from “1” to “0” with
a delay of 0.5 to 1.5 shift clocks. When data transmission is con-
trolled with referring to the flag after writing the data to the transmit
buffer register, note the delay.
6. Transmission control when external clock is selected
● Note
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the SCLK1
input level. Also, write data to the transmit buffer register at “H” of
the SCLK1 input level.
7. Transmit interrupt request when transmit enable bit is set
● Note
When using the transmit interrupt, take the following sequence.
➀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instruction has executed.
√ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
● Reason
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag are
also set to “1”. Therefore, regardless of selecting which timing for
the generating of transmit interrupts, the interrupt request is gener-
ated and the transmit interrupt request bit is set at this point.
Clear both the transmit enable bit
(TE) and the receive enable bit
(RE) to “0”↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at the
same time
Rev.2.00 2003.05.28 page 46 of 81
3803 Group (Spec.H)
Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 Control Register (SIO2CON)]
001D16
The serial I/O2 control register contains eight bits which control
various serial I/O2 functions.
Fig. 37 Structure of serial I/O2 control register
Fig. 38 Block diagram of serial I/O2
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
2
C
O
N
:
a
d
d
r
e
s
s
0
0
1
D1
6)
b
7
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
0
0
0
:
f
(
XI
N)
/
8
(
f
(
XC
I
N)
/
8
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
0
0
1
:
f
(
XI
N)
/
1
6
(
f
(
XC
I
N)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
0
1
0
:
f
(
XI
N)
/
3
2
(
f
(
XC
I
N)
/
3
2
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
0
1
1
:
f
(
XI
N)
/
6
4
(
f
(
XC
I
N)
/
6
4
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
1
0
:
f
(
XI
N)
/
1
2
8
(
f
(
XC
I
N)
/
1
2
8
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
1
1
1
:
f
(
XI
N)
/
2
5
6
(
f
(
XC
I
N)
/
2
5
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
/
O
p
o
r
t
1
:
SO
U
T
2,
SC
L
K
2
s
i
g
n
a
l
o
u
t
p
u
t
SR
D
Y
2
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
:
I
/
O
p
o
r
t
1
:
SR
D
Y
2
s
i
g
n
a
l
o
u
t
p
u
t
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
0
:
E
x
t
e
r
n
a
l
c
l
o
c
k
1
:
I
n
t
e
r
n
a
l
c
l
o
c
k
P
51/
SO
U
T
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
0
:
C
M
O
S
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
1
:
N
-
c
h
a
n
n
e
l
o
p
e
n
d
r
a
i
n
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
b
0
b
2
b
1
b
0
“1”
“0”
“
0
”
“
1
”
“
0
”
“
1
”
S
RDY2
S
C
L
K
2
“
0
”
“
1
”
1/8
1/16
1/32
1/64
1/128
1/256
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
Serial I/O counter 2 (3)
Serial I/O2 register (8)
S
y
n
c
h
r
o
n
i
z
a
t
i
o
n
c
i
r
c
u
i
t
S
e
r
i
a
l
I
/
O
2
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
S
R
D
Y
2
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
E
x
t
e
r
n
a
l
c
l
o
c
k
Internal synchronous
clock selection bits
D
i
v
i
d
e
r
P
5
2
/
S
C
L
K
2
P5
1
/S
OUT2
P
5
0
/
S
I
N
2
P
5
2
l
a
t
c
h
P5
1
latch
P
5
3
l
a
t
c
h
P5
3
/S
RDY2
f(X
IN
)
(
f
(
X
C
I
N
)
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
A
d
d
r
e
s
s
0
0
1
F
1
6
Rev.2.00 2003.05.28 page 47 of 81
3803 Group (Spec.H)
Fig. 39 Timing of serial I/O2
D7D0D1D2D3D4D5D6
T
r
a
n
s
f
e
r
c
l
o
c
k
(
N
o
t
e
1
)
S
e
r
i
a
l
I
/
O
2
o
u
t
p
u
t
S
O
U
T
2
S
e
r
i
a
l
I
/
O
2
i
n
p
u
t
S
I
N
2
R
e
c
e
i
v
e
e
n
a
b
l
e
s
i
g
n
a
l
S
R
D
Y
2
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
w
r
i
t
e
s
i
g
n
a
l
(
N
o
t
e
2
)
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
s
e
t
1
:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
t
r
a
n
s
f
e
r
c
l
o
c
k
,
t
h
e
d
i
v
i
d
e
r
a
t
i
o
o
f
f
(
X
I
N
)
,
o
r
f
(
X
C
I
N
)
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
,
c
a
n
b
e
s
e
l
e
c
t
e
d
b
y
s
e
t
t
i
n
g
b
i
t
s
0
t
o
2
o
f
t
h
e
s
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
2
:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
t
r
a
n
s
f
e
r
c
l
o
c
k
,
t
h
e
SO
U
T
2
p
i
n
g
o
e
s
t
o
h
i
g
h
i
m
p
e
d
a
n
c
e
a
f
t
e
r
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
.
N
o
t
e
s
Rev.2.00 2003.05.28 page 48 of 81
3803 Group (Spec.H)
Serial I/O3
Serial I/O3 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O3 mode can be selected by setting
the serial I/O3 mode selection bit of the serial I/O3 control register
(bit 6 of address 003216) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Fig. 40 Block diagram of clock synchronous serial I/O3
Fig. 41 Operation of clock synchronous serial I/O3
1/4
1
/
4
F/F
P
36/
SC
L
K
3
Serial I/O3 status register
Serial I/O3 control register
P37/SRDY3
P34/RXD3
P35/TXD3
Recei v e buffer regi s ter 3
Address 003016
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
3
Receive buffer full flag (RBF)
Receive interrupt request (RI)
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
Shift clock
Serial I/O3 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator 3
Address 002F16
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Clock control circuit
F
a
l
l
i
n
g
-
e
d
g
e
d
e
t
e
c
t
o
r
Transmit buffer register 3
Data bus Address 003016
Shift cloc
k
Transmit shift completion f lag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 003116
D
a
t
a
b
u
s
A
d
d
r
e
s
s
0
0
3
21
6
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
3
f(XIN)
(f(XCIN) in low-speed mode)
D7
D7
D0D1D2D3D4D5D6
D0D1D2D3D4D5D6
R
B
F
=
1
T
S
C
=
1
T
B
E
=
0TBE = 1
TSC = 0
T
r
a
n
s
f
e
r
s
h
i
f
t
c
l
o
c
k
(
1
/
2
t
o
1
/
2
0
4
8
o
f
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
,
o
r
a
n
e
x
t
e
r
n
a
l
c
l
o
c
k
)
S
e
r
i
a
l
o
u
t
p
u
t
T
x
D
3
S
e
r
i
a
l
i
n
p
u
t
R
x
D
3
W
r
i
t
e
p
u
l
s
e
t
o
r
e
c
e
i
v
e
/
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
3
0
1
6
)
O
v
e
r
r
u
n
e
r
r
o
r
(
O
E
)
d
e
t
e
c
t
i
o
n
Notes 1
:
A
s
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
(
T
I
)
,
w
h
i
c
h
c
a
n
b
e
s
e
l
e
c
t
e
d
,
e
i
t
h
e
r
w
h
e
n
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
h
a
s
e
m
p
t
i
e
d
(
T
B
E
=
1
)
o
r
a
f
t
e
r
t
h
e
t
r
a
n
s
m
i
t
s
h
i
f
t
o
p
e
r
a
t
i
o
n
h
a
s
e
n
d
e
d
(
T
S
C
=
1
)
,
b
y
s
e
t
t
i
n
g
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
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3
Rev.2.00 2003.05.28 page 49 of 81
3803 Group (Spec.H)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O3 mode selection bit of the serial I/O3 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 42 Block diagram of UART serial I/O3
Fig. 43 Operation of UART serial I/O3
f
(
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TSC=0
TBE=1
RBF=0
T
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1
STD
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Generated at 2nd bit in 2-st op-bit mode
1
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]
]
S
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r
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a
d
s
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n
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l
Rev.2.00 2003.05.28 page 50 of 81
3803 Group (Spec.H)
[Serial I/O3 Control Register (SIO3CON)]
003216
The serial I/O3 control register consists of eight control bits for the
serial I/O3 function.
[UART3 Control Register (UART3CON)]
003316
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer, and one bit (bit 4) which is al-
ways valid and sets the output structure of the P35/TXD3 pin.
[Serial I/O3 Status Register (SIO3STS)] 003116
The read-only serial I/O3 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O3
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O3
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O3 enable bit SIOE
(bit 7 of the serial I/O3 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O3 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer Register 3/Receive Buffer
Register 3 (TB3/RB3)] 003016
The transmit buffer register 3 and the receive buffer register 3 are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Baud Rate Generator 3 (BRG3)] 002F16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
Rev.2.00 2003.05.28 page 51 of 81
3803 Group (Spec.H)
Fig. 44 Structure of serial I/O3 control registers
b
7
b
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t
d
i
v
i
d
e
d
b
y
1
6
w
h
e
n
U
A
R
T
i
s
s
e
l
e
c
t
e
d
.
S
R
D
Y
3
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
(
S
R
D
Y
)
0
:
P
3
7
p
i
n
o
p
e
r
a
t
e
s
a
s
n
o
r
m
a
l
I
/
O
p
i
n
1
:
P
3
7
p
i
n
o
p
e
r
a
t
e
s
a
s
S
R
D
Y
3
o
u
t
p
u
t
p
i
n
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
0
:
I
n
t
e
r
r
u
p
t
w
h
e
n
t
r
a
n
s
m
i
t
b
u
f
f
e
r
h
a
s
e
m
p
t
i
e
d
1
:
I
n
t
e
r
r
u
p
t
w
h
e
n
t
r
a
n
s
m
i
t
s
h
i
f
t
o
p
e
r
a
t
i
o
n
i
s
c
o
m
p
l
e
t
e
d
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
(
T
E
)
0
:
T
r
a
n
s
m
i
t
d
i
s
a
b
l
e
d
1
:
T
r
a
n
s
m
i
t
e
n
a
b
l
e
d
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
(
R
E
)
0
:
R
e
c
e
i
v
e
d
i
s
a
b
l
e
d
1
:
R
e
c
e
i
v
e
e
n
a
b
l
e
d
S
e
r
i
a
l
I
/
O
3
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
(
S
I
O
M
)
0
:
C
l
o
c
k
a
s
y
n
c
h
r
o
n
o
u
s
(
U
A
R
T
)
s
e
r
i
a
l
I
/
O
1
:
C
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
S
e
r
i
a
l
I
/
O
3
e
n
a
b
l
e
b
i
t
(
S
I
O
E
)
0
:
S
e
r
i
a
l
I
/
O
d
i
s
a
b
l
e
d
(
p
i
n
s
P
3
4
t
o
P
3
7
o
p
e
r
a
t
e
a
s
n
o
r
m
a
l
I
/
O
p
i
n
s
)
1
:
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
d
(
p
i
n
s
P
3
4
t
o
P
3
7
o
p
e
r
a
t
e
a
s
s
e
r
i
a
l
I
/
O
p
i
n
s
)
b
7
U
A
R
T
3
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
(
C
H
A
S
)
0
:
8
b
i
t
s
1
:
7
b
i
t
s
P
a
r
i
t
y
e
n
a
b
l
e
b
i
t
(
P
A
R
E
)
0
:
P
a
r
i
t
y
c
h
e
c
k
i
n
g
d
i
s
a
b
l
e
d
1
:
P
a
r
i
t
y
c
h
e
c
k
i
n
g
e
n
a
b
l
e
d
P
a
r
i
t
y
s
e
l
e
c
t
i
o
n
b
i
t
(
P
A
R
S
)
0
:
E
v
e
n
p
a
r
i
t
y
1
:
O
d
d
p
a
r
i
t
y
S
t
o
p
b
i
t
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
(
S
T
P
S
)
0
:
1
s
t
o
p
b
i
t
1
:
2
s
t
o
p
b
i
t
s
P
3
5
/
T
X
D
3
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
(
P
O
F
F
)
0
:
C
M
O
S
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
1
:
N
-
c
h
a
n
n
e
l
o
p
e
n
d
r
a
i
n
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
1
”
w
h
e
n
r
e
a
d
)
b
0
(
S
I
O
3
S
T
S
:
a
d
d
r
e
s
s
0
0
3
1
1
6
)
(
S
I
O
3
C
O
N
:
a
d
d
r
e
s
s
0
0
3
2
1
6
)
(UART3CON : address 0033
16
)
Rev.2.00 2003.05.28 page 52 of 81
3803 Group (Spec.H)
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
● Note
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O3 enable
bit to “0”.
● Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O3 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD3 pin and an operation failure occurs.
2.2 Stop of receive operation
● Note
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
● Note 1 (only transmission operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O3 enable
bit to “0”.
● Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O3 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD3 pin and an operation failure occurs.
● Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
■ Notes concerning serial I/O3
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
● Note
Clear the serial I/O3 enable bit and the transmit enable bit to “0”
(serial I/O and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD3 pin and an operation failure occurs.
1.2 Stop of receive operation
● Note
Clear the receive enable bit to “0” (receive disabled), or clear the
serial I/O3 enable bit to “0” (serial I/O disabled).
1.3 Stop of transmit/receive operation
● Note
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception can-
not be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and re-
ception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clear-
ing the serial I/O3 enable bit to “0” (serial I/O disabled) (refer to
1.1).
Rev.2.00 2003.05.28 page 53 of 81
3803 Group (Spec.H)
3. SRDY3 output of reception side
● Note
When signals are output from the SRDY3 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY3 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
4. Setting serial I/O3 control register again
● Note
Set the serial I/O3 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0.”
5. Data transmission control with referring to transmit shift
register completion flag
● Note
After the transmit data is written to the transmit buffer register, the
transmit shift register completion flag changes from “1” to “0” with
a delay of 0.5 to 1.5 shift clocks. When data transmission is con-
trolled with referring to the flag after writing the data to the transmit
buffer register, note the delay.
6. Transmission control when external clock is selected
● Note
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the SCLK3
input level. Also, write data to the transmit buffer register at “H” of
the SCLK input level.
7. Transmit interrupt request when transmit enable bit is set
● Note
When using the transmit interrupt, take the following sequence.
➀ Set the serial I/O3 transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O3 transmit interrupt request bit to “0” after 1 or
more instruction has executed.
√ Set the serial I/O3 transmit interrupt enable bit to “1” (enabled).
● Reason
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag are
also set to “1”. Therefore, regardless of selecting which timing for
the generating of transmit interrupts, the interrupt request is gener-
ated and the transmit interrupt request bit is set at this point.
Clear both the transmit enable bit
(TE) and the receive enable bit
(RE) to “0”↓
Set the bits 0 to 3 and bit 6 of the
serial I/O3 control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at the
same time
Rev.2.00 2003.05.28 page 54 of 81
3803 Group (Spec.H)
PULSE WIDTH MODULATION (PWM)
The 3803 group (Spec. H) has PWM functions with an 8-bit reso-
lution, based on a signal that is the clock input XIN or that clock
input divided by 2 or the clock input XCIN or that clock input di-
vided by 2 in low-speed mode.
Data Setting
The PWM output pin also functions as port P56. Set the PWM pe-
riod by the PWM prescaler, and set the “H” term of output pulse by
the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✕ (n+1) / f(XIN)
= 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz)
Output pulse “H” term = PWM period ✕ m / 255
= 0.125 ✕ (n+1) ✕ m µs
(when f(XIN) = 8 MHz)
Fig. 45 Timing of PWM period
Fig. 46 Block diagram of PWM function
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
31.875 ✕ m ✕(n+1)
2
5
5µs
T = [31.875 ✕ (n+1)] µs
PWM output
m
:
C
o
n
t
e
n
t
s
o
f
P
W
M
r
e
g
i
s
t
e
r
n
:
C
o
n
t
e
n
t
s
o
f
P
W
M
p
r
e
s
c
a
l
e
r
T
:
P
W
M
p
e
r
i
o
d
(
w
h
e
n
f
(
X
I
N
)
=
8
M
H
z
,
c
o
u
n
t
s
o
u
r
c
e
i
s
f
(
X
I
N
)
)
Data bus
Count source
selection bit
“0”
“
1
”
P
W
M
p
r
e
s
c
a
l
e
r
p
r
e
-
l
a
t
c
hPWM
register pr e-latch
PWM
prescaler latch PWM
register latch
T
r
a
n
s
f
e
r
c
o
n
t
r
o
l
c
i
r
c
u
i
t
PWM register
1/2
X
I
N
o
r
X
C
I
N
Port P5
6
la t c h
PWM enable bit
Port P5
6
P
W
M
p
r
e
s
c
a
l
e
r
Rev.2.00 2003.05.28 page 55 of 81
3803 Group (Spec.H)
Fig. 47 Structure of PWM control register
Fig. 48 PWM output timing when PWM register or PWM prescaler is changed
P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
W
M
C
O
N
:
a
d
d
r
e
s
s
0
0
2B
1
6
)
P
W
M
f
u
n
c
t
i
o
n
e
n
a
b
l
e
b
i
t
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
b
7b0
0
:
P
W
M
d
i
s
a
b
l
e
d
1
:
P
W
M
e
n
a
b
l
e
d
0
:
f
(
X
I
N
)
1
:
f
(
X
I
N
)
/
2
ABC
B
TC
T2
=
PWM output
PWM register
write signal
PWM prescaler
write signal
(Changes “H” term from “A” to “B”.)
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
out
p
ut will chan
g
e from the next
p
eriod after the chan
g
e.
TTT2
Rev.2.00 2003.05.28 page 56 of 81
3803 Group (Spec.H)
A-D CONVERTER
[A-D Conversion Register 1, 2 (AD1, AD2)]
003516, 003816
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Bit 7 of the A-D conversion register 2 is the conversion mode se-
lection bit. When this bit is set to “0,” the A-D converter becomes
the 10-bit A-D mode. When this bit is set to “1,” that becomes the
8-bit A-D mode. The conversion result of the 8-bit A-D mode is
stored in the A-D conversion register 1. As for 10-bit A-D mode,
not only 10-bit reading but also only high-order 8-bit reading of
conversion result can be performed by selecting the reading pro-
cedure of the A-D conversion registers 1, 2 after A-D conversion is
completed (in Figure 50).
As for 10-bit A-D mode, the 8-bit reading inclined to MSB is per-
formed when reading the A-D converter register 1 after A-D
conversion is started; and when the A-D converter register 1 is
read after reading the A-D converter register 2, the 8-bit reading
inclined to LSB is performed.
[AD/DA Control Register (ADCON)] 003416
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
VREF and AVSS into 1024, and that outputs the comparison voltage
in the 10-bit A-D mode (256 division in 8-bit A-D mode).
The A-D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF voltage (see below), with the
input voltage.
•10-bit A-D mode (10-bit reading)
Vref = ✕ n (n = 0–1023)
•10-bit A-D mode (8-bit reading)
Vref = ✕ n (n = 0–255)
•8-bit A-D mode
Vref = ✕ (n–0.5) (n = 1–255)
=0 (n = 0)
Fig. 49 Structure of AD/DA control register
Channel Selector
The channel selector selects one of ports P67/AN7 to P60/AN0 or
P07/AN15 to P00/AN8, and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
A-D conversion registers 1, 2. When an A-D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
VREF
256
VREF
256
Fig. 50 Structure of 10-bit A-D mode reading
VREF
1024
A
D
/
D
A
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
4
1
6
)
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
1
0
0
0
:
P
6
0
/
A
N
0
o
r
P
0
0
/
A
N
8
0
0
1
:
P
6
1
/
A
N
1
o
r
P
0
1
/
A
N
9
0
1
0
:
P
6
2
/
A
N
2
o
r
P
0
2
/
A
N
1
0
0
1
1
:
P
6
3
/
A
N
3
o
r
P
0
3
/
A
N
1
1
1
0
0
:
P
6
4
/
A
N
4
o
r
P
0
4
/
A
N
1
2
1
0
1
:
P
6
5
/
A
N
5
o
r
P
0
5
/
A
N
1
3
1
1
0
:
P
6
6
/
A
N
6
o
r
P
0
6
/
A
N
1
4
1
1
1
:
P
6
7
/
A
N
7
o
r
P
0
7
/
A
N
1
5
A
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
b
i
t
0
:
C
o
n
v
e
r
s
i
o
n
i
n
p
r
o
g
r
e
s
s
1
:
C
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
e
d
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
2
0
:
A
N
0
t
o
A
N
7
s
i
d
e
1
:
A
N
8
t
o
A
N
1
5
s
i
d
e
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
D
A
1
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
:
D
A
1
o
u
t
p
u
t
d
i
s
a
b
l
e
d
1
:
D
A
1
o
u
t
p
u
t
e
n
a
b
l
e
d
D
A
2
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
:
D
A
2
o
u
t
p
u
t
d
i
s
a
b
l
e
d
1
:
D
A
2
o
u
t
p
u
t
e
n
a
b
l
e
d
b7 b
0
b2 b1 b0
1
0
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
a
d
d
r
e
s
s
0
0
3
8
1
6
b
e
f
o
r
e
0
0
3
51
6)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
2
(
A
D
2
:
a
d
d
r
e
s
s
0
0
3
81
6)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
1
(
A
D
1
:
a
d
d
r
e
s
s
0
0
3
51
6)
8
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
o
n
l
y
a
d
d
r
e
s
s
0
0
3
5
1
6)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
1
(
A
D
1
:
a
d
d
r
e
s
s
0
0
3
51
6)
Note : Bits 2 to 6 of address 003816 become “0”
at reading.
b
8
b
7
b
6
b
5
b
4b
3b
2
b
1b
0
b7 b
0
b
9
b7 b
0
b
9
b
8
b
7
b
6b
5b
4
b
3
b
2
b7 b
0
0
Rev.2.00 2003.05.28 page 57 of 81
3803 Group (Spec.H)
Fig. 51 Block diagram of A-D converter
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
A-D control circuit
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
1
Resistor ladder
V
REF
AV
SS
C
o
m
p
a
r
a
t
o
r
A
D
c
o
n
v
e
r
t
e
r
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
7b
0
4
10
P
6
0
/
A
N
0
P
6
1
/
A
N
1
P
6
2
/
A
N
2
P
6
3
/
A
N
3
P
6
4
/
A
N
4
D
a
t
a
b
u
s
A
D
/
D
A
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
2
(
A
d
d
r
e
s
s
0
0
3
4
1
6
)
(Address 0038
16
)
(Address 0035
16
)
P
6
5
/
A
N
5
P
6
6
/
A
N
6
P
6
7
/
A
N
7
P0
0
/AN
8
P
0
1
/
A
N
9
P0
2
/AN
10
P0
3
/AN
11
P
0
4
/
A
N
1
2
P0
5
/AN
13
P0
6
/AN
14
P
0
7
/
A
N
1
5
Rev.2.00 2003.05.28 page 58 of 81
3803 Group (Spec.H)
D-A CONVERTER
The 3803 group (Spec. H) has two internal D-A converters (DA1
and DA2) with 8-bit resolution.
The D-A conversion is performed by setting the value in each D-A
conversion register. The result of D-A conversion is output from
the DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (P30/DA1 or P31/DA2) must be set to “0” (input status).
The output analog voltage V is determined by the value n (decimal
notation) in the D-A conversion register as follows:
V = VREF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion registers are cleared to “0016”, and
the DA output enable bits are cleared to “0”, and the P30/DA1 and
P31/DA2 pins become high impedance.
The DA output does not have buffers. Accordingly, connect an ex-
ternal buffer when driving a low-impedance load.
Fig. 52 Block diagram of D-A converter
Fig. 53 Equivalent connection circuit of D-A converter (DA1)
P
3
0
/
D
A
1
D-A1 conversion register (8)
R
-
2
R
r
e
s
i
s
t
o
r
l
a
d
d
e
rDA1 output enable bit
P
3
1
/
D
A
2
D
-
A
2
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
8
)
R-2R resistor ladder D
A2
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
D
a
t
a
b
u
s
AV
SS
V
REF
“0”
“1”
M
S
B
“
0
”“1”
R
2
R
R
2R
R
2R
R
2
R
R
2
R
R
2R
R
2
R2R
L
S
B
2
R
P3
0
/DA
1
D
-
A
1
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
D
A
1
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
Rev.2.00 2003.05.28 page 59 of 81
3803 Group (Spec.H)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Watchdog Timer Initial Value
Watchdog timer L is set to “FF16” and watchdog timer H is set to
“FF16” by writing to the watchdog timer control register (address
001E16) or at a reset. Any write instruction that causes a write sig-
nal can be used, such as the STA, LDM, CLB, etc. Data can only
be written to bits 6 and 7 of the watchdog timer control register.
Regardless of the value written to bits 0 to 5, the above-mentioned
value will be set to each timer.
Watchdog Timer Operations
The watchdog timer stops at reset and a countdown is started by
the writing to the watchdog timer control register. An internal reset
occurs when watchdog timer H underflows. The reset is released
after its release time. After the release, the program is restarted
from the reset vector address. Usually, write to the watchdog timer
control register by software before an underflow of the watchdog
timer H. The watchdog timer does not function if the watchdog
timer control register is not written to at least once.
Fig. 55 Structure of Watchdog timer control register
When bit 6 of the watchdog timer control register is kept at “0”, the
STP instruction is enabled. When that is executed, both the clock
and the watchdog timer stop. Count re-starts at the same time as
the release of stop mode (Note). The watchdog timer does not
stop while a WIT instruction is executed. In addition, the STP in-
struction is disabled by writing “1” to this bit again. When the STP
instruction is executed at this time, it is processed as an undefined
instruction, and an internal reset occurs. Once a “1” is written to
this bit, it cannot be programmed to “0” again.
The following shows the period between the write execution to the
watchdog timer control register and the underflow of watchdog
timer H.
Bit 7 of the watchdog timer control register is “0”:
when XCIN = 32.768 kHz; 32 s
when XIN = 16 MHz; 65.536 ms
Bit 7 of the watchdog timer control register is “1”:
when XCIN = 32.768 kHz; 125 ms
when XIN = 16 MHz; 256 µs
Note: The watchdog timer continues to count even while waiting for a stop
release. Therefore, make sure that watchdog timer H does not un-
derflow during this period.
Fig. 54 Block diagram of Watchdog timer
XIN
Data bus
XCIN
“10”
“00”
“01”
Main clock division
ratio selection bits
(Note)
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction disable bit
Watchdog timer H (8)
“FF16” is set when
watchdog timer
control register is
written to.
Internal reset
RESET
Watchdog timer L (8)
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
STP instruction
“FF16” is set when
watchdog timer
control register is
written to.
Reset release time waiting
b7
Watchdog timer H (for read-out of high -order 6 bit)
STP instruction disable bit
0: STP instruction enabl ed
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(X
IN
)/16 or f(X
CIN
)/16
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
W
D
T
C
O
N
:
a
d
d
r
e
s
s
0
0
1
E1
6)
b
0
Rev.2.00 2003.05.28 page 60 of 81
3803 Group (Spec.H)
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L"
level for 16 cycles or more of XIN. Then the RESET pin is returned
to an "H" level (the power source voltage should be between 1.8 V
and 5.5 V, and the oscillation should be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.36 V for VCC of 1.8 V.
Fig. 57 Reset sequence
Fig. 56 Reset circuit example
RESET
Internal
reset
Data
φ
Address
SYNC
X
IN
: 10.5 to 18.5 clock cycles
X
IN
???? ?FFFC FFFD ADH,L
??? ??ADLADH
1: The frequency relation of f(X
IN
) and f(φ) is f(X
IN
)=8
•
f(φ).
2: Th
e
quest
i
o
n m
a
rk
s
(
?
)
in
d
i
cate
a
n
u
n
de
fin
ed
state
t
h
at
depe
n
ds
o
n
t
h
e
p
r
e
vi
ous
state
.
Reset address from the vector table.
Notes
(Note)
0.2VCC
0V
0V
Poweron
VCCRESET
VCC
RESET
Power source
voltage detection
circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage ; Vcc=2.7 V
Rev.2.00 2003.05.28 page 61 of 81
3803 Group (Spec.H)
Fig. 58 Internal status at reset
XXXXXXXX
1110 0 000
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
Register contents
002816
002916
002A16
002B16
002C16
002D16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
(PS)
(PCH)
(PCL)
Address
FF16
FF16
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
Address Register contents
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
FF16
0116
FF16
0016
FF16
FF16
FF16
FF16
XXXXXXXX
00111111
XXXXXXXX
1
FFFD16 contents
FFFC16 contents
XXXXXXX
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
MISRG
Transmit/Receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator 1 (BRG1)
Serial I/O2 control register (SIO2CON)
Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
00110011
00110011
XXXXXXXX
10000000
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
10000000
11100000
00001000
XX000000
01001000
Timer Z (low-order) (TZL)
Timer Z (high-order) (TZH)
Timer Z mode register (TZM)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Baud rate generator 3 (BRG3)
Transmit/Receive buffer register 3 (TB3/RB3)
Serial I/O3 status register (SIO3STS)
Serial I/O3 control register (SIO3CON)
UART3 control register (UART3CON)
AD/DA control register (ADCON)
A-D conversion register 1 (AD1)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
A-D conversion register 2 (AD2)
Interrupt source selection register (INTSEL)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Port P0 pull-up control register (PULL0)
Port P1 pull-up control register (PULL1)
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
Processor status register
Program counter
Rev.2.00 2003.05.28 page 62 of 81
3803 Group (Spec.H)
CLOCK GENERATING CIRCUIT
The 3803 group (Spec. H) has two built-in oscillation circuits: main
clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscil-
lation circuit. An oscillation circuit can be formed by connecting a
resonator between XIN and XOUT (XCIN and XCOUT). Use the cir-
cuit constants in accordance with the resonator manufacturer’s
recommended values. No external resistor is needed between XIN
and XOUT since a feed-back resistor exists on-chip. However, an
external feed-back resistor is needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set is released, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
After STP instruction is released, the input of the prescaler 12 is
connected to count source which had set at executing the STP in-
struction, and the output of the prescaler 12 is connected to timer
1. Set the timer 1 interrupt enable bit to disabled (“0”) before ex-
ecuting the STP instruction. Oscillator restarts when an external
interrupt is received, but the internal clock φ is not supplied to the
CPU (remains at “H”) until timer 1 underflows. The internal clock φ
is supplied for the first time, when timer 1 underflows. Therefore
make sure not to set the timer 1 interrupt request bit to “1” before
the STP instruction stops the oscillator. When the oscillator is re-
started by reset, apply “L” level to the RESET pin until the
oscillation is stable since a wait time will not be generated.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts when an interrupt is received. Since the oscillator does not
stop, normal operation can be started immediately after the clock
is restarted.
■Note
•If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately
after power on and at returning from stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3f(XCIN).
•When using the quartz-crystal oscillator of high frequency, such
as 16 MHz etc., it may be necessary to select a specific oscillator
with the specification demanded.
Rev.2.00 2003.05.28 page 63 of 81
3803 Group (Spec.H)
Fig. 59 Ceramic resonator circuit
Fig. 60 External clock input circuit
V
CC
V
SS
X
CIN
X
COUT
X
IN
X
OUT
Open Open
External oscillation
circuit External oscillation
circuit
V
CC
V
SS
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OUT
C
CIN
C
COUT
Rf Rd
Rev.2.00 2003.05.28 page 64 of 81
3803 Group (Spec.H)
WIT instruction STP instruction
Timing φ (internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
S
R
Q
1/2 1/4
XIN XOUT
XCOUT
XCIN
Interrupt request
Reset
Interrupt disable flag l
Port X
C
switch bit
“1”“0”
Low-speed
mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note 1)
Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset. The count source before executing the STP
instruction is supplied as the count source at executing STP instruction.
3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is
“1”, set the appropriate value to them in accordance with oscillation stablizing time required by the using oscillator
because nothing is automatically set into timer 1 and prescaler 12.
Main clock division ratio
selection bits (Note 1)
Prescaler 12 Timer 1
Reset or
STP instruction
(Note 2)
Divider
(Note 3)
Reset
Fig. 61 System clock generating circuit block diagram
Rev.2.00 2003.05.28 page 65 of 81
3803 Group (Spec.H)
Fig. 62 State transitions of system clock
C
M4
:
P
o
r
t
X
c
s
w
i
t
c
h
b
i
t
0
:
I
/
O
p
o
r
t
f
u
n
c
t
i
o
n
(
s
t
o
p
o
s
c
i
l
l
a
t
i
n
g
)
1
:
X
C
I
N
-
X
C
O
U
T
o
s
c
i
l
l
a
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“
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“
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6
“1”←→“0”
C
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8
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f
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=
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M
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8
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(
f
(φ)
=
1
M
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CM7=0
CM6=0
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
H
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d
m
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M
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8
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Low-speed mode
(f(φ)=16 kHz)
C
M7=
1
C
M6=
0
C
M5=
1
(
8
M
H
z
s
t
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p
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d
m
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(
f
(φ)
=
1
6
k
H
z
)
CM7=0
CM6=0
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
High-speed mode
(f(φ)=4 MHz)
1
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Rev.2.00 2003.05.28 page 66 of 81
3803 Group (Spec.H)
NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin), and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recom-
mended.
Rev.2.00 2003.05.28 page 67 of 81
3803 Group (Spec.H)
ELECTRICAL CHARACTERISTICS
Absolute maximum ratings
Table 9 Absolute maximum ratings
Power source voltages
Input voltage P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67, VREF
Input voltage P32, P33
Input voltage ____________
RESET, X IN
Input voltage CNVSS
Output voltage P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67, XOUT
Output voltage P32, P33
Power dissipation
Operating temperature
Storage temperature
VCC
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Symbol Parameter Conditions Ratings
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to 5.8
1000 (Note)
–20 to 85
–65 to 125
V
V
V
V
V
V
V
mW
°C
°C
Unit
Note: In flat package, this value is 300 mW.
All voltages are based on Vss.
Output transistors are cut off.
Ta = 25°C
Rev.2.00 2003.05.28 page 68 of 81
3803 Group (Spec.H)
Table 10 Recommended operating conditions
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Recommended operating conditions
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VCC
VCC
5.5
5.5
VCC
VCC
0.16VCC
0.2VCC
0.16VCC
0.2VCC
0.16VCC
Power source voltage
“H” input voltage
P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67
“H” input voltage
P32, P33
“H” input voltage
____________
RESET, XIN, X CIN, CNVSS
“L” input voltage
P00–P07, P10–P17, P20–P27,
P30–P37,P40–P47,
P50–P57, P60–P67
“L” input voltage
____________
RESET, CNVSS
“L” input voltage
XIN, XCIN
Symbol Parameter Limits
Min. V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Unit
2.2
2.0
2.2
2.7
4.0
4.5
1.8
2.2
2.7
4.5
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Typ. Max.
f(XIN) ≤ 2.1 MHz
f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 8.4 MHz
f(XIN) ≤ 12.5 MHz
f(XIN) ≤ 16.8 MHz
f(XIN) ≤ 6.3 MHz
f(XIN) ≤ 8.4 MHz
f(XIN) ≤ 12.5 MHz
f(XIN) ≤ 16.8 MHz
Power source voltage
(Note 1)
VCC
VSS
VIH
VIH
VIL
VIL
VIL
VIH
When start oscillating (Note 2)
High-speed mode
f(φ) = f(XIN)/2
Middle-speed mode
f(φ) = f(XIN)/8
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC ≤ 5.5 V
0.85VCC
0.8VCC
0.85VCC
0.8VCC
0.85VCC
0.8VCC
0
0
0
0
0
Notes 1: When using A-D converter, see A-D converter recommended operating conditions.
2: The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and ope rating
temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation.
Conditions
Rev.2.00 2003.05.28 page 69 of 81
3803 Group (Spec.H)
Table 11 Recommended operating conditions
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Main clock input oscillation
frequency (Note 1)
f(XCIN)
Symbol Parameter Limits
Min. MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Unit
Typ. Max.
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
32.768
f(XIN)
Sub-clock input oscillation
frequency (Notes 1, 2)
Conditions
High-speed mode
f(φ) = f(XIN)/2
Middle-speed mode
f(φ) = f(XIN)/8
2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 4.0 V
4.0 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.2 V
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
(20✕VCC-36)✕1.05
2
(24✕VCC-40.8)✕1.05
3
(9✕VCC-0.3)✕1.05
3
(24✕VCC-60)✕1.05
3
16.8
(15✕VCC-9)✕1.05
3
(24✕VCC-28.8)✕1.05
3
(15✕VCC+39)✕1.1
7
16.8
50
Rev.2.00 2003.05.28 page 70 of 81
3803 Group (Spec.H)
Table 12 Recommended operating conditions
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
–80
–80
80
80
80
–40
–40
40
40
40
–10
10
20
–5
5
10
“H” total peak output current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
, P3
1
, P3
4
–P3
7
(Note 1)
“H” total peak output current P40–P47, P50–P57, P60–P67 (Note 1)
“L” total peak output current
P0
0
–P0
7
, P1
0
–P1
7
, P3
0
–P3
7
(Note 1)
“L” total peak output current P20–P27 (Note 1)
“L” total peak output current P40–P47,P50–P57, P60–P67
(Note 1)
“H” total average output current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
, P3
1
, P3
4
–P3
7
(Note 1)
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total average output current
P0
0
–P0
7
, P1
0
–P1
7
, P3
0
–P3
7
(Note 1)
“L” total average output current P20–P27 (Note 1)
“L” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“H” peak output current P00–P07, P10–P17, P20–P27, P30, P31, P34–P37,
P40–P47, P50–P57, P60–P67 (Note 2)
“L” peak output current P00–P07, P10–P17, P30–P37, P40–P47, P50–P57,
P60–P67 (Note 2)
“L” peak output current P20–P27 (Note 2)
“H” average output current P00–P07, P10–P17, P20–P27, P30, P31, P34–P37,
P40–P47, P50–P57, P60–P67 (Note 3)
“L” average output current P00–P07, P10–P17, P30–P37, P40–P47, P50–P57,
P60–P67 (Note 3)
“L” average output current P20–P27 (Note 3)
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
Symbol Parameter Limits
Min. mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
Typ. Max.
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
Rev.2.00 2003.05.28 page 71 of 81
3803 Group (Spec.H)
Table 13 Electrical characteristics (1)
(VCC = 1.8 to 5.5 V, VSS = 0V, T a = –20 to 85 °C, unless otherwise noted)
Electrical characteristics
“H” output voltage
P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67 (Note 1)
“L” output voltage
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67
Hysteresis
CNTR0, CNTR1, CNTR2,
INT0–INT4
Hysteresis
RxD1, SCLK1, SIN2, SCLK2, RxD3,
SCLK3 ____________
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67
“H” input current ____________
RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67
“L” input current ____________
RESET,CNVSS
“L” input current XIN
“L” input current (at Pull-up)
P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67
RAM hold voltage
Limits
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
V
Parameter Min. Typ. Max.
Symbol Unit
Note 1: P35 is measured when the P35/TxD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”.
P45 is measured when the P45/TxD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
IOH = –10 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 1.8 to 5.5 V
IOL = 10 mA
VCC = 4.0 to 5.5 V
IOL = 1.6 mA
VCC = 1.8 to 5.5 V
VI = VCC
(Pin floating. Pull-up
transistors “off”)
VI = VCC
VI = VCC
VI = VSS
(Pin floating. Pull-up
transistors “off”)
VI = VSS
VI = VSS
VI = VSS
VCC = 5.0 V
VI = VSS
VCC = 3.0 V
When clock stopped
VCC–2.0
VCC–1.0
–80
–30
1.8
Test conditions
0.4
0.5
0.5
4.0
–4.0
–210
–70
2.0
1.0
5.0
5.0
–5.0
–5.0
–420
–140
VCC
VOH
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
Rev.2.00 2003.05.28 page 72 of 81
3803 Group (Spec.H)
Table 14 Electrical characteristics (2)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768kHZ (Stoped in middle-speed mode), Output transistors “off”,
AD converter not operated)
Power source
current
Limits
Parameter Max.
Symbol Unit
f(XIN) = 16.8 MHz
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 4.2 MHz
f(XIN) = 16.8 MHz (in WIT state)
f(XIN) = 8.4 MHz
f(XIN) = 4.2 MHz
f(XIN) = 2.1 MHz
f(XIN) = 16.8 MHz
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 16.8 MHz (in WIT state)
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 6.3 MHz
f(XIN) = stopped
In WIT state
f(XIN) = stopped
In WIT state
f(XIN) = stopped
In WIT state
Ta = 25 °C
Ta = 85 °C
f(XIN) = 16.8 MHz, VCC = 5V
In Middle-, high-speed mode
Test conditions
15.0
12.0
9.0
5.0
3.6
3.8
2.0
1.2
7.0
6.0
5.0
3.3
3.0
2.4
2.0
200
70
40
15
15
6
1.0
10
ICC mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
High-speed
mode
Middle-speed
mode
Low-speed
mode
In STP state
(All oscillation stopped)
Increment when A-D conversion
is executed
Typ.
Min. 8.0
6.5
5.0
2.5
2.0
1.9
1.0
0.6
4.0
3.0
2.5
1.8
1.5
1.2
1.0
55
40
15
8
6
3
0.1
500
VCC = 5V
VCC = 3V
VCC = 5V
VCC = 3V
VCC = 5V
VCC = 3V
VCC = 2V
Rev.2.00 2003.05.28 page 73 of 81
3803 Group (Spec.H)
bit
LSB
2tc(XIN)
kΩ
µA
µA
µA
Resolution
Absolute accuracy
(excluding quantization error)
Conversion time
Ladder resistor
Reference power a t A-D converter operated
source input current at A-D converter operated
A-D port inout current
Max.
8-bit A-D mode (Note 1)
10-bit A-D mode (Note 2)
8-bit A-D mode (Note 1) 2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC ≤ 5.5 V
10-bit A-D mode (Note 2) 2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
8-bit A-D mode (Note 1)
10-bit A-D mode (Note 2)
VREF = 5.0 V
VREF = 5.0 V
Table 16 A-D converter characteristics
(VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Unit
Limits
Parameter
–
–
tCONV
RLADDER
IVREF
II(AD)
Test conditions
Symbol
A-D converter characteristics
Symbol Parameter Limits
Min. Unit
Typ. Max.
Conditions
Table 15 A-D converter recommended operating conditions
(VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V,T a = –20 to 85 °C, unless otherwise noted)
Power source voltage
(When A-D converter is used)
Analog reference voltage
Analog power source voltage
Analog input voltage
Main clock oscillation frequency
(When A-D converter is used)
VCC
VREF
AVSS
VIA
f(XIN)
V
V
V
V
MHZ
2.0
2.2
2.0
0
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
2.0
5.0
5.0
0
High-speed mode
f(φ) = f(XIN)/2
Middle-speed mode
f(φ) = f(XIN)/8
2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 4.0 V
4.0 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
5.5
5.5
VCC
VCC
(20✕VCC-36)✕1.05
2
(24✕VCC-40.8)✕1.05
3
(9✕VCC-0.3)✕1.05
3
(24✕VCC-60)✕1.05
3
16.8
(15✕VCC-9)✕1.05
3
(24✕VCC-28.8)✕1.05
3
(15✕VCC+39)✕1.1
7
16.8
8-bit A-D mode (Note 1)
10-bit A-D mode (Note 2)
Note 1: 8-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”.
2: 10-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”.
Note 1: 8-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”.
2: 10-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”.
Note 1: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”.
Table 17 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
bit
%
%
µs
kΩ
mA
Resolution
Absolute accuracy 4.0 ≤ VCC ≤ 5.5 V
2.7 ≤ VCC < 4.0 V
Setting time
Output resistor
Reference power source input current (Note 1)
Min. Unit
Limits
Parameter
–
–
tsu
RO
IVREF
Test conditionsSymbol
D-A converter characteristics
8
10
±3
±2
±5
±4
50
61
100
200
5
5
12
50 35
150
Min. Typ.
Typ. Max.
23.5
8
1.0
2.5
3
5
3.2
Rev.2.00 2003.05.28 page 74 of 81
3803 Group (Spec.H)
Table 18 Timing requirements (1) (In high-speed mode)
(VCC = 2.0 to 5.5 V, VSS = 0 V, T a = –20 to 85 °C, unless otherwise noted)
Timing requirements and switching characteristics
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
Limits
XIN cycle
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
Parameter Max.
Symbol Unit
Typ.
Reset input “L” pulse width
Main clock XIN
input cycle time
Main clock XIN
input “H” pulse width
Main clock XIN
input “L” pulse width
Sub-clock XCIN input cycle time
Sub-clock XCIN input “H” pulse width
Sub-clock XCIN input “L” pulse width
CNTR0–CNTR2
input cycle time
CNTR0–CNTR2
input “H” pulse width
CNTR0–CNTR2
input “L” pulse width
INT00, INT01, INT1, INT2, INT3, INT40, INT41
input “H” pulse width
INT00, INT01, INT1, INT2, INT3, INT40, INT41
input “L” pulse width
Min.
16
59.5
10000/(86VCC-219)
26✕103/(82VCC-3)
10000/(84VCC-143)
10000/(105VCC-189)
25
4000/(86VCC-219)
10000/(82VCC-3)
4000/(84VCC-143)
4000/(105VCC-189)
25
4000/(86VCC-219)
10000/(82VCC-3)
4000/(84VCC-143)
4000/(105VCC-189)
20
5
5
120
160
250
500
1000
48
64
115
230
460
48
64
115
230
460
48
64
115
230
460
48
64
115
230
460
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
Rev.2.00 2003.05.28 page 75 of 81
3803 Group (Spec.H)
Note : When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART).
Table 19 Timing requirements (2) (In high-speed mode)
(VCC = 2.0 to 5.5 V, VSS = 0 V, T a = –20 to 85 °C, unless otherwise noted)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Max.
Symbol Unit
Typ.
Min.
250
320
500
1000
2000
120
150
240
480
950
120
150
240
480
950
70
90
100
200
400
32
40
50
100
200
500
650
1000
2000
4000
200
260
400
950
2000
200
260
400
950
2000
100
130
200
400
800
100
130
150
300
600
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2 V
Serial I/O1, serial I/O3
clock input cycle time (Note)
Serial I/O1, serial I/O3
clock input “H” pulse width (Note)
Serial I/O1, serial I/O3
clock input “L” pulse width (Note)
Serial I/O1, serial I/O3
clock input setup time
Serial I/O1, serial I/O3
clock input hold time
Serial I/O2
clock input cycle time
Serial I/O2
clock input “H” pulse width
Serial I/O2
clock input “L” pulse width
Serial I/O2
clock input setup time
Serial I/O2
clock input hold time
t
C
(S
CLK1
), t
C
(S
CLK3
)
t
WH
(S
CLK1
), t
WH
(S
CLK3
)
t
WL
(S
CLK1
), t
WL
(S
CLK3
)
tsu(RxD1-SCLK1),
tsu(RxD3-SCLK3)
th(SCLK1-RxD1),
th(SCLK3-RxD3)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Rev.2.00 2003.05.28 page 76 of 81
3803 Group (Spec.H)
Table 20 Timing requirements (3) (In middle-speed mode)
(VCC = 1.8 to 5.5 V, VSS = 0 V, T a = –20 to 85 °C, unless otherwise noted)
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
Limits
XIN cycle
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
Parameter Max.
Symbol Unit
Typ.
Reset input “L” pulse width
Main clock XIN
input cycle time
Main clock XIN
input “H” pulse width
Main clock XIN
input “L” pulse width
Sub-clock XCIN input cycle time
Sub-clock XCIN input “H” pulse width
Sub-clock XCIN input “L” pulse width
CNTR0–CNTR2
input cycle time
CNTR0–CNTR2
input “H” pulse width
CNTR0–CNTR2
input “L” pulse width
INT00, INT01, INT1, INT2, INT3, INT40, INT41
input “H” pulse width
INT00, INT01, INT1, INT2, INT3, INT40, INT41
input “L” pulse width
Min.
16
59.5
10000/(24VCC+61)
10000/(82VCC-96)
10000/(52VCC-31)
25
4000/(24VCC+61)
4000/(82VCC-96)
4000/(52VCC-31)
25
4000/(24VCC+61)
4000/(82VCC-96)
4000/(52VCC-31)
20
5
5
120
160
250
320
48
64
115
150
48
64
115
150
48
64
115
150
48
64
115
150
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
Rev.2.00 2003.05.28 page 77 of 81
3803 Group (Spec.H)
Table 21 Timing requirements (4) (In middle-speed mode)
(VCC = 1.8 to 5.5 V, VSS = 0 V, T a = –20 to 85 °C, unless otherwise noted)
Note : When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART).
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Max.
Symbol Unit
Typ.
Min.
250
320
500
650
120
150
240
310
120
150
240
310
70
90
100
130
32
40
50
65
500
650
1000
1300
200
260
400
520
200
260
400
520
100
130
200
260
100
130
150
200
Serial I/O1, serial I/O3
clock input cycle time (Note)
Serial I/O1, serial I/O3
clock input “H” pulse width (Note)
Serial I/O1, serial I/O3
clock input “L” pulse width (Note)
Serial I/O1, serial I/O3
clock input setup time
Serial I/O1, serial I/O3
clock input hold time
Serial I/O2
clock input cycle time
Serial I/O2
clock input “H” pulse width
Serial I/O2
clock input “L” pulse width
Serial I/O2
clock input setup time
Serial I/O2
clock input hold time
t
C
(S
CLK1
), t
C
(S
CLK3
)
t
WH
(S
CLK1
), t
WH
(S
CLK3
)
t
WL
(S
CLK1
), t
WL
(S
CLK3
)
tsu(RxD1-SCLK1),
tsu(RxD3-SCLK3)
th(SCLK1-RxD1),
th(SCLK3-RxD3)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2 V
Rev.2.00 2003.05.28 page 78 of 81
3803 Group (Spec.H)
Fig. 63 Timing diagram (in single-chip mode)
0.2VCC
tWL(INT)
0.8VCC
tWH(INT)
0.2VCC
0.2VCC
0.8VCC
0.8VCC
0.2VCC
tWL(X
IN
)
0.8VCC
tWH(X
IN)
tC(X
IN
)
XIN
0.2VCC 0.8VCC
tW(RESET)
RESET
0.2
VCC
tWL(CNTR)
0.8
VCC
tWH(CNTR)
tC(CNTR)
tC(S
CLK1
), tC(S
CLK2
), tC(S
CLK3
)
tWL(S
CLK1
), tWL(S
CLK2
), tWL(S
CLK3
)tWH(S
CLK1
), tWH(S
CLK2
), tWH(S
CLK3
)
th(S
CLK1-
R
x
D1),
th(S
CLK2-
S
IN
2),
th(S
CLK3-
R
x
D3)
tsu(R
x
D1
-
S
CLK1
),
tsu(S
IN2-
S
CLK2
),
tsu(R
x
D3
-
S
CLK3
)
TXD1
TXD3
SOUT2
RXD1
RXD3
SIN2
SCLK1
SCLK2
SCLK3
INT1, INT2, INT3
INT00, INT40
INT01, INT41
CNTR
0
, CNTR
1
, CNTR
2
Timing diagram in single-chip mode
0.2VCC
tWL(X
CIN
)
0.8VCC
tWH(X
CIN)
tC(X
CIN
)
XCIN
Rev.2.00 2003.05.28 page 79 of 81
3803 Group (Spec.H)
64 33
32
1
E
c
e1
A2
A1
b
b1b2
e
LA
SEATING PLANE
D
SDIP64-P-750-1.78 Weight(g)
– 7.9
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
64P4B Plastic 64pin 750mil SDIP
Symbol Min Nom Max
A
A2
b
b1
b2
c
E
D
L
Dimension in Millimeters
A10.38 – –
–3.8–
0.4 0.5 0.6
0.9 1.0 1.3
0.65 0.75 1.05
0.2 0.25 0.32
56.2 56.4 56.6
16.85 17.0 17.15
– 1.778 –
– 19.05 –
2.8 – –
0°–15°
– – 5.08
e
e1
PACKAGE OUTLINE
QFP64-P-1414-0.80 1.11
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
64P6N-A Plastic 64pin 14✕14mm body QFP
––
––
–
–
––
–
–––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A10.20.1
0.5 ––
I21.3 ––
MD14.6 ––
ME14.6
10°0°0.1
1.4 0.80.60.4 17.116.816.5 17.116.816.5 0.8 14.214.013.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8
03.05
e
e
e
E
c
HE
1
64 49
32
48
33
17
16
HD
D
MD
ME
A
F
b
A1A2
L1
L
y
b2
I2
Recommended Mount Pad
Detail F
Rev.2.00 2003.05.28 page 80 of 81
3803 Group (Spec.H)
LQFP64-P-1010-0.50 –
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
64P6Q-A Plastic 64pin 10✕10mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A1
0.225 ––
I21.0 ––
MD10.4 ––
ME10.4
10°0°0.1
1.0 0.70.50.3 12.212.011.8 12.212.011.8 0.5 10.110.09.9 10.110.09.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
E
HE
1
64 49
48
33
3217
16
HD
D
MD
ME
A
F
y
b2
I2Recommended Mount Pad
Lp 0.45
–
–
0.6
0.25
–
0.75
–
0.08
x
A3
bxM
A1A2
L1
L
Detail F Lp
A3
c
e
MMP
LQFP64-P-1414-0.8 Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
64P6U-A Plastic 64pin 14✕14mm body LQFP
–
0.1
0.8
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A1
0.225 ––
I2––
MD14.4 ––
ME14.4
0°8°
0.1
0.2
1.0 0.70.50.3
16.215.8
14.113.9
16.215.8
14.0 14.113.9 14.0
16.0
16.0
0.1750.1250.105 0.450.370.32 1.4
01.7
e
Lp 0.45
0.95
–
–
0.6
0.25
–
0.75
–
x
A3
Recommended Mount Pad
Detail F
MMP
E
HE
1
17 32
64 49
16
48
33
HD
D
A
ybxM
eF
MD
l2
b2
ME
e
A1A2
L1
L
Lp
A3
c
Rev.2.00 2003.05.28 page 81 of 81
3803 Group (Spec.H)
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
REVISION HISTORY
Rev. Date Description
Page Summary
(1/1)
3803 Group (Spec.H) Data Sheet
1.00 Sep. 3, 2001
2.00 May. 28, 2003
First edition issued
•Delete the following :“*:KP package is under development.”
•Table 4 pin description
VCC,VSS Apply voltage of 2.7–5.5V → 1.8V–5.5V
•Fig.5 Memory expansion plan
As of Dec. 2002 → As of Mar. 2003
•Notes
(address 3A16) → (address 003A16), (address 2316) → (address 002316),
(address 2A16) → (address 002A16), (address 3916) → (address 003916)
•Fig.61 System clock generating circuit block diagram
•Table 10 Recommended operating conditions
Add : VIL “L” input voltage XIN, XCIN 1.8≤VCC≤5.5V Min. → 0
•Table 11 Recommended operating conditions
f(XIN) High-speed mode f(φ)=f(XIN)/2 2.2≤VCC≤4.0V →2.7≤VCC≤4.0V
•Table 16 A-D converter characteristics
VCC 8bit A-D mode, 10bit A-D mode Max. 5.0 →5.5
•Table 17 D-A converter characteristics
VCC = 4.0 to 5.5V → 4.0≤VCC≤5.5V, VCC = 2.7 to 4.0V → 2.7≤VCC<4.0V
•Table 16 A-D converter characteristics, Table 17 D-A converter characteristics
Resolution Unit Bits → bit
•Table 18 Timing requirements (1) (In high-speed mode)
tC(XIN) Main clock XIN input cycle time 2.7≤VCC<4.0
Min. 2.6✕103/(82VCC-3) → 26✕103/(82VCC-3)
•Table 18 Timing requirements (1) (In high-speed mode),
Table 20 Timing requirements (3) (In middle-speed mode)
tWH(XCIN) Sub-clock input “H” pulse width → Sub-clock XCIN input “H” pulse width
tWL(XCIN) Sub-clock input “L” pulse width → Sub-clock XCIN input “L” pulse width
•Table 19 Timing requirements (2) (In high-speed mode),
Table 20 Timing requirements (4) (In middle-speed mode)
tCL(SCLK2) → tWL(SCLK2)
•Fig.63 Timing diagram (in single-chip mode)
Delete the following underline parts :
SCLK1 SCLK2 SCLK3 tf , tr
TXD1 TXD3 SOUT2 td(SCLK1-TXD1), td(SCLK2-SOUT2), td(SCLK3-TXD3)
tv(SCLK1-TXD1), tv(SCLK2-SOUT2), tv(SCLK3-TXD3)
–
1,2,6,7
5
7
23
64
68
69
73
75
75,77
76,78
79
STP instruction
Timing φ (internal clock)
S
R
Q
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note 1)
Prescaler 12 Timer 1
Reset or
STP instruction
(Note 2)
Divider
(Note 3)
FF
16
01
16
STP instruction
Timing φ (internal clock)
S
R
Q
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note 1)
Prescaler 12 Timer 1
Reset or
STP instruction
(Note 2)
Divider
(Note 3)
Reset