This doc ument descr ibes par t-number -spec ific change s to rec ommended op erating condition s
and revised electrical specifications, as applicable, from those described in the general
MPC7455 RISC Microprocessor Hardware Specifications (Order No. MPC7455EC). The
MPC7455 is a PowerPC™ microprocessor.
Specifications provided in this document supersede those in the MPC7455 RISC
Microprocessor Hardware Specifications, Rev. 0 or later, for the part numbers listed in
Table A only. Specifications not addressed herein are unchanged. Because this document is
frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola
sales office for the latest version.
Note that headings a nd table n umbers in th is document a re not cons ecutivel y number ed. They
are intended to correspond to the heading or table affected in the general hardware
specification.
Part numbers addressed in this document are listed in Table A.
Table A. Part Numbers Addressed by this Data Sheet
Motorola
Part Number
Operating Conditions
Significant Differences from
Hardware Specification
CPU
Frequency
(MHz) VDD Tj
(°C)
XPC7455RX600NC 600 1.3 V ± 50 mV 0 to 105 Modified core and VCO frequency,
and power co nsumpti on specificat ions
XPC7455RX733NC 733
XPC7455RX800NC 800
XPC7445RX600NC 600
XPC7445RX733NC 733
XPC7445RX800NC 800
Note: The X pre fix in a M otorola part num ber designates a “Pil ot Production Prototy pe” as defined by
Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested,
and Q.A. inspected on a qualified technology to simulate normal production. These parts have only
preliminary reliability and characterization data. Before pilot production prototypes may be shipped,
written a uthorization from the customer must be on file in the ap plicable sales office ackno wledging the
qualification status and the fact that product changes may still occur while shipping pilot production
prototypes.
Advance Informatio n
MPC7455RXNXPNS
Rev. 1.1, 1/2004
MPC7455 Part Number
Specificat ion for the
XPC74x5RXnnnNx Series
Motorola Part
Numbers Affect ed:
XPC7455RX600NC
XPC7455RX733NC
XPC7455RX800NC
XPC7445RX600NC
XPC7445RX733NC
XPC7445RX800NC
2MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series MOTOROLA
Features Features
1.1 Features
This section summarizes changes to the features of the MPC7455 described in the MPC7455 RISC
Microprocessor Hardware Specifications.
• Power management
— 1.3-V processor core
1.3 General Parameters
• Core power supply: 1.3 V ± 50 mV DC nominal
1.5.1 DC Electrical Characteristics
Table 4 provides the recommended operating conditions for the MPC7455 part numbers described herein.
Table 4. Recommended Operating Conditions
Characteristic Symbol Recommended
Value Unit
Core supply voltage VDD 1.3 V ± 50 mV V
PLL supply voltage AVDD 1.3 V ± 50 mV V
Note: These are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series 3
General Para meters
Table 7 provides the power consumption for the MPC7455 part numbers described herein.
Table 7. Power Consumption for MPC7455
Processor (CPU) Frequency Unit Notes
600 MHz 733 MHz 800 MHz
Full-Power Mode
Typical 8.4 10.3 11.2 W 1, 3
Maximum 11.9 14.5 15.9 W 1, 2
Doze Mode
Typical — — — W 1, 2, 4
Nap Mode
Typical 1.4 1.7 1.8 W 1, 2
Sleep Mode
Ty pical 700 800 900 mW 1, 2
Deep Sleep Mode (PLL Disabled)
Ty pical 470 490 500 mW 1, 3
Notes:
1. These v alues apply for all vali d processor bus and L3 b us ratios. The values do n ot include I /O supply p ower (OVDD
and GVDD) or PLL supply power (AVDD). OVDD and GVDD powe r i s sy stem depen dent, b ut is typi cally < 5% of VDD
power. Worst case power consumption for AVDD < 3 mW.
2. Maximum power is measured at nominal VDD while running an entirely cache-resident, contrived sequence of
instructions which keep the execution units, with or without AltiVec, maximally busy.
3. Ty pical power is an average value measured at nominal VDD in a system while running a typical code sequence.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode.
As a result, power consumption for this mode is not tested.
4MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series MOTOROLA
General Parameters General Parameters
Table 8 provides the clock AC timing specifications for the MPC7455 part numbers described herein.
Table 12 provides the L3 bus interface AC timing spec ifications for MSUG2 for the MPC7455 part numbers
described herein.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Characteristic Symbol
Maximum Processor Core Frequency
Unit Notes600 MHz 733 MHz 800 MHz
Min Max Min Max Min Max
Processor frequency fcore 500 600 500 733 500 800 MHz 1
VCO frequency fVCO 1000 1200 1000 1466 1000 1600 MHz 1
Notes:
1. Caution: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequenc y, CPU (co r e) f requ enc y, and PL L (VC O) frequency do no t e xc eed th eir respective ma xi mu m or m in im um
operating frequencies (see Table 4 in the MPC7455 RISC Microprocessor Hardware Specifications). Refer to the
PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4] settings.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades
Unit NotesL2CR[12] = 0 and L3CR[12] = 08L2CR [12] = 1 and L3CR[12 ] = 18
Min Max Min Max
L3_CLK rise and
fall time tL3CR,
tL3CF
— 1.0 — 1.0 ns 1
Setup times:
Data and parity tL3DVEH,
tL3DVEL
–0.1 — –0.1 — ns 2, 3, 4
Input hold times:
Data and parity tL3DXEH
,
tL3DXEL
tL3_ECHO_CLK/4
+ 0.6 —t
L3_ECHO_CLK/4
+0.6 —ns2, 4
Valid times:
Data and parity tL3CHDV,
tL3CLDV
—(– t
L3_CLK/4)
+ 0.4 —(– t
L3_CLK/4)
+ 0.8 ns 5, 6, 7
Valid times:
All other outputs tL3CHOV —t
L3_CLK/4 + 1.0 — tL3_CLK/4 + 1.2 ns 5, 7
Output hol d times:
Data and parity tL3CHDX
,
tL3CLDX,
tL3_CLK/4 – 0.4 — tL3_CLK/4 – 0.2 — ns 5, 6, 7
Output hol d times:
All other outputs tL3CHOX tL3_CLK/4 – 0.5 — tL3_CLK/ 4 – 0.3 — ns 5, 7
L3_CLK to high
impedance:
Data and parity
tL3CLDZ —t
L3_CLK/2 — tL3_CLK/2 ns
MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series 5
General Para meters
L3_CLK to high
impedance:
All other outputs
tL3CHOZ —t
L3_CLK/4 + 2.0 — tL3_CLK/4 + 2.0 ns
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage
of the rising or fall ing edge of the input L3_ECHO_CLKn (see Figure 10 in th e MPC7455 RISC Microprocessor
Hardware Specifications). Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10 in the MPC7455
RISC Microprocessor Hardware Specifi cat ion s. F or co ns ist enc y with other input setup ti me speci fic ati ons , thi s wil l
be treated as negative input setup time.
4. tL3_ECHO_CLK/4 is one-fourth the period of L3_ECHO_C LKn. This p ar ameter indic ates that the MPC 7455 c an la tch
an input signal that is valid for only a short time before and a short time after the midpoint between the rising and
falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltag e of the rising (or f or DDR write data, a lso the falling)
edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output
timings assume a purely resistive 50-Ω load (see Figure 8 in the MPC7455 RISC Microprocessor Hardware
Specifications).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10 in the MPC7455 RISC
Microp roc ess or Hardware Specific ati on s. For consistency with other output valid time specifications, this will be
treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid
and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
start ing three-fo urths of a c lock prio r to the edge on which th e SRAM will sample it an d ending on e-fourth of a clock
period after the edge it will be sampled.
8. T hese c onfigu ration bit s al low the AC tim ing o f the L3 interfac e to be altered via soft ware. Th ey m ust be b oth s et or
both cleared; other configurations will increase tL3CSKW1, which may cause unreliable L3 operation.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades
Unit NotesL2CR[12] = 0 and L3CR[12] = 08L2CR [12] = 1 and L3CR[12 ] = 18
Min Max Min Max
6MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series MOTOROLA
General Parameters General Parameters
Table 13 provides the L3 bus AC timing specifications for PB2 and Late Write SRAMs for the MPC7455
part numbers described herein.
Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades
Unit NotesL2CR[12]=0 and L3CR[12]=0 6L2CR[12]=1 and L3CR[12]=1 6
Min Max Min Max
L3_CLK rise and fall
time tL3CR,
tL3CF
— 1.0 — 1.0 ns 1, 5
Setup times:
Data and parity tL3DVEH 1.5 — 1.5 — ns 2, 5
Input hold times:
Data and parity tL3DXEH — 0.5 — 0.5 ns 2, 5
Valid times:
Data and parity tL3CHDV —t
L3_CLK/4 + 1.0 — tL3_CLK/4 + 1.2 ns 3, 4, 5
Valid times:
All other outputs tL3CHOV —t
L3_CLK/4 + 1.0 — tL3_CLK/4 + 1.2 ns 4
Output hold times:
Data and parity tL3CHDX tL3_CLK/4 – 0.4 — tL3_CLK/4 – 0.2 — ns 3, 4, 5
Output hold times:
All other outputs tL3CHOX tL3_CLK/4 – 0.4 — tL3_CLK/4 – 0.2 — ns 4, 5
L3_CLK to high
impedance:
Data and parity
tL3CHDZ —2.0—2.0ns5
L3_CLK to high
impedance:
All other outputs
tL3CHOZ —2.0—2.0ns5
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. All input specif icatio ns are measured from the midpoi nt of th e signal in que stion to the mi dpoint v olt age of the risin g
edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications).
Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of
the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-Ω load (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications).
4. tL3_CLK/4 is one-fourt h the peri od of L 3_C L Kn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid
and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
star ting three -fourths of a clock pri or to the e dge on whi ch the SRAM will sam ple it an d ending one-fourth of a clock
period after the edge it will be sampled.
5. Timing behavior and characte riz ati on are currently being evaluated .
6. These con figuration bits a llow the AC timing of the L3 interfac e to be al tered via s oftware. They must be both set or
both cleared; other configurations will increase tL3CSKW1 and tL3CSKW2, which may cause unreliable L3 operation.
MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series 7
General Para meters
1.9.1 PLL Configuration
The MPC7455 PLL is configured by the PLL_CFG[0:4] signals; note that PLL_CFG[4] was formerly called
PLL_EXT in earlier documentation. For a gi ven SYSCLK (bus) frequency, the PLL configuration signals
set the i nternal CPU and VCO fre quency of operat ion. PLL_CFG[4] will normally be pulled low but can be
asserted for extended modes of operation. The PLL configuration for the MPC7455 is shown in Table 17
for a set of example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK
frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz column in Table 8.
Note that the settings for Rev. C devices ar e different than those for subsequent devices.
Table 17. MPC7455 Microprocessor PLL Configuration Example for 800-MHz Parts
PLL_CFG
[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33.3 MHz Bus
50 MHz Bus
66.6 MHz Bus
75 MHz Bus
83 MHz Bus
100 MHz Bus
133 MHz
00000 0.5x 2x
01000 2x 2x
01100 2.5x 2x
10000 3x 2x
11100 3.5x 2x
10100 4x 2x 533
(1066)
01110 4.5x 2x 600
(1200)
10110 5x 2x 500
(1000) 667
(1333)
10010 5.5x 2x 550
(1100) 733
(1466)
11010 6x 2x 600
(1200) 800
(1600)
01010 6.5x 2x 540
(1080) 650
(1300)
00100 7x 2x 525
(1050) 580
(1160) 700
(1400)
00010 7.5x 2x 500
(1000) 563
(1125) 623
(1245) 750
(1500)
11000 8x 2x 533
(1066) 600
(1200) 664
(1328) 800
(1600)
01111 9x 2x 600
(1200) 675
(1350) 747
(1494)
8MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series MOTOROLA
General Parameters General Parameters
10101 10x 2x 500
(1000) 667
(1333) 750
(1500)
10011 11x 2x 550
(1100) 733
(1466)
10111 12x 2x 600
(1200) 800
(1600)
01011 13x 2x 650
(1300)
11001 14x 2x 700
(1400)
00011 15x 2x 500
(1000) 750
(1500)
11011 16x 2x 533
(1066) 800
(1600)
00110 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly
11110 PLL off PLL off, no core clocking occurs
Table 17. MPC7455 Microprocessor PLL Configuration Example for 800-M Hz Parts (continued)
PLL_CFG
[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33.3 MHz Bus
50 MHz Bus
66.6 MHz Bus
75 MHz Bus
83 MHz Bus
100 MHz Bus
133 MHz
MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series 9
Ordering Information
1.11 Ordering Information
1.11.1 Part Numbers Addressed by this Specification
Table 21 provides the ordering information for the MPC7455 parts described in this document.
1.11.3 Part Marking
Parts are marked as the example shown in Figure 29.
Figure 29. Motorola Part Marking for BGA Devices
Table 21. Part Marking Nomenclature
XPC 74x5RXnnn x x
Product
Code Part
Identifier Package Processor
Frequency 1
1Processor core frequencies supported by parts addressed by this specification only. Parts addressed by other
specifications may support other maximum core frequencies.
Application Modifier Revision Level
XPC 2
2The X prefi x i n a M ot orol a part number designate s a “Pil ot Pro duc tio n Pro toty pe ” as def ine d by Moto rola SO P 3-13 .
These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified
technology to simulate normal production. These parts have only preliminary reliability and characterization data.
Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the
applic able s ales o f fice ackn owledgi ng t he qua lifica tion s tatu s and t he f act tha t produc t chan ges m ay sti ll oc cur w hile
shipping pilot production prototypes.
7455
7445 RX = CBGA 600
733
800
N:1.3 V ± 50 mV
0 to 105°CC: 2.1; PVR = 8001 0201
Notes:
BGA
Notes:
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States
.
MMMMM M is the 6-digit mask number.
ATWLYYWWA is the traceability code.
XPC7455
RX800NC
MMMMMM
ATWLYYWWA
7450
BGA
XPC7445
RX8000NC
MMMMMM
ATWLYYWWA
7440
10 MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series MOTOROLA
Document Revision History Document Revision History
Document Revision History
Table B provides a revision history for this part number specification.
Table B. Document Revision History
Rev. No. Substantive Change(s)
0 Initial rele as e.
0.1 Updated wording in Table A, ‘Significant Differences from Hardware Specification,’ column.
Corrected part number in heading of Tabl e 7 (changed from MPC7450 to MPC7455).
Added Document Revision History section and Table B.
1 Updated Table 7, note 1.
Added Tables 2, 12, 13, and 17.
1.1 Tabled 9: corrected typo in units for Sleep Mode power, changed “W” to “mW”.
Table 17: corrected PLL_CFG values; previous revisions of this specification had swapped PLL_CFG[0]
with PLL_CFG[4].
MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series 11
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC7455RXNXPNS
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