1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• QSFP MSA compatible
• Four independently addressable transmit and
receive channels
• Highly compact: saving of 60% on edge and
board usage compared to four comparable SFP
modules
• Differential, internally AC-coupled data I/Os
• Electrically z-pluggable, allowing port pop ulation
on demand
• Electrically hot-pluggable
• XFP-like latch mechanism for ease-of-insertion
• Digital Diagnostics Monitoring Interface. Allows
customer management and monitoring of key
modules parameters, analogous to SFP
• Optical connectivity via industry standard
MPO/MTP terminated fiber ribbon
Applications
• High-speed interconnects within and between
switches, routers and transport equ ipment
• Server-Server Clusters, Super-compu ting
interconnections
• Proprietary backplanes
• Interconnects rack-to-rack, shelf-to-she lf, board-
to-board, board-to-optical backplane
• XAUI over fiber-ribbon
• 2xGbE applications
• InfiniBand SDR ap plications
July 2009
Ordering Information
ZL60505MKDB QSFP Transceiver
0°C to +70°C
ZL60505
Parallel Fiber Optic Transceiver
(4 + 4) x 3.125 Gbps
Data Sheet
Figure 1 - ZL60505 QSFP Parallel Fiber Optic Transceiver
VCC1
VCCTx
PIN
Array
VCSEL
Array
TIA/LA
VCSEL
Driver
Laser Diode Supervisor
Diagnostic Supervisor
VCCRx
GND
SCL
SDA
ModPrsL
IntL
1
2
3
4
4
3
2
1
Tx1p
Tx1n
Rx1p
Tx4p
Tx4n
Rx4p
Rx4n
Rx1n
ModSelL LPMode ResetL
ZL60505 Data Sheet
2
Zarlink Semiconductor Inc.
Description
Quad Small Form Factor Pluggable (QSFP) modules are the next generation of pluggable modules intended for
high density applications. A QSFP module is a parallel fiber optical transceiver module with four independent
optical transmit and receive channels. It combines the higher density attractions of parallel modules with some of
the key advantages normally associated with SFP based modules.
It is intended for use in switches, rou ters and data center applications where it provides:
• a saving of greater than 60% in edge and board density as compared to th e use of four SFP module s. This
allows the end-user to shrink system size and lower overall costs.
• simplified heat management through reduction in power consumption of > 50% compared to 4xSFP solution.
• z-axis electrically hot-pluggability allowing port po pulation on demand and in the field. Utilises XFP-like
latching mechanism into board mo unted cage.
• a digital diagnostic monitoring interface similar to that used by SFP modules. This allows customer access to
key module parameters as well as providing alarm and warning flags. This improves customer system
management capability.
The QSFP also benefit s from the existence of a multi-sou rce agreement (MSA) which defines the mechanica l form-
factor, electrical pin-out and diagnostic management interface.
Reliability assurance is based on Telcordia GR-468-CORE and the parts are compliant to the EU directive
2002/95/EC issued 27 January 2003 [RoHS].
Below is a listing of the datums, for various components, referenced to in this document.
Datum Description
A Host Board top surface
B Centerline of bezel
C Distance between Connector terminal thru holes on host board
D Hard stop on transceiver
E Width of transceiver
F Height of transceiver housing
G Width of transceiver pc board
H Leading edge of signal contact pads on transceiver pc board
J Top surface of transceiver pc board
K Host Board thru hole #1 to accept connector guide post
L Host Board thru hole #2 to accept connector guide post
M Width of bezel cut-out
X&Y Host board horizontal and depth datum established by customers’ fiducials
© Zarlink Semiconductor 2007. All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
Title
Drawing type
Package code
Projection Method
1
116641 Rev 1
12-JUL-06
M.Andersson
116641
MK
23
116641 Rev 2 116641 Rev 3 116641 Rev 4
15-MAR-07 20-FEB-09 25-MAR-09
M.Andersson M.Andersson M.Andersson
QSFP Definition of datums
© Zarlink Semiconductor 2007. All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
Title
Drawing type
Package code
Projection Method
1
116641 Rev 1
12-JUL-06
M.Andersson
116641
MK
234
116641 Rev 2 116641 Rev 3 116641 Rev 4
15-MAR-07 20-FEB-09 25-MAR-09
M.Andersson M.Andersson M.Andersson
A
B
DETAIL VIEW B
Contact pad numbers 21, 22, 36 and 37 are visible.
DETAIL VIEW A
Break out view of Latch mechanism.
QSFP Transceiver
D
16,5 MIN
qof E
6
`
0,2
(2x)
1,1 MAX
18,35
`
0,1
Valid for 48,4`0,2
E
2,2 MIN
32 MIN
13 MIN
Flatness tolerance applies for indicated area.
Surface thermally conductive.
7,8
10,7
33,4 in locked position.
35,7 in un-locked position.
3n`0,1 Thru hole
13,68
`
0,1
j0,1 E
Label
For label contents, see separate drawing.
Label
For label contents, see separate drawing.
19 MAX
Applies for section that
extends outside of cage.
(16,4)
29,6 `0,1
2,5
48,4 `0,2
8
3,2 `0,1
15,5 TYP
c0,075
4,25 `0,15
1,7
`
0,1
5,2
`
0,15
2,25 `0,1
0,6
`
0,05
3,6 MIN
2`0,15
8,5
`
0,1
F
j0,1 F
5,5 MIN
2 MIN
0,5
`
0,2
4,4
`
0,2
Optical q
DH
1,1 `0,18
1,5 MINo
0,5 MIN
NOTES:-
1. All dimensions in mm.
2. Gen. tol. ISO-2768-mK
2,3
© Zarlink Semiconductor 2007. All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
Title
Drawing type
Package code
Projection Method
1
116641 Rev 1
12-JUL-06
M.Andersson
116641
MK
234
116641 Rev 2 116641 Rev 3 116641 Rev 4
15-MAR-07 20-FEB-09 25-MAR-09
M.Andersson M.Andersson M.Andersson
20
38
TOP VIEW OF MODULE PCB
1
19
BOTTOM VIEW OF MODULE PCB
Pattern layout for QSFP PCB
PCB Top surface
H
qof G
7,4
7
0,8 (18x)
16,4
`
0,1
G
0,6
`
0,05
j0,2 J G H
j0,1 JG
1,55 MIN
0,8 MIN
1,45 `0,1
0,4 `0,05
0,9 `0,05
19x
0,3 x45~ MIN (2x)
J
qof G
H
0,4 `0,05
0,8 MIN
0,9 `0,05
1,55 MIN
7,4
7
0,8 (18x)
0,6
`
0,05
j0,2 J G H
j0,1 JG
19x
Solder mask keep out area Solder mask keep out area
NOTES:-
1. All dimensions in mm.
2. Contact pad plating: 0,38 µm MIN Au over 1,27 µm MIN Ni.
© Zarlink Semiconductor 2007. All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
Title
Drawing type
Package code
Projection Method
1
116641 Rev 1
12-JUL-06
M.Andersson
116641
MK
234
116641 Rev 2 116641 Rev 3 116641 Rev 4
15-MAR-07 20-FEB-09 25-MAR-09
M.Andersson M.Andersson M.Andersson
19 20
138
19 20
138
QSFP Host Mechanical Layout
L
K
qof K & L
3,1
7,6
9 (6x)
10,6
11,3 MIN
3,4
7,2
16,8
C
1,1
19
(17,9)
22,15 MIN
jn0,1 AKL
12x
n1,05±0,05
Hatched area denotes component and
trace keep out (except chassis ground).
3,1 7,6
37 MAX
Location of edge of PCB is application specific
A
Host Board Top Surface
qof K & L
qof C
5,18 2,5
j0,05 K L
38x
1,8`0,03
15,8
0,4
0,8 (36x)
j0,05 K L
38x
0,35`0,03
10,3 MAX
1,69 MAX
3,05 MIN
15,02 MAX
19,2 MAX
j0,05 A X K
j0,05 A X K
n1,55`0,05
n1,55`0,05
See detail view A
DETAIL VIEW A
Area denotes component keep out (traces allowed).
NOTE:-
All dimensions in mm.
Optional
Optional
© Zarlink Semiconductor 2007. All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
Title
Drawing type
Package code
Projection Method
1
116641 Rev1
12-JUL-06
M.Andersson
116641
MK
234
116641 Rev2 116641 Rev3 116641 Rev4
15-MAR-07 20-FEB-09 25-MAR-09
M.Andersson M.Andersson M.Andersson
A
A
QSFP Recommended Bezel Design
qof K & L
B
0,15
`
0,1; Note 2
A
43,8 ` Tolerance; Note 4
37 REF
21 `0,1; Note 3
10,15
`
0,1
20 `0,1
R0,3 MAX
(4x each cut-out)
NOTES:-
1. All dimensions in mm.
2. Not recommended for PCI add-in card application.
3. Calculation of tolerance = 1/2 x Bezel thickness + 0,3
4. Minimum pitch dimension for individual cages. For ganged (1-by-x) applications, the port spacing can be reduced to 19.0 MIN.
SECTION VIEW A-A
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any guarantee th at such methods of use wil l be satisfactory in a sp ecific piece of equip ment. It is the user ’s responsibilit y to fully determin e the performance and
suitability of any equipment usi ng such information and to ensure that any publication or data used is up t o date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or paramete rs. These products are not suitable for use in any medical products whose failure to perform may result in
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Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
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trademarks of Zarlink Semiconductor Inc.
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