LTC6655/LTC6655LN 0.25ppm Noise, Low Drift Precision References DESCRIPTION FEATURES Low Noise: n 0.25ppm P-P (0.1Hz to 10Hz) 625nVP-P for the LTC6655-2.5 n 0.21ppm RMS (10Hz to 1kHz) for the LTC6655LN CNR = 100F n Low Drift: 2ppm/C Max n High Accuracy: 0.025% Max n No Humidity Sensitivity (LS8 Package) n Thermal Hysteresis (LS8): 30ppm (-40C to 85C) n Long-Term Drift (LS8): 20ppm/kHr n 100% Tested at -40C, 25C and 125C n Load Regulation: <10ppm/mA n Sinks and Sources Current: 5mA n Low Dropout: 500mV n Maximum Supply Voltage: 13.2V n Low Power Shutdown: <20A Max n Available Output Voltages: 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V, 5V n Available in an 8-Lead MSOP and High Stability Hermetic 5mm x 5mm LS8 Packages n APPLICATIONS The LTC(R)6655 is a complete family of precision bandgap voltage references, offering exceptional noise and drift performance. This low noise and drift is ideally suited for the high resolution measurements required by instrumentation and test equipment. In addition, the LTC6655 is fully specified over the temperature range of -40C to 125C, ensuring its suitability for demanding automotive and industrial applications. Advanced curvature compensation allows this bandgap reference to achieve a drift of less than 2ppm/C with a predictable temperature characteristic and an output voltage accurate to 0.025%, reducing or eliminating the need for calibration. The LTC6655LN Low Noise comes with a noise reduction pin that enables reduction of wideband noise with the addition of a single capacitor. The LTC6655 can be powered from as little as 500mV above the output voltage to as much as 13.2V. Superior load regulation with source and sink capability, coupled with exceptional line rejection, ensures consistent performance over a wide range of operating conditions. A shutdown mode is provided for low power applications. The LTC6655 references are offered in an 8-lead MSOP package and an 8-lead LS8 package. The LS8 is a 5mm x 5mm surface mount hermetic package that provides outstanding stability. Instrumentation and Test Equipment High Resolution Data Acquisition Systems n Weigh Scales n Precision Battery Monitors n Precision Regulators n Medical Equipment n n All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION Basic Connection 3V < VIN 13.2V CIN 0.1F Low Frequency 0.1Hz to 10Hz Noise (LTC6655-2.5) LTC6655-2.5 VIN VOUT_F SHDN VOUT VOUT_S GND COUT 10F 6655 TA01a 500nV/DIV Basic Connection with Noise Reduction 3V < VIN 13.2V CIN 0.1F LTC6655LN-2.5 VIN VOUT SHDN NR GND CNR 10F VOUT COUT 10F 1s/DIV 6655 TA01b 6655 TA01c Rev. H Document Feedback For more information www.analog.com 1 LTC6655/LTC6655LN ABSOLUTE MAXIMUM RATINGS (Note 1) Input Voltage VIN to GND........................................... -0.3V to 13.2V SHDN to GND............................ -0.3V to (VIN + 0.3V) Output Voltage: VOUT_F....................................... -0.3V to (VIN + 0.3V) VOUT_S...................................................... -0.3V to 6V NR............................................................ -0.3V to 6V Output Short-Circuit Duration....................... Indefinite Operating Temperature Range (Note 2).. -40C to 125C Storage Temperature Range (Note 2)...... -65C to 150C Lead Temperature Range (Soldering, 10 sec) (Note 3).................................................................. 300C PIN CONFIGURATION LTC6655 LTC6655LN TOP VIEW SHDN VIN GND GND 1 2 3 4 8 7 6 5 TOP VIEW SHDN VIN GND GND GND VOUT_F VOUT_S GND 1 2 3 4 8 7 6 5 GND VOUT_F NR GND MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150C, JA = 300C/W STAR ALL GND CONNECTIONS AT PIN 4 MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150C, JA = 300C/W STAR ALL GND CONNECTIONS AT PIN 4 LTC6655 TOP VIEW GND SHDN 1 VIN 2 GND 3 8 4 7 VOUT_F 6 VOUT_S 5 GND GND LS8 PACKAGE 8-PIN LEADLESS CHIP CARRIER (5mm x 5mm) TJMAX = 150C, JA = 120C/W STAR ALL GND CONNECTIONS AT PIN 4 2 Rev. H For more information www.analog.com LTC6655/LTC6655LN ORDER INFORMATION PART LEAD FREE FINISH TAPE AND REEL MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6655BHMS8-1.25#PBF LTC6655BHMS8-1.25#TRPBF LTFDG 8-Lead Plastic MSOP -40C to 125C LTC6655CHMS8-1.25#PBF LTC6655CHMS8-1.25#TRPBF LTFDG 8-Lead Plastic MSOP -40C to 125C LTC6655BHMS8-2.048#PBF LTC6655BHMS8-2.048#TRPBF LTFDH 8-Lead Plastic MSOP -40C to 125C LTC6655CHMS8-2.048#PBF LTC6655CHMS8-2.048#TRPBF LTFDH 8-Lead Plastic MSOP -40C to 125C LTC6655BHMS8-2.5#PBF LTC6655BHMS8-2.5#TRPBF LTFCY 8-Lead Plastic MSOP -40C to 125C LTC6655CHMS8-2.5#PBF LTC6655CHMS8-2.5#TRPBF LTFCY 8-Lead Plastic MSOP -40C to 125C LTC6655BHMS8-3#PBF LTC6655BHMS8-3#TRPBF LTFDJ 8-Lead Plastic MSOP -40C to 125C LTC6655CHMS8-3#PBF LTC6655CHMS8-3#TRPBF LTFDJ 8-Lead Plastic MSOP -40C to 125C LTC6655BHMS8-3.3#PBF LTC6655BHMS8-3.3#TRPBF LTFDK 8-Lead Plastic MSOP -40C to 125C LTC6655CHMS8-3.3#PBF LTC6655CHMS8-3.3#TRPBF LTFDK 8-Lead Plastic MSOP -40C to 125C LTC6655BHMS8-4.096#PBF LTC6655BHMS8-4.096#TRPBF LTFDM 8-Lead Plastic MSOP -40C to 125C LTC6655CHMS8-4.096#PBF LTC6655CHMS8-4.096#TRPBF LTFDM 8-Lead Plastic MSOP -40C to 125C LTC6655BHMS8-5#PBF LTC6655BHMS8-5#TRPBF LTFDN 8-Lead Plastic MSOP -40C to 125C LTC6655CHMS8-5#PBF LTC6655CHMS8-5#TRPBF LTFDN 8-Lead Plastic MSOP -40C to 125C LTC6655LNBHMS8-2.5#PBF LTC6655LNBHMS8-2.5#TRPBF LTHFK 8-Lead Plastic MSOP -40C to 125C LTC6655LNCHMS8-2.5#PBF LTC6655LNCHMS8-2.5#TRPBF LTHFK 8-Lead Plastic MSOP -40C to 125C LTC6655LNBHMS8-5#PBF LTC6655LNBHMS8-5#TRPBF LTHFN 8-Lead Plastic MSOP -40C to 125C LTC6655LNCHMS8-5#PBF LTC6655LNCHMS8-5#TRPBF LTHFN 8-Lead Plastic MSOP -40C to 125C LTC6655BHLS8-2.5 #PBF N/A 665525 8-Lead Ceramic LCC (5mm x 5mm) -40C to 125C LTC6655CHLS8-2.5 #PBF N/A 665525 8-Lead Ceramic LCC (5mm x 5mm) -40C to 125C LTC6655BHLS8-4.096#PBF N/A 554096 8-Lead Ceramic LCC (5mm x 5mm) -40C to 125C LTC6655CHLS8-4.096#PBF N/A 554096 8-Lead Ceramic LCC (5mm x 5mm) -40C to 125C LTC6655BHLS8-5 #PBF N/A 66555 8-Lead Ceramic LCC (5mm x 5mm) -40C to 125C LTC6655CHLS8-5 #PBF N/A 66555 8-Lead Ceramic LCC (5mm x 5mm) -40C to 125C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. This product is only offered in trays. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev. H For more information www.analog.com 3 LTC6655/LTC6655LN AVAILABLE OPTIONS OUTPUT VOLTAGE INITIAL ACCURACY TEMPERATURE COEFFICIENT PART NUMBER 1.250 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHMS8-1.25 LTC6655CHMS8-1.25 2.048 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHMS8-2.048 LTC6655CHMS8-2.048 2.500 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHMS8-2.5 LTC6655CHMS8-2.5 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHLS8-2.5 LTC6655CHLS8-2.5 0.025% 0.05% 2ppm/C 5ppm/C LTC6655LNBHMS8-2.5 LTC6655LNCHMS8-2.5 3.000 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHMS8-3.0 LTC6655CHMS8-3.0 3.300 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHMS8-3.3 LTC6655CHMS8-3.3 4.096 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHMS8-4.096 LTC6655CHMS8-4.096 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHLS8-4.096 LTC6655CHLS8-4.096 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHMS8-5 LTC6655CHMS8-5 0.025% 0.05% 2ppm/C 5ppm/C LTC6655BHLS8-5 LTC6655CHLS8-5 0.025% 0.05% 2ppm/C 5ppm/C LTC6655LNBHMS8-5 LTC6655LNCHMS8-5 5.000 See Order Information section for complete part number listing. 4 Rev. H For more information www.analog.com LTC6655/LTC6655LN ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = VOUT + 0.5V, VOUT_S connected to VOUT_F , unless otherwise noted. PARAMETER CONDITIONS Output Voltage LTC6655B LTC6655C MIN Output Voltage Temperature Coefficient (Note 4) LTC6655B LTC6655C Line Regulation VOUT + 0.5V VIN 13.2V, SHDN = 2V TYP -0.025 -0.05 l l ISOURCE = 5mA LTC6655MS8 ppm/C ppm/C 5 25 40 ppm/V ppm/V 15 ppm/mA ppm/mA 15 ppm/mA ppm/mA 20 ppm/mA ppm/mA 30 ppm/mA ppm/mA 45 ppm/mA ppm/mA 35 ppm/mA ppm/mA 3 3 l LTC6655LNMS8 6 l ISINK = 5mA LTC6655MS8 10 l LTC6655LS8 20 l LTC6655LNMS8 14 l Operating Voltage (Note 6) LTC6655-1.25, LTC6655-2.048, LTC6655-2.5 ISOURCE = 5mA, VOUT Error 0.1% l LTC6655-3, LTC6655-3.3, LTC6655-4.096, LTC6655-5 ISOURCE = 5mA, VOUT Error 0.1% IOUT = 0mA, VOUT Error 0.1% l VOUT + 0.5 l VOUT + 0.2 Output Short-Circuit Current Short VOUT to GND Short VOUT to VIN Shutdown Pin (SHDN) Logic High Input Voltage Logic High Input Current, SHDN = 2V l l Logic Low Input Voltage Logic Low Input Current, SHDN = 0.8V l l Supply Current Shutdown Current 3 13.2 V 13.2 13.2 V V 20 20 2.0 mA mA 12 V A 0.8 15 V A l 7 7.5 mA mA l 20 A No Load 5 SHDN Tied to GND % % 2 5 l LTC6655LS8 UNITS 1 2.5 l Load Regulation (Note 5) MAX 0.025 0.05 Rev. H For more information www.analog.com 5 LTC6655/LTC6655LN ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = VOUT + 0.5V, VOUT_S connected to VOUT_F , unless otherwise noted. PARAMETER CONDITIONS Output Voltage Noise (Note 7) LTC6655 0.1Hz f 10Hz 10Hz f 1kHz 0.25 0.67 ppmP-P ppmRMS LTC6655LN 0.1Hz f 10Hz, CNR = 100F 10Hz f 1kHz, CNR = 100F 0.12 0.21 ppmP-P ppmRMS 0.1% Settling, COUT = 2.7F 400 s 60 20 ppm/kHr ppm/kHr LTC6655MS8 T = 0C to 70C T = -40C to 85C T = -40C to 125C 20 30 60 ppm ppm ppm LTC6655LS8 T = 0C to 70C T = -40C to 85C T = -40C to 125C 5 30 80 ppm ppm ppm Turn-On Time MIN Long-Term Drift of Output Voltage (Note 8) LTC6655MS8 LTC6655LS8 Hysteresis (Note 9) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Precision may be affected if the parts are stored outside of the specified temperature range. Large temperature changes may cause changes in device performance due to thermal hysteresis. For best performance, extreme temperatures should be avoided whenever possible. Note 3: The stated temperature is typical for soldering of the leads during manual rework. For detailed IR reflow recommendations, refer to the Applications Information section. Note 4: Temperature coefficient is measured by dividing the maximum change in output voltage by the specified temperature range. Note 5: Load regulation is measured on a pulse basis from no load to the specified load current. Load current does not include the 2mA sense current. Output changes due to die temperature change must be taken into account separately. Note 6: Excludes load regulation errors. Minimum supply for the LTC66551.25, LTC6655-2.048 and LTC6655-2.5 is set by internal circuitry supply requirements, regardless of load condition. Minimum supply for the LTC6655-3, LTC6655-3.3, LTC6655-4.096 and LTC6655-5 is specified by load current. Note 7: Peak-to-peak noise is measured with a 2-pole highpass filter at 0.1Hz and 3-pole lowpass filter at 10Hz. The unit is enclosed in a still-air environment to eliminate thermocouple effects on the leads, and the test time is 10 seconds. Due to the statistical nature of noise, repeating 6 TYP MAX UNITS noise measurements will yield larger and smaller peak values in a given measurement interval. By repeating the measurement for 1000 intervals, each 10 seconds long, it is shown that there are time intervals during which the noise is higher than in a typical single interval, as predicted by statistical theory. In general, typical values are considered to be those for which at least 50% of the units may be expected to perform similarly or better. For the 1000 interval test, a typical unit will exhibit noise that is less than the typical value listed in the Electrical Characteristics table in more than 50% of its measurement intervals. See Application Note 124 for noise testing details. RMS noise is measured with a spectrum analyzer in a shielded environment. Note 8: Long-term stability typically has a logarithmic characteristic and therefore, changes after 1000 hours tend to be much smaller than before that time. Total drift in the second thousand hours is normally less than one-third that of the first thousand hours with a continuing trend toward reduced drift with time. Long-term stability is also affected by differential stresses between the IC and the board material created during board assembly. Note 9: Hysteresis in output voltage is created by mechanical stress that differs depending on whether the IC was previously at a higher or lower temperature. Output voltage is always measured at 25C, but the IC is cycled to the hot or cold temperature limit before successive measurements. Hysteresis is roughly proportional to the square of the temperature change. For instruments that are stored at well controlled temperatures (within 20 or 30 degrees of operational temperature), hysteresis is usually not a significant error source. Typical hysteresis is the worst case of 25C to cold to 25C or 25C to hot to 25C, preconditioned by one thermal cycle. Rev. H For more information www.analog.com LTC6655/LTC6655LN TYPICAL PERFORMANCE CHARACTERISTICS Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages fall between these curves and can be estimated based on their voltage output. 1.25V Low Frequency 0.1Hz to 10Hz Noise 1.25V Output Voltage Temperature Drift 200nV/ DIV 1s/DIV 6655 G01 1.25V Load Regulation (Sourcing) 20 3 TYPICAL UNITS OUTPUT VOLTAGE CHANGE (ppm) OUTPUT VOLTAGE (V) 1.2504 1.2502 1.2500 1.2498 1.2496 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125C 25C -40C 10 0 -10 -20 -30 -40 0.001 125 0.01 0.1 1 OUTPUT CURRENT (mA) 6655 G03 6655 G02 1.25V Output Voltage Noise Spectrum 1.25V Load Regulation (Sinking) 160 120 80 40 0 0.001 1.25V Sinking Current with a 3.3F Output Capacitor 25 125C 25C -40C NOISE VOLTAGE (nV/Hz) OUTPUT VOLTAGE CHANGE (ppm) 200 0.01 0.1 1 OUTPUT CURRENT (mA) COUT = 100F 20 0mA VOUT 10mV/DIV COUT = 10F 10 5 COUT = 3.3F 0.1 1 10 FREQUENCY (kHz) 100 14 10 8 6 4 40 30 20 10 2 0 TA = 25C 50 NUMBER OF PARTS SUPPLY CURRENT (A) 6655 G07 1.25V VOUT Distribution 60 125C 25C -40C 12 VOUT 10mV/DIV 6655 G06 1000 1.25V Shutdown Supply Current vs Input Voltage 0mA IOUT -5mA 200s/DIV 6655 G05 1.25V Sourcing Current with a 3.3F Output Capacitor 200s/DIV 5mA 15 0 0.01 10 IOUT COUT = 2.7F 6655 G04 COUT = 3.3F 10 0 2 8 6 10 4 INPUT VOLTAGE (V) 12 14 6655 G08 0 1.2495 1.2498 1.2500 VOUT (V) 1.2503 1.2505 6655 G09 Rev. H For more information www.analog.com 7 LTC6655/LTC6655LN TYPICAL PERFORMANCE CHARACTERISTICS Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages fall between these curves and can be estimated based on their voltage output. 2.5V Low Frequency 0.1Hz to 10Hz Noise 2.5V Output Voltage Temperature Drift 500nV/ DIV 6655 G10 1s/DIV 2.5V Load Regulation (Sourcing) 10 3 TYPICAL UNITS OUTPUT VOLTAGE CHANGE (ppm) OUTPUT VOLTAGE (V) 2.5010 2.5005 2.5000 2.4995 2.4990 -50 0 50 100 TEMPERATURE (C) 0 -10 -20 -30 -40 125C 25C -40C -50 0.001 150 0.01 0.1 1 OUTPUT CURRENT (mA) 10 6655 G12 6655 G11 2.5V Supply Current vs Input Voltage 2.5V Load Regulation (Sinking) 120 100 80 60 40 20 8 14 7 12 6 5 4 3 2 0.01 0.1 1 OUTPUT CURRENT (mA) 0 10 6655 G13 2.5V Minimum VIN - VOUT Differential (Sourcing) 2 4 6 8 10 INPUT VOLTAGE (V) 12 8 6 4 0 14 OUTPUT CURRENT (mA) 0.1 125C 25C -40C 0.1 INPUT - OUTPUT VOLTAGE (V) 1 6655 G16 2 4 6 8 10 INPUT VOLTAGE (V) 12 14 6655 G15 60 1 0.1 0.01 -0.15 0 2.5V Output Voltage Noise Spectrum 10 1 125C 25C -40C 6655 G14 2.5V Minimum VIN - VOUT Differential (Sinking) 10 0.01 0.01 0 10 2 NOISE VOLTAGE (nV/Hz) -20 0.001 OUTPUT CURRENT (mA) 125C 25C -40C 1 0 8 SUPPLY CURRENT (A) 125C 25C -40C 140 SUPPLY CURRENT (mA) OUTPUT VOLTAGE CHANGE (ppm) 160 2.5V Shutdown Supply Current vs Input Voltage 125C 25C -40C -0.05 0.05 INPUT - OUTPUT VOLTAGE (V) 0.15 6655 G17 45 COUT = 100F COUT = 2.7F 30 15 0 0.001 COUT = 10F 0.01 0.1 1 10 FREQUENCY (kHz) 100 1000 6655 G18 Rev. H For more information www.analog.com LTC6655/LTC6655LN TYPICAL PERFORMANCE CHARACTERISTICS Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages fall between these curves and can be estimated based on their voltage output. 2.5V Temperature Drift Distribution 2.5V VOUT Distribution 90 14 TA = 25C 12 80 70 NUMBER OF PARTS NUMBER OF PARTS 2.5 -40C TO 125C 60 50 40 30 20 2.0 10 VTH_UP VTRIP (V) 100 8 6 0 2.4992 2.4996 2.5000 VOUT (V) 2.5004 0 2.5008 0 0.4 0.8 1.2 1.6 2 2.5V Output Impedance vs Frequency 2 4 80 60 40 COUT = 2.7F COUT = 10F COUT = 100F 10 100 6655 G22 6 8 VIN (V) 10 12 14 6655 G21 2.5V Line Regulation 2.502 COUT = 2.7F COUT = 10F COUT = 100F OUTPUT VOLTAGE (V) 100 OUTPUT IMPEDENCE () POWER SUPPLY REJECTION RATIO (dB) 10 0.1 1 FREQUENCY (kHz) 0.0 2.8 6655 G20 120 0.01 2.4 DRIFT (ppm/C) 2.5V Power Supply Rejection Ratio vs Frequency 0 0.001 VTH_DN 1.0 0.5 6655 G19 20 1.5 4 2 10 2.5V SHDN Input Voltage Thresholds vs VIN 1 0.1 0.01 0.001 0.01 0.1 1 10 FREQUENCY (kHz) 100 1000 6655 G23 2.501 2.500 2.499 2.498 125C 25C -40C 0 2 10 4 6 8 INPUT VOLTAGE (V) 12 14 6655 G24 Rev. H For more information www.analog.com 9 LTC6655/LTC6655LN TYPICAL PERFORMANCE CHARACTERISTICS Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages fall between these curves and can be estimated based on their voltage output. 5V Low Frequency 0.1Hz to 10Hz Noise 5V Output Voltage Temperature Drift 5.0010 5V Load Regulation (Sourcing) 10 OUTPUT VOLTAGE CHANGE (ppm) 3 TYPICAL UNITS OUTPUT VOLTAGE (V) 5.0005 500nV/ DIV 5.0000 4.9995 4.9990 6655 G25 1s/DIV 4.9985 -50 -25 75 0 25 50 TEMPERATURE (C) 100 0 -10 -20 -30 -40 -50 0.01 125 125C 25C -40C 0.1 1 OUTPUT CURRENT (mA) 6655 G26 80 60 40 20 6 120 5 100 4 3 2 125C 25C -40C 1 0 -20 0.01 0.1 1 OUTPUT CURRENT (mA) 0 10 5V Output Voltage Noise Spectrum NOISE VOLTAGE (nV/Hz) 125C 25C -40C SUPPLY CURRENT (mA) OUTPUT VOLTAGE CHANGE (ppm) 100 0 2 8 6 10 4 INPUT VOLTAGE (V) 12 6655 G28 60 40 COUT = 10F 20 0 0.01 0.1 1 10 FREQUENCY (kHz) 100 1000 6655 G30 5V Start-Up Response with a 3.3F Output Capacitor 10 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) COUT = 2.7F 80 5V Minimum VIN-VOUT Differential (Sinking) 10 1 0.1 125C 25C -40C 0.1 INPUT-OUTPUT VOLTAGE (V) 1 VIN 2V/DIV 1 VOUT 2V/DIV 0.1 0.01 -0.3 125C 25C -40C -0.2 -0.1 0 INPUT-OUTPUT VOLTAGE (V) 6655 G31 10 14 COUT = 100F 6655 G29 5V Minimum VIN-VOUT Differential (Sourcing) 0.01 0.01 6655 G27 5V Supply Current vs Input Voltage 5V Load Regulation (Sinking) 10 COUT = 3.3F 400s/DIV 6655 G33 0.1 6655 G32 Rev. H For more information www.analog.com LTC6655/LTC6655LN TYPICAL PERFORMANCE CHARACTERISTICS Characteristic curves shown below are the LTC6655LN option. LTC6655LN-2.5 Output Voltage Noise Spectrum 70 LTC6655LN-2.5 Output Integrated Noise 5 COUT = 2.7F INTEGRATED NOISE (VRMS) CNR = 10F 50 CNR = 1F CNR = 0.1F 40 30 20 10 0 0.01 COUT = 2.7F 4 CNR = 0.1F 3 CNR = 1F 2 CNR = 10F 1 CNR = 100F 0.1 1 10 FREQUENCY (kHz) 100 1k CNR = 100F 0 0.01 0.1 1 FREQUENCY (kHz) 1000 10 6655 G35 6655 G34 LTC6655LN-2.5 Effect of NR Pin Leakage on VOUT 800 600 CHANGE IN VOUT (V) NOISE VOLTAGE (nV/Hz) 60 400 200 0 -200 -400 -600 -800 -1000 -1000 -750 -500 -250 0 250 500 750 1000 CURRENT INJECTED INTO THE NR PIN (nA) 6655 G36 Rev. H For more information www.analog.com 11 LTC6655/LTC6655LN PIN FUNCTIONS SHDN (Pin 1): Shutdown Input. This active low input powers down the device to <20A. If left open, an internal pull-up resistor puts the part in normal operation. It is recommended to tie this pin high externally for best performance during normal operation. Output error is RTRACE * 2mA, regardless of load current. For load currents <100A, tie directly to VOUT_F pin. VIN (Pin 2): Power Supply. Bypass VIN with a 0.1F, or larger, capacitor to GND. VOUT_F (Pin 7 - LTC6655): VOUT Force Pin. This pin sources and sinks current to the load. An output capacitor of 2.7F to 100F is required. GND (Pin 4): Device Ground. This pin is the main ground and must be connected to a noise-free ground plane. VOUT_S (Pin 6 - LTC6655): VOUT Sense Pin. Connect this pin at the load and route with a wide metal trace to minimize load regulation errors. This pin sinks 2mA. NR (Pin 6 - LTC6655LN): Noise Reduction Pin. To band limit noise, connect a capacitor between this pin and ground. See Applications Information section. VOUT_F (Pin 7 - LTC6655LN): VOUT Pin. This pin sources and sinks current to the load. An output capacitor of 2.7F to 100F is required. GND (Pins 3, 5, 8): Internal Function. Ground these pins. BLOCK DIAGRAM LTC6655 2 1 VIN SHDN + VOUT_F BANDGAP 7 - VOUT_S 4 GND 6 6655 BD GND 3,5,8 LTC6655LN NR 2 1 6 VIN SHDN + BANDGAP VOUT_F 7 - 4 GND 6655LN BD GND 3,5,8 12 Rev. H For more information www.analog.com LTC6655/LTC6655LN APPLICATIONS INFORMATION Bypass and Load Capacitors The LTC6655 voltage references require a 0.1F or larger input capacitor located close to the part to improve power supply rejection. An output capacitor with a value between 2.7F and 100F is also required. The output capacitor has a direct effect on the stability, turn-on time and settling behavior. Choose a capacitor with low ESR to insure stability. Resistance in series with the output capacitor (ESR) introduces a zero in the output buffer transfer function and could cause instability. The 2.7F to 100F range includes several types of capacitors that are readily available as through-hole and surface mount components. It is recommended to keep ESR less than or equal to 0.1. Capacitance and ESR are both frequency dependent. At higher frequencies capacitance drops and ESR increases. To insure stable operation the output capacitor should have the required values at 100kHz. In order to achieve the best performance, caution should be used when choosing a capacitor. X7R ceramic capacitors are small, come in appropriate values and are relatively stable over a wide temperature range. However, for a low noise application X7R capacitors may not be suitable since they may exhibit a piezoelectric effect. The mechanical vibrations cause a charge displacement in the ceramic dielectric and the resulting perturbation can look like noise. If X7R capacitors are necessary, a thorough bench evaluation should be completed to verify proper performance. For very low noise applications where every nanovolt counts, film capacitors should be considered for their low noise and lack of piezoelectric effects. Film capacitors such as polyester, polystyrene, polycarbonate, and polypropylene have good temperature stability. Additional care must be taken as polystyrene and polypropylene have an upper temperature limit of 85C to 105C. Above these temperatures, the working voltages need to be derated according to manufacturer's specifications. Another type of film capacitor is polyphenylene sulfide (PPS). These devices work over a wide temperature range, are stable, and have large capacitance values beyond 1F. In general, film capacitors are found in surface mount and leaded packages. Table1 is a partial list of capacitor companies and some of their available products. In voltage reference applications, film capacitor lifetime is affected by temperature and applied voltage. When polyester capacitors are operated beyond their rated temperatures (some capacitors are not rated for operation above 85C) they need to be derated. Voltage derating is usually accomplished as a ratio of applied voltage to rated voltage limit. Contact specific film capacitor manufacturers to determine exact lifetime and derating information. The lifetime of X7R capacitors is long, especially for reference applications. Capacitor lifetime is degraded by operating near or exceeding the rated voltage, at high temperature, with AC ripple or some combination of these. Most reference applications have AC ripple only during transient events. Table1. Film Capacitor Companies COMPANY DIELECTRIC AVAILABLE CAPACITANCE TEMPERATURE RANGE TYPE Cornell Dublier Polyester 0.5F to 10F -55C to 125C DME Dearborn Electronics Polyester 0.1F to 12F -55C to 125C 218P, 430P, 431P, 442P, and 410P Tecate Polyester 0.01F to 18F -40C to 105C 901, 914, and 914D Wima Polyester 10F to 22F -55C to 100C MKS 4, MKS 2-XL Vishay Polyester 1000pF to 15F -55C to 125C MKT1820 Vishay Polycarbonate 0.01F to 10F -55C to 100C MKC1862, 632P Dearborn Electronics Polyphenylene Sulfide (PPS) 0.01F to 15F -55C to 125C 820P, 832P, 842P, 860P, and 880P Wima Polyphenylene Sulfide (PPS) 0.01F to 6.8F -55C to 140C SMD-PPS Rev. H For more information www.analog.com 13 LTC6655/LTC6655LN APPLICATIONS INFORMATION The choice of output capacitor also affects the bandwidth of the reference circuitry and resultant noise peaking. As shown in Figure1, the bandwidth is inversely proportional to the value of the output capacitor. NOISE VOLTAGE (nV/Hz) 60 Noise peaking is related to the phase margin of the output buffer. Higher peaking generally indicates lower phase margin. Other factors affecting noise peaking are temperature, input voltage, and output load current. 45 The turn-on time is slew limited and determined by the short-circuit current, the output capacitor, and output voltage as shown in the equation: 0.01 0.1 1 10 FREQUENCY (kHz) 100 1000 6655 F01 Figure1. Output Voltage Noise Spectrum 1,2 VIN 3V CIN 0.1F COUT ISC 7 LTC6655-2.5 6 VOUT 100 COUT 3.3F 3,4,5,8 VGEN 0.5V 6655 F02 Figure2. Transient Load Test Circuit For example, the LTC6655-2.5V, with a 3.3F output capacitor and a typical short-circuit current of 20mA, the start-up time would be approximately: COUT = 10F 15 0 0.001 Results for the transient response plots (Figures3 to 8) were produced with the test circuit shown in Figure2 unless otherwise indicated. COUT = 2.7F 30 Start-Up and Load Transient Response tON = VOUT * COUT = 100F 3.3 * 10 -6 F 2.5V * = 412s 0.02A VIN 2V/DIV VOUT 1V/DIV The resulting turn-on time is shown in Figure3. Here the output capacitor is 3.3F and the input capacitor is 0.1F. COUT = 3.3F Figure4 shows the output response to a 500mV step on VIN. The output response to a current step sourcing and sinking is shown in Figures 5 and 6, respectively. Figure7 shows the output response as the current goes from sourcing to sinking. 200s/DIV 6655 F03 Figure3. Start-Up Response VIN 3.5V 3V Shutdown Mode The LTC6655 family of references can be shut down by tying the SHDN pin to ground. There is an internal pull-up resistor tied to this pin. If left unconnected this pin rises to VIN and the part is enabled. Due to the low internal pull-up current, it is recommended that the SHDN pin be pulled high externally for normal operation to prevent accidental 14 VOUT 50mV/DIV COUT = 3.3F 400s/DIV 6655 F04 Figure4. Output Response with a 500mV Step On VIN Rev. H For more information www.analog.com LTC6655/LTC6655LN APPLICATIONS INFORMATION shutdown due to system noise or leakage currents. The turn-on/turn-off response due to shutdown is shown in Figure8. 0mA IOUT -5mA VOUT 10mV/DIV COUT = 3.3F 200s/DIV 6655 F05 Figure5. Output Response with a 5mA Load Step Sourcing To control shutdown from a low voltage source, a MOSFET can be used as a pull-down device as shown in Figure9. Note that an external resistor is unnecessary. A MOSFET with a low drain-to-source leakage over the operating temperature range should be chosen to avoid inadvertently pulling down the SHDN pin. A resistor may be added from SHDN to VIN to overcome excessive MOSFET leakage. The SHDN thresholds have some dependency on VIN and temperature as shown in the Typical Performance Characteristics section. Avoid leaving SHDN at a voltage between the thresholds as this will cause an increase in supply current due to shoot-through current. 5mA IOUT 0mA VOUT 10mV/DIV 3V VIN 13.2V COUT = 3.3F 200s/DIV C1 1F VIN Figure6. Output Response with 5mA Load Step Sinking VOUT_F LTC6655-2.5 6655 F06 SHDN TO C GND VOUT_S VOUT C2 10F 2N7002 6655 F09 Figure9. Open-Drain Shutdown Circuit 2mA IOUT -2mA Long-Term Drift VOUT 10mV/DIV COUT = 3.3F 200s/DIV 6655 F07 Figure7. Output Response Showing a Sinking to Sourcing Transition The LTC6655 long-term drift data was collected on 80 parts that were soldered into printed circuit boards similar to a real world application. The boards were then placed into a constant temperature oven with a TA = 35C, their outputs were scanned regularly and measured with an 8.5 digit DVM. Typical long-term drift is illustrated in Figure10a. The hermetic LS8 package provides additional stability as shown in Figure10b. SHDN 2V/DIV VOUT 1V/DIV COUT = 3.3F 1ms/DIV Long-term drift cannot be extrapolated from accelerated high temperature testing. This erroneous technique gives drift numbers that are wildly optimistic. The only way long-term drift can be determined is to measure it over the time interval of interest. 6655 F08 Figure8. Shutdown Response with 5mA Source Load Rev. H For more information www.analog.com 15 LTC6655/LTC6655LN APPLICATIONS INFORMATION 30 4 TYPICAL UNITS LTC6655-2.5 MS8 PACKAGE 80 25 NUMBER OF UNITS LONG-TERM DRIFT (ppm) 120 40 0 -40 20 15 10 5 -80 0 500 1500 1000 HOURS 2000 0 -90 -70 -50 -30 -10 10 30 50 70 90 110 DISTRIBUTION (ppm) 2500 6655 F11 6655 F10a Figure10a. Long-Term Drift MS8 Figure11. Hysteresis Plot -40C to 125C concern. However, PC board material may absorb water and apply mechanical stress to the LTC6655LS8. Proper board materials and layout are essential. 200 LONG-TERM DRIFT (ppm) LTC6655-2.5 160 LS8 PACKAGE 120 For best stability, the PC board layout is critical. Change in temperature and position of the PC board, as well as aging, can alter the mechanical stress applied to components soldered to the board. FR4 and similar materials also absorb water, causing the board to swell. Even conformal coating or potting of the board does not always eliminate this effect, though it may delay the symptoms by reducing the rate of absorption. 80 40 0 -40 -80 -120 -160 -200 0 600 1800 1200 HOURS 2400 3000 6655 F10b Figure10b. Long-Term Drift LS8 Hysteresis Thermal hysteresis is a measure of change of output voltage as a result of temperature cycling. Figure 11 illustrates the typical hysteresis based on data taken from the LTC6655-2.5. A proprietary design technique minimizes thermal hysteresis. Humidity Sensitivity Plastic mould compounds absorb water. With changes in relative humidity, plastic packaging materials change the amount of pressure they apply to the die inside, which can cause slight changes in the output of a voltage reference, usually on the order of 100ppm. The LS8 package is hermetic, so it is not affected by humidity, and is therefore more stable in environments where humidity may be a 16 Power and ground planes should be omitted under the voltage reference IC for best stability. Figure12a shows a tab cut through the PC board on three sides of an LTC6655, which significantly reduces stress on the IC, as described in Application Note 82. For even better performance, Figure12b shows slots cut through the PC board on all four sides. The slots should be as long as possible, and the corners just large enough to accommodate routing of traces. It has been shown that for PC boards designed in this way, humidity sensitivity can be reduced to less than 35ppm for a change in relative humidity of approximately 60%. Mounting the reference near the center of the board, with slots on four sides, can further reduce the sensitivity to less than 10ppm. An additional advantage of slotting the PC board is that the LTC6655 is thermally isolated from surrounding circuitry. This can help reduce thermocouple effects and improve accuracy. Rev. H For more information www.analog.com LTC6655/LTC6655LN APPLICATIONS INFORMATION 0.14 0.12 5mA LOAD POWER (W) 0.10 LS8 0.08 NO LOAD 0.06 0.04 0.02 6655 F12a 0 Figure12a. 3-Sided PCB Tab Cutout 0 10 5 15 VIN (V) 6655 F13 Figure13. LTC6655-2.5 Power Consumption MAXIMUM AMBIENT OPERATING TEMPERATURE (C) 125 LS8 6655 F12b 115 NO LOAD 105 Figure12b. 4-Sided PCB Cutout 5mA LOAD 95 85 75 65 55 0 3 6 9 VIN (V) Power Dissipation Power dissipation for the LTC6655 depends on VIN and load current. Figure13 illustrates the power consumption versus VIN under a no-load and 5mA load condition at room temperature for the LTC6655-2.5. Other voltage options display similar behavior. The MSOP8 package has a thermal resistance (JA) equal to 300C/W. Under the maximum loaded condition, the increase in die temperature is over 35C. If operated at these conditions with an ambient temperature of 125C, the absolute maximum junction temperature rating of the device would be exceeded. Although the maximum junction temperature is 150C, for best performance it is recommended to not exceed a junction temperature of 125C. The plot in Figure14 shows the recommended 15 12 6655 F14 Figure14. LTC6655-2.5 Maximum Ambient Operating Temperature maximum ambient temperature limits for differing VIN and load conditions using a maximum junction temperature of 125C. PC Board Layout The LTC6655 reference is a precision device that is factory trimmed to an initial accuracy of 0.025%, as shown in the Typical Performance Characteristics section. The mechanical stress caused by soldering parts to a printed circuit board may cause the output voltage to shift and the temperature coefficient to change. Rev. H For more information www.analog.com 17 LTC6655/LTC6655LN APPLICATIONS INFORMATION To reduce the effects of stress-related shifts, mount the reference near the short edge of a printed circuit board or in a corner. In addition, slots can be cut into the board on two sides of the device to reduce mechanical stress. A thicker and smaller board is stiffer and less prone to bend. Finally, use stress relief, such as flexible standoffs, when mounting the board. Additional precautions include making sure the solder joints are clean and the board is flux free to avoid leakage paths. Sample PCB layouts are shown in Figures 15a and 15b. VIN VOUT GND 6655 F15a Figure15a. Sample LTC6655 PCB Layout VOUT GND 6655 F15b Figure15b. Sample LTC6655LN PCB Layout Load Regulation To take advantage of the VOUT Kelvin force/sense pins, the VOUT_S pin should be connected separately from the VOUT_F pin as shown in Figure16. 7 + LTC6655-2.5 6 2mA 4 LOAD STAR 6655 F16 MINIMIZE RESISTANCE OF METAL Figure16. Kelvin Connection for Good Load Regulation 18 Careful attention to grounding is also important, especially when sourcing current. The return load current can produce an I * R drop causing poor load regulation. Use a "star" ground connection and minimize the ground to load metal resistance. Although there are several pins that are required to be connected to ground, Pin 4 is the actual ground for return current. Optimal Noise Performance VIN 2 The VOUT_S pin sinks 2mA, which is unusual for a Kelvin connection. However, this is required to achieve the exceptional low noise performance. The I * R drop on the VOUT_S line directly affects load regulation. The VOUT_S trace should be as short and wide as practical to minimize series resistance The VOUT_S trace adds error as RTRACE * 2mA, so a 0.1 trace adds 200V error. The VOUT_F pin is not as important as the VOUT_S pin in this regard. An I * R drop on the VOUT_F pin increases the minimum supply voltage when sourcing current, but does not directly affect load regulation. For light loading of the output (maximum output current <100A), VOUT_S should be tied to VOUT_F by the shortest possible path to reduce errors caused by resistance in the sense trace. The LTC6655 offers extraordinarily low noise for a bandgap reference--only 0.25ppm in 0.1Hz to 10Hz. As a result, system noise performance may be dominated by system design and physical layout. Some care is required to achieve the best possible noise performance. The use of dissimilar metals in component leads and PC board traces creates thermocouples. Variations in thermal resistance, caused by uneven air flow, create differential lead temperatures, thereby causing thermoelectric voltage noise at the output of the reference. Minimizing the number of thermocouples, as well as limiting airflow, can substantially reduce these errors. Additional information can be found in Analog Devices Application Note 82. Position the input and load capacitors close to the part. Although the LTC6655 has a DC PSRR of over 100dB, the power supply should be as stable as possible to guarantee optimal performance. A plot of the 0.1Hz to 10Hz low frequency noise is shown in the Typical Performance Characteristics section. Noise Rev. H For more information www.analog.com LTC6655/LTC6655LN APPLICATIONS INFORMATION performance can be further improved by wiring several LTC6655s in parallel as shown in the Typical Applications section. With this technique the noise is reduced by N, where N is the number of LTC6655s in parallel. Noise Specification Noise in any frequency band is a random function based on physical properties such as thermal noise, shot noise, and flicker noise. The most precise way to specify a random error such as noise is in terms of its statistics, for example as an RMS value. This allows for relatively simple maximum error estimation, generally involving assumptions about noise bandwidth and crest factor. Unlike wideband noise, low frequency noise, typically specified in a 0.1Hz to 10Hz band, has traditionally been specified in terms of expected error, illustrated as peak-to-peak error. Low frequency noise is generally measured with an oscilloscope over a 10 second time frame. This is a pragmatic approach, given that it can be difficult to measure noise accurately at low frequencies, and that it can also be difficult to agree on the statistical characteristics of the noise, since flicker noise dominates the spectral density. While practical, a random sampling of 10 second intervals is an inadequate method for representation of low frequency noise, especially for systems where this noise is a dominant limit of system performance. Given the random nature of noise, the output voltage may be observed over many time intervals, each giving different results. Noise specifications that were determined using this method are prone to subjectivity, and will tend toward a mean statistical value, rather than the maximum noise that is likely to be produced by the device in question. Because the majority of voltage reference data sheets express low frequency noise as a typical number, and as it tends to be illustrated with a repeatable plot near the mean of a distribution of peak-to-peak values, the LTC6655 data sheet provides a similarly defined typical specification in order to allow a reasonable direct comparison against similar products. Data produced with this method generally suggests that in a series of 10 second output voltage measurements, at least half the observations should have a peak-to-peak value that is below this number. For example, the LTC6655-2.5 measures less than 0.25ppmP-P in at least 50% of the 10 second observations. As mentioned above, the statistical distribution of noise is such that if observed for long periods of time, the peak error in output voltage due to noise may be much larger than that observed in a smaller interval. The likely maximum error due to noise is often estimated using the RMS value, multiplied by an estimated crest factor, assumed to be in the range of 6 to 8.4. This maximum possible value will only be observed if the output voltage is measured for very long periods of time. Therefore, in addition to the common method, a more thorough approach to measuring noise has been used for the LTC6655 (described in detail in Analog Devices AN124) that allows more information to be obtained from the result. In particular, this method characterizes the noise over a significantly greater length of time, resulting in a more complete description of low frequency noise. The peak-to-peak voltage is measured for 10 second intervals over hundreds of intervals. In addition, an electronic peak-detect circuit stores an objective value for each interval. The results are then summarized in terms of the fraction of measurement intervals for which observed noise is below a specified level. For example, the LTC6655-2.5 measures less than 0.27ppmP-P in 80% of the measurement intervals, and less than 0.295ppmP-P in 95% of observation intervals. This statistical variation in noise is illustrated in Table2 and Figure18. The test circuit is shown in Figure17. Table2. 50% 60% 70% 80% 90% Low Frequency Noise (ppmP-P) 0.246 0.252 0.260 0.268 0.292 This method of testing low frequency noise is superior to more common methods. The results yield a comprehensive statistical description, rather than a single observation. In addition, the direct measurement of output voltage over time gives an actual representation of peak noise, rather than an estimate based on statistical assumptions such as crest factor. Additional information can be derived from a measurement of low frequency noise spectral density, as shown in Figure19. Rev. H For more information www.analog.com 19 For more information www.analog.com 15V RST -15V RST LTC6655 2.5V 10k 10k 1F P P 1F F S 1F REFERENCE UNDER TEST SD IN 9V 1300F 1F **1.2k T 100k 0.005F + -15V 4.7k 4.7k A1 LT1012 100k - + 0.005F A6 1/4 LT1058 - + A5 1/4 LT1058 - SHIELD 100k A = 104 LOW NOISE PRE-AMP 100k + 20 0.1F - A8 1/4 LT1058 + - A7 1/4 LT1058 -15V Q2 1k - DVM + 1k 5 A2 LT1097 0.022F SEE APPENDIX C FOR POWER, SHIELDING AND GROUNDING SCHEME = 1/4 LTC202 = 2N4393 = 1N4148 RST = Q2 + 10k* 1M* RC2 +V 10k B2 +15V BAT-85 BAT-85 +15V RESET PULSE GENERATOR = POLYPROPELENE P 10k 330F 16V 330F 16V + 6655 F17 A4 330F OUTPUT CAPACITORS = <200nA LEAKAGE AT 1VDC AT 25C = TANTALUM,WET SLUG ILEAK < 5nA SEE TEXT/APPENDIX B FROM OSCILLOSCOPE SWEEP GATE OUTPUT VIA ISOLATION PULSE TRANSFORMER 10k + A4 LT1012 - ROOT-SUM-SQUARE CORRECTION SEE TEXT T A2 0.1F 124k* 0.1F 0.1F 100* OUT 124k* 74C221 C2 CLR2 +15V 0.22F 330F 16V 330F 16V IN 330* +15V - A3 LT1012 + A = 100 AND 0.1Hz TO 10Hz FILTER Q1, Q2 = THERMALLY MATED 2SK369 (MATCH VGS 10%) OR LSK389 DUAL THERMALLY LAG SEE TEXT TO OSCILLOSCOPE INPUT VIA ISOLATED PROBE, 1V/DIV = 1V/DIV, REFERRED TO INPUT, SWEEP = 1s/DIV 10* 100k* * = 1% METAL FILM ** = 1% WIREWOUND, ULTRONIX105A O TO 1V = O TO 1V SHIELDED CAN - INPUT + - 1F 2k Figure17. Detailed Noise Test Circuitry. See Application Note 124 - PEAK + PEAK + Q1 900* 15V 200* 750* 450* 1k* PEAK TO PEAK NOISE DETECTOR AC LINE GROUND 1F -15V Q3 2N2907 10k 1N4697 10V + 0.15F + 15V LTC6655/LTC6655LN APPLICATIONS INFORMATION Rev. H LTC6655/LTC6655LN APPLICATIONS INFORMATION the typical application circuit with a capacitor on the NR pin. When a capacitor is placed between NR and ground, a LPF is formed. 35 NUMBER OF OBSERVATIONS 30 25 20 2 VIN 15 LTC6655LN R3 + - BANDGAP 10 5 0 450 750 850 650 550 PEAK-TO-PEAK NOISE (nV) 950 VOUT 7 R1 2.7F R2 6655 F18 GND Figure18. LTC6655-2.5 Low Frequency Noise Histogram 3, 4, 5, 8 6 NR 6655 F20 CNR 360 Figure20. The LTC6655LN Typical Application Circuit NOISE VOLTAGE (nV/Hz) 300 240 180 LTC6655-5 120 LTC6655-2.5 60 LTC6655-1.25 0 0.1 1 FREQUENCY (Hz) 10 6655 F19 Figure19. LTC6655-2.5 Low Frequency Noise Spectrum It should be noted from Figure19 that the LTC6655 has not only a low wideband noise, but an exceptionally low flicker noise corner of 1Hz! This substantially reduces low frequency noise, as well as long-term variation in peak noise. Noise Reduction and the NR Pin The LTC6655LN provides access to an internal circuit node preceding the output buffer so that dynamic performance is not affected. This facilitates the use of a low pass filter (LPF) to reduce wide band noise. The Block Diagram section illustrates the LTC6655LN architectural differences. The Low Noise version trades out the Kelvin sense pin for the NR pin. Figure20 shows The LPF reduces the wide band noise from the bandgap circuit before it reaches the output buffer. This is very different from placing a LPF after the reference. A LPF following the buffer would cause poor load regulation and slow down the response affecting dynamic performance. With the LPF internally placed before the low noise buffer, the buffer response is not impeded by the LPF. Placing anything between the output buffer and the converter will likely add noise or cause an error such as a load regulation error, or a dynamic response error. The value of resistor R3 is slightly different depending on the voltage option. Tables 3 and 4 below list the resistance values of R3 for the three available voltage options along with the 3dB cutoff frequencies for four decades of capacitor values. Table3. Resistance Value of R3 for the Three Voltage Options R3 15% 2.500 4.096 5.000 V 300 376 401 Table4. The 3dB Cutoff Frequencies for Different Values of CNR CNR 2.500 4.096 5.000 V 0.1F 5305 4233 3969 Hz 1F 531 423 397 Hz 10F 53 42.3 39.7 Hz 100F 5.3 4.2 4.0 Hz Rev. H For more information www.analog.com 21 LTC6655/LTC6655LN APPLICATIONS INFORMATION Internally the NR pin connects to a sensitive node. Any leakage to this pin can cause excessive shift and drift. Leakage of 10nA will cause a shift of 9V in VOUT. It is recommended to use high quality, low leakage capacitors. A guard ring may also be employed to control leakage. The nominal pin voltage of NR is 1.000V or 1.024V. is reduced to 16nV/Hz. The noise corner frequency produced by the LPF decreases as the capacitor increases. The LTC6655LN-2.5 output noise for three conditions is shown in Figure21. Without a capacitor on the NR pin the wideband noise extends past 10kHz at 50nV/Hz. When a 1F or 100F capacitor is included, the wideband noise Start-Up with CNR 70 COUT = 2.7F NOISE VOLTAGE (nV/Hz) 60 CNR = 10F 50 CNR = 1F CNR = 0.1F 40 30 CNR = 100F 0 0.01 0.1 1 10 FREQUENCY (kHz) 100 1k 6655 F21 Figure21. The LTC6655LN-2.5 Output Voltage Noise Spectrum Using the CNR Capacitor INTEGRATED NOISE (VRMS) 5 4 CNR = 0.1F 3 CNR = 1F 2 CNR = 10F 1 CNR = 100F 0.1 1 FREQUENCY (kHz) 10 6655 F22 Figure22. Total Integrated Noise of the LTC6655LN-2.5 Using the CNR Capacitor 22 IR Reflow Shift The mechanical stress of soldering a part to a board can cause the output voltage to shift. Moreover, the heat of an IR reflow or convection soldering oven can also cause the output voltage to shift. The materials that make up a semiconductor device and its package have different rates of expansion and contraction. After a part undergoes the extreme heat of a lead-free IR reflow profile, like the one shown in Figure24, the output voltage shifts. After the device expands, due to the heat, and then contracts, the stresses on the die have changed position. This shift is similar, but more extreme than thermal hysteresis. COUT = 2.7F 0 0.01 The CNR capacitor will require time to charge. The LTC6655 has an initial accuracy of 0.025%. A single RC time constant circuit will require approximately 8.3 to reach 0.025% settling. For example, assume R3 = 300 and CNR = 10F; the time constant is R * C = 300 * 10F = 3ms. For 0.025% settling multiply 8.3 * 3ms to get 24.9ms. This is the time required for the signal at the NR pin to settle to 0.025% of its final value. The output buffer will follow the NR pin signal with some delay depending on the capacitive loading on the VOUT pin. Example start-up measurements are shown in Figures 23a, 23b, and 23c. Figure23a shows the difference between using no capacitor and a 1F capacitor on the NR pin. Figures 23b and 23c show the start-up with CNR = 10F and 100F, respectively. 20 10 A plot of the total integrated noise for the same three conditions is shown in Figure22. A large value of CNR can have a large impact on the total integrated noise. Experimental results of IR reflow shift are shown below in Figure25. These results show only shift due to reflow and not mechanical stress. Rev. H For more information www.analog.com LTC6655/LTC6655LN APPLICATIONS INFORMATION VIN 5V/DIV 300 TEMPERATURE (C) CNR = 1F COUT = 2.7F TP = 260C TL = 217C TS(MAX) = 200C TS = 190C 225 VNR 500mV/DIV VOUT 1V/DIV 380s CNR = OPEN 150 tP 30s T = 150C tL 130s RAMP TO 150C 75 40s 6655 F23a 1ms/DIV RAMP DOWN 120s Figure23a. CNR = Open and 10F 0 VIN 5V/DIV 0 2 6 4 MINUTES 8 10 6655 F24 Figure24. Lead-Free Reflow Profile VNR 500mV/DIV 8 7 VOUT 1V/DIV 6 NUMBER OF UNITS CNR = 10F COUT = 2.7F 6655 F23b 10ms/DIV Figure23b. CNR = 10F 5 4 3 2 VIN 5V/DIV 1 0 -0.029 -0.023 -0.017 -0.011 -0.005 OUTPUT VOLTAGE SHIFT DUE TO IR REFLOW (%) VNR 500mV/DIV 6655 F25 Figure25. Output Voltage Shift Due to IR Reflow VOUT 1V/DIV CNR = 100F COUT = 2.7F 50ms/DIV 6655 F23c Figure23c. CNR = 100F Figure23. The LTC6655LN-2.5 Start-Up Response with a) No CNR Capacitor and CNR = 1F, b) CNR = 10F, and c) CNR = 100F Rev. H For more information www.analog.com 23 LTC6655/LTC6655LN TYPICAL APPLICATIONS Extended Supply Range Reference Extended Supply Range Reference 4V TO 30V R1 BZX84C12 C1 0.1F 6V TO 80V R1 R2 100k 4.7k LTC6655-2.5 VIN VOUT_F SHDN VOUT_S VOUT BZX84C12 C2 10F GND ON SEMI MMBT5551 C1 0.1F 0.1F VIN SHDN VOUT_F LTC6655-2.5 VOUT_S GND 6655 TA02 VOUT C2 10F 6655 TA03 Boosted Output Current Boosted Output Current 4V TO 13.2V VOUT + 1.8V TO 13.2V LTC6655-2.5 SHDN VOUT_F VIN C1 0.1F 6655 TA05 GND Q1 2N2222 VOUT VOUT_S C3 0.1F C2 4.7F IMAX SET BY NPN C1 1F R1 220 R2 1k C4 1F 2N2905 35mA MAX VIN SHDN VOUT_F LTC6655-2.5 VOUT_S GND VOUT C2 10F 6655 TA04 24 Rev. H For more information www.analog.com LTC6655/LTC6655LN TYPICAL APPLICATIONS Output Voltage Boost VIN VOUT + 0.5V TO 13.2V VIN C1 1F VOUT_F VOUT_S GND VOUT = VOLTAGE OPTION + 0.002 * R THIS EXAMPLE USES 2.5V AS THE VOLTAGE OPTION C2 10F R LTC6655-2.5 SHDN VOUT 2.5V TO 4.5V R = 0k to 1k 6655 TA07 FOR R USE A POTENTIOMETER THAT CAN HANDLE 2mA, IS LOW NOISE AND HAS A LOW TEMPERATURE COEFFICIENT Low Noise Precision Voltage Boost Circuit VIN VOUT + 0.5V TO 13.2V C1 1F VIN VOUT_F VIN LT1677 + + LTC6655-2.5 SHDN VOUT_S -- GND R1 10k VOUT 5V RLOAD R2 10k R3 5k VOUT = VOLTAGE OPTION * (1 + R1/R2) THIS EXAMPLE USES 2.5V AS THE VOLTAGE OPTION C2 10F 6655 TA08 FOR R1, R2 AND R3 USE LT5400-1. WITH A PRECISION ARRAY THE MATCHING AND LOW TC WILL HELP PRESERVE LOW DRIFT. R3 = R1||R2 R3 IS MADE WITH TWO PRALLEL 10k RESISTORS, AVAILABLE IN THE LT5400-1 Ultralow 1/f Noise Reference Buffer LT3042 IN VIN 6V 5% 100A 4.7F EN/UV - + PGFB 1,2 6,7 3,4,5,8 OUTS PG LTC6655-5 VOUT = 5V IOUT(MAX) 200mA OUT SET 4.7F GND ILIM 1k 6655 TA08 10F 49.9k 4.7F Rev. H For more information www.analog.com 25 LTC6655/LTC6655LN TYPICAL APPLICATIONS Low Noise Statistical Averaging Reference eN = eN/N; Where N is the Number of LTC6655s in Parallel LTC6655-2.5 SHDN VOUT_F 3V TO 13.2V VIN C1 0.1F GND R1 32.4 VOUT_S VOUT C2 2.7F C9 4.7F LTC6655-2.5 SHDN VOUT_F VIN C3 0.1F GND R2 32.4 VOUT_S C4 2.7F LTC6655-2.5 SHDN VOUT_F VIN C5 0.1F GND R3 32.4 VOUT_S C6 2.7F LTC6655-2.5 SHDN VOUT_F VIN 6655 TA09a C7 0.1F GND VOUT_S R4 32.4 C8 2.7F Low Frequency Noise (0.1Hz to 10Hz) with Four LTC6655-2.5 in Parallel 200nV/ DIV 320nVP-P 0.1Hz to 10Hz 26 1s/DIV 6655 TA09b Rev. H For more information www.analog.com LTC6655/LTC6655LN PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev G) 0.889 0.127 (.035 .005) 5.10 (.201) MIN 3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 0.65 (.0256) BSC 0.42 0.038 (.0165 .0015) TYP 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) DETAIL "A" 0 - 6 TYP GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.65 (.0256) BSC 0.1016 0.0508 (.004 .002) MSOP (MS8) 0213 REV G NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX Rev. H For more information www.analog.com 27 LTC6655/LTC6655LN PACKAGE DESCRIPTION LS8 Package 8-Pin Leadless Chip Carrier (5mm x 5mm) (Reference LTC DWG # 05-08-1852 Rev B) 8 2.50 0.15 PACKAGE OUTLINE 7 1 0.5 2 6 2.54 0.15 1.4 3 1.50 0.15 4 0.70 0.05 x 8 e4 XYY ZZ ABCDEF Q12345 COMPONENT PIN "A1" 5.00 SQ 0.15 5.80 SQ 0.15 TRAY PIN 1 BEVEL APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 SQ 0.15 1.45 0.10 0.95 0.10 4.20 SQ 0.10 8 1 PIN 1 TOP MARK (SEE NOTE 5) 2 PACKAGE IN TRAY LOADING ORIENTATION 5.00 SQ 0.15 8 R0.20 REF 2.00 REF 7 6 1 7 2 2.54 0.15 0.5 6 4.20 0.10 1.4 3 5 R0.20 REF 5 3 1.00 x 7 TYP 4 0.70 TYP NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS PACKAGE DO NOT INCLUDE PLATING BURRS PLATING BURRS, IF PRESENT, SHALL NOT EXCEED 0.30mm ON ANY SIDE 4. PLATING--ELECTO NICKEL MIN 1.25UM, ELECTRO GOLD MIN 0.30UM 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 28 LS8 0113 REV B 4 0.10 TYP 0.64 x 8 TYP Rev. H For more information www.analog.com LTC6655/LTC6655LN REVISION HISTORY REV DATE DESCRIPTION A 02/10 Voltage Options Added (1.250, 2.048, 3.000, 3.300, 4.096, 5.000), Reflected Throughout the Data Sheet B 12/12 Addition of 5mm x 5mm hermetic LS8 package C 06/13 1, 2, 3, 12, 22 3, 4 Addition of long-term drift and hysteresis plots for LS8 package 13 Addition of Humidity Sensitivity information 13 Addition of Related Parts 22 TJMAX changed from 125C to 150C 2 Addition of PC board layout guidance 01/14 1 to 22 Update to Electrical Characteristics to include LS8 package Addition of 5V Option in the LS8 package D PAGE NUMBER Addition of 4.096V option in the LS8 package 3, 4 14, 15 3, 4 Changed Line Regulation Condition to SHDN = 2V 4 Updated PC board layout guidance 14 Corrected Polarity of 9V battery in Figure17 Updated captions for Figures 10, 12, 18 18 14, 15, 19 Updated note for circuit "Low Noise Precision Voltage Boost Circuit" 21 E 9/14 Corrected LS8-4.096 part marking 3 F 08/17 Trademark information updated. 1 Web links updated. Addition of Ultralow 1/f Noise Reference Buffer schematic. G 02/19 Addition of LTC6655LN Specifications and Features. H 06/20 Addition of LTC6655LN 5V option. Updated Features section. 3, 23, 24 21 1 to 6, 11, 12, 18, 22, 23 3, 4, 10 1 Updated Typical Performance Characteristics. 7, 8 Updated Figure 19, Table 3 and Table 4. 21 Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. moreby information www.analog.com 29 LTC6655/LTC6655LN TYPICAL APPLICATION Low Noise Precision 24-Bit Analog-to-Digital Converter Application 2.5k 5V VREF 10F 4 2.5k VCC ADCINP 0.01F LTC2449 0.01F 1nF - 50 SDI SCK SDO CS 1/2 LTC6241 SPI INTERFACE + BUSY EXT fO REF+ REF- GND GND 1/2 LTC6241 -2.5V GND GND 3,5,8 VREF - 50 MUXOUTP GND 0.1F VIN MUXOUTN + GND LTC6655 7 VOUT_F 1 6 SHDN VOUT_S 2 1nF ADCINN GND THERMOCOUPLE CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 COM GND RTD 7.5V GND 5k RREF 400 6655 TA10 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT(R)1236 Precision Low Drift Low Noise Reference 0.05% Max, 5ppm/C Max, 1ppm (Peak-to-Peak) Noise LT1236LS8 Precision Low Noise, Low Profile Hermetic Voltage Reference 0.05% Max, 5ppm/C Max, 0.3VP-P Noise, 5mm x 5mm Hermetic Package LT1460 Micropower Series References 0.075% Max, 10ppm/C Max, 20mA Output Current LT1461 Micropower Series Low Dropout 0.04% Max, 3ppm/C Max, 50mA Output Current LT1790 Micropower Precision Series References 0.05% Max, 10ppm/C Max, 60mA Supply, SOT23 Package LT6650 Micropower Reference with Buffer Amplifier 0.5% Max, 5.6A Supply, SOT23 Package LTC6652 Precision Low Drift Low Noise Reference 0.05% Max, 5ppm/C Max, -40C to 125C, MSOP8 LT6660 Tiny Micropower Series Reference 0.2% Max, 20ppm/C Max, 20mA Output Current, 2mm x 2mm DFN LTC6652LS8 High Precision, Buffered Voltage Reference Family in 5mm x 5mm Hermetic QFN Package 0.05% Max Initial Error, 5ppm/C Max Drift, Shutdown Current <2A, -40C to 125C Operation LT6654LS8 Precision, Low Noise, High Output Drive Voltage Reference Family in 5mm x 5mm Hermetic QFN Package 1.6ppm Peak-to-Peak Noise (0.1Hz to 10Hz, Sink/Source 10mA, 5ppm/C Max Drift, -40C to 125C Operation REF195 Micropower Low Drift High Output Drive Series Voltage Reference 5ppm/C Max Drift, 30mA Output Current, 45A Max Supply ADR4550 High Precision Low Drift Low Noise Series Voltage Reference 0.02% Max, 2ppm/C Max Drift, 2.8VP-P Noise (0.1Hz to 10Hz), Sink/ Source 10mA, 950A Max Supply 30 Rev. H 06/20 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2009-2020