1
CAT28C17A
16K-Bit CMOS PARALLEL EEPROM
FEATURES
■Fast Read Access Times: 200 ns
■Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 100 µA Max.
■Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
■Fast Write Cycle Time: 10ms Max
■End of Write Detection:
–DATADATA
DATADATA
DATA Polling
–RDY/BSYBSY
BSYBSY
BSY Pin
■Hardware Write Protection
■CMOS and TTL Compatible I/O
■10,000 Program/Erase Cycles
■10 Year Data Retention
■Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C17A is a fast, low power, 5V-only CMOS
parallel EEPROM organized as 2K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and a RDY/BSY pin signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C17A features hardware write protection.
The CAT28C17A is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 28-pin DIP and SOIC or 32-pin PLCC pack-
ages.
BLOCK DIAGRAM
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A4–A10
CE
OE
WE
A0–A3
I/O0–I/O7
I/O BUFFERS
2,048 x 8
EEPROM
ARRAY
VCC
DATA POLLING
& RDY/BUSY
RDY/BUSY
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1075, Rev. B
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CAT28C17A
2
Doc. No. 1075, Rev. B
PIN CONFIGURATION
RDY/BUSY
I/O2
VSS
I/O5
13
14
22
21
20
17
9
12
25
24
23
RDY/BUSY
I/O1
OE
A10
CE
A3
A2
A1
A0
5
6
7
8
1
2
3
4
A7
A6
A5
A4
A9
28
27
26
VCC
WE
A8
A6
A5
A4
A3
5
6
7
8
A2
A1
A0
NC
9
10
11
12
I/O013
A8
A9
NC
NC
29
28
27
26
OE
A10
CE
25
24
23
22 I/O7
21
I/O1
I/O2
V
SS
NC
I/O3
I/O4
I/O5
14 15 16 17 18 19 20
4321323130
A7
NC
NC
VCC
WE
NC
I/O4
I/O3
16
15 I/O6
TOP VIEW
I/O6
19
18
11I/O0
I/O7
NC
10
NC
NC
I/O2
VSS
I/O5
13
14
22
21
20
17
9
12
25
24
23
RDY/BUSY
I/O1
OE
A10
CE
A3
A2
A1
A0
5
6
7
8
1
2
3
4
A7
A6
A5
A4
A9
28
27
26
VCC
WE
A8
I/O4
I/O3
16
15
I/O6
19
1811I/O0
I/O7
NC
10
NC
NC
DIP Package (P, L) PLCC Package (N, G)SOIC Package (J,W) (K, X)
PIN FUNCTIONS
Pin Name Function
A0–A10 Address Inputs
I/O0–I/O7Data Inputs/Outputs
RDY/BUSY Ready/BUSY Status
CE Chip Enable
OE Output Enable
WE Write Enable
VCC 5V Supply
VSS Ground
NC No Connect
MODE SELECTION
Mode CE WE OE I/O Power
Read L H L DOUT ACTIVE
Byte Write (WE Controlled) L H DIN ACTIVE
Byte Write (CE Controlled) L H DIN ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V
CIN(1) Input Capacitance 6 pF VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
CAT28C17A
3Doc. No. 1075, Rev. B
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
ICC VCC Current (Operating, TTL) 35 mA CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
ICCC(5) VCC Current (Operating, CMOS) 25 mA CE = OE = VILC,
f = 1/tRC min, All I/O’s Open
ISB VCC Current (Standby, TTL) 1 mA CE = VIH, All I/O’s Open
ISBC(6) VCC Current (Standby, CMOS) 100 µACE = VIHC,
All I/O’s Open
ILI Input Leakage Current –10 10 µAV
IN = GND to VCC
ILO Output Leakage Current –10 10 µAV
OUT = GND to VCC,
CE = VIH
VIH(6) High Level Input Voltage 2 VCC +0.3 V
VIL(5) Low Level Input Voltage –0.3 0.8 V
VOH High Level Output Voltage 2.4 V IOH = –400µA
VOL Low Level Output Voltage 0.4 V IOL = 2.1mA
VWI Write Inhibit Voltage 3.0 V
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
NEND(1) Endurance 10,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR(1) Data Retention 10 Years MIL-STD-883, Test Method 1008
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(4) Latch-Up 100 mA JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(5) VILC = –0.3V to +0.3V.
(6) VIHC = VCC –0.3V to VCC +0.3V.
CAT28C17A
4
Doc. No. 1075, Rev. B
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V ±10%, unless otherwise specified.
28C17A-20
Symbol Parameter Min. Max. Units
tRC Read Cycle Time 200 ns
tCE CE Access Time 200 ns
tAA Address Access Time 200 ns
tOE OE Access Time 80 ns
tLZ(1) CE Low to Active Output 0 ns
tOLZ(1) OE Low to Active Output 0 ns
tHZ(1)(2) CE High to High-Z Output 55 ns
tOHZ(1)(2) OE High to High-Z Output 55 ns
tOH(1) Output Hold from Address Change 0 ns
Figure 1. A.C. Testing Input/Output Waveform(3)
Figure 2. A.C. Testing Load Circuit (example)
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
CAT28C17A
5Doc. No. 1075, Rev. B
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V ±10%, unless otherwise specified.
28C17A-20
Symbol Parameter Min. Max. Units
tWC Write Cycle Time 10 ms
tAS Address Setup Time 10 ns
tAH Address Hold Time 100 ns
tCS CE Setup Time 0 ns
tCH CE Hold Time 0 ns
tCW(2) CE Pulse Time 150 ns
tOES OE Setup Time 15 ns
tOEH OE Hold Time 15 ns
tWP(2) WE Pulse Width 150 ns
tDS Data Setup Time 50 ns
tDH Data Hold Time 10 ns
tDL Data Latch Time 50 ns
tINIT(1) Write Inhibit Period After Power-up 5 20 ms
tDB Time to Device Busy 80 ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
CAT28C17A
6
Doc. No. 1075, Rev. B
ADDRESS
CE
OE
WE
tRC
DATA OUT DATA VALIDDATA VALID
tCE
tOE
tOH
tAA
tOHZ
tHZ
VIH
HIGH-Z
tLZ
tOLZ
DEVICE OPERATION
Read
Data stored in the CAT28C17A is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
OE
WE
tAS
DATA IN DATA VALID
tCS
tAH
tCH
tWC
tOEH
tDL
tDH
tDS
tOES tWP
RDY/BUSY
tDB
DATA OUT HIGH-Z
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled
low during the write cycle and released at the end of
programming. Several devices may be OR-tied to the
same RDY/BUSY line.
Figure 3. Read Cycle
CAT28C17A
7Doc. No. 1075, Rev. B
ADDRESS
CE
WE
OE
I/O7DIN = X DOUT = X DOUT = X
tOE
tOEH
tWC
tOES
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Figure 5. Byte Write Cycle [CE Controlled]
ADDRESS
CE
OE
WE
RDY/BUSY
tAS
DATA IN DATA VALID
tAH
tWC
tOEH
tDH
tDS
tOES
tDL
tCH
tCS
tCW
tDB
DATA OUT HIGH-Z
Figure 6. DATA Polling
DATA Polling
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O7 (I/O0–I/O6 are indeter-
minate) until the programming cycle is complete. Upon
completion of the self-timed byte write cycle, all I/O’s will
output true data during a read cycle.
CAT28C17A
8
Doc. No. 1075, Rev. B
HARDWARE DATA PROTECTION
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28C17A.
(1) VCC sense provides for write protection when VCC
falls below 3.0V min.
(2) A power on delay mechanism, tINIT (see AC charac-
teristics), provides a 5 to 20 ms delay before a write
sequence, after VCC has reached 3.0V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
CAT28C17A
9Doc. No. 1075, Rev. B
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT28C17ANI-20T (PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel).
Prefix Device # Suffix
28C17A N I T
Product
Number
Tape & Reel
Package
P: PDIP
N: PLCC
J: SOIC (JEDEC)
K: SOIC (EIAJ)
-20CAT
Optional
Company ID
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Speed
20: 200ns
* -40˚C to +125˚C is available upon request
L: PDIP (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
X: SOIC (EIAJ) (Lead free, Halogen free)
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1075
Revison: B
Issue date: 04/19/04
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
REVISION HISTORY
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