A5995 DMOS Dual Full-Bridge PWM Motor Driver FEATURES AND BENEFITS DESCRIPTION * * * * * * * * * * The A5995 is designed to operate at voltages up to 40 V while driving two DC motors at currents up to 3.2 A. The A5995 includes a fixed off-time pulse-width modulation (PWM) regulator for current control. The DC motors are controlled using standard PHASE and ENABLE signals. Fast or slow current decay is selected via the MODE pin. 40 V output rating Two 3.2 A DC motor drivers Synchronous rectification Internal undervoltage lockout (UVLO) Thermal shutdown circuitry Crossover-current protection Very thin profile QFN package Overcurrent protection Low-power sleep mode 3.3 and 5 V compatible logic supply Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Protection features include thermal shutdown with hysteresis, undervoltage lockout (UVLO), crossover-current and short-circuit protection. Special power-up sequencing is not required. The A5995 is supplied in a leadless 6 mm x 6 mm x 0.9 mm, 36-pin QFN package with exposed power tab for enhanced thermal performance. The package is lead (Pb) free, with 100% matte-tin leadframe plating. Package: 36-pin QFN with exposed thermal pad 0.90 mm nominal height (suffix EV) Not to scale 0.1 F 50 V 0.1 F 50 V CP1 CP2 100 F 50 V VCP VBB SLEEPn VBB OUT1A OUT1A MODE1 PHASE1 Microcontroller or Controller Logic A5995 OUT1B OUT1B SENSE1 ENABLE1 SENSE1 VREF1 MODE2 PHASE2 OUT2A ENABLE2 OUT2A VREF2 OUT2B OUT2B SENSE2 SENSE2 GND GND GND GND Figure 1:Typical Application Circuit A5995-DS, Rev. 1 0.22 F 50 V A5995 DMOS Dual Full-Bridge PWM Motor Driver SELECTION GUIDE Part Number A5995GEVSR-T Packing 6000 pieces per reel ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Load Supply Voltage VBB Output Current* IOUT Logic Input Voltage Range VIN SENSEx Pin Voltage VREFx Pin Voltage Operating Temperature Range Junction Temperature Storage Temperature Range VSENSEx Notes DC motor driver, continuous Pulsed tw < 1 s VREFx Rating Units -0.5 to 40 V 3.2 A -0.3 to 7 V 0.5 V 2.5 V 2.5 V -40 to 105 C TJ(max) 150 C Tstg -55 to 150 C TA Range G * May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a Junction Temperature of 150C. THERMAL CHARACTERISTICS: May require derating at maximum conditions Symbol RJA Test Conditions EV package, 4-layer PCB based on JEDEC standard Min. Units 27 C/W Power Dissipation versus Ambient Temperature 5500 5000 4500 4000 Power Dissipation, PD (mW) Characteristic Package Thermal Resistance 3500 3000 2500 2000 1500 EV Package 4-layer PCB (RJA = 27 C/W) 1000 500 0 25 50 75 100 125 Temperature (C) 150 175 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A5995 DMOS Dual Full-Bridge PWM Motor Driver Functional Block Diagram 0.1 F 50 V 0.1 F 50 V SLEEPn CHARGE PUMP OSC DMOS Full Bridge 1 VCP MODE1 OUT1A CONTROL LOGIC PHASE1 OUT1A OUT1B GATE DRIVE 3 OUT1B PWM Latch BLANKING SENSE1 SENSE1 + VREF1 - ENABLE1 Sense1 0.22 F 50 V VBB VBB VCP CP2 CP1 100 F 50 V RS1 DMOS Full Bridge 2 VCP MODE2 OUT2A CONTROL LOGIC PHASE2 OUT2A GATE DRIVE ENABLE2 VREF2 + Sense2 OUT2B PWM Latch BLANKING - 3 OUT2B Sense2 SENSE2 GND GND GND GND NC NC NC NC NC NC SENSE2 RS2 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A5995 DMOS Dual Full-Bridge PWM Motor Driver ELECTRICAL CHARACTERISTICS1: Valid at TA = 25 C, VBB = 40 V, unless otherwise noted Characteristics Load Supply Voltage Range Output On-Resistance Symbol VBB RDS(on) Vf , Outputs Output Leakage VBB Supply Current Output Driver Slew Rate Test Conditions Operating IBB SROUT Typ.2 Max. Units 8 - 40 V Source driver, IOUT = -1.2 A, TJ = 25C - 250 300 m Sink driver, IOUT = 1.2 A, TJ = 25C - 240 300 m IOUT = 1.2 A IDSS Min. - - 1.2 V -20 - 20 A - - 23 mA Outputs off - 11.7 14 mA Sleep mode -10 <1 10 A 10% to 90% 50 100 150 ns 2 - - V Outputs, VOUT = 0 to VBB IOUT = 0 mA, outputs on, fPWM = 50 kHz, duty cycle = 50% Control Logic Logic Input Voltage Logic Input Current Input Hysteresis Sleep Rising Threshold Sleep Falling Threshold Sleep Hysteresis Sleep Input Current VIN(1) - - 0.8 V -20 <1 20 A Vhys 150 300 500 mV VSLEEPn(r) 2.5 2.7 2.95 V VIN(0) IIN VIN = 0 to 5 V VSLEEPn(f) - 2.4 - V VSLEEPn(hys) 250 325 450 mV ISLEEPn PWM change to source on - 100 150 A 550 700 1000 ns PWM change to source off 35 - 450 ns PWM change to sink on 550 700 1000 ns - 450 ns 425 1000 ns 3.2 4 s Propagation Delay Times tpd 35 Crossover Delay tCD 250 Blank Time (DC motor driver) tBLANK 2.5 VREFx Pin Input Voltage Range VREFx PWM change to sink off Operating 0 - 1.5 V VREFx Pin Reference Input Current IREF VREF = 1.5 V - - 1 A Current Trip-Level Error VERR VREF = 1.5 V -5 - 5 % Protection Circuits VBB UVLO Threshold VBB Hysteresis VUV(VBB) VUV(VBB)hys VBB rising 7.3 7.6 7.9 V 400 500 600 mV Overcurrent Protection Threshold IOVP 3.2 - - A Thermal Shutdown Temperature TJTSD 155 165 175 C TJTSDhys - 15 - C Thermal Shutdown Hysteresis 1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF/3) - VSENSE] / (VREF/3). Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A5995 DMOS Dual Full-Bridge PWM Motor Driver DC Control Logic PHASE ENABLE MODE 3 x VS > VREF OUTA OUTB 1 1 1 false H L Function 1 1 0 false H L Forward (fast decay SR) 0 1 1 false L H Reverse (slow decay SR) 0 1 0 false L H Reverse (fast decay SR) X 0 1 X L L Brake (slow decay SR) 1 0 0 X L H Fast decay SR* Forward (slow decay SR) 0 0 0 X H L Fast decay SR* X 1 1 true L L OCL chop / slow decay SR 1 1 0 true L H OCL chop / fast decay SR* 0 1 0 true H L OCL chop / fast decay SR* * To prevent reversal of current during fast decay SR - the outputs will go to the high-impedance state as the current gets near zero. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A5995 DMOS Dual Full-Bridge PWM Motor Driver FUNCTIONAL DESCRIPTION Device Operation Control Logic The A5995 is designed to operate two DC motors. The currents in each of the full bridges, all N-channel DMOS, are regulated with fixed off-time pulse-width-modulated (PWM) control circuitry. The peak current in each full bridge is set by the value of an external current sense resistor, RSx , and a reference voltage, VREFx . DC motor commutation is accomplished by applying a PWM signal together with the PHASE or ENABLE inputs. Fast or slow current decay during the off-time is selected via the MODE pin. Synchronous rectification is always active regardless of the state of the MODE pin. Internal PWM Current Control The charge pump is used to generate a gate supply greater than VBB in order to drive the source-side DMOS gates. A 0.1 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 F ceramic capacitor is required between VCP and VBBx to act as a reservoir to operate the highside DMOS devices. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a user-specified value, ITRIP . Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RSx. When the voltage across the current sense resistor equals the voltage on the VREFx pin, the current sense comparator resets the PWM latch, which turns off the source driver. The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITripMax = VREF / (3 x RS) Note: It is critical to ensure that the maximum rating of 500 mV on each SENSEx pin is not exceeded. Fixed Off-Time The internal PWM current control circuitry uses a one-shot circuit to control the time the drivers remain off. The one-shot off-time, toff , is internally set to 30 s. Blanking This function blanks the output of the current sense comparator when the outputs are switched by the internal current control circuitry. The comparator output is blanked to prevent false detections of overcurrent conditions, due to reverse recovery currents of the clamp diodes, or to switching transients related to the capacitance of the load. DC motors require more blank time than stepper motors. The driver blank time, tBLANK , is approximately 3 s. Phase Input (PHASEx) The state of the PHASEx input determines the direction of rotation of the motor. Charge Pump (CP1 and CP2) Sleep Mode To minimize power consumption when not in use, the A5995 can be put into Sleep Mode by bringing the SLEEPn pin low. Sleep Mode disables much of the internal circuitry, including the charge pump. Overcurrent Protection An overcurrent monitor protects the A5995 from damage due to output shorts. If a short is detected, the A5995 latches the fault and disables the outputs. The latched fault can only be cleared by cycling the power to VBB or by putting the device in Sleep Mode. During OCP events, Absolute Maximum Ratings may be exceeded for a short period of time before outputs are latched off. Shutdown In the event of a fault (excessive junction temperature, or low voltage on VCP), the outputs of the device are disabled until the fault condition is removed. At power-up, the undervoltage lockout (UVLO) circuit disables the drivers. Synchronous Rectification When a PWM off cycle is triggered by an internal fixed off-time cycle, load current will recirculate. The A5995 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay. This effectively shorts the body diode with the low RDS(on) driver. This significantly lowers power dissipation. When a zero current level is detected, synchronous rectification is turned off to prevent reversal of the load current. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A5995 DMOS Dual Full-Bridge PWM Motor Driver MODE Braking Control input MODE is used to toggle between fast decay mode and slow decay mode for the DC driver. A logic high puts the device in slow decay mode. Synchronous rectification is always enabled when ENABLE is low. Driving the device in slow decay mode via the MODE pin and applying an ENABLE chop command implements the Braking function. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts the motor-generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations: high speed and high inertia loads. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A5995 DMOS Dual Full-Bridge PWM Motor Driver LOGIC TIMING DIAGRAM, DC DRIVER ENB PH MODE VBB OUTA 0V VBB OUTB 0V IOUT 0A A 1 2 3 4 5 6 7 VBB 8 9 VBB 1 5 6 OutA OutB 3 A 2 4 7 OutA OutB 8 9 Charge Pump and VREG Power-up Delay (200 s) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A5995 DMOS Dual Full-Bridge PWM Motor Driver APPLICATIONS INFORMATION Motor Configurations For applications that require either a stepper/DC motor driver or dual stepper motor driver, Allegro offers the A5989 and A5988. These devices are offered in the same QFN package as the A5995. The A5988 is capable of driving two bipolar stepper motors at output currents up to 1.2 A. The stepper control logic is industry-standard parallel communication. Refer to the Allegro website for datasheets and further information about those devices. Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A5995 must be soldered directly onto the board. On the underside of the A5995 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. Grounding In order to minimize the effects of ground bounce and offset issues, it is important to have a low-impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the groundplane directly under the A5995, that area becomes an ideal location for a star ground point. A low-impedance ground will prevent ground bounce during high-current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low-impedance ground point and thermal path. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is necessary because the ceramic capacitor will be responsible for delivering the high-frequency current components. Sense Pins The sense resistors, RSx, should have a very low-impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in the layout below, the SENSEx pins have very short traces to the RSx resistors and very thick, low-impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. Note: When selecting a value for the sense resistors, be sure not to exceed the maximum voltage on the SENSEx pins of 500 mV. VBB VBB CVCP CVCP CIN3 CCP NC NC MODE1 GND CP1 VCP VBB OUT1B OUT2B SENSE1 SENSE2 OUT1A OUT2A RS2 CIN2 NC GND OUT2A OUT2B VBB NC OUT1A PAD OUT1B PHASE1 CIN2 SENSE2 GND CIN1 SENSE1 NC CIN1 OUT2A A5995 NC RS1 OUT2B CP2 GND MODE2 OUT1A U1 VREF2 1 VREF1 RS2 ENABLE1 CIN3 GND SLEEPn OUT1B CCP PHASE2 RS1 ENABLE2 GND GND Figure 2: Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A5995 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A5995 19 NC 20 OUT2A 21 SENSE2 22 OUT2B 23 VBB 24 OUT2B 25 SENSE2 MODE1 28 18 GND NC 29 17 PHASE1 GND 30 16 GND 15 NC CP1 32 14 VREF2 CP2 33 13 VREF1 GND 34 12 NC ENABLE1 35 11 SLEEPn ENABLE2 36 10 PHASE2 PAD 1 2 3 4 5 6 7 8 9 NC SENSE1 OUT1B VBB OUT1B SENSE1 OUT1A NC VCP 31 OUT1A Pinout Diagram 26 OUT2A 27 MODE2 DMOS Dual Full-Bridge PWM Motor Driver Terminal List Table Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - Name NC OUT1A SENSE1 OUT1B VBB OUT1B SENSE1 OUT1A NC PHASE2 SLEEPn NC VREF1 VREF2 NC GND PHASE1 GND NC OUT2A SENSE2 OUT2B VBB OUT2B SENSE2 OUT2A MODE2 MODE1 NC GND VCP CP1 CP2 GND ENABLE1 ENABLE2 PAD Description No Connect DMOS Full Bridge 1 Output A Sense Resistor Terminal for Bridge 1 DMOS Full Bridge 1 Output B Load Supply Voltage DMOS Full Bridge 1 Output B Sense Resistor Terminal for Bridge 1 DMOS Full Bridge 1 Output A No Connect Control Input Active-Low Sleep Mode Input No Connect Analog Input Analog Input No Connect Ground Control Input Ground No Connect DMOS Full Bridge 2 Output A Sense Resistor Terminal for Bridge 2 DMOS Full Bridge 2 Output B Load Supply Voltage DMOS Full Bridge 2 Output B Sense Resistor Terminal for Bridge 2 DMOS Full Bridge 2 Output A Control Input Control Input No Connect Ground Reservoir Capacitor Terminal Charge Pump Capacitor Terminal Charge Pump Capacitor Terminal Ground Control Input Control Input Exposed pad for enhanced thermal performance. Should be soldered to the PCB Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A5995 DMOS Dual Full-Bridge PWM Motor Driver PACKAGE OUTLINE DRAWING 1.15 6.00 0.15 1 2 0.30 0.50 36 36 1 2 A 6.00 0.15 D 37X SEATING PLANE 0.08 C 4.15 C 5.80 4.15 5.80 0.90 0.10 +0.05 0.25 -0.07 0.50 All dimensions nominal, not for tooling use (reference JEDEC MO-220VJJD-3, except pin count) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 0.55 0.20 B A Terminal #1 mark area 4.15 2 1 36 4.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals EV Package, 36-Pin QFN with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A5995 DMOS Dual Full-Bridge PWM Motor Driver Revision History Number Date Description - June 20, 2016 Initial release 1 July 29, 2016 Updated Selection Guide table Copyright (c)2016, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12