A5995GEVSR-T - ALLEGRO MICROSYSTEMS

DESCRIPTION

The A5995 is designed to operate at voltages up to 40 V while driving

two DC motors at currents up to 3.2 A. The A5995 includes a fixed

off-time pulse-width modulation (PWM) regulator for current control.

The DC motors are controlled using standard PHASE and ENABLE

signals. Fast or slow current decay is selected via the MODE pin.

Internal synchronous rectification control circuitry is provided to

improve power dissipation during PWM operation.

Protection features include thermal shutdown with hysteresis,

undervoltage lockout (UVLO), crossover-current and short-circuit

protection. Special power-up sequencing is not required.

The A5995 is supplied in a leadless 6 mm × 6 mm × 0.9 mm, 36-pin QFN

package with exposed power tab for enhanced thermal performance.

The package is lead (Pb) free, with 100% matte-tin leadframe plating.

A5995-DS, Rev. 1

FEATURES AND BENEFITS

• 40 V output rating

• Two 3.2 A DC motor drivers

• Synchronous rectification

• Internal undervoltage lockout (UVLO)

• Thermal shutdown circuitry

• Crossover-current protection

• Very thin profile QFN package

• Overcurrent protection

• Low-power sleep mode

• 3.3 and 5 V compatible logic supply

DMOS Dual Full-Bridge PWM Motor Driver

Package: 36-pin QFN with exposed thermal pad

0.90 mm nominal height (suffix EV)

A5995

Not to scale

Microcontroller or

Controller Logic

MODE1

PHASE1

ENABLE1

VREF1

MODE2

PHASE2

ENABLE2

VREF2

SLEEPn

CP1 CP2 VCP VBB VBB

OUT1A

SENSE1

OUT1B

A5995

0.1 µF

50 V 100 µF

50 V

0.22 µF

50 V

0.1 µF

50 V

OUT1B

OUT2A

SENSE2

OUT2B

GND GND GND GND

Figure 1:Typical Application Circuit

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Units

Load Supply Voltage VBB –0.5 to 40 V

Output Current* IOUT DC motor driver, continuous 3.2 A

Logic Input Voltage Range VIN –0.3 to 7 V

SENSEx Pin Voltage VSENSEx

0.5 V

Pulsed tw < 1 µs 2.5 V

VREFx Pin Voltage VREFx 2.5 V

Operating Temperature Range TARange G –40 to 105 °C

Junction Temperature TJ(max) 150 °C

Storage Temperature Range Tstg –55 to 150 °C

* May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a

Junction Temperature of 150°C.

THERMAL CHARACTERISTICS: May require derating at maximum conditions

5500

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

25 50 75 100 125 150 175

Temperature (°C)

Power Dissipation, P

(mW)

Power Dissipation versus Ambient Temperature

(RθJA = 27 ºC/W)

EV Package

4-layer PCB

SELECTION GUIDE

Part Number Packing

A5995GEVSR-T 6000 pieces per reel

Characteristic Symbol Test Conditions Min. Units

Package Thermal Resistance RθJA EV package, 4-layer PCB based on JEDEC standard 27 °C/W

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

CHARGE

PUMP

DMOS Full Bridge 1

DMOS Full Bridge 2

MODE1

PHASE1

ENABLE1 OUT1B

OUT1A

SENSE2

OUT2B

OUT2A

VCP

OSC

Sense2

VREF2

CONTROL

LOGIC

GATE

DRIVE

+ -

Sense1

Sense2

PWM Latch

BLANKING

PWM Latch

BLANKING

CONTROL

LOGIC

GATE

DRIVE

GND

CP1

VBB

CP2

VREF1

MODE2

PHASE2

ENABLE2

VBB

SLEEPn

OUT1A

OUT1B

OUT2A

OUT2B

SENSE2

SENSE1

GND

0.1 µF

50 V

0.1 µF

50 V

100 µF

50 V

0.22 µF

50 V

Functional Block Diagram

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS1: Valid at TA = 25 °C, VBB = 40 V, unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ.2Max. Units

Load Supply Voltage Range VBB Operating 8 – 40 V

Output On-Resistance RDS(on)

Source driver, IOUT = –1.2 A, TJ = 25°C – 250 300 mΩ

Sink driver, IOUT = 1.2 A, TJ = 25°C – 240 300 mΩ

Vf , Outputs IOUT = 1.2 A – – 1.2 V

Output Leakage IDSS Outputs, VOUT = 0 to VBB –20 – 20 µA

VBB Supply Current IBB

IOUT = 0 mA, outputs on, fPWM = 50 kHz,

duty cycle = 50% – – 23 mA

Outputs off – 11.7 14 mA

Sleep mode –10 < 1 10 µA

Output Driver Slew Rate SROUT 10% to 90% 50 100 150 ns

Control Logic

Logic Input Voltage VIN(1) 2 – – V

VIN(0) – – 0.8 V

Logic Input Current IIN VIN = 0 to 5 V –20 < 1 20 µA

Input Hysteresis Vhys 150 300 500 mV

Sleep Rising Threshold VSLEEPn(r) 2.5 2.7 2.95 V

Sleep Falling Threshold VSLEEPn(f) – 2.4 – V

Sleep Hysteresis VSLEEPn(hys) 250 325 450 mV

Sleep Input Current ISLEEPn – 100 150 µA

Propagation Delay Times tpd

PWM change to source on 550 700 1000 ns

PWM change to source off 35 – 450 ns

PWM change to sink on 550 700 1000 ns

PWM change to sink off 35 – 450 ns

Crossover Delay tCD 250 425 1000 ns

Blank Time (DC motor driver) tBLANK 2.5 3.2 4 µs

VREFx Pin Input Voltage Range VREFxOperating 0 – 1.5 V

VREFx Pin Reference Input Current IREF VREF = 1.5 V – – ±1 μA

Current Trip-Level Error VERR VREF = 1.5 V –5 – 5 %

Protection Circuits

VBB UVLO Threshold VUV(VBB) VBB rising 7.3 7.6 7.9 V

VBB Hysteresis VUV(VBB)hys 400 500 600 mV

Overcurrent Protection Threshold IOVP 3.2 – – A

Thermal Shutdown Temperature TJTSD 155 165 175 °C

Thermal Shutdown Hysteresis TJTSDhys – 15 – °C

1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.

2 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-

vidual units, within the specified maximum and minimum limits.

3 VERR = [(VREF/3) – VSENSE] / (VREF/3).

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

DC Control Logic

PHASE ENABLE MODE 3 × VS > VREF OUTA OUTB Function

1 1 1 false H L Forward (slow decay SR)

1 1 0 false H L Forward (fast decay SR)

0 1 1 false L H Reverse (slow decay SR)

0 1 0 false L H Reverse (fast decay SR)

X 0 1 X L L Brake (slow decay SR)

1 0 0 X L H Fast decay SR*

0 0 0 X H L Fast decay SR*

X 1 1 true L L OCL chop / slow decay SR

1 1 0 true L H OCL chop / fast decay SR*

0 1 0 true H L OCL chop / fast decay SR*

* To prevent reversal of current during fast decay SR – the outputs will go to the high-impedance state as the current gets near zero.

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Device Operation

The A5995 is designed to operate two DC motors. The currents

in each of the full bridges, all N-channel DMOS, are regulated

with fixed off-time pulse-width-modulated (PWM) control

circuitry. The peak current in each full bridge is set by the value

of an external current sense resistor, RSx , and a reference voltage,

VREFx .

Internal PWM Current Control

Each full-bridge is controlled by a fixed off-time PWM current

control circuit that limits the load current to a user-specified

value, ITRIP . Initially, a diagonal pair of source and sink DMOS

outputs are enabled and current flows through the motor wind-

ing and RSx. When the voltage across the current sense resistor

equals the voltage on the VREFx pin, the current sense compara-

tor resets the PWM latch, which turns off the source driver.

The maximum value of current limiting is set by the selection of

RS and the voltage at the VREF input with a transconductance

function approximated by:

ITripMax = VREF / (3 × RS)

Note: It is critical to ensure that the maximum rating of ±500 mV

on each SENSEx pin is not exceeded.

Fixed Off-Time

The internal PWM current control circuitry uses a one-shot

circuit to control the time the drivers remain off. The one-shot

off-time, toff

, is internally set to 30 µs.

Blanking

This function blanks the output of the current sense compara-

tor when the outputs are switched by the internal current control

circuitry. The comparator output is blanked to prevent false

detections of overcurrent conditions, due to reverse recovery cur-

rents of the clamp diodes, or to switching transients related to the

capacitance of the load. DC motors require more blank time than

stepper motors. The driver blank time, tBLANK , is approximately

3 μs.

Phase Input (PHASEx)

The state of the PHASEx input determines the direction of rota-

tion of the motor.

Control Logic

DC motor commutation is accomplished by applying a PWM

signal together with the PHASE or ENABLE inputs. Fast or slow

current decay during the off-time is selected via the MODE pin.

Synchronous rectification is always active regardless of the state

of the MODE pin.

Charge Pump (CP1 and CP2)

The charge pump is used to generate a gate supply greater than

VBB in order to drive the source-side DMOS gates. A 0.1 μF

ceramic capacitor should be connected between CP1 and CP2

for pumping purposes. A 0.1 μF ceramic capacitor is required

between VCP and VBBx to act as a reservoir to operate the high-

side DMOS devices.

Sleep Mode

To minimize power consumption when not in use, the A5995

can be put into Sleep Mode by bringing the SLEEPn pin low.

Sleep Mode disables much of the internal circuitry, including the

charge pump.

Overcurrent Protection

An overcurrent monitor protects the A5995 from damage due to

output shorts. If a short is detected, the A5995 latches the fault

and disables the outputs. The latched fault can only be cleared

by cycling the power to VBB or by putting the device in Sleep

Mode. During OCP events, Absolute Maximum Ratings may be

exceeded for a short period of time before outputs are latched off.

Shutdown

In the event of a fault (excessive junction temperature, or low

voltage on VCP), the outputs of the device are disabled until the

fault condition is removed. At power-up, the undervoltage lock-

out (UVLO) circuit disables the drivers.

Synchronous Rectification

When a PWM off cycle is triggered by an internal fixed off-time

cycle, load current will recirculate. The A5995 synchronous rec-

tification feature will turn on the appropriate MOSFETs during

the current decay. This effectively shorts the body diode with the

low RDS(on) driver. This significantly lowers power dissipation.

When a zero current level is detected, synchronous rectification

is turned off to prevent reversal of the load current.

FUNCTIONAL DESCRIPTION

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

MODE

Control input MODE is used to toggle between fast decay mode

and slow decay mode for the DC driver. A logic high puts the

device in slow decay mode. Synchronous rectification is always

enabled when ENABLE is low.

Braking

Driving the device in slow decay mode via the MODE pin and

applying an ENABLE chop command implements the Braking

function. Because it is possible to drive current in both direc-

tions through the DMOS switches, this configuration effectively

shorts the motor-generated BEMF as long as the ENABLE chop

mode is asserted. The maximum current can be approximated

by VBEMF/RL. Care should be taken to ensure that the maximum

ratings of the device are not exceeded in worst-case braking situ-

ations: high speed and high inertia loads.

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ENB

MODE

OUTA

OUTB

OUT

0 V

2 3 4 5 6 7

98A

A Charge Pump and VREG Power-up Delay (

≈

200 µs)

OutBOutAOutA OutB

0 A

LOGIC TIMING DIAGRAM, DC DRIVER

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

CIN1

OUT1B

GND

CIN3

VBB

OUT1A

RS2

RS1

CVCP

CIN2

CCP

OUT2A

OUT2B

Motor Configurations

For applications that require either a stepper/DC motor driver

or dual stepper motor driver, Allegro offers the A5989 and

A5988. These devices are offered in the same QFN package as

the A5995. The A5988 is capable of driving two bipolar stepper

motors at output currents up to 1.2 A. The stepper control logic

is industry-standard parallel communication. Refer to the Allegro

website for datasheets and further information about those

devices.

Layout

The printed circuit board should use a heavy groundplane. For

optimum electrical and thermal performance, the A5995 must be

soldered directly onto the board. On the underside of the A5995

package is an exposed pad, which provides a path for enhanced

thermal dissipation. The thermal pad should be soldered directly

to an exposed surface on the PCB. Thermal vias are used to trans-

fer heat to other layers of the PCB.

Grounding

In order to minimize the effects of ground bounce and offset

issues, it is important to have a low-impedance single-point

ground, known as a star ground, located very close to the device.

By making the connection between the exposed thermal pad and

the groundplane directly under the A5995, that area becomes an

ideal location for a star ground point.

A low-impedance ground will prevent ground bounce during

high-current operation and ensure that the supply voltage remains

stable at the input terminal. The recommended PCB layout shown

in the diagram below, illustrates how to create a star ground

under the device, to serve both as low-impedance ground point

and thermal path.

The two input capacitors should be placed in parallel, and as

close to the device supply pins as possible. The ceramic capaci-

tor should be closer to the pins than the bulk capacitor. This is

necessary because the ceramic capacitor will be responsible for

delivering the high-frequency current components.

Sense Pins

The sense resistors, RSx, should have a very low-impedance

path to ground, because they must carry a large current while

supporting very accurate voltage measurements by the current

sense comparators. Long ground traces will cause additional

voltage drops, adversely affecting the ability of the comparators

to accurately measure the current in the windings. As shown in

the layout below, the SENSEx pins have very short traces to the

RSx resistors and very thick, low-impedance traces directly to the

star ground underneath the device. If possible, there should be no

other components on the sense circuits.

Note: When selecting a value for the sense resistors, be sure not to

exceed the maximum voltage on the SENSEx pins of ±500 mV.

Figure 2: Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A5995

(U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, con-

necting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground.

APPLICATIONS INFORMATION

CCP

CVCP CIN3

RS1 PAD

A5995

CIN2

CIN1

RS2

MODE2

OUT2A

SENSE2

OUT2B

VBB

OUT2B

SENSE2

OUT2A

OUT1A

SENSE1

OUT1B

VBB

OUT1B

SENSE1

OUT1A

PHASE2

SLEEPn

VREF1

VREF2

GND

PHASE1

GND

ENABLE2

ENABLE1

GND

CP2

CP1

VCP

GND

MODE1

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Terminal List Table

MODE2

OUT2A

SENSE2

OUT2B

VBB

OUT2B

SENSE2

OUT2A

OUT1A

SENSE1

OUT1B

VBB

OUT1B

SENSE1

OUT1A

GND

PHASE1

GND

VREF2

VREF1

SLEEPn

PHASE2

MODE1

GND

VCP

CP1

CP2

GND

ENABLE1

ENABLE2

PAD

Pinout Diagram

Number Name Description

1 NC No Connect

2 OUT1A DMOS Full Bridge 1 Output A

3 SENSE1 Sense Resistor Terminal for Bridge 1

4 OUT1B DMOS Full Bridge 1 Output B

5 VBB Load Supply Voltage

6 OUT1B DMOS Full Bridge 1 Output B

7 SENSE1 Sense Resistor Terminal for Bridge 1

8 OUT1A DMOS Full Bridge 1 Output A

9 NC No Connect

10 PHASE2 Control Input

11 SLEEPn Active-Low Sleep Mode Input

12 NC No Connect

13 VREF1 Analog Input

14 VREF2 Analog Input

15 NC No Connect

16 GND Ground

17 PHASE1 Control Input

18 GND Ground

19 NC No Connect

20 OUT2A DMOS Full Bridge 2 Output A

21 SENSE2 Sense Resistor Terminal for Bridge 2

22 OUT2B DMOS Full Bridge 2 Output B

23 VBB Load Supply Voltage

24 OUT2B DMOS Full Bridge 2 Output B

25 SENSE2 Sense Resistor Terminal for Bridge 2

26 OUT2A DMOS Full Bridge 2 Output A

27 MODE2 Control Input

28 MODE1 Control Input

29 NC No Connect

30 GND Ground

31 VCP Reservoir Capacitor Terminal

32 CP1Charge Pump Capacitor Terminal

33 CP2Charge Pump Capacitor Terminal

34 GND Ground

35 ENABLE1 Control Input

36 ENABLE2 Control Input

–PAD Exposed pad for enhanced thermal performance. Should

be soldered to the PCB

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PACKAGE OUTLINE DRAWING

0.25 +0.05

–0.07 0.50

0.90 ±0.10

0.55 ±0.20

SEATING

PLANE

6.00 ±0.15

0.30

1.15 0.50

5.80

4.15

C0.08

37X

DCoplanarity includes exposed thermal pad and terminals

ATerminal #1 mark area

Exposed thermal pad (reference only, terminal #1

identifier appearance at supplier discretion)

CReference land pattern layout (reference IPC7351

QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from

all adjacent pads; adjust as necessary to meet application process

requirements and PCB layout tolerances; when mounting on a

multilayer PCB, thermal vias at the exposed thermal pad land can

improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

All dimensions nominal, not for tooling use

(reference JEDEC MO-220VJJD-3, except pin count)

Dimensions in millimeters

Exact case and lead configuration at supplier discretion within limits shown

EV Package, 36-Pin QFN with Exposed Thermal Pad

DMOS Dual Full-Bridge PWM Motor Driver

A5995

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

For the latest version of this document, visit our website:

www.allegromicro.com

Revision History

Number Date Description

– June 20, 2016 Initial release

1 July 29, 2016 Updated Selection Guide table

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.