IS66WVD4M16ALL
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Overview
The IS66WVD4M 16ALL is an integra ted memory device c ontaining 64Mbit Pseudo Sta tic Random
Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device uses a
multiplexed address and data bus scheme to minimize pins and includes a industry standard burst
mode for increased read and write bandwidth. The device includes several power saving modes :
Reduced Array Refresh mode where data is retained in a portion of the array and Temperature
Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a
standa rd asynchrono us m ode and high perform ance burst mod e. The die has sepa ra te power rails,
VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Single de vice support s a synchrono us and burst
operation
Mixed Mode supports asynchronous w rite and
synchronous read operation
Dual voltage rails for optional performance
VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
Multiplexed address and data bus
ADQ0~ADQ15
Asynchronous mode read access : 70ns
Burst mode for Read and Write operation
4, 8, 16 or Continuous
Low Power Consumption
Asynchronous Operation < 25 mA
Burst operation < 35 mA (@104Mhz)
Standby < 150 uA(max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power F eatu re
Reduced Array Refresh
Temperature Controlled Refresh
Opera tio n Freq uency up to 104MHz
Operating temperature Range
Industrial -40°C~85°C
Packa ge: 54-ball VFBGA
64Mb Async and Burst CellularRAM 2.0
Features
Copyright © 2011 Integrated S i l i con Solution, Inc. All rights reserved. ISS I reserves the right t o make changes to this specific ation and it s
products at any tim e without noti ce. ISSI assum es no liability arising out of the application or use of any i nformat i on, products or services
described herein. Custom ers are advised to obtain the latest version of this device specif ic ation before relying on any publi shed inf orm ati on
and before pl acing orders f or produc ts.
Integrated Sili con Solution, Inc. does not recommend the use of any of its products in l i f e support applications where t he failure or
malf unction of the product can reasonabl y be expected to cause failure of t he life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use i n such applicat i ons unless I ntegrated S i l i con Solution, I nc. receives written assurance t o
its satisfactio n, that:
a.) the risk of injury or damage has been minimized;
b.) the user ass ume all such risk s; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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General Desc ription
CellularRAM™ (Trademark of MicronTechnology) products are high-speed, CMOS pseudo-static
random ac ces s memories develop ed f or low-power, portable applications.
The 64Mb DRAM core device is orga nized as 4 Meg x 16 bits. This d evice is a variation
of the industry-standard Flash control interface, with a multiplexed address/data bus.
The multiplexed address and data functionality dramatically red uce the required
signal count, and increase READ/WRITE bandwidth.
To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a
transparent self-refr esh m echa nism . The hidde n re fres h req uire s no ad dit iona l support
from the system mem ory controller and has no significant impact on device read/write
performance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly ide ntica l to its counterpart on burst mode Flash devices.
The refresh configuration register (RCR) is used to control how refresh is performed on
the DRAM array. These registers are a utom atically loaded with default settings during
power-up and can be updated anytime during normal opera tion.
Special atte ntion ha s be en focused on st and by curre nt consum pti on during s elf re fre sh.
CellularRAM products include three me chanisms to minimize standby current. Partial
array refresh (PAR) enables the system to limit refresh to only that part of the DRAM
array that contains essential data. Temperature-compensated refresh (TCR) uses an
on-chip sensor to adjust the refresh rate to match the device temperature —the refresh
rate decreases at lower temperatures to minimize current consumption during standby.
Deep power-down (DPD) enables the system to halt the refresh operation altogether
when no vital information is stored in the device. The system-configurable refresh
mechanism s a re adjusted throug h t he R CR .
This CellularRAM device is compliant with the industry-standard CellularRAM 2.0
feature set established by the CellularRAM Workgroup. It includes support for both
variable and fixed latency, with three drive strengths, a variety of wrap options, and a
device ID register (DIDR).
[ Functional Block Diagram]
Address
Decode Logic
Refresh
Configuration Register
(RCR)
Bus
Configuration Register
(BCR)
4096K X 16
DRAM
Memory Array
Input
/Output
Mux
And
Buffers
Control
Logic
ADQ0~ADQ15
A16~A21
CE#
WE#
OE#
CLK
ADV#
CRE
LB#
UB#
WAIT
Device ID Register
(DIDR)
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54Ball VFBGA Ball Assignment
[Top View]
(Ball Down)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
LB# OE# NC
ADQ8 UB# NC
ADQ9 ADQ10 NC
VSSQ ADQ11 A17
ADQ14 ADQ13 NC
ADQ15 A19 NC
A18 NC NC
WAIT CLK ADV#
NC NC CRE
NC CE# ADQ0
NC ADQ1 ADQ2
NC ADQ3 VDD
NC ADQ5 ADQ6
NC WE# ADQ7
NC NC A20
NC NC NC
VDDQ ADQ12 A21 A16 ADQ4 VSS
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Signal Descriptions
All signals for the device are listed below in Table 1.
Symbol Type Description
VDD Power Supply Core Power supply (1.7V~1.95V)
VDDQ PowerSupply I/O Power supply (1.7V~1.95V)
VSS PowerSupply All VSS supply pi ns must be connected t o Ground
VSSQ PowerSupply All VSSQ supply pins must be connected t o Ground
ADQ0~
ADQ15 Input / Output Address Input(A0~A15)
Data Input/Ou tpu t (DQ0~DQ15)
A16~A21 Input Address Input(A16~A21)
LB# InputLower Byte select
UB# InputUpper Byte select
CE# InputChip Enable/Select
OE# InputOutput Ena ble
WE# InputWrite Enable
CRE Input Control Register Enable: When CRE is HIGH, READ and WRITE operations
access registers.
ADV# InputAddress Valid signal
Signal that a valid address is present on the address bus. Address are
latched on the rising ed ge of ADV# during asynchrono u s Read /W rit e
operations. Addresses are latched on the rising edge of CLK with ADV#
low during synchronous operation.
CLK InputClock
Latches addresses and commands on the first rising CLK edge when
ADV# is active in synchronous mode. CLK must be kept static Low during
asynchronous Read/Write operations.
WAIT Output WAIT
Data valid signal during burst Read/Writ e operation. WAIT is used to
arbitrate collisions between refresh and Read/Write operation. WAIT is
also asserted at the end of a row unless w r apping within the burst length.
WAIT is asserted and should be ignored during asynchronous READ
operation. WAIT is gated by CE# and is high-Z w hen CE # is high.
Table 1. Signal D es cr iptions
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Functional Description
All functions for the device are listed below in Table 2.
Mode Power CLK1ADV# CE# OE# WE# CRE2UB#/
LB# WAIT3ADQ
[15:0]4Note
Asynchronous M ode
Read Active L L L H L L Low-Z Data-out 5
Write Active L L X L L L High-Z Data-in 5
Standby Stand
by L X H X X L X High-Z High-Z 6,7
No Operation Idle L X L X X L X Low-Z X 5,7
Configuration
Register W rit e Active L L H L H X High-Z High-Z
Configuration
Register R ead Active L L L H H L Low-Z Config-Reg
Out
Deep Pow er-
Down DPD L X H X X X X High-Z High-Z 10
Sync h r o n o u s Mode (Bur st M o de)
Async read Active L L L H L L Low-Z Data-Out 5
Async write Active L L X L L L High-Z Data-In 5
Standby Stand
by L X H X X L X High-Z High-Z 6,7
No oper a t i on Idle L X L X X L X Low-Z X 5,8
Initial
burst read Active L L X H L L Low-Z Address 5,8
Initial
burst w ri t e Active L L H L L X Low-Z Address 5,8
Burst
continue Active H L X X L L Low-Z Data-In or
Data-Out 5,8
Burst suspend Active L L L H X L X Low-Z High-Z 5,8
Configuration
register w rite Active L L H L H X Low-Z High-Z 8,11
Configuration
register read Active L L L H H L Low-Z Config-Reg
Out 8,11
Deep Pow er-
Down DPD L X H X X X X High-Z High-Z 10
Table 2. Functional D esc ri ptions
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Notes 1. CLK must be LOW during Asynch Read and Asynch Write modes. CLK must be LOW to achieve
low standby current during standby mode and DPD modes. CLK must be static (LOW or HIGH)
during b urst suspe nd.
2. Configuration registers are accessed when CRE is HIGH during the address portion
of a READ or WRITE cycle.
3. WAIT polarity is configured through the bus configuration register (BCR[10]).
4. When UB# and LB# are in select mode (LOW), ADQ0~ADQ15 are affected as shown.
When only LB# is in select mo de, ADQ0~ADQ7 are affected as shown. When only UB# is
in select mode, ADQ8 ~ ADQ15 are affected as shown.
5. The device will consume active power in this mode whenever addresses are changed with ADV#
LOW
6. When the device is in standby mode, address inputs and data inputs/outputs are internally
isolated from any external influence.
7. Vin=VDDQ or 0V, all device pins be static (unswitched) in ord er to achieve sta ndb y curre nt.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. Byte operation can be supported Write & Read at asynchronous mode and Write at
synchronou s mode.
10. DPD is initiated when CE# transition from LOW to HIGH after writing RCR[4] to 0. DPD is
maintained until CE# transitions from HIGH to LOW
11. Initial cycle. Following cycles ar e the same as BURST CONTINUE. CE# must stay LOW
for the equivalent of a single w ord burst (as indicated by WAIT).
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Functional Description
In general, this device is high-de nsit y a lt er nat ives t o SRAM a nd Pseudo SRAM prod ucts po pula r
in low-power, portable applications.
The 64Mb device contains a 67,108,864-bit DRA M core organi zed as 4,194,304 addresses by
16 bits. This device imple ments a multiplexed address/data bus.
This multiplexed configuration supports greater bandwidth through a x16 data bus, yet still
reduces the required signal co unt.
The Cellula rR AM bus inte rfa ce sup port s bot h asynchr onou s a nd burst m ode transfers.
Power-Up Initialization
CellularRAM products include an on-chip volta ge sensor used to launch the power -up initialization
process. Initialization will configure the B C R and the RCR with their default settings (see Table 3
and Table 8). VDD and VDDQ must be app lie d simultaneously.
When they reach a stable level at or above 1.7V, the device will require 150μs to complete
its self-initialization process. During the initialization period, CE# should remain HIGH. When
initialization is complete, the device is ready for normal operation.
Figure 1: Power-Up Initialization Timing
VDD=1.7V
Device Initialization
tPU > 150us Device r eady for
normal operation
VDD
VDDQ
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Bus Operating Modes
CellularRAM products incorporate a burst mode interface target ed at low -power,
wireless applications. This bus interface supports asynchronous and burst mode read
and write transfers. The specific interface supported is defined by the value loaded into
the bus configurati on register.
Burst Mode Operation
Burst mode operations enable high-sp ee d synchro nou s READ and WR ITE ope ra tions .
Burst operations consist of a multi-clock sequence that must be performed in an
ordered fashion.
The size of a burst can be specified in the B C R either as a fixed length or continuous.
Fixed-length bursts consist of four, eight, or sixteen words of sixteen bits. Continuous
bursts have the ability to start at a specified address a nd burst to the end of the row.
(Row length of 128 words or 256 words is a manufacturer opti on.)
The late ncy count stor ed in the BCR defines t he numb er of clock cycles tha t el ap se
before the initial data value is transferred betwe en the processor and CellularRAM
device. The initial latency for READ operations can be configured as fixed or variable.
Variable latency allows the CellularRAM to be configured for minimum latency at high
clock frequencies, but the controller must monitor WAIT to detect any conflict with
refresh cycles (see Figure 23).
Fixed latency outputs the first data word after the worst-case access delay, including
allowance for refresh collisions. The initial latency time and clock speed determine the
latency count s et ting . Fixe d la te ncy is used whe n the contro lle r cannot monit or WAIT.
Fixed latency also provides improved performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated and de-asserts to indicate when dat a
is to be transferred into (or out of) the memory. WAIT will again be asserted at the
boundary of the row unless wr ap ping wit hin the burst le ngth.
To access other devices on the same bus without the timing penalty of the initial latency
for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK.
CLK must be stopped LOW. If another device will use the data bus while the burst is
suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise,
OE# can remain LOW. Note that the WAIT output will continue to be active, and as a
result no other devices should directly share the WAIT connection to the controller. To
continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is
available on the bus.
CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than
tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE#
should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle.
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Burst Read Operation
After CE# goes LOW, the address to access is latched on the rising edge of the next clock
that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation
is going to be a READ (WE# = HIGH, Figure 2)
Then the data needs to be output to multiplexed data bus (ADQ0~ADQ15)
according to set WAIT states.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data
is to be transferred into (or out of ) the memory. WAIT will again be asserted at t he
boundary of a row, unless wr ap ping wit hin the burst leng th.
A full 4 word synchronous read access is shown in Figure 2 and the AC characteristics a re specified
in Table 16.
Figure 2. Synchronous Read Access Timing
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
Read Burst Identified (WE#=HIGH)
tCLK
VALID
ADDRESS
VALID
ADDRESS
tSP tHD
tSP tHD tKOH
tACLK
tCEM
tCSP
tHD
tSP tHD
tOE
tOLZ
tKW
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tCBPH
tHZ
tABA
tWZ
HiZ
tKW
tOHZ
tSP tHD
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Burst Write Operation
After CE# goes LOW, the address to access is latched on the rising edge of the next clock
that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation
is going to be a WRITE (WE# =LOW, Figure 3).
Data is placed to the multiplexed data bus (ADQ0~ADQ15) with consecutive clock cycles
when WAI T de-asserts.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data
is to be transferred into (or out of ) the memory. WAIT will again be asserted at t he
boundary of a row, unless wr ap ping wit hin the burst leng th.
A full 4 word synchronous write access is shown in Figure 3 and the AC characteristics a re
specified in Table 18.
Figure 3. Synchronous Write Access Timing
Write Burst Identified (WE#=LOW)
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
CLK
tCLK
VALID
ADDRESS
tKW
VALID
ADDRESS
tSP tHD tHD
tCEM
tCSP
tHD
tSP tHD
tKW
DATA IN DATA INDATA INDATA IN
tCBPH
HiZ
tSP
tHD
tSP
tAS
tAS
tHD
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Asynchronous Mode
Asynchronous mode uses industry-sta ndar d SR AM control signals (CE#, ADV#, OE#,
WE#, UB#, and LB#). R EAD operations (Figure 4) are initiated by bringing CE#, ADV#,
UB# and LB# LOW while keeping OE# and WE# HIGH, and driving the address onto the
multiplexed address/data bus. ADV# is taken HIGH to capture the address, and OE# is
taken LOW. Valid data will be driven out of the I/Os after the specified access time has
elapsed.
WRITE opera t ions (Fi gure 5) occur w hen CE #, ADV #, WE#, UB#, and LB# are driven LOW
with the address on the multiplexed address/data bus. ADV# is taken HIGH to capture
the address, then the write data is driven onto the bus. During asynchronous WRITE
operations, the OE# level is a “Don't Care,” and WE# will override OE#; however, OE#
must be HIGH while the addr ess is driven onto the ADQ bus. The data t o be written is
latched on the rising edge of CE#, WE#, UB#, and LB# (whichever occurs fi rst).
During asynchrono us opera tion, the C LK input must be held LOW. W AIT wi ll be driven
during asynchro nous READs, and its state should be ignored . WE# must not be held
LOW longer than tCEM.
Figure 4. Asynchronous Read Access Timing
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
OE#
WE# HiZ HiZ
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
tCO
tAADV
tOE
tHZ
tCVP
tOLZ
tBA
tAA
tBHZ
tOHZ
tOEW
tWZ
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Mixed-Mode Operation
The device can s upport a combination of synchro nous READ and asynchronou s READ
and WRITE operations when the BCR is configured for s ynchr onous operation. The
asynchronous R E AD a nd WRITE o per at ions r equi re that the clock (C LK) r em ain LO W
during the entire sequence. The ADV# latches the target address. CE# can remain LOW
when transitioning between mixed -mode operations with fixed latency enabled;
however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a
seamless interface to legacy burst mode Flash memory controllers. See Figure 33 for the
“Asynchronous WR ITE Followed by Burst READ” timing diagram.
WAIT Operation
WAIT output on the CellularRAM device is typically connected to a shared, system-level
WAIT signal. The shared WAIT signal is used by the processor to coordinate transactions
with multiple memories on the synchronous bus.
When a synchronous READ or WRITE opera tion has been initia ted, WAIT goes active to
indicate that the CellularRAM device requires additional time before data can be
transferred. For READ operations, WAIT will remain active until valid data is output
from the device. For WRITE operations, WAIT will indicate to the memory controller
when data will be accepted into the Cellular RAM device. When WAIT transitions to an
inactive state, the data burst will progress on successive rising clock edges.
During a burst cycle CE# must remain asserted until the first data is valid. Bringing CE#
HIGH during this initial latency may cause data corruption.
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an
arbitration role for READ operations launched while an on-chip refresh is in progress. If
a collision occurs, the WA IT pin is asserted for additional clock cycles until the refresh
has completed (see Figure 23). When the refresh operation has completed, the
READ operation will continue normally.
WAIT will be asserted but should be ignored during asynchronous READ operations.
WAIT will be High-Z during asynchrono us W RITE ope ra tions .
By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst
mode without monitoring the WAIT pin. However, WAIT can still be used to determine
when valid data is available at the start of the burst and at the end of the row. If wait is
not monitored, the controller must stop burst accesses at row boundaries on its own.
UB#/LB# Operation
The UB#/LB# enable signals support byte-wide data WRITEs. During WRITE operations,
any disabled bytes will not be transferred to the RAM array and the internal value will
remain unchanged. During an asynchronous WRITE cycle, the data to be written is
latched on the rising edge of CE#, WE#, UB#, and LB# whichever occur s first.
UB#/LB# must be LOW duri ng R EA D cycle s.
When UB#/LB# are disabled (HIGH) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected,
it remains in an active mode as long as CE# remains LOW.
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Low-Power Feature
Standby Mode Opera tion
During stand by, the de vice curr ent consump tion is red uced t o the leve l necess ar y t o
perform the DRAM r efresh operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operat ion, or when the ad dre ss and contr ol inp uts re ma in stat ic for an ext end ed period
of time. This mode w ill continue until a change occurs to the address or control inputs.
Temperature-Comp ensated Refresh
Temperature-compensated refresh (TCR) allows for adequate refresh at different
temperatures. This CellularRAM device includes an on-chip temperature sensor that
automatically adjusts the refresh rate according to the operating temperature. The
device continually adjusts the refresh rate to match that temperature.
Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device t o reduce standb y current by refreshing only that
part of the memory array required by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. The mapping
of these partitions can start at either the beginning or the end of the address map (see
Table 9 ). READ and WRITE operations to address ranges receiving refresh will not be affected.
Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional
portions of the array, the new portions are available immediately upon writing to the RCR.
Deep Power-Dow n O pera tion
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, th e CellularRAM device will require 150μs to perform an initialization
procedure before normal operations can resume. During this 150μs period, the current
consumption will be higher than t he specified standby levels, but considerably lower
than the acti ve curr ent sp ecifica t ion.
DPD can be enabled by writing to the RCR using CRE or the software a ccess sequence;
DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW.
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Registers
Two user-accessible configuration registers define the device operation. The bus
configuration register (BCR) defines how the CellularRAM interacts with the system
memory bus and is nearly identica l to its counterpart on burst mode Flash devices. The
refresh configuration register (RCR) is used to control how refresh is performe d on the
DRAM array. These registers are automatically loaded with default settings during
power-up, and can be updated any time the devices are operating in a standby state.
A DIDR provides informat ion on the de vice manufa cture r, Ce llula rR AM genera ti on, and
the specific device configuration. The DIDR is read-only.
Access Using CRE
The regist er s can be acces sed using e ithe r a synchronous or an asynchronous op era t ion
when the configura tio n r egi ste r enab le (CR E) input is HIGH (se e Fig ures 6 throug h 9) .
When CRE is LOW, a READ or WRITE operation will access the memory array. The register
values a re written as an address (ADV# LOW) on the ADQ pins.
In an asynchronous WRITE, t he va lues ar e latche d int o the configura ti on reg iste r
on the rising edge of CE# or WE#, whichever occurs first; UB#/LB# are “Don’t Care.”
The BCR is acces se d w hen A [19:18] i s 10b; t he R CR is acce sse d w he n A[ 19:18] is 00b; the
DIDR is accesse d w he n A[19:18] is 01b. For R EA Ds, a dd re ss inputs othe r t ha n A [19:18]
are “Don’t Care,” and register bits are output as data (ADV # HIGH) on ADQ.
Figure 6: Configuration Register WRITE
–Asynchr onous Mode Followed by RE AD A RRAY O pera tion
Address
ADQ0-
ADQ151
ADV#
CE#
UB#/LB#
CRE2
WE#
OE#
tVP
tAVS tAVH
OPCODE
OPCODE
tCW
tVS
tWP
tCVP
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
tCO
tAADV
tOE
tBA
tHZ
tCPP
tOLZ
tCPH
tAVS
Write Address Bus
Valu e t o Contr ol
Register
tAVH
Notes: 1. A[19:18] = 00b to load RCR ADQ[15:0]; 10b to load BCR ADQ[15:0].
2. CRE must be HIGH to access regi sters.
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Figure 7: Configuration Register WRITE
–Synchron ous Mode Follow ed by REA D ARRA Y O pera tion
VALID
ADDRESS
VALID
ADDRESS
tSP tHD tKOH
tACLK
tCEM
tHD
tOE
tKW
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tABA
tWZ
tKW
tOHZ
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
Notes: 1. Non-default BCR settings for configuration register WRITE in synchronous mode, followed by READ ARRAY
operation: Latency code three (four clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to load RCR ADQ[15:0]; 10b to load BCR ADQ[15:0].
3. CE# must remai n LO W to complet e a bu r st-of-o n e W R I T E . WAI T m u st be mo n i tored additio n a l W A I T
cycl es caused by ref resh c oll ision s require a c or respon ding num ber of additio nal CE # LOW cycles.
4. CRE must be HIGH to access regi sters.
tCLK
OPCODE
tKW
OPCODE
tSP tHD
tCEM
tCSP
tKW
tCBPH3
HiZ
tSP
tAS
tAS
tHD
CRE4
tSP
tHD
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Figure 8: Configuration Register READ
–Asynchr onous Mode Followed by D A TA REA D
Address
ADQ0-
ADQ151
ADV#
CE#
UB#/LB#
CRE2
WE#
OE#
tVP
tAVS tAVH
Don’t Care
Select
Control
Register
tCO
tAADV
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
tCO
tAADV
tOE
tBA
tHZ
tCPP
tOLZ
tCPH
tAVS tAVH
Notes: 1. A[19:18] = 00b to load RCR ADQ[15:0]; 10b to load BCR ADQ[15:0]; 01b to load DIDR ADQ[15:0].
2. CRE must be HIGH to access regi sters.
CR Valid
tOE
tAA
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Figure 9: Configuration Register READ
–Synchron ous Mode Follow ed by D ata REA D
VALID
ADDRESS
VALID
ADDRESS
tSP tHD tKOH
tACLK
tCEM
tHD
tOE
tKW
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tABA
tWZ
tKW
tOHZ
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
Notes: 1. Non-default BCR settings for configuration register READ in synchronous mode, followed by READ ARRAY
operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to load RCR ADQ[15:0]; 10b to load BCR ADQ[15:0]; 01b to load DIDR ADQ[15:0].
3. CE# must remai n LO W to complet e a bu r st-of-one READ. WAIT must be monitored additional WAIT
cycl es caused by ref resh c oll ision s require a c or respon ding num ber of additio nal CE # LOW cycles.
4. CRE must be HIGH to access regi sters.
tCLK
tKW
tSP tHD
tABA
tCSP
tKW
tCBPH3
HiZ
tSP
tAS
tAS
tHD
CRE4
tSP
tHD
Select
Control
Register
Don’t
Care CR
valid
tACLK tKOH
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Software Access Sequence
Software access of the configuration register s uses a sequence of asynchronous READ
and asynchronous WRITE operations. The contents of the co nfiguration registers can be
read or modified using the software sequence.
The configuration registers are loaded using a four-step sequence consisting of two
asynchronous READ operations followed by two asynchronous WRITE operations (see
Figure 11). The re a d sequence is vir tua lly id enti cal except that an a synchronou s R EA D is
performe d during the fourth ope ra tion (se e Fig ure 10). The a dd re ss used duri ng al l
READ and WRITE operations is the highest address of the CellularRAM device being
accessed (3FFFFFh); the contents of t his address are not changed by using thi s sequence.
The data value prese nte d dur ing the thir d ope ra ti on (WRITE ) in the se quence
defines whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence
will a ccess the RCR; if the data is 0001h, the sequence will access the BCR;
if the data is 0002h, t he sequence will access the DIDR. During the fourth opera tion,
ADQ[15:0] transfer data into or out of bits 15:0 of the control registers.
The use of the software sequence does not affect the ability to perform the standard
(CRE-controlled) method of loading the configuration reg i s ters. How ever, the software
nature of this access mechanism eliminates the need for the control register ena ble
(CRE) pin. If the software mechanism is used, the CRE pin can simply be tied to VSS.
The port line often used for CRE control purposes is no longer required.
Notes : 1. RCR : 0000h , BCR : 0001h , DIDR : 0002h
Figure 10 : Configuration Register Read
MAX
ADDRESS
MAX
ADDRESS
OUTPUT
DATA MAX
ADDRESS
MAX
ADDRESS
OUTPUT
DATA MAX
ADDRESS
MAX
ADDRESS
MAX
ADDRESS
MAX
ADDRESS
CR
VALUE OUT
*Note1
Read Read Write Read
OE#
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WE#
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Figure 11 : Configuration Register Write
Notes : 1. RCR : 0000h , BCR : 0001h
MAX
ADDRESS
MAX
ADDRESS
OUTPUT
DATA MAX
ADDRESS
MAX
ADDRESS
OUTPUT
DATA MAX
ADDRESS
MAX
ADDRESS
MAX
ADDRESS
MAX
ADDRESS
CR
VALUE IN
*Note1
OE#
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WE#
Read Read Write Write
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Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus.
Table 3 describes the control bits in the BCR. At power-up, the BCR is set to 1D1Fh.
The BCR is accessed using CRE and A[19:18] = 10b, or through the configuration
regis ter softw are sequence with ADQ[15:0] = 0001h on the third cycle.
Bit Num ber Definition Remark
21-20 Reserved Mu st be set to “0”
19 –18 Register S elec t 00 = Select RCR
01 = Select DIDR
10 = Select BCR
17 –16 Reserved Must be set to “0”
15 Operatin g mode 0 = Synchronous burst access mode (default)
1 = Asynchronous access mode
14 Initial Latency 0 = Variable (default)
1 = Fixed
13 –11 Latency Count
000 = 9 clock cycles
001 = reserved
010 = 3 clock cycles
011 = 4 clock cycles (default)
100 = 5 clock cycles
101 = 6 clock cycles
110 = 7 clock cycles
111 = reserved
10 WAIT Polarity 0 = Active LOW : Data valid at WAIT HIGH
1 = Active HIGH : Data valid at WAIT LOW (default)
9Reserved Mu st be set to “0”
8WAIT Configuration 0 = Asserted during delay
1 = A sserted one data cyc le befo re delay (def ault)
7 –6 Reserved Mu st be set to “0”
5 –4 Output Impedance
00 = Full drive
01 = ½ Drive (default)
10 = ¼ Drive
11 = Reserved
3Burst mode 0 = Burst wrap within the burst length
1 = Burst no wrap (default)
2 – 0 Burst Length
001 = 4 words
010 = 8 words
011 = 16 words
111 = continuous (default )
Others = Reserved
Table 3. Bus configuration Register
Notes : 1.Bu rst wrap an d length appl y to bo t h REA D an d WRIT E operat ions.
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Burst Length (BCR[2:0]) Default = Continuous Burst
Burst leng ths d efine the numbe r of words the device outp uts dur ing bur st R EA D and
WRITE operations. The device supports a burst le ngth of four, eight, or sixteen w ords of
sixteen bits. The device can also be set in continuous b urst mode where data is
accessed sequentially up to the end of the row.
Burst Wrap (BCR[3]) Defau l t = No Wrap
The burst-wrap option determ ines if a 4-, 8-, or 16-word READ or WRITE burst wraps
within the burs t le ngth, or ste ps throug h se que ntia l a ddr ess es i f continuous bur st
operation is selected in BCR[2:0]. If the wrap option is not enabled, the device accesses
data from sequential addresses up to the end of the row.
Table 4. Sequence and B urs t L ength
Starting
Address Wrap BL4 BL8 BL16 Continuous
DEC BCR[3] Linear Linear Linear Linear
0
“0”
Wrap
0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3- ••• -12-13-14-15 0-1-2-3-4-5-6- •••
1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4- ••• -13-14-15-0 1-2-3-4-5-6-7- •••
2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5- ••• -14-15-0-1 2-3-4-5-6-7-8- •••
3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6- ••• -15-0-1-2 3-4-5-6-7-8-9- •••
••• ••• ••• ••• •••
6 6-7-4-5 6-7-0-1-2-3-4-5 6-7-8-9- ••• -2-3-4-5 6-7-8-9-10-11-12-•••
7 7-4-5-6 7-0-1-2-3-4-5-6 7-8-9-10-••• -3-4-5-6 7-8-9-10-11-12-13-•••
••• ••• ••• ••• •••
14 14-15-12-13 14-15-8-9-10-11-12-13 14-15-0-1- ••• -10-11-12-13 14-15-16-17-18-19-20-•••
15 15-12-13-14 15-8-9-10-11-12-13-14 15-0-1-2-3- ••• -11-13-13-14 15-16-17-18-19-20-21-•••
••• ••• ••• ••• •••
254 254-255-252-253 254-255-248-249-250-251-252-253 254-255-240-241-••• -250-251-252-253 254-255-0-1-2-•••
255 255-252-253-254 255-248-249-250-251-252-253-254 255-240-241-242-••• -251-252-253-254 255-0-1-2-•••
0
“1”
No Wrap
0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4- ••• -12-13-14-15 0-1-2-3-4-5-6- •••
1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4- ••• -13-14-15-16 1-2-3-4-5-6-7- •••
2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5- ••• -14-15-16-17 2-3-4-5-6-7-8- •••
3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6- ••• -15-16-17-18 3-4-5-6-7-8-9- •••
••• ••• ••• ••• •••
6 6-7-8-9 6-7-8-9-10-11-12-13 6-7-8-9- ••• -18-19-20-21 6-7-8-9-10-11-12-•••
7 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-••• -19-20-21-22 7-8-9-10-11-12-13-•••
••• ••• ••• ••• •••
14 14-15-16-17 14-15-16-17-18-19-20-21 14-15-16-17-••• -26-27-28-29 14-15-16-17-18-19-20-•••
15 15-16-17-18 15-16-17-18-19-20-21-22 15-16-17-18-••• -27-28-29-30 15-16-17-18-19-20-21-•••
••• ••• ••• ••• •••
254 254-255 254-255 254-255 254-255
255 255 255 255 255
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Drive Strength ( B CR[5 :4 ] ) Defaul t = Outputs Use Ha lf -Dr ive Strength
The output dri ver s tre ngt h ca n be alte red to full, one-half, or one-quarter strength to
adjust for different data bus loading scenarios. The reduced-strength options are intended
for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory
bus. The reduced-drive-s trength option minimizes the noise genera ted on the dat a bus
during READ operations . Ful l output d rive strength should be selected when using a
discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are
configured at half-drive stre ngt h d uring t es ting. See Table 5.
BCR[5] BCR[4] Drive Strength Impedance Typ (Ω) Use Recommendatio n
0 0 Full 25 ~ 30 CL= 30pF to 50pF
0 1 1/2(Default) 50 CL= 15pF to 30pF
104MHz at light load
1 0 1/4 100 CL= 15pF or lower
1 1 Reserved
Table 5. Drive Strength
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions betwee n the
asserted and the de-asserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during
synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid
on the clock edge immediately after WAIT transitions to the de-asserted or assert ed state
respectively. When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data
bus going valid or invalid (see Figure 12).
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine w hether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserte d state .
ADQ0-
ADQ15
WAIT
CLK
WAIT
VALID
OUTPUT
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
BCR[8]=0
Data valid/invalid in curre nt cycle
BCR[8]=1
Data valid/invalid in next cyc le
Figure 12. WAIT Confi gura tion D ur ing Bu rs t Opera tion
Notes : Non-default BCR setting : WAIT active LOW
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Latency Counter (BCR[13:11]) Default = Three Clock Latency
The late ncy counter b its det er mine how many clocks occur be tw e en the beginning of a
READ or WRITE operation and the first data value transferred. Latency codes from two
(three clocks) to six (seven clocks) and eight (nine clocks) are supported (see Tables 6
and 7, Figure 13, and Fig ure 14) .
Initi al Access Late ncy (BCR[14]) De fault = Variab le
Variable initial access latency outputs da ta after the number of clocks set by the latency
counter. However, WAIT must be monitored t o detect delays caused by collisions with
refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for
worst-case refres h collis ions. The la te ncy counte r must be configured to match the
initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed
initial latency. The burst be gins after the number of clock cycles configured by the
latency counter. (See Table 6 and Figure 13)
BCR
[13:11]
Latency
Configuration
Code
Latency Max Input CLK Frequency (MHz)
Normal Refresh
Collision -96 -12
010 2 (3 cloc ks) 2 4 66 (15.0ns) 52 (18.5ns)
011 3 (4 cloc ks)-default 3 6 104 (9.62ns) 80 (12.5ns)
100 4 (5 cloc ks) 4 8
others Reserved - - - -
Table 6. Variable L a tency Confi gura tion Codes (BCR[ 14 ] = 0)
Notes: 1. Latency is th e nu m ber o f clock cyc les f r o m the in i ti ali zat ion of a bur st operatio n u n t i l data appear s.
Data is transferred on the next clock c ycle. READ latency can range from the normal latency to the value
shown for refresh collision.
ADQ0-
ADQ15
ADV#
CLK
VALID
OUTPUT
VALID
ADDRESS VALID
OUTPUT
VALID
OUTPUT VALID
OUTPUT
ADQ0-
ADQ15 VALID
ADDRESS VALID
OUTPUT
VALID
OUTPUT VALID
OUTPUT
ADQ0-
ADQ15 VALID
ADDRESS VALID
OUTPUT VALID
OUTPUT
Code 2 (3 clocks)
Code 3 (4 clocks) : Default
Code 4 (5 clocks)
Figure 13. Latency Counter (Variable L atency , No Refresh Collis ion)
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BCR
[13:11]
Latency
Configuration
Code
Latency
Count (N) Max Input CLK Frequency (MHz)
-96 -12
010 2 (3 cloc ks) 233 (30ns) 25 (40ns)
011 3 (4 cloc ks)-default 352 (19.2ns) 40 (25ns)
100 4 (5 cloc ks) 466 (15.0ns) 52 (19.2ns)
101 5 (6 cloc ks) 575 (13.3ns) 66 (15.0ns)
110 6 (7 cloc ks) 6104 (9.62ns) 80 (12.5ns)
others Reserved - - -
Table 7. Fixed Latency Conf igur ation Codes (B CR[ 14 ] = 1)
Operating Mode (BCR[15]) Default = Synchronous Operation
The operating mode bit enables synchronous burst ope r ation or limits the device to the
asynchronous mode of operation only. If the clock is stopped LOW, all accesses are
asynchronous, e ven w hen synchr o nou s m ode is enabled.
ADV#
CLK
ADQ0-
ADQ15
(READ)
VALID
ADDRESS VALID
OUTPUT
VALID
OUTPUT VALID
OUTPUT
ADQ0-
ADQ15
(WRITE)
VALID
ADDRESS
Figure 14. Latency Counter (Fixed La tenc y)
CE#
VALID
INPUT
VALID
INPUT VALID
INPUT
tAA
tCO
tAADV
Burst I de ntifie d
(ADV#=LOW)
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Refresh Configur ation Register
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatica lly reduce
current consumption during standby mode. Table 8 describes the control bits used in
the RCR.
The R CR is accessed using CRE and A[19:18] = 00b, or through the configuration
register software access sequence with ADQ = 0000h on the third cycle (see “Registers”)
Bit Num ber Definition Remark
21-20 Reserved Mu st be set to “0”
19 –18 Register Sel ect 00 = Select RCR
01 = Select DIDR
10 = Select BCR
17 – 7 Reserved Mu st be set to “0”
6 – 5 Reserved Setting is ignored
4DPD 0 = DPD enable
1 = DPD disable (default)
3Reserved Mu st be set to “0”
2 – 0 Partial R ef r esh
000 = Full array (default)
001 = Bottom 1/2 array
010 = Bottom 1/4 array
011 = Bottom 1/8 array
100 = None of array
101 = Top 1/2 array
110 = Top 1/4 array
111 = Top 1/8 array
Table 8. Refresh Configuration Register
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Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part of the
memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these
partitions can start at either the beginning or the end of the address map (see Tables 9)
RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density
0 0 0 Full 000000h ~ 3FFFFFh 4MX16 64Mb
0 0 1 Bottom 1/2 array 000000h ~ 1FFFFFh 2MX16 32Mb
0 1 0 Bottom 1/4 array 000000h ~ 0FFFFFh 1MX16 16Mb
0 1 1 Bottom 1/8 array 000000h ~ 07FFFFh 512KX16 8Mb
1 0 0 None of array 00Mb
1 0 1 Top 1/2 array 200000h ~ 3FFFFFh 2MX16 32Mb
1 1 0 Top 1/4 array 300000h ~ 3FFFFFh 1MX16 16Mb
1 1 1 Top 1/8 array 380000h ~ 3FFFFFh 512KX16 8Mb
Table 9. 64Mb A ddres s P a tterns for PA R ( RCR[ 4] = 1)
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150μs to perform an initialization
procedure before normal operations can resume.
Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. Taking CE# LOW
disables DPD and sets RCR[ 4] = 1; it is not necessary to write to the R C R to disable DPD. DPD
can be enabled using CRE or the software sequence to access the RCR. BCR and RCR
values (o ther than BCR[4]) are preserve d during DPD.
Device Identific a tion Register
The DIDR provides informa ti on on the devi ce m anufact ure r, Ce llula rR AM gene ra tio n,
and the specific device configuration. Table 10 describes the bit fields in the DIDR. This
register is read-only.
The DIDR is accessed w ith CRE HIGH and A[19:18] = 01b, or through the s oftware access
sequence wit h ADQ = 0002h on the third cycle.
Bit Field DIDR[15] DIDR[14:11] DIDR[10:8] DIDR[7:5] DIDR[4:0]
Field Name Row Length Devic e V er si o n Devic e D en si ty CellularRAM
Generation Vendor ID
Length
-words Bit
Setting Version Bit
Setting Density Bit
Setting Genera
tion Bit
Setting Vendor Bit
Setting
128 0b 1st 0000b 64Mb 010b CR1.5 010b ISSI 00101b
256 1b 2nd 0001b 128Mb 011b CR2.0 011b
Table 10. Devic e Identification Register Mapping
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Electrical Characteristics
Parameter Rating
Voltage to Any Ball Except VDD, VDDQ Relative to VSS -0.3V to VDDQ + 0.3V
Voltage on VDD Supply Relative to VSS -0.2V to + 2.45V
Volta ge on VDDQ Supply R el at ive to VSS -0.2V to + 2.45V
Storage T emperatu re (plastic) -55°Cto + 150°C
Operating Temperature (case) -40°Cto + 85°C
Soldering Temperature and Time : 10s (solde r ball only) + 260°C
Table 11. Absolute Maximum Ratings
Notes: Stresses gr eat er th an t h o se l ist ed m ay cause per m an en t damage to t h e device. T h is i s a
stress ratin g only, and func tion al operation o f the device at these or any other
conditions above those indicated in this specification is not implied. Exposure to
absolut e maximum rating con ditio ns for extended perio ds may aff ect reliabilit y.
Description Conditions Symbol MIN MAX Unit Note
Supply V o l tage VDD 1.7 1.95 V
I/O Supply Voltage VDDQ 1.7 1.95 V
Input High Voltage VIH VDDQ-0.4 VDDQ+0.2 V 1
Input Low Voltage VIL -0.20 0.4 V 2
Output High Voltage IOH = -0.2mA VOH 0.80 VDDQ V 3
Output Low Voltage IOL = +0.2mA VOL 0.20 VDDQ V 3
Input Leakage Current VIN = 0 to VDDQ ILI 1uA
Output Leakage Current OE#=VIH or
Chip Di sabled ILO 1uA
Operatin g Current Conditions Symbol TYP MAX Unit Note
Asynchronous Rand om
READ/WRITE
VIN = VDDQ or 0V
Chip enabled,
IOUT = 0
IDD1 -70 25 mA 4
Initial Access, Burst
READ/WRITE IDD2 104Mhz 35 mA 4
80Mhz 30
Continuous Burs t READ IDD3R 104Mhz 30 mA 4
80Mhz 25
Continuous Burs t WRITE IDD3W 104Mhz 35 mA 4
80Mhz 30
Standby C urren t VIN=VDDQ or 0V
CE#=VDDQ ISB 150 uA 5
Table 12. Electrical Charac teristics and Operating Conditions
Industrial Temperature (–40ºC < TC < +85ºC)
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Notes: 1. Input sign al s may o ver sh o ot to V D D Q + 1.0 V fo r periods less than 2n s duri n g t r an sit i o n s.
2. Input sign al s may u n der sh o o t to Vss –1. 0 V for per io ds less t h an 2 n s dur i n g tr an si ti o n s.
3. BCR[5:4] = 01b (default setting of one-half drive strengt h ) .
4. This paramet er is specified wi t h the ou t pu t s disabl ed to avo i d ex ter n al lo adi n g eff ects.
User mu st add requir ed c u rr en t to dr ive o u tpu t capacitanc e expect ed in th e actual syst em.
5. ISB (MAX) values measu red w ith PAR set to FULL ARR AY at +85°C . In order to achieve low
standby cu r ren t , al l inpu t s mu st be dr iv en t o eit h er V D D Q o r V S S . ISB might be set sl igh t ly
higher f o r u p t o 5 00 m s after po w er -up, or when entering st andby mode.
Description Conditions Symbol TYP MAX Unit
Deep Pow er-Down VIN=VDDQ or 0V
VDD,VDDQ=1.95V, +85°CIDPD 310 uA
Table 13. Deep Power-Down S pecific ations
Description Conditions Symbol MIN MAX Unit Note
Input Capacitance TC=+25°C;
f=1Mhz;
VIN=0V
CIN 2.0 6.0 pF 1
Input/Output Capacitance (ADQ) CIO 3.0 6.5 pF 1
Table 14. C apacitance
Notes: Typical (TYP) IDPD val ue applies ac ro ss all operating tem peratu res an d volt ages.
Notes: 1. These parameters ar e ver ified in device ch arac teri zatio n and are no t 100% tested.
VDDQ/23Output
Figure 15. AC Input/Output Reference Waveform
Test Points
∫∫
∫∫
VDDQ/22Output
VDDQ
VSS
Notes: 1. AC test inputs are driven at V DDQ for a logic 1 and VSS for a logic 0. Input rise and fal l times
(10% to 90%) < 1.6ns.
2. Input timin g begins at VDDQ/ 2.
3. Ou tput timing ends at VDDQ/2.
DUT
30pF
50Ω
VDDQ/2
Test Point
Figure 16. Output Load Circuit
Notes: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).
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Table15 . Asyn chr onous REA D Cyc le T iming Requireme nts
Symbol Parameter -70 Unit Notes
Min Max
tAA Address Acess Time 70 ns
tAADV ADV# Access Time 70 ns
tAVH Address hold from ADV# HIGH 2ns
tAVS Address setup to ADV# HIGH 5ns
tBA UB#, LB# Access Ti me 70 ns 1
tBHZ UB#, LB# Disable to High-Z Output 7
tCPH CE# HIGH between Subsequent Asynchronous cycles 5ns
tCO Chip Select Access Time 70 ns
tCVP CE# low to ADV# HIGH 7ns
tHZ Chip Disable to High-Z Output 7 1
tOE OE# low to Valid Output 20 ns
tOEW OE# low to WAIT Valid 17.5
tOHZ OE# high to High-Z Out put 7ns 1
tOLZ OE# low to Low-Z output 3ns 2
tVP ADV# Low pulse width 7ns
tWZ CE# high to WAIT High-Z 7 ns 1
AC Chara cteristics
Notes: 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 23. The High-Z timin gs
measure a 100mV transition from either VOH or VOL toward VDDQ/ 2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 23. The Low-Z timings
measure a 10 0mV transition away fro m the High-Z (V D D Q / 2 ) level t o w a rd ei th er VOH o r VOL.
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Table16 . Burst REA D Cycle Timing Requirements
Symbol Parameter -7010 -7008 Unit Note
Min Max Min Max
tAA Address Acess Time (Fixed Latency) 70 70 ns
tAADV ADV# Access Time (Fixed Latency) 70 70 ns
tABA Burst to READ Access Time
(Variable Latency) 35.9 46.5 ns
tACLK CLK to Output Delay 7 9 ns 1
tCBPH CE# High between Subsequent
Burst or Mixed-Mode Opera tions 5 6 ns 2
tCEM Maximum CE# Pulse width 4 4 us 2
tCLK CLK Period 9.62 12.5 ns
tCO Chip Select Access Time (Fixed
Latency) 70 70 ns
tCSP CE# Setup Time to Active CLK Edge 3 4 ns
tHD Hold Time from Active CLK Edge 2 2 ns
tHZ Chip Disable to High-Z Output 7 7 ns 3
tKH/tKL CLK HIGH or LOW Time 3 4 ns
tKOH Output Hold from CLK 2 2 ns
tKW CLK to WAIT Valid 7 9 ns 1
tOE Burst OE# LOW to Output Valid 20 20 ns
tOHZ OE# high to High-Z Out put 7 7 ns 4
tOLZ OE# low to Low-Z output 3 3 ns 4
tSP Setup time to Active CLK Edge 3 3 ns
tTCLK Rise or Fall Time 1.6 1.8 ns
tWZ CE# high to WAIT High-Z 7 7 ns 3
Notes: 1. A refresh oppor tun ity mu st be provided every tCEM by taking CE# HIGH .
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 16.
The Hi gh -Z timings meas ure a 100mV transiti on from either VOH or VOL toward VDDQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 16.
The Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level towar d
either VOH or VOL.
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Table17 . Asyn chr onous WRIT E Cy cl e Timi ng Requirem ents
Symbol Parameter -70 Unit Notes
Min Max
tAS Address and ADV# LOW Setup Time 0ns
tAVH Address hold from ADV# HIGH 2ns
tAVS Address setup to ADV# HIGH 5ns
tAW Address Valid to End of Write 70 ns
tBW UB#, LB# Select to End of Write 70 ns
tCPH CE# HIGH between Subsequent Asynchronous cycles 5ns
tCVP CE# low to ADV# HIGH 7ns
tCW Chip Enable to End of Write 70
tDH Data Hold from Write Time 0ns
tDS Data Write Setup Time 20
tVP ADV# Low pulse width 7ns
tVS ADV# Setup to End of Write 70 ns
tWHZ WRITE to ADQ High-Z Output 7ns
tWP WRITE Pulse Width 45 ns 1
tWR WRITE Recovery Time 0ns
tWZ CE# high to WAIT High-Z 7 ns 2
Notes:
1. WE# must not remain LOW longer than 4μs (tCEM) while the device is selected (CE# LOW).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 16.
The Hi gh -Z timings meas ure a 100mV transiti on from either VOH or VOL toward VDDQ/2.
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Table18 . Burst WRIT E Cy c le Ti ming Requiremen ts
Symbol Parameter -7010 -7008 Unit Note
Min Max Min Max
tAS Address and ADV# LOW Setup
Time 0 0 ns 1
tCBPH CE# High between Subsequent
Burst or Mixed-Mode Opera tions 5 6 ns 2
tCEM Maximum CE# Pulse width 4 4 us 2
tCLK CLK Period 9.62 12.5 ns
tCSP CE# Setup Time to Active CLK
Edge 3 4 ns
tHD Hold Time from Active CLK Edge 2 2 ns
tKH/tKL CLK HIGH or LOW Time 3 4 ns
tKW CLK to WAIT Valid 7 9 ns 3
tSP Setup time to Active CLK Edge 3 3 ns
tTCLK Rise or Fall Time 1.6 1.8 ns
tWZ CE# high to WAIT High-Z 7 7 ns 4
Notes: 1. tAS required if tCSP > 20ns.
2. A r efresh oppo rtu nity m ust be provided ever y tCEM by taking CE# H IGH.
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 16.
The Hi gh -Z timings meas ure a 100mV transiti on from either VOH or VOL toward VDDQ/2.
Symbol Parameter -70 Unit Notes
Min Max
tDPD Time from DPD entry to DPD exit 150 us
tDPDX CE# LOW time to exit DPD 70 ns
tPU Initialization Period (required before normal operations) 150 us
Table19 . Initialization and DPD Timing Requirements
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Timing Di agrams
Figure 17: Power-Up Initializ ation Timing
VDD, VDDQ=1.7V
Device Initialization
tPU > 150us Device ready for
normal operation
VDD(MIN)
CE#
tDPD tDPDX tPU
Write
RCR[4]=0 DPD Enabled DPD Exit Device Initializ ation Device ready for
normal operation
Figure 18: DPD Entry and Exit Timing Parameters
Figure 19: Asynchronous READ
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
OE#
WE# HiZ HiZ
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
tCO
tAADV
tOE
tHZ
tCVP
tOLZ
tBA
tAA
tBHZ
tOHZ
tOEW
tWZ
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Figure21: Single Acc es s Burs t READ O pera tion –Varia ble La tenc y w ithout ref res h coll is ion
tCLK
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
HiZ
VALID
ADDRESS
tKW
tSP
VALID
ADDRESS VALID
OUTPUT
tHD
tSP tHD tKOH
tACLK
tCEM
tCSP tHD
tSP tHD
tOE
tKW
tOHZ
Read Burst Identified (WE#=HIGH)
tABA
Notes: 1. Non-default variabl e lat enc y BCR settings for singl e-access bu rst R EAD operation : Latenc y
code two (three clocks); WAIT active LOW; WAIT asserted during delay.
tOLZ
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Figure 22: Four-Word Burs t READ Oper ation –V ar ia ble La tency w ithout ref res h coll is ion
Notes: 1. Non-default variabl e lat enc y BCR settings for 4-word burst READ operation: Latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
Read Burst Identified (WE#=HIGH)
tCLK
VALID
ADDRESS
VALID
ADDRESS
tSP tHD
tSP tHD tKOH
tACLK
tCEM
tCSP
tHD
tSP tHD
tOE
tOLZ
tKW
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tCBPH
tHZ
tABA
tWZ
HiZ
tKW
tOHZ
tSP tHD
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Figure 23: Four-Word Burst REA D O pera tion –Var iable Latency with refresh collision
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WE#
CLK
Read Burst Identified (WE#=HIGH)
tCLK
VALID
ADDRESS
VALID
ADDRESS
tSP tHD
tSP tHD tKOH
tACLK
tCEM
tCSP
tHD
tSP tHD
tOE
tOLZ
tKW
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tCBPH
tHZ
WAIT
OE#
tKW
HiZ
tSP tHD tWZ
Notes: 1. Non-default variabl e lat enc y BCR settings for 4-word burst READ operation: Latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. If refresh c olli sion happen ed, W AIT will be asserted betw een t he latenc y co unt number of cloc k cycl es
and 2x the latency count
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Figure 24: Single Access Burst READ Operation –Fixed L atenc y
tCLK
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
VALID
ADDRESS
tKW
VALID
ADDRESS
tSP tHD
tSP tHD tKOH
tCEM
tCSP
tHD
tHD
tOE
tOLZ
tKW
Read Burst Identified (WE#=HIGH)
VALID
OUTPUT
tAA
tWZ
HiZ
tCO
tAADV
tHZ
tSP
tOHZ
Notes: 1. Non-default fixed l atenc y BCR settings for single-acc ess burst REA D operation : Fixed Laten cy;
Latency code fo u r (fi ve cloc ks); WAIT ac t iv e LOW; WA I T asserted during delay.
tSP tHD
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Figure 25: Four-Word Burst REA D O pera tion –Fixed L a tency
tCLK
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
VALID
ADDRESS
tKW
VALID
ADDRESS
tSP tHD tKOH
tCEM
tCSP
tHD
tSP tHD
tOE
tOLZ
tKW
Read Burst Identified (WE#=HIGH)
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tCBPH
tHZ
tAA
tWZ
HiZ
tAADV
tCO
tSP tHD
tSP tHD
Notes: 1. Non-default fixed l atenc y BCR settings for 4-word burst READ operation: Fixed latency;
latenc y c ode two (th r ee cloc ks) ; WAIT act ive LO W ; WAI T asserted during delay.
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Figure 26: READ Burs t S us pend
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
VALID
ADDRESS
tKW
VALID
ADDRESS
tSP tHD tKOH
tCEM
tCSP
tHD
tSP tHD
tOE
tOLZ
tKW
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
HiZ
tAADV
tCO
tSP tHD
tSP tHD
Notes: 1. Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. CLK can be st o pped LOW or H I G H , bu t mu st be st at ic, wi th no LOW-to-HIGH transitions
during bu r st su spen d.
3. OE# can stay LOW during BURST SUSPEND. If OE# is LOW, ADQ[15:0] will continue to
output valid data.
tHD
tHD
VALID
OUTPUT VALID
OUTPUT
tCBPH
tHZ
tWZ
Note2
Note3
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Figure 27: Burst READ a t End of Row (Wrap Off )
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
tCLK
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VIL
VIL
VIL
tKW
VIH
NOTE2
VIH tHZ
tHZ
End of Row (A[7:0]=F Fh )
Notes: 1. Non-default BCR settings fo r burst RE AD at end of row: fixed or variable la tenc y; WAI T
active LO W ; WAIT asserted during delay.
2. For bu r st READs, C E# must go HIG H befor e t h e th i r d CLK af t er the W A I T perio d begi n s
(befo re the t h ir d CL K af t er W A I T asserts w it h BCR [ 8 ] = 0, o r bef o r e t h e f o u r th CLK af t er
WAIT asserts with BCR[8] = 1).
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Figure 28: Asynchronous WRITE
NOTE2
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT3#
WE#
HiZ HiZ
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
DATA
tCW
tVS
tWP
tBW
tCVP
tDS tDH
Notes: 1. The end o f t h e W RITE cycle is co n t r o ll ed by CE # , UB#, LB#, or W E#, which ever de-asserts f irst.
2. WE# must not remain LOW longer than 4μs (tCEM) while the device is selected (CE# LOW).
3. During asynchronous WRITE cycles, WAIT will be High-Z while WE# is LOW or OE# is HIGH.
tAS
tAS
tAW
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Figure 29: Four-Word Burst WRIT E Oper ation –Variable Latency
Write Burst Identified (WE#=LOW)
Notes: 1. Non-default BCR settings for burst WRITE operation, with fixed-length bur st o f 4 , burst wrap enabled:
Variable latency; laten cy co de two (thr ee cloc ks); WAIT ac t iv e LOW; WA I T asserted during dela y.
2. WAIT assert s for LC c yc l es f o r both f ix ed and var ia ble latenc y. LC = laten c y co de ( BC R [13: 1 1 ] ) .
3. tAS required if tCSP > 20ns.
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
CLK
NOTE3
tCLK
VALID
ADDRESS
tKW
VALID
ADDRESS
tSP tHD tHD
tCEM
tCSP
tHD
tSP tHD
tKW
DATA IN DATA INDATA INDATA IN
tCBPH
HiZ
tSP
tHD
tSP
tAS
tAS
tHD
NOTE2
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Figure 30: Four-Word Burst WRIT E Oper ation –Fi xed L atenc y
tCLK
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
CLK
VALID
ADDRESS
tKW
VALID
ADDRESS
tAVH
tSP tHD tHD
tCEM
tCSP
tHD
tSP tHD
tKW
Write Burst Identified (WE#=LOW)
DATA IN DATA INDATA INDATA IN
tCBPH
HiZ
tSP
tHD
tSP
tAS
tAS
NOTE3
Notes: 1. Non-default BCR settings for burst WRITE operation, with fixed-length bur st o f 4 , burst wrap enabled:
Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT assert s for LC c yc l es f o r both f ix ed and var ia ble latenc y. LC = laten c y co de ( BC R [13: 1 1 ] ) .
3. tAS required if tCSP > 20ns.
tHD
NOTE2
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Figure 31: Continuous Burst WRITE at End-of-Row (Wrap Off)
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
tCLK
VALID
INPUT
VALID
INPUT
VALID
INPUT
VIL
VIH
tKW
VIH
NOTE2
VIH tHZ
tHZ
End of Row (A[7:0]=F Fh )
Notes: 1. Non-default B CR settings for burst WRIT E at en d o f r o w: fixed o r var i able lat en c y ; W A I T
active LO W ; WAIT asserted during delay.
2. For bu r st W RITE s, CE # must go HIGH before the th i rd C LK af ter t h e W A I T per io d begins
(befo re the t h ir d CL K af t er W A I T asserts w it h BCR [ 8 ] = 0, o r bef o r e t h e f o u r th CLK af t er
WAIT asserts with BCR[8] = 1).
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VALID
ADDRESS
VALID
ADDRESS
tSP tHD tKOH
tACLK
tCEM
tHD
tOE
tOLZ
tKW
VALID
OUTPUT VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tABA
tWZ
HiZ tKW
tOHZ
Figure 32: Burst WRITE f oll owed by Burst REA D
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
Notes: 1. Non-default BCR settings fo r burst WR IT E follow ed by burst READ ; latency code t wo ( thr ee c lo cks) ;
WAIT active LOW; WAIT asserted during delay.
2. A r efresh oppo rtu nity m ust be provided ever y tC EM by taking CE# HIGH.
tCLK
VALID
ADDRESS
tKW
VALID
ADDRESS
tSP tHD tHD
tCEM
tCSP
tSP
tKW
DATA INDATA INDATA INDATA IN
tCBPH
HiZ
tSP
tHD
tSP
tAS
tAS
tHD
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Figure 33: Async hron ous WRITE follow ed by B urs t READ
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
CLK
tCLK
VALID
ADDRESS
tSP
VALID
ADDRESS VALID
OUTPUT
tHD
tSP tHD tKOH
tACLK
tCSP tHD
tSP tHD
tOE
tOLZ
tKW
tWZ
tCBPH
NOTE2
HiZ
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
DATA
tCW
tVS
tWP
tBW
tCSP
tDS tDH
tAW
tWR
Notes: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency;
latenc y c ode two (th r ee cloc ks) ; WAIT act ive LO W ; WAI T asserted during delay.
2. When transitioning between asynchronous WRITE and variable-latency burst READ operations,
CE# must go HIGH. CE# can stay LOW wh en transitioning to fixed-latency bu r st R E AD s.
A refresh opportunity must be provided every tCEM by taking CE# HIGH.
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Figure 34: Async hron ous WRITE f oll owed by A s yn ch ronous REA D
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
HiZ
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
DATA
tCW
tVS
tWP
tBW
tCVP
tDS tDH
HiZ
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
tCO
tAADV
tOE
tBA
tOEW
tHZ
tCPP
tOLZ
tCPH
Notes: 1. CE# can stay L OW when tran sit ioning bet w een asynch r o n ous operations. I f C E# goes HI G H ,
it must remai n H I G H f o r at l east t CP H t o sch edu l e t h e appropriate intern al r ef r esh o per at ion.
Otherw i se, t CP H is o n l y r equ ir ed aft er C E # -controlled WRITEs.
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Figure 35: Async hron ous READ followed by WRITE at the S am e A ddres s
Address
ADQ0-
ADQ15
ADV#
CE#
UB#/LB#
WAIT
WE#
OE#
HiZ
tVP
tAVS tAVH
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
tCO
tAADV
tWP
tBA
tCVP
tDS tDH
HiZ
VALID
INPUT
tOE
tWZ
Notes: 1. The end o f t h e W RITE cycle is co n t r o ll ed by CE # , UB#, LB#, or W E#, which ever de-asserts f irst.
2. WE# must not remain LOW longer than 4μs (tCEM) while the device is selected (CE# LOW).
tAA
tOLZ
tOEW
