STK20C04-WF25I - Simtek Corporation

March 2006 1 Document Control # ML0001 rev 0.2

STK20C04

512 x 8 nvSRAM

QuantumTrap™ CMOS

Nonvolatile Static RAM

Obsolete - Not Recommend for new Designs

DESCRIPTION

The Simtek STK20C04 is a fast static RAM with a non-

volatile element incorporated in each static memory

cell. The SRAM can be read and written an unlimited

number of times, while independent nonvolatile data

resides in nonvolatile elements. Data may easily be

transferred from the SRAM to the Nonvolatile Elements

(the STORE operation), or from the Nonvolatile Ele-

ments to the SRAM (the RECALL operation), using the

NE pin. Transfers from the Nonvolatile Elements to the

SRAM (the RECALL operation) also take place auto-

matically on restoration of power. The STK20C04

combines the high performance and ease of use of a

fast SRAM with nonvolatile data integrity.

The STK20C04 features industry-standard pinout for

nonvolatile RAMs in a 28-pin 600 mil plastic DIP.

BLOCK DIAGRAM

Quantum Trap

16 x 2 56

STORE

RECALL

CO L UMN I/O

COLU MN D E C

STATIC RAM

ARRAY

16 x 256

ROW DECODER

INPUT BUFFERS

STORE/

RECALL

CONTROL

PIN NAMES

A0 - A8Address Inputs

WWrite Enabl e

DQ0 - DQ7Data In/Out

EChip Enab le

GOutput Enable

NE Nonvolatile Enable

VCC Power (+ 5V)

VSS Ground

PIN CONFIGURATIONS

DQ0

DQ1

DQ2

VSS

VCC

DQ7

DQ6

DQ5

DQ4

DQ328 - 600 PDIP

FEATURES

• 25ns, 35ns and 45ns Access Times

•STORE to Nonvolatile Elements Initiated by

Hardware

•RECALL to SRAM Initiated by Hardware or

Power Restore

• Automatic STORE Timing

• 10mA Typical ICC at 200ns Cycle Time

• Unlimited READ, WRITE and RECALL Cycles

• 1,000,000 STORE Cycles to Nonvolatile Ele-

ments

• 100-Year Data Retention over Full Industrial

Temperature Range

• Commercial and Industrial Temperatures

STK20C04

March 2006 2 Document Control # ML0001 rev 0.2

ABSOLUTE MAXIMUM RATINGSa

Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V

Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)

Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)

Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W

DC Output Current (1 output at a time, 1s duration). . . . . . . .15mA

DC CHARACTERISTIC S (VCC = 5.0V ± 10%)

Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

Note c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE) .

Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

AC TEST CONDITIONS

CAPACITANCEe(TA = 25°C, f = 1.0MHz)

Note e: These parameters are guaranteed but not tested.

SYMBOL PARAMETER COMMERCIAL INDUSTRIAL UNITS NOTES

MIN MAX MIN MAX

ICC1bAverag e V CC Current 85

tAVAV = 25ns

tAVAV = 35ns

tAVAV = 45ns

ICC2cAverag e V CC Current during STORE 3 3 mA All Inpu ts Don’t Ca re, VCC = max

ICC3bAverag e V CC Current at tAVAV = 200ns

5V, 25 °C, Typical 10 10 mA W ≥ (VCC – 0.2V)

All Others Cycling, CMOS Levels

ISB1dAverage VCC Current

(S tandby, Cycling TTL Input Levels) 25

tAVAV = 25ns, E ≥ VIH

tAVAV = 35ns, E ≥ VIH

tAVAV = 45ns, E ≥ VIH

ISB2dVCC Standby Current

(Standby, Stable CMOS In put Levels ) 750 750 μAE ≥ (VCC – 0.2V)

All Other s VIN ≤ 0.2V or ≥ (VCC – 0. 2V )

IILK Input Leakage Cur rent ±1±1μAVCC = max

VIN = VSS to VCC

IOLK Off-State Output Leakage Current ±5±5μAVCC = max

VIN = VSS to VCC, E or G ≥ VIH

VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 VAll Inputs

VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 VAll Inputs

VOH Output Logic “1” V oltage 2.4 2.4 V IOUT = –4mA

VOL Output Logic “0” V oltage 0.4 0.4 V IOUT = 8mA

TAOperating Temperat ur e 070 –40 85 °C

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1

SYMBOL PARAMETER MAX UNITS CONDITIONS

CIN Input Ca pacit ance 8pF ΔV = 0 to 3V

COUT Output Capacitance 7pF ΔV = 0 to 3V

Figure 1: AC Output Loading

480 Ohms

30 pF

255 Ohms

5.0V

INCLUDING

OUTPUT

SCOPE AND

FIXTURE

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at condi-

tions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect reliability.

STK20C04
March 2006 3 Document Control # ML0001 rev 0.2
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E, G < VIL, W > VIH , and NE ≥ VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
SRAM READ CYCLE #2: E Controlledf
NO.
SYMBOLS PARAMETER STK20C04-25 STK20C04-35 STK20C04-45 UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX
1 tELQV tACS Chip Enable Access Time 25 35 45 ns
2 tAVAVftRC Read Cycle Time 25 35 45 ns
3 tAVQVgtAA Address Access Ti me 25 35 45 ns
4 tGLQV tOE Output Enable to Data Valid 10 15 20 ns
5 tAXQXgtOH Output Hold after Address Change 5 5 5 ns
6 tELQX tLZ Chip Enable to Output Active 5 5 5 ns
7 tEHQZhtHZ Chip Disable to Output Inactive 10 13 15 ns
8 tGLQX tOLZ Output Enable to Output Active 0 0 0 ns
9 tGHQZhtOHZ Output Di sable to Output Inactive 10 13 15 ns
10 tELICCHetPA Chip Enable to Power Active 0 0 0 ns
11 tEHICCLd, e tPS Chip Disable to Power Stand by 25 35 45 ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DAT A  VALID
8
tGLQX
4
tGLQV
DQ (DATA OUT)
E
ADDRESS
2
tAVAV
G
ICC
ACTIVE
1
tELQV
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ

STK20C04
March 2006  4 Document Control # ML0001 rev 0.2
SRAM WRITE CY C L ES #1 & #2 (VCC = 5.0V ± 10%)
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions. NE ≥ VIH.
SRAM WRITE CYCLE #1: W Controlled j
SRAM WRITE CYCLE #2: E Controlledj
NO. SYMBOLS PARAMETER STK20C04-25 STK20C04-35 STK20C04-45 UNITS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
12 tAVAV tAVAV tWC Write Cy cle Time 25 35 45 ns
13 tWLWH tWLEH tWP Write P u lse Width 20 25 30 ns
14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns
16 tWHDX tEHDX tDH Data Hold after End of  Wri te 0 0 0 ns
17 tAVWH tAVEH tAW Addres s Set-up to End of Write 20 25 30 ns
18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns
19 tWHAX tEHAX tWR Ad dress Hold after End o f Wri te 0 0 0 ns
20 tWLQZh, i tWZ Write Enable to Out put Disable 10 13 15 ns
21 tWHQX tOW Output Active after End of Write 5 5 5 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DAT A  VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA OUT
E
ADDRESS
12
tAVAV
W
DATA IN
13
tWLEH
17
tAVEH
DAT A  VALID
HIGH IMPEDANCE
14
tELEH
18
tAVEL 19
tEHAX
15
tDVEH 16
tEHDX

STK20C04
March 2006 5 Document Control # ML0001 rev 0.2
MODE SELECTION
Note k: An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking tRESTORE.
STORE CYCLES #1 & #2 (VCC = 5.0V ± 10%)
Note l: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V.
Note m: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may  be  used to terminate 
the STORE initiation cycle.
Note n: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated.
STORE CYCLE #1: W Controlledn
STORE CYCLE #2: E Controlle d n
E W G NE MODE POWER
H X X X Not Se l ected Standby
L H L H Read SRAM Active
L L X H Write SRAM Active
L H L L Nonvolatile RECALLkActive
L L H L Nonvolatile STORE ICC2
L
LL
HL
HL
XNo Operation Active
NO. SYMBOLS PARAMETER MIN MAX UNITS
#1 #2 Alt.
22 tWLQXltELQX tSTORE STORE Cycle Time 10 ms
23 tWLNHmtELNH tWC STORE Initiation Cycle Time 20 ns
24 tGHNL Output Disable Set-up to NE Fall 0ns
25 tGHEL Output Disable Set-up to E Fa l l 0ns
26 tNLWL tNLEL NE Set-up 0ns
27 tELWL Chi p E nable Set-up 0ns
28 tWLEL Write Enable  Se t-up 0ns
HIGH IMPEDANCE
NE
G
W
E
DQ (DATA OUT)
24
tGHNL 26
tNLWL 23
tWLNH
27
tELWL 22
tWLQX
NE
G
W
E
DQ (DATA OUT) HIGH IMPEDANCE
26
tNLEL
25
tGHEL
28
tWLEL
23
tELNH
22
tELQX

STK20C04

March 2006 6 Document Control # ML0001 rev 0.2

STORE INHIBIT/POWER-UP RECALL (VCC = 5.0V + 10%)

Note o: tRESTORE starts from the time VCC rises above VSWITCH.

STORE INHIBIT/POWER-UP RECALL

NO. SYMBOLS PARAMETER STK20C04 UNITS NOTES

Standard MIN MAX

29 tRESTORE Power-up RECALL Duration 550 μs o

30 tSTORE STORE Cycle Duration 10 ms

31 VSWITCH Low Voltage Tri gger Level 4.0 4.5 V

32 VRESET Low Voltage Reset Level 3.6 V

SWITCH

RESET

POWER-UP RECALL

DQ (DATA OUT)

STORE INHIBIT

tRESTORE

POWER-UP

RECALL BROWN OUT

STORE INHIB I T

NO RECALL

(VCC DID NOT GO

BELOW VRESET)

BROWN OUT

STORE INHIBIT

NO RECALL

(VCC DID NOT GO

BELOW VRESET)

BROWN OU T

STORE INHIBIT

RECALL WHEN

VCC RETURNS

ABOVE VSWITCH

STK20C04
March 2006 7 Document Control # ML0001 rev 0.2
RECALL CYCLES #1,  #2 & #3 (VCC = 5.0V  ± 10%)
Note p: Measured with W and NE both high, and G and E low.
Note q: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or  E may be used  to terminate 
the RECALL initiation cycle.
Note r: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
RECALL CYCLE #1:  NE Controlledn
RECALL CYCLE #2:  E Contr olledn
RECALL CYCLE #3:  G Controlledn, r
NO. SYMBOLS PARAMETER MIN MAX UNITS
#1 #2 #3
33 tNLQXptELQXR tGLQXR RECALL Cycle Time 20 μs
34 tNLNHqtELNHR tGLNH RECALL In itiation Cy c le Time 20 ns
35 tNLEL tNLGL NE Set-up 0ns
36 tGLNL tGLEL Output Enable Set-up 0ns
37 tWHNL tWHEL tWHGL Write E nable Set-up 0ns
38 tELNL tGLEL tELGL Chip Enable Set- up 0ns
39 tNLQZ NE Fall to  Outputs  In active 20 ns
40 tRESTORE Power-up RECALL Durati on 550 μs
NE
G
W
E
DQ (DA TA OUT) HIGH IMPEDANCE
34
tNLNH
36
tGLNL
37
tWHNL
38
tELNL 39
tNLQZ
33
tNLQX
NE
G
W
E
DQ (DA TA OUT) HIGH IMPEDANCE
35
tNLEL
36
tGLEL
37
tWHEL 34
tELNHR
33
tELQXR
NE
G
W
E
DQ (DA TA OUT) HIGH IMPEDANCE
35
tNLGL
33
tGLQXR
34
tGLNH
37
tWHGL
38
tELGL

STK20C04

March 2006 8 Document Control # ML0001 rev 0.2

STK20C04

March 2006 9 Document Control # ML0001 rev 0.2

The STK20C04 has two modes of operation: SRAM

mode and nonvolatile mode, determined by the

state of the NE pin. When in SRAM mode, the mem-

ory operates as a standard fast static RAM. While in

nonvolatile mode, data is transferred in parallel from

SRAM to Nonvolatile Elements or from Nonvolatile

Elements to SRAM.

NOISE CONSIDERATIONS

Note that the STK20C04 is a high-speed memory

and so must have a high-frequency bypass capaci-

tor of approximately 0.1μF connected between VCC

and VSS, using leads and traces that are as short as

possible. As with all high-speed CMOS ICs, normal

careful routing of power, ground and signals will

help prevent noise problems.

SRAM READ

The STK20C04 performs a READ cycle whenever E

and G are low and NE and W are high. The address

specified on pins A0-8 determines which of the 512

data bytes will be accessed. When the READ is initi-

ated by an address transition, the outputs will be

valid after a delay of tAVQV (READ cycle #1). If the

READ is initiated by E or G, the outputs will be valid

at tELQV or at tGLQV, whichever is later (READ cycle #2 ) .

The data outputs will repeatedly respond to address

changes within the tAVQV access time without the need

for transitions on any control input pins, and will

remain valid until another address change or until E

or G is brought high or W or NE is brought low.

SRAM WRITE

A WRITE cycle is performed whenever E and W are

low and NE is high. The address inputs must be sta-

ble prior to entering the WRITE cycle and must

remain stable until either E or W goes high at the

end of the cycle. The data on pins DQ0-7 will be writ-

ten into the memory if it is valid tDVWH before the end

of a W controlled WRITE or tDVEH before the end of an

E controlled WRITE.

It is recommended that G be kept high during the

entire WRITE cycle to avoid data bus contention on

the comm on I/ O lin es. I f G is le ft low, intern al ci rcui try

will turn off the output buffers tWLQZ after W goes low.

NONVOLATILE STORE

A STORE cycle is performed when NE, E and W and

low and G is high. While any sequence that

achieves this state will initiate a STORE, only W initi-

ation (STORE cycle #1) and E initi ation (STORE cycle

#2) are practical without risking an unintentional

SRAM WRITE that would disturb SRAM data. During a

STORE cycle, previous nonvolatile data is erased

and the SRAM contents are then programmed into

nonvolatile elements. Once a STORE cycle is initi-

ated, further input and output are disabled and the

DQ0-7 pins are tri-stated until the cycle is complete.

If E and G are low and W and NE are high at the end

of the cycle, a READ will be performed and the out-

puts will go active, signaling the end of the STORE.

NONVOLATILE RECALL

A RECALL cycle is performed when E, G and NE are

low and W is high. Like the STORE cycle, RECALL is

initiated when the last of the four clock signals goes

to the RECALL state. Once initiated, the RECALL

cycle will take tNLQX to complete, during which all

inputs are ignored. When the RECALL completes,

any READ or WRITE state on the input pins will take

effect.

Internally, RECALL is a t wo-step procedure. Fi rst, the

SRAM data is cleared, and second, the nonvolatile

information is transferred into the SRAM cells. The

RECALL operation in no way alters the data in the

nonvolatile cells. The nonvolatile data can be

recalled an unlimited number of times.

As with the STORE cycle, a transition must occur on

any one control pin to cause a RECALL, preventing

inadvertent multi-triggering. On power up, once VCC

exceeds 4.25V, a RECALL cycle is automatically ini-

tiated. Due to this automatic RECALL, SRAM opera-

tion cannot commence until tRESTORE after VCC

exceeds 4.25V.

POWER-UP RECALL

During power up, or after any low-power condition

(VCC < 3.0V), an internal RECALL request will be

latched. When VCC once again exceeds 4.25V, a

RECALL cycle will automatically be initiated and will

take tRESTORE to complete.

DEVICE OPERATION

STK20C04

March 2006 10 Document Control # ML0001 rev 0.2

If the STK20C04 is in a WRITE state at the end of

power-up RECALL, the SRAM data will be corrupted.

To help avoid this situation, a 10K Ohm resistor

should be connected either between W and system

VCC or between E and system VCC.

HARDWARE PROTECT

The STK20C04 offers two levels of protection to

suppress inadvertent STORE cycles. If the control

signals (E, G, W and NE) remain in the STORE con-

dition at the end of a STORE cycle, a second

STORE cycle will not be started. The STORE (or

RECALL) will be initiated only after a transition on

any one of these signals to the required state. In

addition to multi-trigger protection, STOREs are

inhibited when VCC is below 4.0V, protecting

against inadvertent STOREs.

LOW AVERAGE ACTIVE POWER

The STK20C04 draws significantly less current

when it is cycled at times longer than 55ns. Figure 2

shows the relationship between ICC and READ cycle

time. Worst-case current consumption is shown for

both CMOS and TTL input levels (commercial tem-

perature range, VCC = 5.5V, 100% duty cycle on

chip enable). Figure 3 shows the same relationship

for WRITE cycles. If the chip enable duty cycle is

less than 100%, only standby current is drawn

when the chip is disabled. The overall average cur-

rent drawn by the STK20C04 depends on the fol-

lowing items: 1) CMOS vs. TTL input levels; 2) the

duty cycle of chip enable; 3) the overall cycle rate

for accesses; 4) the ratio of READs to WRITEs; 5)

the operating temperature; 6) the VCC level; and 7 ) I/

O loading.

Figure 3: ICC (max) Writes

100

50 100 150 200

Cycle T ime (ns)

TTL

CMOS

Average Active Current (mA)

Figure 2: ICC (max) Reads

100

50 100 150 200

Cycle Time (ns)

TTL

CMOS

Average Active Current (mA)

STK20C04

March 2006 11 Documen t Control # ML0001 rev 0.2

ORDERING INFOR MATION

Temperature Range

Blank = Commercial (0 to 70°C)

I = Industrial (–40 to 85°C)

Access Time

25 = 25ns

35 = 35ns

45 = 45ns

Lead Finish

Blank = 85%Sn/15%Pb

F = 100% Sn (Matte Tin)

Package

W = Plastic 28-pin 600 mil DIP

- W F 45 I

STK20C04

Document Revision History

Revision Date Summary

0.0 December 2002 Replaced 30 nsec device with 25 nsec device.

0.1 September 2003 Added lead-free lead fini sh

0.2 February 2006 Marked as Obsol et e, Not recommen ded for new design.