Using the HI5721 Evaluation Module Application Note Introduction May 1995 AN9410.1 mometer encoder converts the incoming 4 bits to 15 control lines to enable the most significant current sources. The HI5721 is a 10-bit 125MHz Digital to Analog Converter. This current out DAC is designed for low glitch and high Spurious Free Dynamic Range operation. This DAC is ideally suited for Signal Reconstruction and DDS (Direct Digital Synthesis) applications due to it's inherent low noise design. Architecture The HI5721 DAC is designed with a split architecture to minimize glitch while maximizing linearity. Figure 1 shows the functional architecture of the device. The 6 least significant bits of the converter are derived by a traditional R/2R network to binaurally weight the 1mA current sources. The upper 4, most significant bits are implemented as segmented or thermometer encoded current sources. The ther- As shown in Figure 2 the thermometer encoder translates the 4 bit binary input data into a decode that enables individual current sources. For example a binary code of 0110 on the data bits D6 thru D9 will enable current sources I1, I2, I3, I4, I5, and I6. The thermometer encoding architecture ensures good linearity without laser trimming. Also, compared to a straight R/2R design, the worst case glitch is greatly reduced since creating the MSB current is the sum of current sources I1 thru I8. Overall glitch is reduced by a factor of 16. This also reduces the theoretical switching skew from current source to current source by using identically sized switches with identical gain, leakage, and transient responses. QUADRATURE LOGIC (LSB) D0 D1 6 LSB'S CURRENT CELLS D2 D3 R/2R NETWORK DATA BUFFER/ LEVEL SHIFTER D4 D5 10-BIT REGISTER D6 D7 15 SWITCHED CURRENT CELLS UPPER 4-BIT DECODER D8 IOUT (MSB) D9 IOUT INVERT CLK REF IN VOLTAGE REFERENCE + REF OUT -AVEE AGND -DVEE DGND RSET 25 CTRL AMP OUT CTRL AMP IN VCC FIGURE 1. BLOCK DIAGRAM 1 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 Application Note 9410 GLITCH AREA = 1/2 (H X W) V I1 BIT 6 I2 BIT 7 I3 HEIGHT (H) t(ps) WIDTH (W) FIGURE 3. GLITCH AREA I4 BIT 8 Input Timing/Logic Levels I5 BIT 9 (MSB) The HI5721 has a maximum clock rate specification of 100MHz. The data setup time before the 50% point of the rising edge of the clock is tS = 1.2ns (MIN) and the hold time is tH = 0.5ns (MIN). Logic levels are 0.8V (MAX) for an input low and 2.0V (MIN) for a logic high. The HI5721 is both TTL and CMOS input compatible. I6 I7 I8 4-BIT BINARY TO THERMOMETER ENCODER I9 D9 - D0 I10 I11 CLK I12 tS tH I13 FIGURE 4. HI5721 DATA TIMING I14 INVERT Control Pin I15 I16 SUMMING JUNCTION (IOUT) FIGURE 2. THERMOMETER ENCODER The INVERT control pin is used to enable the internal quadrature logic on the data bits. The internal quadrature logic feature is used to reduce the amount of memory store in a given Numerically Controlled Oscillator (NCO). The NCO need only store one quadrant of the sine wave data and use the invert pin to create the remaining 3 quadrants of the sine wave. Designing to Minimize Glitch D0 One cause of Glitch is the time skew between bits of the incoming digital data. Typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time. Unequal delay paths through the device can cause one current source to change before another. To minimize this, the Intersil HI5721 employes an internal register just prior to the current sources updated on the rising clock edge. In traditional DACs the worst case glitch usually happens at the major transition i.e. 01 1111 1111 to 10 0000 0000. But in the HI5721 the worst case glitch is moved to the 00 0001 1111 to 11 1110 0000 transition. This is achieved by the split R/2R segmented current source architecture. This decreases the amount of current switching at any one time and reduces the glitch by a factor of 16. Since the glitch is a transient event, this leads designers to believe that a simple low pass filter can be used to eliminate or reduce the size of the glitch. In effect low pass filtering a glitch tends to "smear" the event and does little to remove the energy of the transient. D1 D2 D3 1 QUADRANT OF SINE WAVE DATA D4 D5 D6 D7 D8 INV D9 FIGURE 5. USING THE INTERNAL QUADRATURE LOGIC To use the internal quadrature logic simply connect the INVERT pin to bit D9 of the HI5721 DAC. In normal operation INVERT should be connected to 0V or Digital Ground. 2 Application Note 9410 Integral Linearity The HI5721 has a FSR range of 20.48mA. When driving an equivalent 50 load the full scale voltage swing is 0V to +1.024V. Most video and communication applications use a 1VP-P voltage swing which yields 20mA full scale current sink capability. With a 1VP-P voltage swing on the HI5721 output an LSB is: INL 0.5 0.4 0.3 LSB = Full Scale Range/(2N-1) where N is the number of bits and the Full Scale Range is 1VP-P. The LSB size for this application is 977V. To determine the Integral Linearity of the HI5721 the bit weights of each major transition is taken. The Best Fit Straight Line method is used to calculate the overall INL. Measurements are taken at bits 0 thru 6 at each bit transition. Then all combinations of the upper 4 bits are measured. Finally some worst case codes are measured and the full scale is measured. Once this is completed a best fit straight line is drawn through the data points and the worst case deviation is determined. The worst case integral linearity of the HI5721 is specified to be less than 1.5 LSBs. The linearity of the HI5721 is worst in the segmented current sources in the thermometer encoded section. This is due to the errors of each current source being biased in one direction and being additive with increasing data values. The R/2R resistor matching need be to a 6-bit level to ensure overall 10-bit linearity. Process control of resistor matching in the BiCMOS process used is easily adequate to do the job. For the overall transfer function the typical INL performance is shown in Figure 6. DNL 0.25 0.20 0.2 0.1 0 -0.1 -0.2 CODE FIGURE 6B. TYPICAL PERFORMANCE CURVE FIGURE 6. Differential Linearity and Missing Codes For a D/A Converter the differential linearity is the step size difference throughout the entire code range. For the HI5721 the step to step maximum difference is 1.0 LSBs. For any given D/A converter, to guarantee no missing codes the converter must be monotonic. The definition of monotonicity is; as the input code is increased the output should increase. When an input code is increased and the output of the DAC does not increase or reverses direction, then this converter is assumed to be missing codes. INPUT CODE GREATER THAN ZERO 0.15 0.10 11 GREATER THAN -1.0 LSB ERROR 0.05 0.00 10 (MISSING CODE) -0.05 01 -0.10 -0.5 LSB ERROR CODE FIGURE 6A. INL TYPICAL PERFORMANCE CURVE OUTPUT VOLTAGE 00 FIGURE 7. DNL EXAMPLE Shown in Figure 7, as the input code increases the output voltage should increase. When an error of greater than 1.0 LSB is incurred, that bit can be assumed to be a missing code since the output did not increase but rather remained the same. 3 Application Note 9410 Adjusting Full Scale A: NCOMCTRL The RSET pin is used to set the Full Scale Output Current. The output current is a function of the reference voltage applied to the CONTROL AMP IN pin and the value of the RSET resistor. To calculate the IOUT Full Scale Current use the following formula: the HSP45116 Control Panel will be loaded. To exercise the board the following parameters should be set: IOUT Full Scale = 32 x (CONTROL AMP IN/RSET) CENTER FREQUENCY = 01000000HEX So where CONTROL AMP IN = 1.25V and RSET = 1960 IOUT = 20.4mA To adjust the output full scale current, use a potentiometer in rheostat mode as shown in Figure 8. RSET (17) BINFMT# = 0 and then set the Center Frequency to: where the center frequency is in hex. At this point the output of the HI5721 DAC module should be converting a sine wave at 48KHz. Connect the output of the HI5721 module to an oscilloscope. The HI5721 module has Jumper plug for selecting INVERT feature of the HI5721. When J2 is installed, quadrature logic is disabled. When J2 is removed, quadrature logic is enabled and the DAC data will be complemented. the the the 1's DDS Interface 5K 1960 FIGURE 8. FULL SCALE OUTPUT APPLICATION CIRCUIT The HSP45116 board is a TTL/CMOS compatible logic board. The HI5721 is a TTL/CMOS compatible logic D/A converter. The design of the DAC module is to interface to the 10 Most Significant Bits of the NCO. The HI5721 module should be plugged into P2 of the HSP-EVAL board. Spurious Free Dynamic Range The Control Amplifier The internal Control Amplifier is used to buffer the internal or an external reference. The precision current cells require an adequate amount of drive to bias. The Control Amplifier frees the user from having to provide an external amplifier. The Evaluation Board The HI5721 Evaluation board is a 1/2 size daughter board designed to interface to the HSP-EVAL board. When used together these boards create a flexible and powerful DDS system. The HSP45116 board is used to generate the high speed digital sine wave patterns for the D/A module. The HI5721 board reconstructs the incoming digital data to an analog representation that can be analyzed on a spectrum analyzer or oscilloscope. Plugging In After setting-up the HSP45116 board and the HI5721 board; power should be applied to the banana jacks. A +5V, and a 5.2V supply will be needed. To reduce noise the power supply leads should be twisted pairs. Connect the interface cable to an IBM PC or compatible's parallel port. Power should be applied to the board and then run the software directly from floppy disk. To run the software place the floppy disk into drive A: and type: 4 The Spurious Free Dynamic Range of the HI5721 DACs is the most important specification for communication applications. This specification shows how Integral Linearity, Glitch, and Switching noise affect the spectral purity of the output signal. Several important things must be noted first. When a quantized signal is reconstructed, certain artifacts are created. Let's take the example of trying to recreate a 1MHz sine wave with a 1VP-P output. In the frequency domain the fundamental should appear at 1MHz as shown in Figure 9. 0 FUNDAMENTAL (PURE TONE) AMPLITUDE (dB) -50 NOISE FLOOR -85 f 1MHz fN FIGURE 9. FREQUENCY PLOT OF 1MHz TONE The fundamental of a pure 1MHz tone should appear as an impulse in the frequency domain at 1MHz. In a sampled system noise terms are produced near the sampling frequencies called aliases. These aliases are related to the fundamental in that they are located at fN around the sampling frequency as shown in Figure 10. Application Note 9410 So for a 1MHz fundamental and a 5MHz sampling rate an alias term is created at 4MHz and 6MHz. A (SIN)/X function shaping is also induced by sampling a signal. Aliases continue up through the frequency spectrum repeating around the sampling frequency and its harmonics (i.e. 2fS, 3fS, 4fS). FUNDAMENTAL 0 SAMPLING FUNCTION (SIN X)/X A reconstructed sine wave out of the HI5721 is not ideal and as such has harmonics of the fundamental. The difference between the magnitude of the fundamental and the highest noise spur whether it is harmonically related to the fundamental or not, is the definition of Spurious Free Dynamic Range. Figures 11, through 16 are sample plots taken of the HI5721 at various frequencies. Included are the oscilloscope plots. AMPLITUDE (dB) -50 ALIAS (fS - 1MHz) -85 f 1MHz fN 4MHz fS FIGURE 10. SAMPLING ALIAS PRODUCTS MKR -65.50dBC f N = 1MHz UNFILTERED ATTEN 20dB RL 0dB 10dB/ 1.00MHz f S = 40MHz MKR 1.00MHz -65.50dB START 0Hz RBW 1.0kHz FIGURE 11A. OSCILLOSCOPE PLOT VBW 1.0kHz FIGURE 11B. SAMPLE PLOT FIGURE 11. A 1MHz FUNDAMENTAL TO fS UNFILTERED f N = 1MHz UNFILTERED LIMIT SPAN ATTEN 20dB RL 0dB 10dB/ MKR -81.50dBC 33kHz f S = 40MHz MKR 33kHz -81.50dB CENTER 1.000MHz RBW 300Hz VBW 300Hz SPAN 1.000MHz SWP 28.0s FIGURE 12. A 1MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED 5 STOP 20.00MHz SWP 50.0s Application Note 9410 MKR 64.16dBC f N = 1MHz FILTERED ATTEN 20dB RL 0dB 10dB/ 1.00MHz f S = 40MHz MKR 1.00MHz -64.16dB START 0Hz RBW 3.0kHz FIGURE 13A. OSCILLOSCOPE PLOT VBW 3.0kHz STOP 20.00MHz SWP 5.60s FIGURE 13B. A 1MHz FUNDAMENTAL TO NIQUIST WITH A 20MHz BANDPASS FILTER FIGURE 13. A 1MHz FUNDAMENTAL TO NYQUIST WITH A 20MHz BANDPASS FILTER MKR -55.50dBC f N = 5MHz UNFILTERED ATTEN 20dB RL 0dB 10dB/ 10.00MHz f S = 40MHz MKR 10.00MHz -55.50dB START 0Hz RBW 1.0kHz FIGURE 14A. OSCILLOSCOPE PLOT VBW 1.0kHz FIGURE 14B. SAMPLE PLOT FIGURE 14. A 5MHz FUNDAMENTAL TO fS UNFILTERED f N = 5MHz UNFILTERED LIMIT SPAN ATTEN 20dB RL 0dB 10dB/ MKR -66.83dBC 5kHz f S = 40MHz MKR 5kHz -66.83dB CENTER 5.000MHz RBW 300Hz VBW 300Hz SPAN 1.000MHz SWP 28.0s FIGURE 15. A 5MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED 6 STOP 20.00MHz SWP 50.0s Application Note 9410 fN = 5MHz FILTERED ATTEN 20dB RL 0dB MKR -65.34dBC 10dB/ 5.00MHz fS = 40MHz PEAK THRESHOLD -80.6dBm START 0Hz RBW 3.0kHz FIGURE 16A. OSCILLOSCOPE PLOT VBW 3.0kHz FIGURE 16B. SAMPLE PLOT FIGURE 16. A 5MHz FUNDAMENTAL TO fS WITH A BANDPASS FILTER 7 STOP 20.00MHz SWP 5.60s Application Note 9410 Using the HSP-EVAL Test Platform The HSP-EVAL DDS platform allows quick testing of spectral properties of a given DAC. The Numerically Controlled Oscillator/Modulator (NCOM) generates digital sinewave patterns that are loaded into the DAC. The analog output of the DAC is the reconstructed sinewave pattern. The program NCOMCTRL allows downloading of the desired center frequency. The clock or sampling frequency is 25MHz. To determine the center frequency codeword the following formula is used: Center FrequencyHEX = (Desired Frequency/25MHZ) x 232 This 32-bit hexadecimal word will create the fundamental. In order to ensure zero phase offset the cursor should be moved to the LOAD select. Pressing the spacebar the value should be toggled from 1 to 0 and back to 1 again. This will ensure that any previous values in the phase register are cleared and the sinewave pattern is started at zero phase. The HSP-EVAL setup is powered from the DAC module power-supply banana jacks. The output of the setup can be observed on an oscilloscope or a spectrum analyzer. HSP-EVAL/HPS45116 NCOM EVALUATION BOARD CLOCK CIRCUIT HI5721 DAC MODULE HSP45116 NUMERICALLY CONTROLLED OSCILLATOR HI5721 DAC PC INTERFACE 50 SMA CABLE -5.2V +5V POWER SUPPLY SOFTWARE INCLUDED SPECTRUM ANALYZER PERSONAL COMPUTER FIGURE 17. INTERSIL HI5721/DDS EVALUATION SYSTEM SETUP BLOCK DIAGRAM 8 Schematic Diagram VCC J1C 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DB0 DB3 DB5 DB7 DB9 CON32 CON32 DB1 DB2 DB4 DB6 DB8 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 P1 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 VCC R17 50 VCC CLK J2 R5 22K R6- R15 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R16 28 15 CON2 27 16 -5.2V DVDD D9 (MSB) IOUT D8 D7 D6 IOUT/ D5 D4 REF IN D3 D2 C AMP OUT D1 D0 (LSB) CLK C AMP IN REF OUT INVERT RSET DV SS DVSS ARET AVSS DVEE DVEE AVEE 20 R2 21 50 R1 23 CON32 26 25 17 19 + C1 0.1F R3 C2 0.1F VCC C8 0.1F + 22 -AVEE PLACE AS CLOSE TO PIN 22 AS POSSIBLE C10 + 10F C3 0.01F C11 0.01F R4 SYSTEM GROUND 10 + SPACE LIKE A FERRITE BEAD L1 -AVEE ECL SUPPLY -5.2V 10H NOTES: 1. All passive components are SMT devices, except polarized capacitors and ferrite beads. 2. HI5721 is a 28 lead DIP. FIGURE 18. C9 10F 1960 18 PLACE AS CLOSE TO PIN 16 AS POSSIBLE VCC BJACK 50 24 -5.2V +5V BJACK BJ1 J3 SMA HI5721 BJ1 BJACK BJ1 11 13 50 1 2 U1 14 1 2 3 4 5 6 7 8 9 10 C4 0.1F -AVEE C5 0.01F Application Note 9410 J1B 9 J1A Application Note 9410 HI5721 EVAL. BOARD Evaluation Board Layers FIGURE 19A. HI5721 SILKSCREEN FIGURE 19B. HI5721 LAYER 1 10 Application Note 9410 Evaluation Board Layers (Continued) FIGURE 19C. HI5721 LAYER 2 FIGURE 19D. HI5721 LAYER 3 11 Application Note 9410 Evaluation Board Layers (Continued) FIGURE 19E. HI5721 LAYER 4 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 12 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029